JP6337570B2 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Description

  The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

  The arithmetic processing unit (processor) has an arithmetic processing unit (ALU: Arithmetic Logic Unit) and a cache memory unit, and stores a part of data (including instruction code and data) in the main memory in the cache memory unit, Speeds up memory access requests by the processing unit. Generally, a processor core has an arithmetic processing unit and a primary cache memory unit (hereinafter simply referred to as a primary cache), and the processor is a secondary cache memory unit (hereinafter simply referred to as a secondary cache) between a plurality of cores. ).

  The arithmetic processing unit of the core issues a memory access instruction based on the virtual address. The virtual address is converted into a physical address by a TLB (Translation Lookaside Buffer) which is an address conversion table. However, in order to increase the speed, the primary cache tag memory is searched with a virtual address, and the cache address is determined by comparing the physical address read from the primary cache tag memory with the physical address converted by the TLB. Do.

  The search address of the primary cache is a virtual address. On the other hand, when the correspondence between the virtual address and the physical address is changed by updating the address translation table TLB due to process change etc., there is an address in the address translation table. The virtual address corresponding to the physical address may not match the virtual address corresponding to the same physical address in the primary cache tag. As a result, when the arithmetic processing unit requests access to the data at a certain physical address registered in the primary cache before updating with the updated virtual address, the physical address searched in the primary cache tag memory does not match the primary cache. And a cache miss is determined. This state is called a synonym.

  If the primary cache determines a cache miss due to the occurrence of a synonym, an access request is made to the secondary cache. In response to this, when the secondary cache determines that the cache hits, a data response is made to the primary cache. The primary cache registers the data of the data response and registration information in the primary cache data memory and the primary cache tag memory in the primary cache, respectively. When this data registration is performed, if data with a virtual address before update remains in the primary cache, the same data is registered twice in the primary cache. In order to prevent this, the secondary cache performs a synonym determination by determining whether or not the virtual addresses match, and if it is determined to be a synonym, executes the synonym process to execute a synonym process. Prevent double registration of data. As will be described later, this synonym process includes a process for determining whether or not the same data is registered in the primary cache, and a process for deleting the data from the primary cache if the same data is registered.

JP 2008-165626 A International Publication No. 2007/094046

  On the other hand, in recent years, it has been proposed to perform cache injection for registering data in the lowest level cache when transferring data to the main memory from outside the processor via an I / O (Input / Output) device. Yes. When the processor has a configuration of a primary cache and a secondary cache, data is registered in the secondary cache at the lowest level by the cache injection process, but the data is not registered in the primary cache.

  Since the cache injection process is performed from the I / O device and is not accompanied by a virtual address, the secondary cache cannot register the virtual address for the injected data in the secondary cache tag. Therefore, the synonym state is determined by the synonym determination in the secondary cache at the time of a subsequent memory access request. As a result, the secondary cache executes the above synonym processing even though it is not in the synonym state. In synonym processing, a plurality of requests are input to the cache pipeline of the secondary cache and executed, resulting in a decrease in processor processing efficiency.

  Accordingly, an object of one embodiment is to provide an arithmetic processing device and a control method for the arithmetic processing device that avoid unnecessary synonym processing.

One aspect of the embodiment includes a primary cache memory unit including a primary cache tag and a primary cache data memory searched by a virtual address, and a primary cache control unit that performs cache control,
A secondary cache tag and a secondary cache data memory searched by a physical address, and a secondary cache control unit for performing cache control, wherein the secondary cache control unit detects that the primary cache memory unit has a cache miss If it is determined that the secondary cache tag is a cache hit in response to the generated access request, the cache in the synonym state in the primary cache memory unit based on the primary cache state information in the secondary cache tag And a secondary cache memory unit that executes a synonym process for deleting registration.

  Processing efficiency can be improved without performing unnecessary synonym processing.

It is a figure which shows the structure of the arithmetic processing unit in this Embodiment. It is a figure explaining operation | movement of the data request | requirement which is a typical example of the access request from the arithmetic processing part 12 of FIG. FIG. 3 is a sequence diagram illustrating an operation of a data request in FIG. 2. It is a figure which shows the example of four requests | requirements in a data request. It is a figure explaining generation | occurrence | production of a synonym state by which different virtual address VA is allocated to the same physical address PA in L1 cache tag L1-TAG1. It is a figure explaining generation | occurrence | production of a synonym state. It is a figure explaining the operation | movement which avoids a synonym state. FIG. 8 is a flowchart showing an operation for the data request in FIGS. 2 and 3 and an operation when a synonym state is detected at the time of the data request in FIG. 7. FIG. 9 is a sequence diagram showing an operation (third operation) when a cache hit occurs in the L1 cache tag copy L1-TAG2 among the operations for avoiding the synonym state of FIG. 7; FIG. 9 is a sequence diagram showing an operation (fourth operation) in a case where a cache miss occurs in the L1 cache tag copy L1-TAG2 among the operations for avoiding the synonym state of FIG. It is a figure which shows a cache injection operation | movement. It is a figure which shows the operation | movement of the data request | requirement after the cache injection of this Embodiment. It is a figure which shows the 3rd operation | movement in the case of this Embodiment. It is a flowchart figure in this Embodiment. It is a sequence diagram which shows the operation | movement (5th operation | movement) of the data request | requirement after cache injection. It is a figure which shows the logic circuit which performs synonym determination of L2 cache pipeline and VA update of L2-TAG1 in this Embodiment. It is a figure which shows the specific example of the L1 cache tag and L2 cache tag in this Embodiment. It is a figure which shows the specific example of the data format of the L1 cache tag and L2 cache tag in this Embodiment.

  FIG. 1 is a diagram showing a configuration of an arithmetic processing device according to the present embodiment. The arithmetic processing unit (CPU) 1 includes a CPU core (arithmetic processing unit) 10 and a secondary cache memory unit 20. The CPU core 10 includes an arithmetic unit 12 and a primary cache memory unit 14.

  The primary cache memory unit (hereinafter referred to as L1 cache) 14 includes a primary cache pipeline (primary cache memory control unit) 16, an address translation unit TLB that converts a virtual address into a physical address, and a primary cache tag memory (hereinafter referred to as “first cache tag memory”). L1 cache tag) L1-TAG1 and primary cache data memory L1-DATA. The L1 cache tag L1-TAG1 is searched with the virtual address VA, and the physical address PA read from the L1-TAG1 is compared with the physical address PA converted by the address translation unit TLB to determine whether it is a cache hit or a miss To do. Thus, the L1 cache tag L1-TAG1 is searched for and read from the virtual address VA is the physical address PA, and is VIPT (Virtually Indexed Physically Tagged). The search address is the upper bit of the access destination address, and the lower bits of the access destination address (excluding the lower address of the cache block size) are read from the L1 cache tag.

  The secondary cache memory unit (or L2 cache) 20 receives a request for both ports, a move import MIPORT that accepts an access request from the primary cache memory unit (L1 cache) 14, a move out port MOPORT that accepts a data write request, and so on. A request input unit (selector) SEL that selects and inputs to the secondary cache pipeline 22 is included. Further, the secondary cache memory unit 20 includes a secondary cache tag memory (hereinafter referred to as L2 cache tag) L2-TAG1, a secondary cache data memory L2-DATA, and a primary cache that is a copy of the primary cache tag L1-TAG1. A tag copy L1-TAG2 and a request lock unit 24 are provided. The secondary cache tag and the secondary cache data memories L2-TAG1 and L2-DATA are searched by physical addresses. On the other hand, the primary cache tag copy L1-TAG2 is searched with a virtual address. Thus, the secondary cache tag L2-TAG1 is also searched for and read from the physical address PA is the physical address PA, and is PIPT (Physically Indexed Physical Tagged).

  The CPU 1 further includes an input / output control unit I / O that interfaces with the outside and a memory access controller MAC that controls access to the main memory 30. The input / output control unit I / O is connected to a storage device HDD having a large capacity (for example, a hard disk) via, for example, an external bus BUS.

  FIG. 2 is a diagram for explaining the operation of a data request, which is a typical example of an access request from the arithmetic processing unit 12 in FIG. FIG. 3 is a sequence diagram showing the data request operation. The data request operations shown in FIGS. 2 and 3 are examples in which the primary cache memory unit becomes a cache miss and the data request is output to the move import MIPORT to the secondary cache memory unit. In FIG. 3, (1) is an example of hit with the secondary cache tag L2-TAG1, and (2) is an example of miss with the secondary cache tag L2-TAG1. In FIG. 3, the process number in FIG. 2 and the process number in FIG.

  The arithmetic unit 12 in the CPU core 10 inputs a data request to the primary cache control unit 14 (S51). The primary cache control unit 14 searches the primary cache tag L1-TAG1 with the virtual address VA of the data request, compares the physical address read from L1-TAG1 with the physical address converted by the address conversion unit TLB, A cache miss occurs (S52). Therefore, the primary cache control unit 14 inputs a data request to the move import MIPORT of the secondary cache memory unit 20 (S53), and the request input unit SEL inputs a READ request to the secondary cache control unit 22 (S54). . The secondary cache control unit 22 searches the secondary cache tag L2-TAG1 with the physical address PA of the data request, and when a cache hit occurs (S55), the secondary cache control unit 22 responds to the primary cache memory unit 14 with a data response. At the same time, the registration information (physical address etc.) of the hit data is registered in the primary cache tag copy L1-TAG2 (S56_A), and the data response is registered in the primary cache tag L1-TAG1 and the primary cache data memory L1-DATA. Information and data are registered respectively (S56_B).

  When the secondary cache control unit 22 searches the secondary cache tag L2-TAG1 and detects a cache miss (S57), it issues a data read request to the memory access controller MAC (S58), and the memory access controller MAC stores the main memory. Data is read from 30 and a data response is made to the secondary cache control unit 22 (S59). This data response is input to a move import (not shown) in the secondary cache memory unit 20, and the request input unit SEL inputs an MVIN request to the secondary cache pipeline 22, and the data returned from the memory access controller MAC and its data The address is registered in the secondary cache tag L2-TAG1 and the data memory L2-DATA (S60_A), registered in the primary cache tag copy L1-TAG2 (S56_A), and a data response is made to the primary cache memory unit 14. In response to this, the primary cache memory unit 14 registers registration information and data in the primary cache tag L1-TAG1 and the data memory L1-DATA (S56_B).

  In the example of a cache hit in the secondary cache of FIG. 3 (1), by inputting a READ request to the L2 cache pipeline 22, the secondary cache tag search, the primary cache tag copy L1-TAG2, and the primary cache are performed. Complete registration to tag L1-TAG1 and data memory L1-DATA. On the other hand, in the example of a cache miss in the L2 cache in FIG. 3B, in addition to the READ request, an MVIN request is input to the secondary cache pipeline 22.

  FIG. 4 is a diagram illustrating an example of four requests in a data request. The READ request is a request instruction for reading data in the secondary cache memory unit, and the MVIN request is a request instruction for newly registering data in the secondary cache memory unit and the primary cache memory unit. , 3 explained.

  The MOEX request is a request instruction that deletes the entry of the old virtual address VA in the primary cache memory unit, moves the data if the entry is stored, and registers the data in the secondary cache memory unit. . In addition, when data is registered in the secondary cache memory unit such as when a synonym occurs, the MIRD request registers new data in the primary cache memory unit and sets the virtual address VA of the secondary cache tag L2-TAG1. This is a request command to be updated. The MIRD request includes a process for updating the L1 type code L1-TC in the secondary cache tag L2-TAG1.

  Hereinafter, for the sake of simplicity, the primary cache memory unit 14 is the L1 cache 14, the primary cache tag memory L1-TAG1 is the L1 cache tag, the secondary cache memory unit 20 is the L2 cache 22, and the secondary cache tag memory. L2-TAG1 is called L2 cache tag, and primary cache tag copy L1-TAG2 is called L1 cache tag copy. The L1 cache control unit 16 and the L2 cache control unit 22 are referred to as an L1 cache pipeline 16 and an L2 cache pipeline 22, respectively.

[Synonym state]
FIG. 5 is a diagram for explaining the occurrence of a synonym state in which different virtual addresses VA are assigned to the same physical address PA in the L1 cache tag L1-TAG1. FIG. 6 is a diagram for explaining the occurrence of a synonym state.

  In FIG. 5, as shown in FIGS. 2 and 3, the physical address PA_T1 corresponding to the lower bits of the virtual address VA1 is stored in the L1 cache tag L1-TAG1 by the data request by the virtual address VA1 (including the upper address and the lower address). Indicates the registered state. When the physical address for the virtual address VA of the data request is PA_I for the upper address and PA_T for the lower address, the upper address PA_I is used as an index for searching the L2 cache tag L2-TAG1, and the lower address PA_T is used for the L1 cache tag L1. -Tag address in TAG1 and L2 cache tag L2-TAG1. However, since the L2 cache tag L2-TAG1 generally has a larger capacity than the L1 cache tag L1-TAG1, the number of bits of the physical address in the L1 cache tag L1-TAG1 and the physical address in the L2 cache tag L2-TAG1 Is different. In FIG. 5, for the sake of simplicity, the same physical address PA_T1 is stored in the L1 and L2 cache tags.

  In the above state, when the translation table of the address translation unit TLB is updated by process exchange or the like, different virtual addresses VA2 may be assigned to the same physical addresses PA_I1 and PA_T1.

  FIG. 6 shows an example of updating the address translation unit TLB. In FIG. 6, for the sake of simplicity, the 13-bit virtual address VA [12: 0] is divided into the most significant bit VA [12] and the lower bit VA [11: 0], and the most significant bit VA [12] is the L1 cache. It is assumed that it is used for the index address of the tag L1-TAG1. The 13-bit physical address PA [12: 0] is also divided into the most significant bit PA [12] and the lower bit PA [11: 0], and the most significant bit PA [12] is the index of the L2 cache tag L2-TAG1. It shall be used for address.

  In the state of FIG. 6A, the physical address PA [12: 0] corresponding to the virtual address VA1 is PA_I1, PA_T1, and the physical address PA [12: 0] corresponding to the virtual address VA2 is PA_I2, PA_T2. . In contrast, in the state of FIG. 6B in which the address conversion table TLB has been updated, the physical addresses PA_I1, PA_T1, PA_I2, and PA_T2 with respect to the virtual addresses VA1 and VA2 have an inverse relationship. In this way, the address conversion table TLB may be updated. As a result, a synonym state in which the old virtual address VA1 before the update of the address translation table TLB and the new virtual address VA2 after the update are allocated to the same physical address PA_I1, PA_T1 occurs.

  Therefore, FIG. 5 shows a state where the L1 cache tag L1-TAG1 is not updated even though the address translation table TLB is updated as shown in FIG. 6 and a synonym state occurs. When the tag L1-TAG1 and the data L1-DATA in the L1 cache are reset, a new access to the main memory occurs. Therefore, even if the TLB is updated, the L1 cache is not updated. As a result, in the L1 cache tag L1-TAG1, the physical address PA_T1 of the tag is associated with the virtual address VA1, and PA_T2 is associated with VA2.

  In this state, a case where a data request is generated from the arithmetic processing unit at the virtual address VA2 for the data D1 of the same physical address PA1 will be described. Each step S51-S56 in FIG. 5 corresponds to each step S51-S56 in FIG.

  First, when a data request is issued from the arithmetic processing unit with the virtual address VA2, the L1 cache pipeline 16 searches the L1 cache tag L1-TAG1 with the virtual address VA2 and reads the physical address PA_T2. On the other hand, the address translation unit TLB translates the virtual address VA2 and outputs a physical address PA_T1. As a result, the comparison between the physical addresses PA_T1 and PA_T2 becomes inconsistent and a cache miss occurs (S52). Therefore, the L1 cache pipeline 16 issues a data request to the move import MIPORT in the L2 cache 20 (S53).

  Next, when a READ request is input to the L2 cache pipeline 22 in response to the data request of the move import MIPORT, the L2 cache tag L2-TAG1 is retrieved from the physical address PA_I1, and the physical address PA_T1 is read. It matches the physical address PA_T1 translated from the virtual address VA2, resulting in a cache hit (S55). As a result, a data response is made from the L2 cache to the L1 cache, the physical address PA_T1 is registered for the virtual address VA2 in the L1 cache tag L1-TAG1 of the L1 cache 14, and the data D1 is stored in the L1 cache data memory L1-DATA. Registered (S56).

  This state means that the data D1 corresponding to the same physical address PA_T1 is double registered in the L1 cache tag L1-TAG1. Such double registration of the same data in the L1 cache causes a situation where data consistency is lost when data D1 is updated by subsequent writing, and must be avoided.

[Action to avoid synonym state]
FIG. 7 is a diagram for explaining an operation for avoiding the synonym state. The precondition of FIG. 7 is the same as FIG. Then, steps S51-S55 from when a data request for the new virtual address VA2 occurs in FIG. 7 until a cache miss occurs at the L1 cache tag L1-TAG1 and a cache hit occurs at the L2 cache tag L2-TAG1 are the same as in FIG. . Therefore, the description so far is omitted.

  As shown in FIG. 7, in order to detect the synonym state, the L2 cache pipeline 22 uses the old virtual address VA1 of the access destination when data is registered in the L1 cache as the L2 cache tag L2- in the L2 cache 20. Record in TAG1. Thereafter, when there is a data request from the L1 cache to the L2 cache (S53) and a cache hit occurs with the L2 cache tag L2-TAG1 (S55), the L2 cache pipeline 22 sends the new virtual addresses VA2 and L2 of the current data request. The old virtual address VA1 in the cache tag L2-TAG1 is compared (S61). If the new and old virtual addresses VA1 and VA2 do not match, it is found that the data request is for the new virtual address VA2 after the address translation unit TLB is updated. Therefore, if the same data is registered in the L1 cache, it is in a synonym state and must be confirmed.

  Therefore, an L1 cache tag copy L1-TAG2 that is a copy of the L1 cache tag L1-TAG1 is provided in the L2 cache 20, and the L2 cache pipeline 22 reads the old virtual address VA1 from the L2 cache tag L1-TAG1, The L1 cache tag copy L1-TAG2 is searched with the old virtual address VA1, and it is checked whether or not the same physical address PA_T1 corresponding to the current data request is registered for the old virtual address VA1 (S62). This check can also be performed for the L1 cache tag L1-TAG1, but since the L2 cache 20 needs to make a request to the L1 cache 14, the L1 cache tag copy L1-TAG2 is stored in the L2 cache, It can be confirmed in the L2 cache.

  If the L1 cache tag copy L1-TAG2 is searched and hit in the above step S62, it means that data of the same physical address is registered in the L1 cache. Therefore, the L2 cache pipeline 22 first deletes the entry (cache block) of the old virtual address VA1 in the L1 cache from the L1 cache tag L1-TAG1 and the data memory L1-DATA, and at the same time, the L1 cache tag copy L1-TAG2 The cache block of the old virtual address VA1 is also deleted, and a data response is sent to the L1 cache with the new virtual address VA2 (S64). In response, the data is registered in the L1 cache with the new virtual address VA2.

  In the above step S62, there may be a cache miss as a result of searching the L1 cache tag copy L1-TAG2 with the old virtual address VA1. In this case, after updating the address translation unit TLB, it means that the registration of the old virtual address VA1 has been erased from the L1 cache, so there is no need to erase the entry of the old address VA1 from the L1 cache in step S63. .

  In the above step S61, if the old virtual address and the new virtual address match, it means that the address translation unit TLB has not been updated, and there is no possibility of a synonym state, so the L2 cache pipeline Performs a data response in step S64 to the L1 cache after step S61.

  FIG. 8 is a flowchart showing the operation for the data request in FIGS. 2 and 3 and the operation when the synonym state is detected at the time of the data request in FIG.

  In FIG. 8, two types of operations (FIG. 3 (1) and (2)) in the case of a cache hit and a miss in the L2 cache tag L2-TAG1 in the data request of FIGS. It becomes street.

[First action when missed at L1 and hit at L2 (FIG. 3 (1))]
This operation is shown in steps S1-S11 in FIG. FIG. 8 also shows steps S51 to S56 in the sequence diagram of FIG. The operations in steps S1-S11 are as follows.
S1 (S51): The arithmetic processing unit 12 in the CPU core requests data from the L1 cache. Specifically, it issues a READ request to the L1 cache pipeline.
S2 (S52): The L1 cache pipeline searches the L1 cache tag L1-TAG1 with the virtual address VA. Here, a cache miss occurs.
S4 (S53): The L1 cache issues a data request to the L2 cache.
S5 (S54): In the L2 cache, the request input unit SEL inputs a READ request from the move import MIPORT to the L2 cache pipeline.
S6 (S55): The L2 cache pipeline searches the L2 cache tag L2-TAG1 with the physical address PA and hits it.
S7 (S61): The L2 cache pipeline compares the old virtual address in the L2 cache tag L2-TAG1 with the new virtual address of the current data request, and checks the synonym status. Here, since the address translation unit TLB has not been updated, the comparison result is coincident (MATCH).
S8, S9: The L2 cache pipeline updates a later-described L1 type code L1-TC in the L2 cache tag L2-TAG1, and registers the registration information of the hit data in the L1 cache tag copy L1-TAG2. The reason for registering in the L1 cache tag copy L1-TAG2 is that registration information is registered in the L1 cache tag L1-TAG1 when data is registered in the L1 cache in the subsequent step S10.
S10 (S56): The L2 cache pipeline returns data to the L1 cache. In response, the L1 cache registers the data.
S11: Finally, the L1 cache responds the data to the CPU core.

[Second action when L1 misses and L2 misses (Fig. 3 (2))]
This operation is shown in steps S1-S6 and S22-S28 in FIG. FIG. 8 also shows steps S51-S55, S58-60, and S56 in the sequence diagram of FIG. The operations in steps S1-S5 are as described above. Therefore, the operations of steps S6 and S22-S28 are as follows.
S6 (S55): The L2 cache pipeline searches the L2 cache tag L2-TAG1 with the physical address PA and makes a cache miss.
S22 (S58): The L2 cache pipeline issues a data request to the memory access controller MAC. In response to this, the MAC accesses the main memory and reads the data of the physical address.
S23 (S59): The MAC returns data to the L2 cache after reading data from the main memory.
S24 (S60): An MVIN request is input from the move-in buffer MIB (not shown) in the L2 cache to the L2 cache pipeline. The MVIN request is a request for registering new data in the L2 and L1 caches as shown in FIG.
S25: The L2 cache pipeline registers with the L2 cache tag L2-TAG1. By this registration, the current virtual address and physical address PA are stored in the L2 cache tag in correspondence with the physical address PA of the current data request in the L2 cache tag L2-TAG1. In addition, an L1 type code L1-TC, which will be described later, is also updated.
S26: The L2 cache pipeline registers data registration information from the MAC in the L1 cache tag copy L1-TAG2. The reason why the data is registered in the L1 cache tag copy L1-TAG2 is that data is registered in the L1 cache and registered in the L1 cache tag L1-TAG1 in the subsequent step S27.
S27 (S56): The L2 cache pipeline returns data to the L1 cache. In response, the L1 cache registers the data.
S28: Finally, the L1 cache sends a data response to the CPU core.

  As described above, steps S25-S28 are substantially the same as steps S8-S11. As can be understood from FIGS. 8 and 3, in the first operation when the L1 cache misses and the L2 cache hits (steps S1-S11, FIG. 3 (1)), the L2 cache pipeline has a READ request. Is completed, the process up to the last step S10 is completed. On the other hand, in the second operation (S1-S6, S22-S28, Fig. 3 (2)) when the L1 cache misses and the L2 cache misses, READ requests and MVIN requests flow into the L2 cache pipeline. As a result, the processing up to the last step S28 is completed.

  In FIG. 8, operations for avoiding the synonym state in FIG. 7 are as follows in FIG. 8 when two types of operations are performed when a cache hit occurs in L1 cache tag copy L1-TAG2 and when a miss occurs.

[Third action when L1 misses, L2 hits, VA does not match, L1-TAG2 hits (Figure 7)]
FIG. 9 is a sequence diagram showing an operation (third operation) when a cache hit occurs in the L1 cache tag copy L1-TAG2 among the operations for avoiding the synonym state of FIG. The third operation will be described below with reference to FIGS. The third operation is the longest operation of S1-S7, S12-S21, and S27-S28 in FIG. Steps S1-S6 are the same as those in the first operation, and thus are omitted.
S7 (S61): The L2 cache pipeline compares the old virtual address VA1 in the L2 cache tag L2-TAG1 with the new virtual address VA2 of the current data request, and checks the synonym status. Here, since the address translation unit TLB has been updated, the comparison result is unmatched (UNMATCH). In other words, it becomes a synonym hit.
S12: Therefore, the request input unit SEL inputs a MOEX request from MIPORT to the L2 cache pipeline. As shown in FIG. 4, the MOEX request is a request to delete the old VA entry (registration) in the L1 cache and move it out (write processing) to the L2 cache if the L1 cache data is stored data. .
S13 (S62): The L2 cache pipeline searches the L1 cache tag copy L1-TAG2 with the old virtual address VA1 read from L2-TAG1, and checks whether duplicate data is registered in the L1 cache. Here, the L1 cache tag copy L1-TAG2 detects a cache hit and detects that duplicate data is registered in the L1 cache.
S14: Therefore, the L2 cache issues a moveout request to the L1 cache to move out duplicate data in the L1 cache.
S15 (S63): In response to the move-out request, the L1 cache pipeline deletes the registration of the L1 cache tag L1-TAG1 and L1 cache data L1-DATA.
S16: The L1 cache pipeline makes an order response notifying the L2 cache that the registration has been deleted from the L1 cache.
S17: In response to this, a WRBK request (write back request) corresponding to the above order response is input from the move-out port MOPORT to the L2 cache pipeline. As a result, when the data erased in the L1 cache is stored, the L2 cache pipeline performs a data write process (write back process) in the L2 cache.
S18: Then, the L2 cache pipeline deletes the registration of the L1 cache tag copy L1-TAG2. This is because the registration of L1-TAG2 of the copy is deleted because the registration is deleted in the L1 cache. This completes the processing for the old virtual address VA1.
S19: Next, the request input unit SEL inputs a MIRD request from MIPORT to the L2 cache pipeline. As shown in FIG. 4, the MIRD request is a request for updating the virtual address VA of the L2 cache tag L2-TAG1 while newly registering data in the L1 cache.
S20: The L2 cache pipeline updates the virtual address VA in the L2 cache tag L2-TAG1 to the new virtual address VA2, and later registers data in the L1 cache. Update the L1 type code Ll-TC to valid (VALID).
S21: The L2 cache pipeline registers the registration information of the new virtual address VA2 in the L1 cache tag copy L1-TAG2. The reason why the data is registered in the L1 cache tag copy L1-TAG2 is that data is registered in the L1 cache and registered in the L1 cache tag L1-TAG1 in the subsequent S28.
S27 (S64): The L2 cache pipeline returns data to the L1 cache. In response, the L1 cache registers the data.
S28: Finally, the L1 cache sends a data response to the CPU core.

  Therefore, as shown in FIG. 9, steps S14-S18 are processes for the old virtual address VA1 (OLD-VA), the registration is deleted from the L1 cache, and if necessary, the deleted data is moved out to the L2 cache. This process also deletes the registration of the cache tag copy L1-TAG2. Processes S19-S21 and S27-S28 are processes for the new virtual address VA2 (NEW-VA), which is a process for updating the virtual address of L2-TAG1, registering it in L1-TAG2, and registering it in the L1 cache .

  In the third operation, a READ request, a MOEX request, an order response (WRBK), and a MIRD request are input to the L2 cache pipeline.

  Steps S20-S21 and S27-S28 are substantially the same as steps S8-S11 of the first operation and steps S25-S28 of the second operation.

[Fourth operation when L1 misses, L2 hits, VA does not match, L1-TAG2 misses (Figure 7)]
FIG. 10 is a sequence diagram showing an operation (fourth operation) in the case of a cache miss in the L1 cache tag copy L1-TAG2 among the operations for avoiding the synonym state of FIG. The fourth operation will be described below with reference to FIGS. The fourth operation is the operation of S1-S7, S12-S13, S19-S21, S27-28 in FIG. Steps S1-S7 are the same as the third operation. Steps S19-S21 and S27-S28 are the same as the third operation. Hereinafter, the fourth operation will be described.

S12: Since the new virtual address VA2 and the old virtual address VA1 do not match in step S7, the request input unit SEL inputs a MOEX request from the MIPORT to the L2 cache pipeline. The MOEX request is a request to delete the old VA entry (registration) in the L1 cache and move out (write processing) to the L2 cache if the data in the L1 cache is stored data.
S13 (S62): Next, the L2 cache pipeline searches the L1 cache tag copy L1-TAG2 with the old virtual address VA1 read from L2-TAG1, and checks whether duplicate data is registered in the L1 cache To do. Here, a cache miss is detected at L1-TAG2, and it is detected that duplicate data is not registered in the L1 cache.
S19: Next, the request input unit SEL inputs a MIRD request from MIPORT to the L2 cache pipeline. The MIRD request is a request for updating the virtual address VA of L2-TAG1 while newly registering data in the L1 cache.

  Thereafter, the processing is the same as the processing S20-S21, S27-S28 for the new virtual address in the third operation of FIG. As can be understood by comparing the sequence diagram of the fourth operation in FIG. 10 with the third operation in FIG. 9, in the fourth operation in FIG. 10, since the cache miss occurred in the L1 cache tag copy L1-TAG2, the old virtual address ( There is no L1 cache registration deletion process for OLD-VA), and only the processes S20-S21 and S27-S28 for the new virtual address (NEW-VA) are performed.

  Further, in the fourth operation, a READ request, a MOEX request, and a MIRD request are input to the L2 cache pipeline.

[Problems of cache injection operation]
FIG. 11 is a diagram showing a cache injection operation. When the I / O controller I / O in the CPU 1 in FIG. 1 transfers data from the outside to the main memory 30 and writes it to the main memory 30, the cache injection is also applied to the lowest level cache, in the example of FIG. This is a process of registering data. Further, the input / output control unit I / O may register the data in the L2 cache without writing external data into the main memory 30. In this way, if data is registered in the L2 cache, the data can be read from the L2 cache without accessing the main memory when a data request is subsequently issued by the CPU core. Can be improved.

  As shown in FIG. 11, the input / output control unit I / O requests that data D1 be registered in the physical address PA1 (PA_I1 and PA_T1) of the main memory 30 (S71). In response to this, the L2 cache pipeline searches the L2 cache tag L2-TAG1 with the search physical address PA_I1, and deletes the registration if a cache hit occurs (S72). Further, the L2 cache pipeline makes a request for writing the data D1 to the main memory 30 via the MAC (S73), and registers the data D1 in the L2 cache (S74).

  In the case of cache injection, since there is no data request from the CPU core, it becomes a data registration request without the virtual address VA. Therefore, the L2 cache pipeline cannot register a correct virtual address in the virtual address in the L2 cache tag L2-TAG1. In this case, the L2 cache pipeline may register a physical address PA_I1 that is a search address, for example. Alternatively, an address other than the physical address PA_I1 may be registered.

  In any case, the L2 cache pipeline sets an incorrect address to the virtual address in the L2 cache tag L2-TAG1. As a result, when the new virtual address of the current data request is compared with the virtual address in the L2 cache tag L2-TAG1 in step S61 in FIG. 7 and step S7 in FIG. 8, a determination result of mismatch (UNMATCH) is obtained.

  As shown in FIG. 8, a MOEX request is input from MOPORT to the L2 cache pipeline (S12), and a cache miss is caused by searching the L1 cache tag copy L1-TAG2 (S13). , S62 miss), it is confirmed that no data is registered in the L1 cache, a MIRD request is input from the MIPORT to the L2 cache pipeline (S19), and steps S20-S21, S27-S28 are executed. In other words, in the data request after cache injection, the judgment result of the old virtual address and the new virtual address in the L2 cache tag L2-TAG1 is inconsistent (synonym hit), and synonym processing (OLD-VA erase and NEW-VA (Registration) occurs and processing efficiency decreases. In the data request after cache injection, since no data is registered in the L1 cache, a synonym hit occurs because a virtual address is not specified in the data registration request at the time of cache injection even though a synonym state has not occurred. As a result, the processing efficiency is reduced. In addition, when a large amount of data is registered in the L2 cache by cache injection, synonym hits due to the above-mentioned virtual address mismatch frequently occur for subsequent data requests from the CPU core. Every time a synonym hit occurs, the MOEX request and MIRD request are input to the L2 cache pipeline, so the degree of processing degradation is serious.

  Therefore, in the data request after the cache injection, the L2 cache unnecessarily executes the processes S12, S13, and S19 surrounded by the broken line in FIG.

[This embodiment]
Therefore, in the present embodiment, an area for recording information indicating registration by cache injection is provided in the L2 cache tag L2-TAG1. When the L2 cache pipeline registers data in the L2 cache by cache injection, the cache injection information is set to ON. After that, when a data request is issued from the CPU core, a cache miss occurs in the L1 cache and a cache hit occurs in the L2 cache. At this time, the L2 cache pipeline performs synonym determination based on the comparison result between the old virtual address OLD-VA and the current virtual address NEW-VA in the L2 cache tag L2-TAG1, and the cache injection information. That is, in the synonym determination, if the comparison result of the virtual address is unmatched (UNMATCH) and the cache injection information is off, it is determined as a synonym hit, and even if the comparison result of the virtual address is unmatched (UNMATCH) When the injection information is on (indicating that it has been written by cache injection), it is determined as a synonym miss hit. If the L2 cache pipeline is determined to be a synonym miss hit, the operation of the READ request is continued as in the case of VA MATCH in step S7 of FIG. 8, and steps S20-S21, S27-S28 are performed. Execute.

  The state in which the above-described cache injection information is on can be detected when the L1 type code L1-TC, which is the L1 cache state information, is in an invalid (INVALID) state. Generally, the L1 type code L1-TC in the L2 cache tag L2-TAG1 is shared by multiple CPU cores (whether it is shared) or can be shared with other CPU cores (shared) Status information is registered. When data is not registered in the L1 cache, the L1 type code L1-TC is in an invalid (INVALID) state, which is neither state. Therefore, it can be detected that only the L2 cache is registered by the cache injection and is not registered in the L1 cache depending on whether or not the L1 type code is in an invalid state.

  Therefore, according to the present embodiment, when the secondary cache control unit determines a cache hit by the secondary cache tag in response to the current access request cache missed by the primary cache memory unit, the secondary cache control unit Based on whether or not the primary cache state information in the tag is invalid, synonym processing is executed to delete the cache registration in the synonym state in the primary cache memory unit. When the secondary cache control unit determines a cache hit with the secondary cache tag, if the primary cache state information is valid, it executes synonym processing, and if it is invalid, it does not perform synonym processing. This will be specifically described below.

  FIG. 12 is a diagram showing the data request operation after cache injection according to the present embodiment. In cache injection, data is registered in the L2 cache, but not yet registered in the L1 cache. Therefore, in the data request after the cache injection in FIG. 12, the requested data D1 is not registered in the L1 cache and registered in the L2 cache.

  An L1 type code L1-TC is recorded in the L2 cache tag L2-TAG1 in FIG. Based on the information of the L1 type code L1-TC and the virtual address VA, the L2 cache pipeline determines the synonym state.

  FIG. 14 is a flowchart in the present embodiment. In contrast to the flowchart of FIG. 8, the flowchart of FIG. 14 shows that L1 in the L2 cache tag L2-TAG1 when the old virtual address OLD-VA and the new virtual address NEW-VA do not match (UNMATCH) in step S7. A step S29 for determining whether the type code L1-TC is in an invalid state (INVALID) or a valid state other than the invalid state (VALID) is added. In addition, the search for the L1 cache tag copy L1-TAG2 in step S13 always results in a hit, so there is no miss path. The rest is the same as FIG.

  Therefore, the L2 cache pipeline is inconsistent (UNMATCH) and valid depending on whether the virtual address coincidence is determined in step S7 and whether the L1 type code L1-TC is invalid in step S29. For example, the synonym processing of steps S12-S21 and S27-S28 is executed as in FIG. However, the L2 cache pipeline does not execute steps S12-S19 if the L1 type code L1-TC is invalid in step S29 even if the virtual address match determination in step S7 results in a mismatch (UNMATCH). Instead, steps S20-S21, S27-S28 are executed. Steps S20-S21 and S27-S28 are substantially the same as steps S8-S11. That is, the L2 cache pipeline can complete the processing by continuously executing the READ request input in step S5 if the L1 type code is invalid even if the old and new virtual addresses do not match. That is, it is not necessary to input the MOEX request and MIRD request to the L2 cache pipeline in steps S12 and S19 as in the flowchart of FIG.

[Fifth operation in data request after cache injection]
FIG. 15 is a sequence diagram showing the data request operation (fifth operation) after cache injection. The fifth operation of the data request after the cache injection shown in FIG. 14 will be described with reference to FIGS.

  First, a data request from the arithmetic control unit is issued for data D1 corresponding to physical addresses PA_I1 and PA_T1 accompanied by virtual address VA2 (S51, S1). In response to this, the L1 cache pipeline searches the L1 cache tag L1-TAG1 with the virtual address VA2 (S52, S2). The physical address PA_T1 output by the address translation unit TLB is the physical address read from the L1 cache tag L1-TAG1 because the tag has an unregistered physical address or an address different from the physical address of the data request And a cache miss (S52, S2).

  Therefore, the L1 cache issues a data request to the L2 cache (S53, S4), and the L2 cache issues a READ request from MIPORT to the L2 cache pipeline (S54, S5). The L2 cache pipeline searches the L2 cache tag L2-TAG1 with the physical address PA_I1 and detects a cache hit (S55, S6). At this time, the L2 cache pipeline compares the old virtual address PA_I1 in the L2 cache tag L2-TAG1 with the new virtual address VA2 of the current data request to detect a mismatch (UNMATCH) (S61, S7). Here, the address PA_I1 registered as the old virtual address in the L2 cache tag L2-TAG1 is the physical address PA_I1 at the time of the cache injection request.

  In this embodiment, the L2 cache pipeline further detects the invalid state (INVALID) by referring to the L1 type code L1-TC in the cache hit L2 cache tag L2-TAG1 (S29). As a result, the L2 cache pipeline updates the L1 type code L1-TC in the L2 cache tag L2-TAG1 to the valid state, updates the virtual address VA to the new virtual address VA2 (S20), and the L1 cache tag copy L1 -Register TAG2 with the L2 cache tag L2-TAG1 and register the registration information of the data that hit the cache (S21), respond to the L1 cache (S27), and register the data in the L1 cache. Furthermore, the L1 cache sends a data response to the CPU core (S28).

  As shown in FIG. 15, the L2 cache pipeline can register the data in the L2 cache in the L1 cache by processing the input READ request. The operation sequence of the fifth operation in FIG. 15 is almost the same as the operation sequence of the first operation in (1) of FIG. 3, and only a READ request is input to the L2 cache pipeline. Further, in the fifth operation sequence of FIG. 15, steps S12, S13, and S19 by inputting the MOEX request and MIRD request in the operation sequence of the fourth operation of FIG. 10 are omitted.

  As described above, in this embodiment, the L2 cache pipeline performs the determination S29 of whether or not the L1 type code L1-TC is invalid in addition to the comparison determination S7 of the old and new virtual addresses for the synonym hit determination. , It is possible to distinguish between a pseudo old and new virtual address mismatch state due to cache injection and a true new and old virtual address mismatch state.

[Missing at L1, hit at L2, VA mismatch, L1-TC valid, third action when hit at L1-TAG2 (Figure 13)]
Next, the third operation in the present embodiment in the true synonym state will be described. FIG. 13 is a diagram showing a third operation in the case of the present embodiment. In FIG. 14, the operations of steps S1-S7, S29, S12-S21, S27-S28 are performed.

  In FIG. 13, the process after the step (S5, S54) in which a READ request is input from the MIPORT to the L2 cache pipeline will be described. The L2 cache pipeline searches the L2 cache tag L2-TAG1 with the physical address PA_I1 and determines a cache hit (S6, S55). At that time, the L2 cache pipeline reads the old virtual address VA1 from the L2 cache tag L2-TAG1 and compares it with the new virtual address VA2 to detect a mismatch (UNMATCH) (S7, S61), and further, the L1 type code L1-TC And a valid state is detected (S29). As a result, the L2 cache pipeline executes steps S12-S21.

  The L2 cache pipeline searches the L1 cache tag copy L1-TAG2 with the old virtual address VA1, and obtains the way information in the L1 cache that stores the physical address PA_T1 that matches the physical address PA_T1 in the L2 cache tag L2-TAG1 To do. However, FIG. 13 does not show a plurality of ways. In the search by the old virtual address VA1 of the L1 cache tag copy L1-TAG2, the L1 type code L1-TC is in a valid state, so it always hits.

  After that, the L2 cache issues an order for deleting the L1 cache registration based on the L1 cache way information detected as the old virtual address VA1 to the L1 cache (S14), and deletes the L1 cache registration (S15, S63). In response to an order response from the L1 cache to the L2 cache (S16), the request input unit SEL inputs a write back request WRBK to the L2 cache pipeline (S17), and writes back to the L2 cache if necessary. The registration of the L1 cache tag copy L1-TAG2 is deleted (S18). Thereafter, steps S19-S21 and S27-S28 are executed.

  Therefore, in the operation sequence of the third operation in FIG. 9, the L2 cache pipeline determines whether or not the L1 type code L1-TC is in an invalid state in addition to the virtual address comparison determination (S7, S61). .

[Fourth operation when L1 misses, L2 hits, VA does not match, and L1-TC is invalid]
The fourth operation of FIG. 10 is executed in steps S1-S7, S29, S20-S21, and S27-S28 in FIG. 14 of the present embodiment. That is, in step S29, it is found that the L1 cache type code L1-TC is invalid, and it is found that the old virtual address VA1 is not registered in the L1 cache, so the old virtual address VA1 is not processed. In steps S20-S21 and S27-S28, registration processing for the new virtual address VA2 is executed. Therefore, the fourth operation is also simplified.

  In this embodiment, the L2 cache pipeline determines whether or not it is truly a synonym state by comparing the old and new virtual addresses and determining whether or not the L1 type code is invalid. If the L1 type code is in an invalid state, it means that no data is registered in the L1 cache. Therefore, in addition to the case where the L2 cache is registered by cache injection, it is registered in the L2 cache by some other request. However, it is possible to detect an unregistered state in the L1 cache. Even in that case, synonym processing can be avoided.

  FIG. 16 is a diagram illustrating a logic circuit that performs synonym determination of the L2 cache pipeline and VA update of L2-TAG1 in the present embodiment. (1) in FIG. 16 is a logic circuit corresponding to the flowchart in FIG. 8, and (2) in FIG. 16 is a logic circuit corresponding to the flowchart in FIG. 14 of the present embodiment.

  In the AND gate AND1 in (1) of FIG. 16, it is a READ request (S5), the physical address PA matches with the L2 cache tag L2-TAG1, and it is a cache hit (HIT of S6), and the old and new virtual The address mismatch (S7 UNMATCH) is a condition for the synonym hit determination. Further, the OR gate OR1 updates the virtual address VA of the L2 cache tag L2-TAG1 in the case of the MIRD request (S19) or the MVIN request (S24) (S20, S25).

  On the other hand, in AND gate AND2 of (2) of FIG. 16, it is a READ request (S5), physical address PA matches L2 cache tag L2-TAG1, and it is a cache hit (HIT of S6), old and new virtual In addition to the address mismatch (UNMATCH in S7), the L1 type code L1-TC is in a valid state (VALID) (VALID in S29) is a condition for the synonym hit determination. And in AND gate AND3, it is a READ request (S5), physical address PA matches in L2 cache tag L2-TAG1, and it is a cache hit (HIT in S6), and old and new virtual addresses do not match In addition to (UNMATCH of S7), the fact that the L1 type code L1-TC is invalid (INVALID) (INVALID of S29) is a condition for updating the virtual address VA of the L2 cache tag L2-TAG1 (S20) Become. The OR gate OR2 updates the virtual address VA of the L2 cache tag L2-TAG1 when the output of the AND gate AND3 is true (1) in addition to the MIRD request (S19) or MVIN request (S24). (S20, S25).

  FIG. 17 is a diagram showing specific examples of the L1 cache tag and the L2 cache tag in the present embodiment. FIG. 17 shows a configuration example of the L1 cache tag L1-TAG and the L2 cache tag L2-TAG1. As a premise, the address translation unit TLB has a translation unit of 4 Kbytes (12 bits). Therefore, the address translation unit TLB translates the virtual address VA [63:12] into the physical address PA [39:12]. The lower 12 bits of the virtual address and the physical address are common (VA [11: 0] = PA [11: 0]).

  The L1 cache tag L1-TAG stores VA [15: 7] as an index and the physical address PA [39:12] as tag information corresponding to each of the ways way0 and way1. Then, the physical address PA [39:12] is output from the address translation unit TLB and compared with the physical address PA [39:12] of the tag information. The translation unit of the address translation unit is different from the cache block unit of the L1 cache.

  On the other hand, since the L2 cache has a larger capacity than the L1 cache, the number of entries is also large. As a result, the L2 cache tag L2-TAG1 stores the physical address PA [39:20] for each way as tag information corresponding to PA [19: 7] as an index. The number of ways in the L2 cache is 24, which is larger than the number of ways in the L1 cache.

  FIG. 18 is a diagram showing a specific example of the data format of the L1 cache tag and the L2 cache tag in the present embodiment. L2 cache tag L2-TAG1 is error check / correction code ECC [6: 0], L1 type code L1-TC [2: 0], L2 type code L2-TC [1: 0], and L1 cache Stores the registered virtual address VA [15:12] and physical address PA [39:20]. The virtual address VA [15:12] has a smaller number of bits than the index of the L1 cache tag L1-TAG, but there is no problem because VA [11: 0] = PA [11: 0] as described above.

  In the L1 cache tag copy L1-TAG2, the two ways OPway0 and OPway1 of the data cache and the two ways IFway0 and IFway1 of the instruction cache are each composed of 20 bits, and the 20 bits are error check / correction code ECC [5 : 0], valid bit V, physical address PA [19:12], and way address WAY [4: 0]. Since the L2 cache is an inclusion cache of the L1 cache, the physical address PA [39:12] can be expressed by the physical address PA [19:12] and the way address WAY [4: 0].

  As described above, according to the present embodiment, the L1 type code L1-TC is stored in addition to the virtual address VA in the L2 cache tag L2-TAG1, and the data is registered in the L1 cache in the L1 type code L1-TC. Stores the invalid state (INVALID) indicating that there is no. In the data request after cache injection, when the L2 cache pipeline searches for and hits the L2 cache tag L2-TAG1, the comparison judgment of the old and new virtual addresses VA and whether the L1 type code L1-TC is invalid By determining whether or not, it is possible to distinguish whether the data is not registered in the L1 cache for a reason such as after cache injection or whether the data is registered in the L1 cache tag with the old virtual address VA. Thereby, in the data request after the cache injection, the synonym processing including the search for the L1 cache tag copy L1-TAG2 can be omitted.

  The above embodiment is summarized as follows.

(Appendix 1)
A primary cache memory unit having a primary cache tag and a primary cache data memory searched by a virtual address, and a primary cache control unit for performing cache control;
A secondary cache tag and a secondary cache data memory searched by a physical address, and a secondary cache control unit for performing cache control, wherein the secondary cache control unit detects that the primary cache memory unit has a cache miss If it is determined that the secondary cache tag is a cache hit in response to the generated access request, the cache in the synonym state in the primary cache memory unit based on the primary cache state information in the secondary cache tag And a secondary cache memory unit that executes a synonym process for deleting registration.

(Appendix 2)
In Appendix 1,
The secondary cache control unit responds to the primary cache memory unit with the cache hit data without executing the synonym processing when the primary cache status information in the secondary cache tag is invalid. An arithmetic processing unit that executes the synonym processing and responds to the cache hit data to the primary cache memory unit in a valid state.

(Appendix 3)
In Appendix 1 or 2,
The secondary cache tag stores an old virtual address of an access request when registering a cache in the secondary cache memory unit,
When the secondary cache control unit determines a cache hit with the secondary cache tag in response to the current access request, the new virtual address of the current access request is stored in the secondary cache tag. An arithmetic processing unit that executes the synonym processing based on whether or not the primary cache state information is invalid when the old virtual address does not match.

(Appendix 4)
In Appendix 3,
The secondary cache control unit pipelines the first request in response to a current access request cache missed in the primary cache memory unit, determines a cache hit based on a secondary cache tag, The comparison determination of the new virtual address and the old virtual address and the determination of the primary cache state information are executed, the cache hit determination is a cache hit, the comparison determination does not match, and the primary cache state information is invalid In this case, the arithmetic processing unit updates the old virtual address in the secondary cache tag to a new virtual address, updates the primary cache state information to a valid state, and makes a data response to the primary cache memory unit.

(Appendix 5)
In Appendix 4,
When the secondary cache control unit pipelines the first request, the cache hit determination based on the secondary cache tag is a cache hit, the comparison determination does not match, and the primary cache state information is An arithmetic processing unit that pipeline-processes the second request corresponding to the synonym processing in the valid state.

(Appendix 6)
In Appendix 4 or 5,
When the second cache control unit pipelines the first request, if the cache hit determination based on the secondary cache tag is a cache hit and the comparison determination is the same, the secondary cache tag An arithmetic processing unit that updates primary cache state information in the cache to a valid state and responds to the primary cache memory unit with data.

(Appendix 7)
In Appendix 5,
The secondary cache memory unit further includes a primary cache tag copy that is a copy of the primary cache tag,
The secondary cache control unit obtains registration information corresponding to the old virtual address by referring to the copy primary cache tag in the pipeline processing of the second request (MOEX) corresponding to the synonym processing. , An arithmetic processing unit for erasing the cache registration in the synonym state in the primary cache memory unit.

(Appendix 8)
In Appendix 1,
Furthermore, it has an input / output control unit,
And an address conversion unit that converts the virtual address of the access request into a physical address,
The primary cache control unit compares the physical address read from the primary cache tag based on the virtual address of the access request with the physical address converted by the address conversion unit, and if they match, the cache hit, An arithmetic processing unit that detects a cache miss when there is a mismatch.

(Appendix 9)
In Appendix 1,
The synonym state is an arithmetic processing unit including a state in which different virtual addresses are assigned to data of the same physical address in the primary cache memory unit.

(Appendix 10)
In Appendix 1,
The secondary cache control unit is an arithmetic processing unit that registers data in a secondary cache tag and a secondary cache data memory when data is transferred from the outside by the input / output control unit.

(Appendix 11)
A primary cache memory unit having a primary cache tag and a primary cache data memory searched by a virtual address, and a primary cache control unit for performing cache control;
A control method for an arithmetic processing unit having a secondary cache tag and a secondary cache data memory searched by a physical address, and a secondary cache memory unit having a secondary cache control unit for performing cache control,
The primary cache control unit generates a cache miss due to an access request,
In response to the access request in which the primary cache memory unit misses the cache, if the secondary cache control unit determines a cache hit in the secondary cache tag, the primary cache state in the secondary cache tag A control method for an arithmetic processing unit that executes a synonym process for deleting a cache registration in a synonym state in the primary cache memory unit based on information.

1: CPU, processing unit 10: CPU core, processing unit 12: processing unit, ALU
14: primary cache memory unit, L1 cache 16: primary cache pipeline, primary cache control unit, L1 cache pipeline
L1-TAG1: Primary cache tag, L1 cache tag
L1-DATA: primary cache data memory
TLB: address translation unit 20: secondary cache memory unit, L2 cache 22: secondary cache pipeline, secondary cache control unit, L2 cache pipeline 24: request lock unit
MIPORT: Move Import
MOPORT: Move-out port
SEL: Request input part, selector
L2-TAG1: Secondary cache tag, L2 cache tag
L2-DATA: Secondary cache data memory
L1-TAG2: Primary cache tag copy, L1 cache tag copy
I / O: I / O controller
MAC: Memory access controller 30: Main memory

Claims (4)

A primary cache memory unit having a primary cache tag and a primary cache data memory searched by a virtual address, and a primary cache control unit for performing cache control;
Has a secondary cache tag and a secondary cache data memory to be retrieved by the physical address, and a secondary cache memory for chromatic and secondary cache control pipeline circuit for performing cache control,
The secondary cache control pipeline circuit includes:
(A) When the first request (READ) is input to the secondary cache control pipeline circuit in response to an access request in which the primary cache memory unit has caused a cache miss ,
When the secondary cache tag determines that the cache hit,
(A1) performing a comparison determination between the new virtual address of the current access request and the old virtual address stored in the secondary cache tag, and determining the primary cache state information in the secondary cache tag ; A second synonym process for erasing a cache registration in the synonym state in the primary cache memory unit when the comparison determination is inconsistent and the primary cache state information is invalid ; Without inputting the request (MOEX) to the secondary cache control pipeline circuit, the old virtual address in the secondary cache tag is updated to the new virtual address, and the primary cache state information is made valid. Update the cache hit data to the primary cache memory unit,
(A2) When the comparison determination is inconsistent and the primary cache state information is valid, the second request (MOEX) is input to the secondary cache control pipeline circuit;
(B) When the second request (MOEX) is input to the secondary cache control pipeline circuit, synonym processing for erasing the cache registration in the synonym state in the primary cache memory unit is performed in the primary cache control. A processor that updates the old virtual address in the secondary cache tag to the new virtual address and responds the cache hit data to the primary cache memory unit . In claim 1,
And an address conversion unit that converts the virtual address of the access request into a physical address,
The primary cache control unit compares the physical address read from the primary cache tag based on the virtual address of the access request with the physical address converted by the address conversion unit, and if they match, the cache hit, An arithmetic processing unit that detects a cache miss when there is a mismatch. In claim 1,
Furthermore, it has an input / output control unit,
The secondary cache control pipeline circuit is an arithmetic processing unit that registers data in a secondary cache tag and a secondary cache data memory when data is transferred from the outside by the input / output control unit. A primary cache memory unit having a primary cache tag and a primary cache data memory searched by a virtual address, and a primary cache control unit for performing cache control;
A secondary cache tag and a secondary cache data memory to be retrieved by the physical address, a control method of a processing device having a secondary cache memory for chromatic and secondary cache control pipeline circuit for performing cache control ,
The secondary cache control pipeline circuit includes:
(A) When the first request (READ) is input to the secondary cache control pipeline circuit in response to an access request in which the primary cache memory unit has caused a cache miss ,
When the secondary cache tag determines that the cache hit,
(A1) performing a comparison determination between the new virtual address of the current access request and the old virtual address stored in the secondary cache tag, and determining the primary cache state information in the secondary cache tag ; A second synonym process for erasing a cache registration in the synonym state in the primary cache memory unit when the comparison determination is inconsistent and the primary cache state information is invalid ; Without inputting the request (MOEX) to the secondary cache control pipeline circuit, the old virtual address in the secondary cache tag is updated to the new virtual address, and the primary cache state information is made valid. Update the cache hit data to the primary cache memory unit,
(A2) When the comparison determination is inconsistent and the primary cache state information is valid, the second request (MOEX) is input to the secondary cache control pipeline circuit;
(B) When the second request (MOEX) is input to the secondary cache control pipeline circuit, synonym processing for erasing the cache registration in the synonym state in the primary cache memory unit is performed in the primary cache control. A control method of the arithmetic processing unit, wherein the control unit executes the processing , updates the old virtual address in the secondary cache tag to the new virtual address, and responds the cache hit data to the primary cache memory unit .

Images