JP6088951B2 - Cache memory system and processor system - Google Patents

Description

  Embodiments described herein relate generally to a cache memory system and a processor system using a nonvolatile memory.

  Since the cache memory has a higher access speed than the main memory and directly affects the processing capability of the processor, the increase in the capacity of the cache memory is expected to continue.

  When the capacity of the cache memory becomes large, the tag information for managing the data in the cache memory also becomes enormous, and it takes time to determine whether or not the data requested by the processor is in the cache memory. If this determination process takes time, access to the main memory also takes time, leading to a decrease in the processing capacity of the processor.

Special Table 2002-536715 gazette Japanese translation of PCT publication No. 2002-536716 JP-T-2002-536717

  The problem to be solved by the present invention is to provide a cache memory system and a processor system capable of improving access efficiency to a large-capacity cache memory.

In the present embodiment, a kth-order cache memory (all integers from k = 1 to n, where n is an integer equal to or greater than 1),
A large-capacity cache memory using a non-volatile memory having a memory capacity larger than that of the kth-order cache memory and capable of being accessed at a higher speed than the main memory;
Whether the data is stored in the large-capacity cache memory in units of pages with a larger amount of data than the address conversion information from the virtual address to the physical address issued by the processor and the cache line that is the access unit of the k-th cache memory A cache memory system is provided that includes flag information for recording whether or not, and a translation lookaside buffer for storing the flag information.

1 is a diagram showing a schematic configuration of a processor system 1 according to a first embodiment of the present invention. The figure which shows the access priority of TLB3, each cache memory 4-6, and the main memory 7 in 1st Embodiment. The figure which shows the internal structure of TLB3 in 1st Embodiment. The figure which shows the internal structure of TLB3 of a set associative structure. 6 is a flowchart illustrating a processing procedure when the CPU 2 according to the first embodiment issues a read request address. The block diagram which shows schematic structure of the processor system 1 which concerns on 2nd Embodiment. The figure which shows the access priority of TLB3, each cache memory 4-6, and the main memory 7 in 2nd Embodiment. The figure which shows the internal structure of TLB3 in 2nd Embodiment. 9 is a flowchart showing a processing procedure when the CPU 2 according to the second embodiment issues a read request address. The block diagram which shows schematic structure of the processor system 1 which concerns on 3rd Embodiment. The figure which shows the access priority of TLB3, the page table 10, each cache memory 4-6, and the main memory 7 in 3rd Embodiment. 10 is a flowchart showing a processing procedure when the CPU 2 according to the third embodiment issues a read request address. The block diagram which shows schematic structure of the processor system 1 which concerns on 4th Embodiment. The figure which shows the access priority of TLB3, each cache memory, and the main memory 7 in 4th Embodiment. 10 is a flowchart showing a processing procedure when the CPU 2 according to the fourth embodiment issues a read request address.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a schematic configuration of a processor system 1 according to the first embodiment of the present invention. A processor system 1 in FIG. 1 includes a processor (CPU) 2, a translation lookaside buffer (TLB) 3, a primary cache memory (L1 cache) 4, and a secondary cache memory (L2 cache). ) 5, a large-capacity cache memory (page mapping cache) 6, and a main memory 7.

  The processor 2, TLB 3, L1 cache 4, L2 cache 5, and page mapping cache 6 other than the main memory 7 are integrated on one chip 8, for example. TLB 3, L 1 cache 4, L 2 cache 5, and page mapping cache 6 correspond to memory system 9.

  The L1 cache 4 and the L2 cache 5 are configured by semiconductor memories (for example, SRAM) that can be accessed at a higher speed than the main memory 7. The page mapping cache 6 is configured by a nonvolatile memory (for example, MRAM) that can be accessed at a higher speed than the main memory 7 and has a larger memory capacity than the L1 cache 4 and the L2 cache 5. In the present specification, an example in which the page mapping cache 6 is configured by a low power consumption spin-injection magnetization switching MRAM (STT-MRAM) will be described.

  The TLB 3 is address conversion information from the virtual address to the physical address issued by the CPU 2 and a cache line that is an access unit of the next cache memory k (all integers from k = 1 to n, where n is an integer of 1 or more). And flag information for recording whether or not data is stored in the page mapping cache 6 in units of pages having a larger amount of data. Since the TLB 3 according to the present embodiment is accessed by the CPU 2 in preference to the L1 cache 4 and the L2 cache 5, the TLB 3 includes a high-speed memory (for example, SRAM).

  Since the main memory 7 has a memory capacity larger than any memory in the memory system 9, it is constituted by, for example, a DRAM using the outside of the chip 8 or a package stacking technique.

  FIG. 2 is a diagram showing access priorities of the TLB 3, the cache memories 4 to 6, and the main memory 7 in the first embodiment. As illustrated, the CPU 2 accesses the TLB 3, the L1 cache 4, the L2 cache 5, the page mapping cache 6, and the main memory 7 in this order. Data in the frequently accessed memory is also stored in the infrequently accessed memory. That is, the data in the L1 cache 4 is also stored in the L2 cache 5, the data in the L2 cache 5 is also stored in the page mapping cache 6, and the data in the page mapping cache 6 is also stored in the main memory 7. In this way, the memories 4 to 7 maintain a hierarchical relationship, and the TLB 3 holds address conversion information and the like for accessing these memories.

  In FIG. 2, the CPU 2 is configured by a flip-flop (F / F) or the like combining MOS transistors, the TLB 3, the L1 cache 4 and the L2 cache 5 are configured by SRAM, the page mapping cache 6 is configured by STT-MRAM, An example in which the main memory 7 is constituted by a DRAM is shown.

  FIG. 3 is a diagram showing an internal configuration of the TLB 3 in the first embodiment. The TLB 3 in FIG. 3 includes, in page units, Valid information, Dirty information, virtual address information (VPN: Virtual Page Number), physical address information (PPN: Physical Page Number), flag information (Flag), and cache address information (CPN). : Cache Page Number).

  The address from which the CPU 2 makes a read request is a virtual address, and this virtual address includes virtual address information VPN and a page offset as shown in FIG. The TLB 3 converts the virtual address from the CPU 2 into a physical address. As shown in FIG. 3, the converted physical address includes physical address information PPN and a page offset. The page offset in the physical address is the same as the page offset in the virtual address requested by the CPU 2.

  As shown in FIG. 3, cache address information is stored in the TLB 3, and the TLB 3 accesses the page mapping cache 6 using this cache address information. The cache address information includes a cache page number CPN and a page offset as shown in FIG. The page offset in the cache address is the same as the page offset in the virtual address requested by the CPU 2.

  As shown in FIG. 3, if the cache address information is included in the TLB 3, the page mapping cache 6 can be accessed with the cache address information, so that the access efficiency is improved, but the memory capacity of the page mapping cache 6 ( As the number of page entries) increases, the cache address information to be stored in the TLB 3 increases, and the TLB 3 increases in capacity and takes longer to search. Therefore, when the memory capacity of the page mapping cache 6 is large, the cache address information may be deleted from the TLB 3 to reduce the information amount of the TLB 3. However, in this case, since the page mapping cache 6 must be accessed using the physical address of the TLB 3, access takes longer than when the TLB 3 includes cache address information.

  When the task (process) of the operating system (OS) executed by the CPU 2 is switched, it is necessary to rewrite (flash) the information in the TLB 3. This is because the correspondence between the virtual address and the physical address is different for each task, and the physical address is different even for the same virtual address. For this reason, when the task is switched, all page entries of the TLB 3 need to be invalidated. If the size of the TLB 3 is small, it is not a big problem, but if the size of the TLB 3 is large, it takes a long time to update the TLB 3, so that the processing delay of the CPU 2 occurs. In order to eliminate such a processing delay, an address space ID (ASID) for identifying the virtual space of each task is provided, and if the page information is stored for each address space ID in the TLB 3 in advance, the task is switched. There is no need to flush TLB3 every time.

  Further, when the capacity of the page mapping cache 6 is increased, the number of entries in the TLB 3 is also increased, so that a search delay of the TLB 3 occurs. Therefore, when the number of TLB3 entries is large, the TLB3 has a plurality of hierarchical structures, or has a set associative configuration in which some bits (for example, the lower 10 bits) of the virtual address information VPN are used as indexes, and the TLB3 search delay It is desirable to reduce

  FIG. 4 is a diagram illustrating an internal configuration of the TLB 3 having a set associative configuration. The TLB 3 in FIG. 4 has a plurality of ways by using some bits of the virtual address information VPN as an index. Some bits (for example, lower 10 bits) of the virtual address information VPN used as the set associative index are duplicated in the same set, but the remaining bits of the virtual address information VPN are different for each way. Therefore, the physical address information PPN output from the TLB 3 is different.

  In the TLB 3 in FIG. 4, the CPU 2 selects a set in the TLB 3 based on a part of the virtual address requested to be read, and the remaining part of the virtual address is the virtual address information VPN held by each way in the selected set. If they match, the corresponding physical address information PPN is output.

  FIG. 5 is a flowchart showing a processing procedure when the CPU 2 according to the first embodiment issues a read request address. First, it is determined whether or not the read request address issued by the CPU 2 hits the virtual address information VPN in the TLB 3 (step S1). If there is no hit, the address translation information is loaded from a page table entry (PTE) (not shown) in the main memory 7 and the information in the TLB 3 is updated (step S2). These processes in steps S1 and S2 correspond to the first process.

  If it is determined in step S1 that a hit has occurred, or if the processing in step S2 is completed, it is determined whether or not the read request address issued by the CPU 2 hits the tag information in the L1 cache 4 (step S3). If there is a hit, the corresponding data stored in the L1 cache 4 is read out and transferred to the CPU 2, and the processing of FIG. 5 is terminated (step S4). If the index of the L1 cache 4 is composed of addresses in the page, it is possible to access the tag memory of the L1 cache 4 speculatively at the same time as the first processing. The determination must be after the end of the first process.

  If it is determined in step S3 that there is no hit, it is determined whether or not the read request address issued by the CPU 2 hits the tag information in the L2 cache 5 (step S5). If there is a hit, the data stored in the L2 cache 5 is read out and transferred to the CPU 2, and the process of FIG. 5 is terminated (step S6). These processes in steps S3 to S6 correspond to the second process.

  If it is determined in step S5 that no hit has occurred, it is determined based on the flag information held in the TLB 3 whether or not the data corresponding to the read request address issued by the CPU 2 is stored in the page mapping cache 6 (step S7). ). If it is stored, the data for the page corresponding to this address is read from the page mapping cache 6 and transferred to the CPU 2, and the data for the cache line corresponding to this address is transferred to the L1 cache 4 and L2 cache 5. (Step S8). The processes in steps S7 and S8 correspond to the third process.

  If it is determined in step S7 that the data is not stored, the data corresponding to the read request address issued by the CPU 2 is read from the main memory 7 and transferred to the CPU 2, and the data for the page corresponding to this address is transferred to the page mapping cache. 6 and the data for the cache line corresponding to this address is transferred to the L1 cache 4 and the L2 cache 5, and the TLB 3 is updated (step S9). The process in step S9 corresponds to the fourth process.

  As described above, in the first embodiment, the page mapping cache 6 having a larger capacity than the L1 cache 4 and the L2 cache 5 and capable of being accessed faster than the main memory 7 is provided. Information is stored in the existing TLB 3 in units of pages. By storing tag information in the TLB 3 in page units, the amount of information can be reduced compared to storing tag information in cache line units as in the L1 cache 4 and L2 cache 5, and a dedicated tag memory is provided in the page mapping cache 6. There is no need to provide it. That is, according to the present embodiment, tag information of the large-capacity and high-speed page mapping cache 6 can be stored in the existing TLB 3.

  In this embodiment, since the L1 cache 4 and the L2 cache 5 are accessed in preference to the page mapping cache 6, the L1 cache 4 and the L2 cache 5 can be accessed quickly. Furthermore, since data that cannot be stored in the L1 cache 4 and the L2 cache 5 is stored in the large-capacity and high-speed page mapping cache 6, data can be read / written faster than accessing the main memory 7.

  In the present embodiment, since the TLB 3 has cache address information for the page mapping cache 6, when the L2 cache 5 is not hit, the cache address information is used to quickly retrieve the page mapping cache 6. Desired data can be read out.

(Second Embodiment)
In the second embodiment described below, access to the L2 cache 5 and the page mapping cache 6 is parallelized.

  In the present embodiment, when the access latency of the page mapping cache 6 is as high as that of the L2 cache 5, or when the memory capacity of the page mapping cache 6 is several times to several tens of times the memory capacity of the L2 cache 5. It is particularly effective.

  The page mapping cache 6 and the L2 cache 5 store data of different physical addresses. That is, the page mapping cache 6 and the L2 cache 5 store data exclusively from each other.

  The page mapping cache 6 of the present embodiment stores data that frequently occurs throughout the page. On the other hand, the L2 cache 5 stores data of this line when access frequently occurs only for a specific line in the page.

  As described above, in this embodiment, in one page, the page mapping cache 6 or the L2 cache 5 is dynamically switched to store data.

  FIG. 6 is a block diagram showing a schematic configuration of the processor system 1 according to the second embodiment. The processor system 1 in FIG. 6 is different from that in FIG. 1 in that the CPU 2 accesses the L2 cache 5 and the page mapping cache 6 in parallel.

  FIG. 7 is a diagram showing access priorities of the TLB 3, the cache memories 4 to 6, and the main memory 7 in the second embodiment. As shown in the figure, the CPU 2 accesses the TLB 3 and the L1 cache 4 in this order. After the L1 cache 4, the CPU 2 accesses the L2 cache 5 and the page mapping cache 6 in parallel, and then accesses the main memory 7.

  FIG. 8 is a diagram showing an internal configuration of the TLB 3 in the second embodiment. The TLB 3 in FIG. 8 has an access map for each page in addition to the configuration of the TLB 3 in FIG. The access map has, for example, bits for all lines in the page for each page. When data is stored in the L2 cache 5, the bit of the corresponding line is set to 1, for example. Then, when the number of bits that are 1 out of all bits for one page in the access map exceeds a predetermined threshold, the page is stored in the page mapping cache 6 and L2 Corresponding data in the cache 5 is invalidated.

  The TLB 3 in FIG. 8 has cache address information for accessing the page mapping cache 6 in the same manner as the TLB 3 in FIG. 2, but this cache address information is not always essential. If the number of entries in the page mapping cache 6 is large, the TLB 3 may be set associative. Further, when the data is stored in the L2 cache 5, the cache address information is not required. On the contrary, when the data is stored in the page mapping cache 6, the access map is not required. The up bit and the cache address information bit can be shared, and the capacity of the TLB 3 can be saved.

  FIG. 9 is a flowchart showing a processing procedure when the CPU 2 according to the second embodiment issues a read request address. Steps S11 to S14 are the same as steps S1 to S4 in FIG. If it is determined in step S13 that the L1 cache 4 has not been hit, whether or not the data corresponding to the read request address is stored in the page mapping cache 6 is determined based on the flag information held in the TLB 3 (step S15). ). If it is stored, the data for the page corresponding to this address is read from the page mapping cache 6 and transferred to the CPU 2, and the data for the cache line corresponding to this address is transferred to the L1 cache 4 (step S16). ). The processes in steps S11 and S12 correspond to the first process. The processes of steps S13 and S14 correspond to the second process. The processes of steps S15 and S16 correspond to the third process.

  If it is determined that it is not stored in step S15, it is determined whether or not the read request address issued by the CPU 2 hits the tag information in the L2 cache 5 (step S17). If there is a hit, the data stored in the L2 cache 5 is read and transferred to the CPU 2 (step S18). The processing in steps S17 and S18 corresponds to the fourth processing. In step S15, since necessary information is read from the TLB 3 in advance when the TLB 3 is accessed in step S11, the access timing to the L2 cache 5 is delayed compared to a memory system that does not have the page mapping cache 6. There is nothing.

  If it is determined in step S17 that there is no hit, the data corresponding to the read request address issued by the CPU 2 is read from the main memory 7 and transferred to the CPU 2, and the data for the page corresponding to this address is transferred to the page mapping cache 6 And data for the cache line corresponding to this address is transferred to the L1 cache 4 and the L2 cache 5 (step S19). The process in step S19 corresponds to the fifth process.

  Next, the corresponding page of the access map in the TLB 3 is checked (step S20). That is, when the data read from the main memory 7 is written in the L2 cache 5 and the access map in the TLB 3 is updated, whether or not the number of bits of the corresponding page in the access map becomes 1 exceeds the threshold value. Check (steps S20 and S21).

  If it is determined that the threshold value is exceeded, the data of all lines in the corresponding page is transferred from the L2 cache 5 and the main memory 7 to the page mapping cache 6, and the data in the L2 cache 5 of all lines in the corresponding page is invalidated. , TLB3 is updated. At this time, the data evicted in the page mapping cache 6 is written back to the main memory 7 as necessary. Further, the data corresponding to the read request address issued by the CPU 2 is transferred to the L1 cache 4 (step S22). The processes in steps S20 to S22 correspond to the sixth process.

  If it is determined in step S20 that it has not exceeded, the data corresponding to the read request address issued by the CPU 2 is transferred to the L1 cache 4 and the L2 cache 5 (step S23). The process in step S23 corresponds to the seventh process.

  As described above, in the second embodiment, since the access to the L2 cache 5 and the page mapping cache 6 is performed in parallel, access frequently occurs over the entire corresponding page or a specific page in the corresponding page is specified. Whether the data is stored in the L2 cache 5 or the page mapping cache 6 can be switched depending on whether access concentrates on the line. Therefore, the L2 cache 5 and the page mapping cache 6 can be used efficiently.

(Third embodiment)
In the third embodiment described below, a page table is provided separately from the TLB 3. When the number of entries in the page mapping cache 6 increases, there is a possibility that address translation information, flag information, etc. relating to all entries cannot be stored in the TLB 3. Therefore, in the present embodiment, information that could not fit in the TLB 3 is stored in the page table.

  FIG. 10 is a block diagram showing a schematic configuration of the processor system 1 according to the third embodiment. In the processor system 1 of FIG. 10, a page table 10 is newly arranged between the L2 cache 5 and the page mapping cache 6 as compared with FIG. The page table 10 stores address conversion information, flag information, etc. that could not be stored in the TLB 3. Therefore, the page table 10 basically has the same internal configuration as the TLB 3. Similar to the page mapping cache 6, the page table 10 is configured by a memory (for example, MRAM) that can be accessed at a higher speed than the main memory 7.

  FIG. 11 is a diagram showing access priorities of the TLB 3, the page table 10, the cache memories 4 to 6 and the main memory 7 in the third embodiment. As illustrated, the CPU 2 accesses the TLB 3, the L1 cache 4, the L2 cache 5, the page table 10, the page mapping cache 6, and the main memory 7 in this order.

  When the read request address of the CPU 2 does not hit the TLB 3, the page table 10 is searched before accessing the main memory 7. If the page table 10 is hit, the address conversion is performed without accessing the main memory 7. When the information can be loaded and there is no corresponding data in the L1 cache 4 and the L2 cache 5, the corresponding data is retrieved from the page mapping cache 6. Thereby, the access frequency to the main memory 7 can be reduced.

  As described above, the page table 10 basically has the same internal configuration as that of the TLB 3 and desirably has cache address information for directly accessing the page mapping cache 6. Further, when the number of entries in the page mapping cache 6 is large, it is desirable that the page table 10 has a set associative configuration. In addition, when the task executed by the CPU 2 is switched, an address space ID (ASID) is assigned to each task to manage address conversion information so that the entire page table 10 need not be invalidated and updated. Also good.

  FIG. 12 is a flowchart showing a processing procedure when the CPU 2 according to the third embodiment issues a read request address. Steps S31 to S36 are the same as steps S1 to S6 in FIG. Steps S31 and S32 correspond to the first process. Steps S33 to S36 correspond to the second process.

  If it is determined in step S35 that the L2 cache 5 has been missed, it is determined whether or not the read request address of the CPU 2 has hit the page table 10 (step S37). If it is determined that there is a hit, the corresponding data is read from the page mapping cache 6 and transferred to the CPU 2, and the data for the cache line corresponding to the read request address is transferred to the L1 cache 4 and the L2 cache 5 (step S38). ). Steps S37 and S38 correspond to the third process.

  If it is determined in step S37 that a miss has occurred, the data corresponding to the read request address issued by the CPU 2 is read from the main memory 7 and transferred to the CPU 2, and the data for the page corresponding to this address is stored in the page mapping cache 6. The data for the cache line corresponding to this address is transferred to the L1 cache 4 and the L2 cache 5, and the TLB 3 and the page table 10 are updated (step S39). Step S39 corresponds to the fourth process.

  As described above, in the third embodiment, since the page table 10 is provided separately from the TLB 3, even if the number of entries in the page mapping cache 6 increases and the address translation information cannot be stored in the TLB 3, the page table 10, and the capacity of the page mapping cache 6 can be increased.

(Fourth embodiment)
In the first to third embodiments described above, the CPU 2 first accesses the TLB 3 and then accesses each of the cache memories 4 to 6 and the main memory 7 in order. For this reason, when the capacity of the TLB 3 is increased, it takes time to search in the TLB 3, and the L1 cache 4 cannot be quickly accessed. Therefore, in the following fourth embodiment, the CPU 2 accesses the L1 cache 4 before the TLB 3.

  FIG. 13 is a block diagram showing a schematic configuration of the processor system 1 according to the fourth embodiment, and FIG. 14 is a diagram showing access priorities of the TLB 3, each cache memory, and the main memory 7 in the fourth embodiment. In the present embodiment, the L1 cache 4 and the TLB 3 are interchanged as compared with FIGS.

  When the CPU 2 issues a read request address, it first accesses the L1 cache 4. The L1 cache 4 in FIG. 13 can be directly accessed with a read request address composed of a virtual address issued by the CPU 2. When the L1 cache 4 misses, the CPU 2 accesses the TLB 3.

  When accessing the L1 cache 4 with a virtual address as in this embodiment, when the CPU 2 switches tasks, the entire L1 cache 4 must be invalidated (flushed). However, since the data stored in the L1 cache 4 is stored in either the L2 cache 5 or the page mapping cache 6, there is almost no need to access the main memory 7, and the address space is switched at high speed. be able to.

  FIG. 15 is a flowchart showing a processing procedure when the CPU 2 according to the fourth embodiment issues a read request address. The flowchart in FIG. 15 has a configuration in which the determination processes in steps S11 and S13 in FIG. 9 are interchanged as compared with the flowchart in FIG. That is, it is determined whether or not the read request address issued by the CPU 2 hits the L1 cache 4 (step S41). If it hits, the data read from the L1 cache 4 is transferred to the CPU 2 (step S42). If there is no hit, it is determined whether or not the read request address issued by the CPU 2 hits the TLB 3 (step S43). If there is no hit, the address conversion information is loaded from the page table entry in the main memory 7 and the TLB 3 is loaded. The data inside is updated (step S44). Steps S41 and S42 correspond to the first process. Steps S43 and S44 correspond to the second process.

  If it is determined that the data is stored in step S43, or if the process in step S44 ends, the TLB 3 determines whether data corresponding to the read request address issued by the CPU 2 is stored in the page mapping cache 6. A determination is made based on the held flag information (step S45). Thereafter, the same processing as that after step S17 in FIG. 9 is performed (steps S46 to S53). Steps S45 and S46 correspond to the third process. Steps S47 and S48 correspond to the fourth process. Step S49 corresponds to the fifth process. Steps S50 to S52 correspond to the sixth process. Step S53 corresponds to the seventh process.

  Also in this embodiment, an address space identification ID (ASID) may be provided in the TLB 3 to manage address conversion information and the like for each task.

  FIG. 13 shows an example in which the L2 cache 5 and the page mapping cache 6 are parallelized. However, when the L2 cache 5 and the page mapping cache 6 are not paralleled as shown in FIG. 1 and FIG. 4 and TLB3 access order may be interchanged.

  As described above, in the fourth embodiment, since the L1 cache 4 is accessed before the TLB 3, the L1 cache 4 can be quickly accessed even when the TLB 3 has a large capacity and takes time to access the TLB 3. .

  Note that not only the L1 cache 4 but also the L2 cache 5 may be accessed before the TLB 3.

  In the embodiment described above, an example in which the L1 cache 4 and the L2 cache 5 that are two-level cache memories are provided has been described, but a cache memory having three or more levels may be provided. k (all integers from k = 1 to n, where n is an integer equal to or greater than 1) When the next cache memory is provided, the process of FIG. 5 accesses the page mapping cache 6 when all the cache memories miss. Will do. In the process of FIG. 9, after a miss in step S <b> 15, if a miss occurs in all higher-order cache memories higher than the L2 cache 5, the processes after step S <b> 19 are performed. In the process of FIG. 12, the process of step S37 is performed after making a miss in all the cache memories. In the process of FIG. 15, after a miss in step S <b> 45, if all of the higher-order cache memories higher than the L2 cache 5 miss, the process from step S <b> 49 is performed.

  In each of the embodiments described above, an example in which the memory cell of the L2 cache 57 is an MRAM cell has been described. However, other nonvolatile memories (for example, a ReRAM memory cell, a phase change RAM (PRAM or PCM) memory cell, a NAND flash memory cell) ). In each embodiment described above, part or all of the memory control circuit 1 may be built in the L1 cache 46 or the L2 cache 57. Furthermore, in each of the above-described embodiments, when the power to a specific memory is shut off, the power can be shut down among the n-order cache memory and the main memory 78 other than the specific memory (n is an integer of 2 or more). A part or all of the memory may be blocked at once. Alternatively, the power-off timing may be individually controlled for each of the non-volatile cache memories including the specific memory.

  At least a part of the processor system 1 described in the above-described embodiment may be configured by hardware or software. When configured by software, a program for realizing at least a part of the functions of the processor system 1 may be stored in a recording medium such as a flexible disk or a CD-ROM, and read and executed by a computer. The recording medium is not limited to a removable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory.

  Further, a program for realizing at least a part of the functions of the processor system 1 may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be distributed in a state where the program is encrypted, modulated or compressed, and stored in a recording medium via a wired line such as the Internet or a wireless line.

  The aspect of the present invention is not limited to the individual embodiments described above, and includes various modifications that can be conceived by those skilled in the art, and the effects of the present invention are not limited to the contents described above. That is, various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

  1 processor system, 2 CPU, 3 TLB, 4 L1 cache, 5 L2 cache, 6 page mapping cache, 7 main memory, 9 memory system, 10 page table

Claims (18)

a k-th order cache memory (all integers from k = 1 to n, where n is an integer of 1 or more);
A large-capacity cache memory using a non-volatile memory having a memory capacity larger than that of the kth-order cache memory and capable of being accessed at a higher speed than the main memory;
Whether the data is stored in the large-capacity cache memory in units of pages with a larger amount of data than the address conversion information from the virtual address to the physical address issued by the processor and the cache line that is the access unit of the k-th cache memory A cache memory system comprising: flag information for recording whether or not; and a translation lookaside buffer for storing the flag information.   The cache memory system according to claim 1, wherein the translation lookaside buffer is accessed by a processor prior to the k-th order cache memory.   The cache memory system according to claim 2, wherein the k-th cache memory is accessed by a processor in preference to the large-capacity cache memory.   The cache memory system according to claim 2 or 3, wherein the large-capacity cache memory stores all data stored in the kth-order cache memory.   The cache memory system according to claim 1, wherein the translation lookaside buffer is accessed by a processor next to a primary cache memory in the k-th cache memory.   The cache memory system according to claim 5, wherein the large-capacity cache memory stores all data stored in all cache memories other than the primary cache memory in the k-th cache memory. The specific cache memory higher than the primary cache memory in the k-th cache memory and the large-capacity cache memory are accessed in parallel by the processor,
The cache memory system according to claim 1 or 2, wherein the specific cache memory and the large-capacity cache memory store data corresponding to different addresses.   The said translation lookaside buffer has an access map which stores the information which shows whether the data are stored in the said specific cache memory for every cache line in each page per page. Cache memory system.   9. The cache memory system according to claim 1, wherein the translation lookaside buffer stores address information for accessing the large-capacity cache memory in units of pages.   The cache memory according to claim 1, wherein the translation lookaside buffer has dirty information indicating whether data in the large-capacity cache memory is written back to the main memory in units of pages. system.   11. The cache memory system according to claim 1, wherein the translation lookaside buffer has a set associative configuration using a part of bits of a virtual address as an index.   12. The cache according to claim 1, further comprising a page table storing address translation information and flag information that could not be stored in the translation lookaside buffer and capable of being accessed faster than the main memory. Memory system. The page table is accessed by the processor after accessing the k th cache memory;
The cache memory system according to claim 12, wherein the large-capacity cache memory is accessed after access to the page table by a processor. A processor;
Main memory,
a k-th order cache memory (all integers from k = 1 to n, where n is an integer of 1 or more);
A large-capacity cache memory using a non-volatile memory having a memory capacity larger than that of the kth-order cache memory and capable of being accessed at a higher speed than the main memory;
Data is stored in the large-capacity cache memory in units of pages with a larger amount of data than the address conversion information from the virtual address to the physical address issued by the processor and the cache line that is the access unit of the k-th cache memory. A processor system comprising flag information for recording whether or not there is a translation lookaside buffer for storing the flag information. The processor is
It is determined whether or not a read request address has hit the translation lookaside buffer. If not, the address translation information related to the read request address is loaded from the main memory and the translation lookaside buffer is loaded. A first process for updating the buffer;
After the first processing, it is examined in order from the low-order cache memory whether the data corresponding to the read request address is stored in the k-th order cache memory, and if stored, the stored data is A second process of reading;
If the data corresponding to the read request address is not stored in any of the k-th cache memories, it is determined whether the data corresponding to the read request address is stored in the large-capacity cache memory. If the determination is made based on the flag information held by the look-aside buffer and stored in the large-capacity cache memory, the data corresponding to the read request address is read from the large-capacity cache memory, and the read request A third process of storing data for a cache line corresponding to an address in the k-th cache memory;
If there is no hit in the third process, the data corresponding to the read request address is read from the main memory, the page unit data corresponding to the read request address is stored in the large-capacity cache memory, and the read And a fourth process of storing data for a cache line corresponding to a request address in the k-th cache memory and updating the translation lookaside buffer based on the read request address. 14. The processor system according to 14. The specific cache memory higher than the primary cache memory in the k-th cache memory and the large-capacity cache memory are accessed in parallel by the processor,
The translation lookaside buffer has an access map for storing information indicating whether data is stored in the specific cache memory for each cache line in each page in units of pages,
The processor is
It is determined whether or not a read request address has hit the translation lookaside buffer. If not, the address translation information related to the read request address is loaded from the main memory and the translation lookaside buffer is loaded. A first process for updating the buffer;
After the first processing, it is checked whether data corresponding to the read request address is stored in the primary cache memory in the k-th cache memory, and if stored, the stored data is A second process of reading;
If it is determined in the second process that the data is not stored in the primary cache memory, it is determined whether the data corresponding to the read request address is stored in the large-capacity cache memory. Determine based on the flag information held in the buffer, and if stored in the large-capacity cache memory, read data corresponding to the read request address from the large-capacity cache memory and correspond to the read request address A third process of storing data for the cache line to be stored in the primary cache memory;
If it is determined in the third process that the translation lookaside buffer has not been hit, does the read request address hit a secondary or higher order cache memory in the kth order cache memory? A fourth process for reading out data corresponding to the read request address from the higher-level cache memory if it is determined in order, and if hit,
A fifth process of reading data corresponding to the read request address from the main memory when it is determined in the fourth process that the data is not stored in the higher-order cache memory;
With reference to a page corresponding to the read request address of the access map in the translation lookaside buffer, when the number of data stored in the specific cache memory exceeds a predetermined threshold, All the data of the corresponding page is stored in the large-capacity cache memory, the data in the specific cache memory is invalidated, and the data for the cache line corresponding to the read request address is read from the main memory and the 1 A sixth process of storing in the next cache memory and updating the translation lookaside buffer;
If it is determined in the sixth process that the predetermined threshold is not exceeded, a seventh process of reading data for the cache line corresponding to the read request address from the main memory and storing it in the specific cache memory; 15. The processor system according to claim 14, wherein the processor system is executed. A page table that stores address translation information and flag information that could not be stored in the translation lookaside buffer, and that can be accessed faster than the main memory,
The processor is
It is determined whether or not a read request address has hit the translation lookaside buffer. If not, the address translation information related to the read request address is loaded from the main memory and the translation lookaside buffer is loaded. A first process for updating the buffer;
After the first processing, it is examined in order from the low-order cache memory whether the data corresponding to the read request address is stored in the k-th order cache memory, and if stored, the stored data is A second process of reading;
If the data corresponding to the read request address is not stored in any of the k-th cache memories, it is determined whether or not the read request address hits the page table. A third process of reading data corresponding to the read request address from a cache memory and storing data for a cache line corresponding to the read request address in the primary cache memory and the secondary cache memory;
If there is no hit in the third process, the data corresponding to the read request address is read from the main memory, the page unit data corresponding to the read request address is stored in the large-capacity cache memory, and the read A fourth process of storing data for a cache line corresponding to a request address in the k-th cache memory and updating the translation lookaside buffer and the page table based on the read request address; 15. The processor system according to claim 14, which is executed. The specific cache memory higher than the primary cache memory in the k-th cache memory and the large-capacity cache memory are accessed in parallel by the processor,
The translation lookaside buffer has an access map for storing information indicating whether data is stored in the specific cache memory for each cache line in each page in units of pages,
The processor is
Checking whether data corresponding to the read request address is stored in a primary cache memory in the k-th cache memory, and if stored, a first process of reading the stored data;
If the data corresponding to the read request address is not stored in the primary cache memory, it is determined whether or not the read request address hits the translation lookaside buffer. A second process of loading address translation information relating to the read request address from main memory and updating the translation lookaside buffer;
After the end of the second process, it is determined based on the flag information held by the translation lookaside buffer whether data corresponding to the read request address is stored in the large-capacity cache memory, If stored in the large-capacity cache memory, data corresponding to the read request address is read from the large-capacity cache memory, and data in units of cache lines corresponding to the read request address is read to the primary cache memory. A third process to store;
If it is determined in the third process that the address is not stored in the translation lookaside buffer, the read request address is stored in a higher-order cache memory than the first-order cache in the k-th order cache memory. Whether or not to hit, in order, and if hit, a fourth process of reading data corresponding to the read request address from the higher-order cache memory;
A fifth process of reading data corresponding to the read request address from the main memory when it is determined in the fourth process that the data is not stored in the higher-order cache memory;
With reference to a page corresponding to the read request address of the access map in the translation lookaside buffer, when the number of data stored in the specific cache memory exceeds a predetermined threshold, All the data of the corresponding page is stored in the large-capacity cache memory, the data in the specific cache memory is invalidated, and the data for the cache line corresponding to the read request address is stored in the primary cache memory And a sixth process for updating the translation lookaside buffer;
7. The seventh process of storing data for a cache line corresponding to the read request address in the k-th cache memory when it is determined in the sixth process that the predetermined threshold is not exceeded. 14. The processor system according to 14.

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