JP2019164411A - Management device, information processing device, management method, and program - Google Patents

Abstract

To provide information used for the allocation of data for a plurality of kinds of memory.SOLUTION: A management device 18 manages accesses to a plurality of kinds of storage units 14 by a processing circuit 12. The storage unit 14 includes a plurality of first regions, and the first region includes a plurality of second regions. The management device 18 includes a management unit 22. The management unit 22 manages a management table 30A. The management table 30A is a table associating identification information of the first region with access management information specifying access information indicating whether or not the processing circuit 12 has already accessed the second region for each of the plurality of second regions included in the first region.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a management apparatus, an information processing apparatus, a management method, and a program.

  Various storage class memories (SCM) such as MRAM (Magnetic Resistive Random Access Memory), ReRAM (Resistive RAM), and PCM (Phase-Change Memory) have been developed. SCM has a slower access speed than DRAM (Dynamic Random Access Memory), but has a high degree of integration. On the other hand, DRAM is less integrated than SCM but has a high access speed. For this reason, in the case of a system equipped with a plurality of types of memories, it is necessary to use these memories separately.

  However, conventionally, since it is assumed that only DRAM is used as the main memory, information used for data allocation to a plurality of types of memories has not been managed. For example, a method is disclosed in which information indicating whether access has been made is recorded in a page table in units of pages. However, conventionally, it has not been managed which area in the page has been accessed, and it has been difficult to determine the allocation of data to a plurality of types of memory using information that has been conventionally managed.

Computer Organization and Design RISC-V Edition, David A. Patterson & John L. Hennessy, Morgan Kaufmann Publishers, ISBN 978-0-12-812275-4, 5.7 Virtual Memory.

  The problem to be solved by the present invention is to provide a management device, an information processing device, a management method, and a program capable of providing information used for data allocation to a plurality of types of memories.

  The management apparatus according to the embodiment manages access to a plurality of types of storage units by a processing circuit. The storage unit includes a plurality of first areas, and the first area includes a plurality of second areas. The management device includes a management unit that manages a management table. The management table indicates whether the second area has been accessed by the processing circuit for each of the identification information of the first area and each of the plurality of second areas included in the first area. Corresponds to the access management information that defines the information.

1 is a schematic diagram of an information processing apparatus. The schematic diagram which shows physical address space. The schematic diagram which shows the data structure of a management table. The flowchart of the procedure of information processing. The schematic diagram which shows the data structure of a management table. 1 is a schematic diagram of an information processing apparatus. 1 is a schematic diagram of an information processing apparatus.

  Details of the present embodiment will be described below with reference to the accompanying drawings.

  FIG. 1 is a schematic diagram illustrating an example of the configuration of the information processing apparatus 10 according to the present embodiment. The information processing apparatus 10 includes a processing circuit 12, a management apparatus 18, a cache memory 16, and a storage unit 14.

  The processing circuit 12 and the cache memory 16, the processing circuit 12 and the management device 18, the cache memory 16 and the management device 18, and the management device 18 and the storage unit 14 are connected so as to be able to exchange data and signals.

  The processing circuit 12 has one or more processors. The processor is, for example, a CPU (Central Processing Unit). The processor may include one or more CPU cores. The processing circuit 12 reads data from the storage unit 14 and writes data to the storage unit 14 in accordance with execution of the program.

  The processing circuit 12 and the management device 18 to be described later temporarily store data stored in the storage unit 14 in the cache memory 16 and use it for processing.

  The storage unit 14 is a main memory used as a work area by the processing circuit 12. The information processing apparatus 10 according to the present embodiment includes a plurality of types of storage units 14. That is, the information processing apparatus 10 according to the present embodiment uses a plurality of types of storage units 14 as a main memory.

  The plurality of types of storage units 14 have different access speeds by the processing circuit 12. Hereinafter, the access speed by the processing circuit 12 may be simply referred to as an access speed. The access speed may also be referred to as access delay. The high access speed means that the access delay time is short.

  In the present embodiment, the information processing apparatus 10 includes a first storage unit 14A and a second storage unit 14B as a plurality of types of storage units 14 having different access speeds. Note that the information processing apparatus 10 may be configured to include three or more types of storage units 14.

  The first storage unit 14A has a higher access speed than the second storage unit 14B. In the present embodiment, the first storage unit 14A is less integrated than the second storage unit 14B.

  The first storage unit 14A is, for example, a volatile memory. Specifically, the first storage unit 14A is a DRAM (Dynamic Random Access Memory). Note that the first storage unit 14A may be a non-volatile memory such as an MRAM (Magnetic Resistive Random Access Memory) that can be accessed at high speed in the same way as a DRAM.

  On the other hand, the second storage unit 14B has a lower access speed than the first storage unit 14A. In the present embodiment, the second storage unit 14B has a larger capacity than the first storage unit 14A.

  The second storage unit 14B is, for example, a nonvolatile memory. Specifically, the second storage unit 14B is a large-capacity high-speed nonvolatile memory (Non-volatile Memory) that is larger in capacity than a DRAM.

  More specifically, the second storage unit 14B includes an MRAM, a PCM (Phase Change Memory), a PRAM (Phase Random Access Memory), a PCRAM (Phase Change Random Access Memory), and a ReRAM (ResisAce Memory Memory). Ferroelectric Random Access Memory), 3DXPoint or Memristor.

  The second storage unit 14B may be a memory called a so-called storage class memory (SCM). Further, the second storage unit 14B may be a module in which a plurality of semiconductor devices are provided on one substrate or a housing.

  In the present embodiment, a case where the first storage unit 14A is a DRAM and the second storage unit 14B is an SCM will be described as an example. The access speed of the first storage unit 14A only needs to be higher than that of the second storage unit 14B, and these combinations are not limited to the form in which the first storage unit 14A is a DRAM and the second storage unit 14B is an SCM. For example, the first storage unit 14A may be an MRAM, and the second storage unit 14B may be a ReRAM.

  Note that when the first storage unit 14A and the second storage unit 14B are collectively described, they are simply referred to as the storage unit 14 for description.

  The storage unit 14 includes a plurality of first areas. The first region includes a plurality of second regions. In other words, in the present embodiment, the processing circuit 12 and the management device 18 manage the first storage unit 14A and the second storage unit 14B for each first region, and for each second region in the first region. to manage.

  FIG. 2 is a schematic diagram showing a physical address space viewed from the processing circuit 12.

  As shown in FIG. 2, each of the first storage unit 14A and the second storage unit 14B includes a plurality of first regions.

  The first area is, for example, a data management unit (for example, a page) by the processing circuit 12. The first area may be a unit of a predetermined number of data management units by the processing circuit 12. In the present embodiment, a case where the first region corresponds to a page will be described as an example.

  The second area is an area smaller than the first area. For example, the second area is a data rewrite unit associated with access to the storage unit 14 by the processing circuit 12. Specifically, the second area is a unit called a cache line. The cache line corresponds to a data rewrite unit for the cache memory 16. That is, the management device 18 that has received the memory access request from the processing circuit 12 accesses the first storage unit 14A or the second storage unit 14B in units of cache lines.

  The cache line is, for example, 64 bytes. The second area may be a unit (for example, byte unit) smaller than the cache line. The second area may be a unit of a predetermined number of times the size of the cache line.

  In the present embodiment, the processing circuit 12 and the management device 18 determine the area in the first storage unit 14A and the second storage unit 14B mapped in the physical address space 15 shown in FIG. , Page size). And the processing circuit 12 and the management apparatus 18 implement | achieve virtual memory by converting from a logical address to a physical address using a page table.

  In the present embodiment, the processing circuit 12 and the management device 18 manage the first area by dividing it into the size of the second area (for example, a cache line).

  As described above, the information processing apparatus 10 according to the present embodiment manages each of the plurality of types of storage units 14 for each second area (for example, cache line) that is a unit smaller than the first area (for example, page unit). It is configured to be possible.

  Returning to FIG. 1, the description will be continued. The management device 18 manages access to a plurality of types of storage units 14 (first storage unit 14A and second storage unit 14B) by the processing circuit 12. The management device 18 may be referred to as a memory management unit (MMU: Memory Management Unit).

  The management device 18 includes an access control unit 20 and a management unit 22. The management unit 22 includes an update unit 24, a determination unit 26, a transfer unit 28, and a management information storage unit 30.

  The update unit 24, the determination unit 26, and the transfer unit 28 are realized by, for example, hardware (logic circuit). Further, the update unit 24, the determination unit 26, and the transfer unit 28 may be realized by one or a plurality of processors. For example, at least one of the update unit 24, the determination unit 26, and the transfer unit 28 may be realized by causing a processor such as a CPU to execute a program, that is, by software. Further, at least one of the update unit 24, the determination unit 26, and the transfer unit 28 may be realized by hardware such as a dedicated IC (Integrated Circuit). Further, the update unit 24, the determination unit 26, and the transfer unit 28 may be realized by using software and hardware together. When a plurality of processors are used, each processor may realize one of the updating unit 24, the determination unit 26, and the transfer unit 28, or two or more of the units.

  The access control unit 20 processes the memory access request received from the processing circuit 12. The memory access request is an access request from the processing circuit 12 to the storage unit 14. The memory access request indicates data writing to the storage unit 14 or data reading from the storage unit 14. The memory access request includes address information of the first area and address information of the second area of the storage unit 14 to be accessed. These pieces of address information are represented by logical addresses.

  The access control unit 20 accesses the storage unit 14 when the access target data indicated by the memory access request received from the processing circuit 12 is not stored in the cache memory 16. In this case, the access control unit 20 accesses the second area in the first area in the access target storage unit 14 indicated by the memory access request received from the processing circuit 12. Then, the management device 18 executes processing (write or read) indicated by the memory access request for the accessed second area.

  Specifically, the memory access request received from the processing circuit 12 may indicate writing to a specific second area. In this case, the access control unit 20 writes the data indicated by the memory access request in the second area in the first area to be accessed in the storage unit 14 to be accessed indicated by the memory access request. In addition, the memory access request received from the processing circuit 12 may indicate reading data from a specific second area. In this case, the access control unit 20 reads the data from the second area in the first area to be accessed in the storage section 14 to be accessed indicated by the memory access request, stores the data in the cache memory 16, and the processing circuit 12 is output.

  Next, the management unit 22 will be described. The management unit 22 manages the management table 30A. FIG. 3 is a schematic diagram illustrating an example of a data configuration of the management table 30A.

  The management table 30A is a table in which the identification information of the first area is associated with the access management information. The identification information of the first area is information for identifying the first areas of the first storage unit 14A and the second storage unit 14B.

  In the present embodiment, as described above, a case where the first area corresponds to a page will be described. For this reason, in this Embodiment, the case where the identification information of a 1st area | region is a page number is demonstrated as an example.

  In the present embodiment, the identification information of the first area registered in the management table 30A is represented by a logical address. That is, in the present embodiment, the identification information of the first area is represented by a page number in the logical address space. For this reason, in the information processing apparatus 10, by specifying the physical address corresponding to the logical address in the page table, the page number indicated in the management table 30A can be stored in any type of storage unit 14 (the first storage unit 14A, the first storage unit 14A). 2) It is possible to specify whether to indicate the page number in the storage unit 14B).

  The access management information defines access information for each of a plurality of second areas included in the first area identified by the corresponding page number.

  The access information is a flag indicating whether or not the second area has been accessed by the processing circuit 12. In the example illustrated in FIG. 3, the access information “0” indicates a second area that has not been accessed by the processing circuit 12. The access information “1” indicates the second area that has been accessed by the processing circuit 12.

  FIG. 3 shows an example in which 16 cache lines as second areas are assigned to one page (one first area). For example, assume that the size of one page (first area) is 4K bytes. Further, it is assumed that the size of the cache line which is the second area is 64 bytes. In this case, one first region has 64 second regions. In the management table 30A, the access management information that defines the access information of each of the 64 second areas is defined for each first area identified by the page number.

  Returning to FIG. The management unit 22 includes an update unit 24, a determination unit 26, a transfer unit 28, and a management information storage unit 30. The management information storage unit 30 stores a management table 30A.

  When the update unit 24 receives a memory access request from the processing circuit 12, the update unit 24 updates the management table 30A. Specifically, the update unit 24 accesses, in the management table 30A, the access information of the second area to be accessed indicated by the memory access request corresponding to the page number indicating the first area to be accessed indicated by the memory access request. Is updated to “1”.

  Specifically, it is assumed that the access target data indicated in the memory access request received from the processing circuit 12 is not stored in the cache memory 16. In this case, the access control unit 20 accesses the storage unit 14 based on the memory access request. Then, the update unit 24 receives the memory access request from the access control unit 20.

  Then, the update unit 24 updates the access information of the second area accessed by the processing circuit 12 from “0” not accessed to “1” accessed based on the received memory access request.

  Note that the update unit 24 changes the access information of the second area accessed by the processing circuit 12 from the unaccessed “0” to the accessed “1” only when the memory access request indicates data writing to the storage unit 14. May be updated. Also, the update unit 24 changes the access information of the second area accessed by the processing circuit 12 from the unaccessed “0” to the accessed “1” only when the memory access request indicates reading of data from the storage unit 14. May be updated. In addition, when the memory access request indicates data writing to the memory unit 14 or data reading from the memory unit 14, the update unit 24 displays the access information of the second area accessed by the processing circuit 12 as “unaccessed” “0”. "1" may be updated to "1" already accessed.

  In this way, the update unit 24 updates the access information in the management table 30A each time the processing circuit 12 performs an access such as data reading or data writing from the storage unit 14.

  Therefore, an access pattern indicating what kind of memory access request is issued by the processing circuit 12 is registered in the management table 30A.

  Note that the page number indicated by the address information of the first area indicated in the memory access request may not exist in the management table 30A. That is, the entry of the first area to be accessed indicated in the memory access request may not exist in the management table 30A.

  In this case, the update unit 24 needs to create a new entry (a pair of page number and access management information) and register it in the management table 30A. Here, there is an upper limit to the number of entries registered in the management table 30A. For this reason, if there is no empty entry in the management table 30A, the update unit 24 may release any entry registered in the management table 30A and create a new entry.

  A known method may be used as a method for specifying the entry to be released. For example, the update unit 24 preferably specifies an entry to be released using an algorithm such as LRU (Least Recently Used). By using this method, the update unit 24 can specify an entry that is least used, an entry that has not been used for a long period of time, or an entry with a low reference frequency as an entry to be released.

  Then, the update unit 24 registers the page number of the first area indicated in the accepted memory access request in the newly created entry (hereinafter sometimes referred to as a new entry), and all of the corresponding access management information No access “0” is registered as the access information of the second area. Then, the update unit 24 may update the access information of the second area to be accessed indicated by the memory access request in the newly created new entry in the management table 30A to “1”.

  Based on the access management information in the management table 30A, the determination unit 26 determines the transfer destination of the data in the first area identified by the page number in the management table 30A. In the present embodiment, “transfer” means copying.

  That is, the determination unit 26 uses the access management information corresponding to each page number in the management table 30A to determine the optimal management method for the data in the first area identified by the corresponding page number.

  For example, the determination unit 26 determines the transfer destination of each data in the first area based on the access management information every predetermined time. In addition, when the update unit 24 releases the entry in the management table 30A, the determination unit 26 sets the transfer destination of the data in the first area identified by the page number of the entry to be released as the access management information of the entry. You may decide based on. Further, the determination unit 26 may determine the data transfer destination at both the predetermined time and at the time of releasing the entry of the management table 30A.

  In the present embodiment, the determination unit 26 determines whether the number of access information indicating “1” that has been accessed in the management table 30 </ b> A corresponds to the access management information that is equal to or greater than the first threshold, in the first area identified by the page number. Is transferred to another type of storage unit 14 having a higher access speed by the processing circuit 12 than the currently stored storage unit 14. Note that the storage unit 14 in which data is currently stored may be the storage unit with the fastest access speed. In this case, the determination unit 26 may determine the current storage unit 14 in which data is stored as the data transfer destination. In the present embodiment, specifically, the determination unit 26 is identified by the page number corresponding to the access management information in which the number of access information indicating “1” that has been accessed in the management table 30A is equal to or greater than the first threshold. The first storage unit 14A determines the transfer destination of data in the first area.

  The first threshold may be determined in advance. For example, the first threshold value is preferably a value equal to or greater than ½ of the number of second areas included in one page (first area), and is preferably a value equal to or greater than 2/3.

  It is estimated that the first area where the number of pieces of access information indicating “1” that has been accessed is equal to or greater than the first threshold has high locality of memory access by the processing circuit 12. Therefore, the determination unit 26 determines another storage unit 14 having a higher access speed by the processing circuit 12 than the currently stored storage unit 14 as the transfer destination for the data in the first area.

  For example, it is assumed that data in the first area where the number of access information indicating “1” that has been accessed is equal to or greater than the first threshold is stored in the second storage unit 14B. In this case, the determination unit 26 determines the first storage unit 14A, which has a higher access speed than the second storage unit 14B, as the transfer destination of the data. When the data is transferred to the first storage unit 14A, the processing circuit 12 can access the data by accessing the first storage unit 14A having a higher access speed than the second storage unit 14B. It becomes.

  On the other hand, the determination unit 26 transfers the data in the first area identified by the page number corresponding to the access management information in which the number of access information indicating “1” being accessed is less than the second threshold in the management table 30A. The destination is determined as the currently stored storage unit 14 or another type of storage unit 14 having a slower access speed by the processing circuit 12 than the currently stored storage unit 14. Note that the storage unit 14 that currently stores data may be the storage unit with the slowest access speed. In this case, the determination unit 26 may determine the current storage unit 14 in which data is stored as the data transfer destination. In the present embodiment, specifically, the determination unit 26 is identified by the page number corresponding to the access management information in which the number of access information indicating “1” being accessed is less than the second threshold in the management table 30A. The second storage unit 14B determines the transfer destination of data in the first area.

  The second threshold is a value equal to or less than the first threshold. The second threshold may be determined in advance. For example, the second threshold is preferably a value that is ½ or less of the number of second regions included in one page (first region), and is preferably a value that is １ ／ or less.

  In the first area where the number of pieces of access information indicating “1” that has been accessed is less than the second threshold value, the locality of memory access by the processing circuit 12 is estimated to be low. For this reason, the determination unit 26 stores the data stored in the first area in the storage unit 14 that is currently stored, or other storage in which the access speed by the processing circuit 12 is slower than the storage unit 14 that is currently stored. The unit 14 is determined as the transfer destination.

  For example, it is assumed that data in the first area where the number of pieces of access information indicating “1” being accessed is less than the second threshold is stored in the first storage unit 14A. In this case, the determination unit 26 determines the second storage unit 14B, which has a slower access speed than the first storage unit 14A, as the transfer destination of the data. When the data is transferred to the second storage unit 14B, the processing circuit 12 can access the data by accessing the second storage unit 14B, which has a lower access speed than the first storage unit 14A. It becomes.

  Note that the method of determining the data transfer destination by the determination unit 26 is not limited to the above.

  For example, the determination unit 26 transfers the data in the first area identified by the page number corresponding to the access management information in which the access information indicating “1” that has been accessed continues for the third threshold or more in the management table 30A May be determined as another type of storage unit 14 having a higher access speed than the currently stored storage unit 14. Similarly to the above, the storage unit 14 in which data is currently stored may be the storage unit with the fastest access speed. In this case, the determination unit 26 may determine the current storage unit 14 in which data is stored as the data transfer destination. In the present embodiment, specifically, the determination unit 26 is identified by the page number corresponding to the access management information in which the access information indicating “1” that has been accessed continues for the third threshold or more in the management table 30A. The transfer destination of the data in the first area is determined in the first storage unit 14A.

  Access information indicating “1” that has been accessed continues for the third threshold or more. The second area in which the access information that indicates “1” that has been accessed is specified is adjacent to the third threshold or more in the order of addresses in the first area. And the state arrange | positioned continuously is shown.

  The third threshold may be determined in advance. The third threshold value is preferably a value equal to or greater than ¼ of the number of second regions included in one page (first region), for example.

  On the other hand, the determination unit 26 stores the data in the first area identified by the page number corresponding to the access management information in which the number of consecutive access information indicating “1” being accessed is less than the fourth threshold in the management table 30A. The transfer destination may be determined as the currently stored storage unit 14 or another type of storage unit 14 having a slower access speed than the currently stored storage unit 14. Similarly to the above, the storage unit 14 in which current data is stored may be the storage unit with the slowest access speed. In this case, the determination unit 26 may determine the current storage unit 14 in which data is stored as the data transfer destination. In the present embodiment, specifically, the determination unit 26 identifies the page number corresponding to the access management information in which the consecutive number of access information indicating “1” that has been accessed is less than the fourth threshold in the management table 30A. The second storage unit 14B determines the transfer destination of the data in the first area.

  The fourth threshold value is a value equal to or smaller than the third threshold value. The fourth threshold may be determined in advance. For example, the fourth threshold value is preferably 1/8 or less of the number of second areas included in one page (first area).

  Next, the transfer unit 28 will be described. The transfer unit 28 transfers the data in the first area determined by the determination unit 26 using the storage unit 14 as a transfer destination to the storage unit 14 determined by the determination unit 26.

  The timing at which the transfer unit 28 transfers data is not limited. For example, each time the transfer destination is determined by the determination unit 26, the transfer unit 28 may transfer the data in the first area determined using the storage unit 14 as the transfer destination to the determined storage unit 14. Good.

  The transfer unit 28 may transfer data at a predetermined timing after a predetermined period has elapsed since the determination unit 26 determined the transfer destination storage unit 14. For example, the transfer unit 28 may transfer data during a period in which the processing circuit 12 has little access to the storage unit 14.

  As described above, the transfer unit 28 transfers the data in the first area determined by the determination unit 26 using the storage unit 14 as the transfer destination to the storage unit 14 determined by the determination unit 26. An effect is obtained. That is, the transfer unit 28 can automatically transfer (that is, assign) data to the transfer destination storage unit 14 determined by the determination unit 26 without the user's work.

  Then, the transfer unit 28 updates the physical address corresponding to the transferred logical address of the first area in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14. Therefore, the processing circuit 12 can directly access the transfer destination storage unit 14. The page table may be updated by the determination unit 26.

  Next, an example of an information processing procedure executed by the information processing apparatus 10 according to the present embodiment will be described. FIG. 4 is a flowchart illustrating an example of an information processing procedure executed by the information processing apparatus 10.

  First, the updating unit 24 determines whether a memory access request is received from the processing circuit 12 via the access control unit 20 (step S100). If a negative determination is made in step S100 (step S100: No), this routine ends. If an affirmative determination is made in step S100 (step S100: Yes), the process proceeds to step S102.

  In step S102, the updating unit 24 determines whether an entry including the page number indicated by the address information of the first area indicated in the memory access request received in step S100 is present in the management table 30A (step S102). ). The updating unit 24 determines whether or not the page number of the first area to be accessed included in the memory access request received in step S100 is registered in the management table 30A, thereby determining step S102.

  If a positive determination is made in step S102 (step S102: Yes), the process proceeds to step S126 described later. If a negative determination is made in step S102 (step S102: No), the process proceeds to step S104.

  In step S104, the update unit 24 identifies an entry to be released in the management table 30A (step S104).

  Next, the determination unit 26 determines whether or not the number of pieces of access information indicating “1” that has been accessed is greater than or equal to the first threshold for the access management information in the entry identified in step S104 (step S106).

  If the number of pieces of access information indicating “1” already accessed is equal to or greater than the first threshold (step S106: Yes), the process proceeds to step S108. In step S108, the determination unit 26 stores the transfer destination of the data in the first area identified by the page number included in the entry specified in step S104 as the currently stored storage unit 14 (for example, the second storage unit). 14B) is determined to be another type of storage unit 14 (for example, the first storage unit 14A) having a higher access speed by the processing circuit 12 (step S108).

  Next, the transfer unit 28 transfers the data in the first area identified by the page number included in the entry specified in step S104 to the storage unit 14 (for example, the first storage unit 14A) determined in step S108. Transfer (step S110).

  Next, the transfer unit 28 transfers the physical address corresponding to the logical address of the first area transferred in step S110 in the page table to the transfer destination storage unit 14 transferred in step S110 (for example, the first storage unit 14A). Is updated to a physical address indicating the storage location (step S112). Therefore, when accessing the data, the processing circuit 12 can access the data by accessing the first storage unit 14A. And it progresses to step S122 mentioned later.

  The page table update in step S112 may be executed by the determination unit 26 after the process in step S108. In step S112, the transfer unit 28 only needs to execute a process that enables direct access to the first storage unit 14A when the processing circuit 12 accesses the data, and is limited to the process of updating the page table. Not.

  On the other hand, if it is determined in step S106 that the number of pieces of access information indicating “1” already accessed is less than the first threshold (step S106: No), the process proceeds to step S114. Then, the determination unit 26 determines whether or not the number of pieces of access information indicating “1” that has been accessed is less than the second threshold for the access management information in the entry identified in step S104 (step S114). When it is equal to or greater than the second threshold (step S114: No), the process proceeds to step S122 described later. When it is less than the second threshold (step S114: Yes), the process proceeds to step S116.

  In step S116, the determination unit 26 determines the transfer destination of the data in the first area identified by the page number included in the entry specified in step S104 as the currently stored storage unit 14 (for example, the second storage unit). 14B) (step S116). As described above, when the data in the first area identified by the page number is stored in the first storage unit 14A, the determination unit 26 determines the second storage unit 14B as the transfer destination. do it.

  Then, the transfer unit 28 transfers the data in the first area identified by the page number included in the entry specified in step S104 to the storage unit 14 (for example, the second storage unit 14B) determined in step S116. (Step S118).

  Next, the transfer unit 28 transfers the physical address corresponding to the logical address of the first area transferred in step S118 in the page table to the transfer destination storage unit 14 (for example, the second storage unit 14B) transferred in step S118. Is updated to a physical address indicating the storage location (step S120).

  Therefore, when accessing the data, the processing circuit 12 can access the data by accessing the second storage unit 14B. Then, the process proceeds to step S122. If the data is already stored in the second storage unit 14B before the process of step S118, the processes of step S118 and step S120 may be omitted.

  The page table update in step S120 may be executed by the determination unit 26 after the process in step S116. In step S120, the transfer unit 28 only needs to execute a process that enables direct access to the second storage unit 14B when the processing circuit 12 accesses the data, and is limited to the process of updating the page table. Not.

  In step S122, the update unit 24 releases the entry specified in step S104 in the management table 30A (step S122). Then, the update unit 24 registers the new entry in the management table 30A (Step S124). In step S124, the update unit 24 obtains the page number of the first area indicated in the memory access request received in step S100, and the access management information in which all the access information of the second area is not accessed “0”. Register the new entry associated with it.

  Next, the updating unit 24 corresponds to the second access target indicated by the memory access request corresponding to the page number indicating the first area to be accessed indicated by the memory access request received at step S100 in the management table 30A. The access information of the area is updated to “1” that has been accessed (step S126). Then, this routine ends.

  As described above, the management device 18 according to the present embodiment manages access to a plurality of types of storage units 14 by the processing circuit 12. The storage unit 14 includes a plurality of first areas, and the first area includes a plurality of second areas. The management device 18 includes a management unit 22. The management unit 22 manages the management table 30A. The management table 30A indicates the identification information (page number) of the first area and whether or not the second area has been accessed by the processing circuit 12 for each of the plurality of second areas included in the first area. It is the table which matched the access management information which prescribed | regulated access information.

  As described above, in the management device 18 according to the present embodiment, whether or not each of the plurality of types of storage units 14 has been accessed by the processing circuit 12 for each second area that is a unit smaller than the first area. Manage the access information shown. Therefore, for each of the plurality of types of storage units 14, it is possible to easily manage which second area in the first area such as a page has been accessed by the processing circuit 12.

  Therefore, the management device 18 according to the present embodiment can provide information used for data allocation to a plurality of types of memories (storage unit 14).

  Here, when a plurality of types of storage units 14 are used as the main memory, it may be required to allocate and use data for each of the plurality of types of storage units 14 according to the access pattern by the processing circuit 12. .

  For example, although the SCM has a larger capacity than the DRAM, the access speed is slow. For this reason, if data is allocated and stored in a plurality of types of storage units 14 in accordance with the characteristics of access by the processing circuit 12, the processing circuit 12 can efficiently perform data processing.

  For example, data with low locality of access by the processing circuit 12 and large size is arranged in the SCM, and the processing circuit 12 directly accesses the SCM. Then, the processing circuit 12 can perform data processing efficiently. Further, data with high access locality is arranged in a DRAM having a higher access speed than the SCM, and the processing circuit 12 accesses the data on the DRAM. Then, the processing circuit 12 can perform data processing efficiently.

  Conventionally, however, it is difficult to determine how efficiently data is distributed and stored in a plurality of types of storage units 14, and complicated programming is required.

  In addition, the method of recording information indicating whether or not access has been performed in the page table in units of pages is insufficient as information used for data allocation to a plurality of types of memories, and an access pattern by the processing circuit 12 It is difficult to provide information that can be detected in detail.

  On the other hand, in the management apparatus 18 according to the present embodiment, each of the plurality of types of storage units 14 is processed for each second area having a finer granularity (for example, a 64-byte cache line size) than the first area. Access management information indicating an access pattern by the circuit 12 is managed.

  For this reason, the management apparatus 18 of this Embodiment can provide the information used for allocation of the data with respect to multiple types of memory.

(Modification 1)
In the above embodiment, the case has been described where the management table 30A associates the identification information (page number) of the first area represented by the logical address with the access management information.

  However, the management table 30A may further be associated with physical addresses.

  FIG. 5 is a schematic diagram illustrating an example of a data configuration of the management table 30B according to the present embodiment. The management table 30B may have a configuration in which a logical address as identification information of the first area, a physical address of the first area in the storage unit 14, and access management information are associated with each other. In this case, the management information storage unit 30 may store the management table 30B instead of the management table 30A (see FIG. 1).

  When the management table 30B has the data configuration shown in FIG. 5, a TLB (Translation Lookaside Buffer) that functions as a page table cache can be integrated and managed in the management table 30A. That is, by using a logical address as a search key, it is possible to search both the physical address of the TLB and the access management information. Therefore, by using the management table 30B, it is possible to share hardware for associative memory that searches for an entry using a page number represented by a logical address as a search key.

(Modification 2)
FIG. 6 is a schematic diagram illustrating an example of an information processing apparatus 10A according to the present modification. As illustrated in FIG. 6, the processing circuit 12 </ b> A of the information processing device 10 </ b> A may include a cache memory 16 and a management device 18. The processing circuit 12A is the same as the processing circuit 12 of the above embodiment except that the processing circuit 12A includes a cache memory 16 and a management device 18 therein.

(Modification 3)
FIG. 7 is a schematic diagram illustrating an example of the information processing apparatus 10B according to the present modification. As illustrated in FIG. 7, the management device 18 </ b> A may include a cache memory 16, an access control unit 20, a management unit 22, and a storage unit 14.

  As mentioned above, although embodiment and the modification of this invention were demonstrated, these embodiment and the modification are shown as an example, and are not intending limiting the range of invention. These novel embodiments and modifications can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 10A, 10B Information processing device 12, 12A Processing circuit 14 Storage unit 18, 18A Management device 22 Management unit 24 Update unit 26 Determination unit 28 Transfer unit

Claims (15)

A management device for managing access to a plurality of types of storage units by a processing circuit,
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. A management unit that manages a management table that associates access management information with each other;
Management device with. The management unit
When a memory access request is received from the processing circuit,
In the management table,
An update unit configured to update the access information of the second area to be accessed, which is indicated in the memory access request, to be accessed;
The management apparatus according to claim 1. The plurality of types of storage units are
The access speeds by the processing circuits are different from each other.
The management apparatus according to claim 1 or 2. The management unit
A determination unit that determines a transfer destination of data in the first area identified by the identification information based on the access management information in the management table;
The management apparatus of any one of Claims 1-3. The plurality of types of storage units include a first storage unit, and a second storage unit having a slower access speed by the processing circuit than the first storage unit,
The management device according to claim 4. The determination unit
In the management table, a transfer destination of data in the first area identified by the identification information corresponding to the access management information in which the number of the access information indicating accessed is equal to or greater than a first threshold is set to the first Determine the storage part of
The management device according to claim 5. The determination unit
In the management table, a transfer destination of data in the first area identified by the identification information corresponding to the access management information in which the number of the access information indicating accessed is less than a second threshold is set to the second Determine the storage part of
The management apparatus according to claim 5 or 6. The determination unit
In the management table, a transfer destination of data in the first area identified by the identification information corresponding to the access management information in which the access information indicating that access has been continued is equal to or greater than a third threshold value, Determine the storage part,
The management device according to claim 5. The determination unit
In the management table, a transfer destination of data in the first area identified by the identification information corresponding to the access management information in which the continuous number of the access information indicating access is less than a fourth threshold is represented by the data The storage unit is stored or the storage unit of the data is determined to be another type of the storage unit whose access speed by the processing circuit is slower than the storage unit.
The management device according to claim 5 or 8. The management unit
A transfer unit that transfers data in the first area determined using the storage unit as a transfer destination to the storage unit determined by the determination unit;
The management apparatus according to any one of claims 4 to 9. The management table is
For each of the logical address as identification information of the first area, the physical address of the first area in the storage unit, and the plurality of second areas included in the first area, the second area is the Corresponding access management information that defines access information indicating whether or not it has been accessed by the processing circuit,
The management apparatus of any one of Claims 1-10. The first area is a data management unit by the processing circuit;
The second area is a data rewrite unit for the storage unit by the processing circuit.
The management apparatus according to any one of claims 1 to 11. A processing circuit;
Multiple types of storage units;
A management device for managing access to the storage unit by the processing circuit;
With
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The management device
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. A management unit that manages a management table that associates access management information with
Information processing device. A management method in a management device for managing access to a plurality of types of storage units by a processing circuit,
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. Including a management step for managing a management table that associates access management information with
Management method. A program for causing a computer to manage access to a plurality of types of storage units by a processing circuit,
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. Including a management step for managing a management table that associates access management information with
program.

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