JP6786541B2 - Management equipment, information processing equipment, management methods, and programs - Google Patents

Description

Embodiments of the present invention relate to management devices, information processing devices, management methods, and programs.

Various storage class memories (SCM) such as MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive RAM), and PCM (Phase-Change Memory) have been developed. Although the access speed of SCM is slower than that of DRAM (Dynamic Random Access Memory), it can be used as a large-capacity main memory because of its high degree of integration. When SCM is installed in addition to the conventional DRAM as the main memory of the computer system, when the CPU accesses the SCM, the data arrival waiting time of the CPU becomes longer than when the DRAM is used, and the access speed becomes faster. It decreases and causes an increase in processing time.

Therefore, it is conceivable that a processing circuit such as a CPU predicts data to be accessed in the future and transfers the data to a memory that the CPU can access at a higher speed before access to shorten the data arrival waiting time and speed up the processing. However, conventionally, it has been difficult to accurately predict the data that the processing circuit will access in the future. For example, conventionally, a method of recording information indicating whether or not an access has been made in a page table for each page has been disclosed. However, it is not possible to control which area on the page is accessed, and it is difficult to predict the data to be accessed by the processing circuit in the future with high accuracy by the conventional technique.

Computer Organization and Design RISC-V Edition, David A.M. Paterson & John L. Hennessy, Morgan Kaufmann Publishers, ISBN 978-0-12-812275-4, 5.7 Virtual Memory.

An object to be solved by the present invention is to provide a management device, an information processing device, a management method, and a program capable of predicting data to be accessed in the future by a processing circuit with high accuracy.

The management device of the embodiment manages access to a plurality of types of storage units by the processing circuit. The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions. The management device includes a management unit and a prediction unit. The management department manages the management table. The management table indicates the identification information of the first area and each of the plurality of second areas included in the first area, indicating whether or not the second area has been accessed by the processing circuit. It is a table in which access control information that defines information is associated with it. The prediction unit predicts the second region to be accessed in the future by the processing circuit based on the access management information.

Schematic diagram of an information processing device. An explanatory diagram of access to the storage unit. Schematic diagram of the physical address space. The schematic diagram which shows the data structure of the management table. The schematic diagram which shows the data structure of the management table. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Flowchart of information processing procedure. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Flowchart of information processing procedure. Explanatory drawing of the prediction of the second region. Explanatory drawing of the prediction of the second region. Explanatory diagram of data transfer. Flowchart of information processing procedure. Schematic diagram of an information processing device. Schematic diagram of an information processing device.

The details of the present embodiment will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing an example of the configuration of the information processing device 10 of the present embodiment. The information processing device 10 includes a processing circuit 12, a storage unit 14, a cache memory 16, and a management device 18.

The processing circuit 12 and the cache memory 16, the cache memory 16 and the management device 18, the processing circuit 12 and the management device 18, and the management device 18 and the storage unit 14 are each connected so as to be able to exchange data and signals.

The processing circuit 12 has one or more processors. The processor is, for example, a CPU (Central Processing Unit). The processor may include one or more CPU cores. The processing circuit 12 reads data from the storage unit 14 and writes data to the storage unit 14 according to the execution of the program.

The processing circuit 12 and the management device 18 temporarily store the data stored in the storage unit 14 in the cache memory 16 and use it for processing.

The storage unit 14 is a main memory used as a work area by the processing circuit 12. The information processing device 10 of the present embodiment includes a plurality of types of storage units 14. That is, the information processing device 10 of the present embodiment uses a plurality of types of storage units 14 as the main memory.

The access speeds of the plurality of types of storage units 14 by the processing circuits 12 are different from each other. In the following, the access speed by the processing circuit 12 may be described simply as an access speed.

In the present embodiment, the information processing device 10 includes a first storage unit 14A and a second storage unit 14B as a plurality of types of storage units 14 having different access speeds. The information processing device 10 may be configured to include three or more types of storage units 14.

The first storage unit 14A is, for example, a volatile memory. Specifically, the first storage unit 14A is a DRAM (Dynamic Random Access Memory). The first storage unit 14A may be a non-volatile memory such as an MRAM (Magnetoresistive Ramdom Access Memory) capable of high-speed access.

The access speed of the second storage unit 14B is slower than that of the first storage unit 14A. Further, the capacity of the second storage unit 14B is the same as or larger than the capacity of the first storage unit 14A.

The second storage unit 14B is, for example, a non-volatile memory. Specifically, the second storage unit 14B is a large-capacity high-speed non-volatile memory (Non-volatile Memory) having a higher degree of integration and a larger capacity than the DRAM.

More specifically, the second storage unit 14B is a memory called a storage class memory (SCM). For example, MRAM, PCM (Phase Change Memory), PRAM (Phase Random Access Memory), PCRAM (Phase Change Random Access Memory), ReRAM (Resistance Change Random Access Memory), FeRAM (Ferroelectric Random Access Memory), 3DXPoint or Memristor etc. is there.

In the present embodiment, the case where the first storage unit 14A is a DRAM and the second storage unit 14B is an SCM will be described as an example. The access speed of the first storage unit 14A may be faster than that of the second storage unit 14B, and the combination thereof is not limited to the form in which the first storage unit 14A is a DRAM and the second storage unit 14B is an SCM. For example, the first storage unit 14A may be an MRAM and the second storage unit 14B may be a ReRAM.

FIG. 2 is an explanatory diagram of an access method to the first storage unit 14A and the second storage unit 14B. When SCM is installed in addition to the conventional DRAM as the main memory of the computer system, it is necessary to properly use both. That is, SCM has a larger capacity than DRAM, but its access speed is slow. Therefore, efficient data processing becomes possible by successfully distributing the memory for arranging the data between the DRAM and the SCM according to the characteristics of the data to be processed. That is, it is desirable that the data having low access locality and large size is arranged in the SCM and the processor directly accesses the SCM in units of cache lines. Further, it is desirable that the data having high access locality is transferred from the SCM to the DRAM in page units, and the processor accesses the data on the DRAM in cache line units.

The explanation will be continued by returning to FIG. When the first storage unit 14A and the second storage unit 14B are generically described, they are simply referred to as the storage unit 14.

The storage unit 14 includes a plurality of first regions. In the present embodiment, a mode in which the first storage unit 14A and the second storage unit 14B include a plurality of first regions will be described. The first region includes a plurality of second regions. That is, in the present embodiment, the processing circuit 12 and the management device 18 divide the first storage unit 14A and the second storage unit 14B into units of the first region or a second region in which the first region is further divided. Manage in units.

FIG. 3 is a schematic diagram showing a physical address space as seen from the processing circuit 12.

As shown in FIG. 3, the first storage unit 14A and the second storage unit 14B each include a plurality of first regions.

The first region is, for example, a data management unit (for example, a page) by the processing circuit 12 or an OS (Operating System) operating on the processing circuit. For example, 4KB. The first region may be a unit of a predetermined number of times the data management unit of the processing circuit 12 or the OS operating on the processing circuit. In the present embodiment, a case where the first area corresponds to a page will be described as an example.

The second region is a region smaller than the first region. For example, the second region is a unit in which the processing circuit 12 reads and writes data on the storage unit 14. Specifically, the second area is a cash line unit. That is, the processing circuit 12 accesses the first storage unit 14A or the second storage unit 14B in units of cash lines.

The cache line is, for example, 64 bytes. The second region may be a unit smaller than the cache line (for example, a byte unit).

In the present embodiment, the processing circuit 12 and the management device 18 make the area in the first storage unit 14A and the second storage unit 14B mapped to the physical address space 15 shown in FIG. 3 the size of the first area (for example,). , Page size) and manage. Then, the processing circuit 12 and the management device 18 realize virtual memory by converting a logical address into a physical address using a page table.

Further, in the present embodiment, the processing circuit 12 and the management device 18 divide the first region into the size of the second region (for example, a cache line) and manage each of the second regions.

As described above, the information processing apparatus 10 of the present embodiment manages each of the plurality of types of storage units 14 for each second area (for example, cache line) which is a unit finer than the first area (for example, page unit). It is configured to be possible.

The information processing apparatus 10 of the present embodiment will be described as an example in which the first storage unit 14A and the second storage unit 14B are combined and used as the main storage as the plurality of types of storage units used in the present invention.

Returning to FIG. 1, the explanation will be continued. The management device 18 manages access by the processing circuit 12 to the plurality of types of storage units 14. The management device 18 is, for example, a memory management unit (MMU: Memory Management Unit).

The management device 18 has an access control unit 20 and a management unit 22. The management unit 22 includes an update unit 24, a prediction unit 26, a transfer unit 28, and a management information storage unit 30.

The access control unit 20 processes the memory access request received from the processing circuit 12. The memory access request is a memory access request to the storage unit 14. The memory access request indicates writing data to or reading data from the storage unit 14.

The access control unit 20 accesses the storage unit 14 when the data to be accessed indicated by the memory access request received from the processing circuit 12 is not stored in the cache memory 16. In this case, the access control unit 20 accesses the second area in the storage unit 14 to be accessed, which is indicated by the memory access request received from the processing circuit 12. Then, the management device 18 executes the process (write or read) indicated by the memory access request for the accessed second area.

Next, the management unit 22 will be described. The management unit 22 manages the management table 31A. The management table 31A is an example of the management table 31. FIG. 4 is a schematic diagram showing an example of the data structure of the management table 31A.

The management table 31A is a table in which the identification information of the first area and the access management information are associated with each other. That is, in the management table 31A, a plurality of entries E in which the identification information of the first region and the access management information are associated with each other on a one-to-one basis are registered.

The identification information of the first region is information for identifying the first region of each of the first storage unit 14A and the second storage unit 14B.

In the present embodiment, the case where the first region corresponds to the page will be described as described above. Therefore, in the present embodiment, the case where the identification information of the first region is a page number will be described as an example. Further, in the following, the identification information of the first area may be described as a page number.

Further, in the present embodiment, the identification information of the first region registered in the management table 31A is represented by a logical address. That is, in the present embodiment, the identification information of the first region is represented by the page number in the logical address space. Therefore, in the information processing apparatus 10, by specifying the physical address corresponding to the logical address in the page table, the page number shown in the management table 31A can be any kind of storage unit 14 (first storage unit 14A, first storage unit 14A, first). 2 It is possible to specify whether to indicate the page number in the storage unit 14B).

The access management information defines the access information for each of the plurality of second areas included in the first area identified by the corresponding page number.

The access information is a flag indicating whether or not the second region has been accessed by the processing circuit 12. In the example shown in FIG. 4, the access information "0" indicates a second region that has not been accessed by the processing circuit 12. Further, the access information "1" indicates a second region that has been accessed by the processing circuit 12.

FIG. 4 shows an example in which 16 cache lines as the second area are allocated to one page (one first area). For example, it is assumed that the size of one page (first area) is 4 Kbytes. Further, it is assumed that the size of the cache line, which is the second region, is 64 bytes. In this case, one first region will have 64 second regions. Further, in the management table 31A, access management information that defines access information for each of the 64 second areas is defined for each first area identified by the page number.

The management table 31B may be used instead of the management table 31A. The management table 31B is an example of the management table 31.

FIG. 5 is a schematic diagram showing an example of the data structure of the management table 31B. The management table 31B further associates a physical address with the management table 31A. Specifically, the management table 31B has a configuration in which a logical address as identification information of the first area, a physical address of the first area in the storage unit 14, and access management information are associated with each other. In this case, the management information storage unit 30 may store the management table 31B instead of the management table 31A (see FIG. 1).

By using the management table 31B of the data structure shown in FIG. 5, the management table 31A (see FIG. 4) and the TLB (Translation Lookaside Buffer) that functions as a cache of the page table can be integrated and managed. That is, by using the logical address as the search key, the processing circuit 12 can search for both the physical address of the TLB and the access control information of each of the second regions. Therefore, by using the management table 31B, it is possible to provide hardware for associative storage that searches the entry E using the page number represented by the logical address as the search key. Note that entry E in the management table 31B has a one-to-one correspondence between a logical address, a physical address, and access management information.

The explanation will be continued by returning to FIG. The management unit 22 includes an update unit 24, a prediction unit 26, a transfer unit 28, and a management information storage unit 30.

The management information storage unit 30 stores the management table 31A or the management table 31B. That is, the management information storage unit 30 is an example of the management unit of the present invention. In the present embodiment, a case where the management table 31A (see FIG. 4) is used as the management table 31 will be described as an example.

The update unit 24 updates the management table 31A when the memory access request is received from the processing circuit 12. Specifically, the update unit 24 has access information of the access target second area indicated in the memory access request corresponding to the page number indicating the access target first area indicated in the memory access request in the management table 31A. Is updated to accessed "1". The initial value of the access information in the management table 31A is "0" that has not been accessed, and is updated to "1" that has been accessed by the update unit 24.

Specifically, it is assumed that the data to be accessed indicated in the memory access request received from the processing circuit 12 is not stored in the cache memory 16. In this case, the access control unit 20 accesses the storage unit 14 based on the memory access request. Then, the update unit 24 receives the memory access request from the access control unit 20.

Then, based on the received memory access request, the update unit 24 updates the access information of the second region accessed by the processing circuit 12 from "0" that has not been accessed to "1" that has been accessed.

Note that the update unit 24 can access the access information of the second region accessed by the processing circuit 12 from "0" not accessed to "1" accessed only when the memory access request indicates writing data to the storage unit 14. May be updated to. Further, the update unit 24 obtains the access information of the second region accessed by the processing circuit 12 from the access not yet “0” to the accessed “1” only when the memory access request indicates the data read from the storage unit 14. May be updated to. Further, when the memory access request indicates writing data to the storage unit 14 or reading data from the storage unit 14, the update unit 24 accesses the access information of the second region accessed by the processing circuit 12 to "0". May be updated from "" to accessed "1".

In this way, the update unit 24 updates the access information in the management table 31A each time the processing circuit 12 executes access such as reading data or writing data from the storage unit 14.

Therefore, the access management information in the management table 31A indicates what pattern of memory access request the processing circuit 12 has issued to the second area in the first area identified by the page number. It will be.

The page number indicated by the logical address of the first area indicated in the memory access request may not exist in the management table 31A. That is, the entry E of the first area to be accessed, which is shown in the memory access request, may not exist in the management table 31A.

In this case, the update unit 24 needs to create a new entry E and register it in the management table 31A. Here, there is an upper limit to the number of entries registered in the management table 31A. Therefore, when there is no empty entry E in the management table 31A, the update unit 24 may release any entry E registered in the management table 31A and create a new entry E.

A known method may be used as a method for specifying the entry E to be released. For example, it is preferable that the update unit 24 specifies the entry E to be released by using an algorithm such as LRU (Last Recentry Used). By using this method, the update unit 24 can identify the least used entry, the entry E that has not been used for a long period of time, and the entry E that is rarely referred to as the entry E to be released.

Then, the update unit 24 registers the page number of the first area indicated in the received memory access request in the newly created entry E. Then, the update unit 24 registers "0" that has not been accessed as the access information of all the second regions in the access management information corresponding to the page number in the entry E. Then, the update unit 24 may update the access information of the access target second area indicated in the memory access request in the newly created entry E to the accessed "1". In the following, the newly created entry E may be simply referred to as a new entry E.

The prediction unit 26 predicts a second region to be accessed in the future by the processing circuit 12 based on the access management information in the management table 31A. The second region to be accessed in the future indicates a second region that is predicted to be accessed by the processing circuit 12 at a timing in the future (after the present) from the present.

Then, the prediction unit 26 updates the access information of the second region predicted to be accessed in the future in the management table 31A to the accessed "1".

The timing of prediction by the prediction unit 26 is not limited.

For example, the prediction unit 26 predicts the second area to be accessed in the future each time the access information of the second area in the management table 31A is updated to the accessed "1" by the update unit 24. In this case, for example, the prediction unit 26 sets the access non-accessible “0” in the first area based on the access management information corresponding to the page number of the first area including the second area whose access information is updated. Any of the indicated second regions is predicted as the second region to be accessed in the future.

Further, for example, the prediction unit 26 may predict a second region to be accessed in the future by the processing circuit 12 at predetermined intervals.

In this case, the prediction unit 26 has not accessed for each predetermined period based on the access information of the second area included in each of the first areas identified by each of the page numbers defined in the management table 31A. Any one of the second regions indicating "0" may be predicted as the second region to be accessed in the future.

Further, the prediction unit 26 predicts the second area to be accessed in the future at both the timings when the access information in the management table 31A is updated to the accessed "1" by the update unit 24 and every predetermined period. May be good.

The prediction by the prediction unit 26 will be specifically described.

For example, the prediction unit 26 predicts a second region to be accessed in the future by the processing circuit 12 according to the pattern indicated by the access information in the management table 31A.

The pattern indicated by the access information indicates an access pattern to the storage unit 14 by the processing circuit 12. Specifically, the pattern is represented by the positional relationship in the storage unit 14 of one or a plurality of second regions in which access information indicating the accessed "1" is defined. For example, the pattern indicated by the access information indicates the regularity of the access information indicating the accessed "1". In particular, the pattern represented by the access information is represented by at least one of the arrangement continuity and the arrangement interval of the access information indicating the accessed "1". However, it is not limited to this.

For example, when the update unit 24 makes a prediction every time the access information of the second region in the management table 31A is updated, the prediction unit 26 makes a prediction by the following method using the pattern indicated by the access information. Do.

For example, the prediction unit 26 has access management information in the management table 31A that the processing circuit 12 will access in the future according to a pattern indicated by a plurality of access information including the access information immediately updated by the update unit 24. Predict two regions.

6 and 7 are explanatory views of an example of prediction of the second region to be accessed in the future.

As shown in FIG. 6, for example, it is assumed that the access information of the second area C3, which is the third from the start address in the first area in which the page number is specified in the entry E1, is updated by the update unit 24. At this time, it is assumed that the access information is continuously accessed "1" from the first second area C1 to the second area C3 updated immediately before.

In this case, the prediction unit 26 specifies a pattern in which the accessed "1" is continuously arranged from the first second region C1 toward the immediately updated second region C3. Then, the prediction unit 26 predicts that a pattern similar to the specified pattern is also shown in the address information of the second region after the second region C3. That is, the prediction unit 26 predicts that the other second regions (second regions C4 to C16) continuous with the second region C3 will be continuously accessed "1" at the same intervals as the specified pattern. Therefore, the prediction unit 26 predicts the second region C4 to the second region C16 in the entry E1 as the second region to be accessed by the processing circuit 12 in the future.

Then, the prediction unit 26 updates the predicted access information of the second region to the accessed “1”. The access control information of the entry E'after the prediction is, for example, the state shown in FIG. 6 (see entry E1'in FIG. 6).

Note that, in FIG. 6, the prediction unit 26 will access all the second regions (second region C4 to second region C16) that are continuous after the second region C3 that was updated immediately before in entry E1 in the future. The case of predicting as the second region is shown.

However, the number of second regions predicted by the prediction unit 26 is not limited. For example, the prediction unit 26 may predict only one second region C4 adjacent to the second region C3 that has been updated immediately before by the update unit 24 as the second region that the processing circuit 12 will access in the future. Further, the prediction unit 26 predicts a predetermined number of second regions (for example, the second region C4 to the second region C5) adjacent to the second region C3 as the second region to be accessed by the processing circuit 12 in the future. May be good. Further, the prediction unit 26 may predict the second region to be accessed in the future by the processing circuit 12 over a plurality of first regions.

Further, as shown in FIG. 7, it is said that the access information of the second area C7, which is the seventh from the start address in the first area in which the page number is specified in the entry EX of the management table 31A, has been updated by the update unit 24. Suppose. At this time, it is assumed that the access information is accessed "1" every two times from the first second area C1 to the second area C7 updated immediately before.

In this case, the prediction unit 26 specifies a pattern in which the accessed "1" is arranged for each of the two second regions from the first second region C1 toward the immediately updated second region C7. Then, the prediction unit 26 predicts that a pattern similar to the specified pattern is also shown in the address information of the second region after the second region C7. That is, the prediction unit 26 has already accessed the other second regions (second regions C8 to C16) that are continuous after the second region C7 at the same intervals as the specified pattern for each of the two second regions. It is predicted that "1" will be placed. Therefore, in this case, the prediction unit 26 predicts the second region C10, the second region C13, and the second region C16 in the entry EX as the second region to be accessed in the future.

Then, the prediction unit 26 updates the predicted access information of the second region to the accessed “1”. The access control information of the entry E'after the prediction is, for example, the state shown in FIG. 7 (see entry EX' in FIG. 7).

Further, for example, the prediction unit 26 may predict the second region to be accessed in the future by the processing circuit 12 according to the pattern indicated by the access information updated in a certain period in the access management information. The fixed period is a period from the timing of updating the access information by the updating unit 24 to the timing of going back a predetermined time from the timing of the reference. This fixed period may be set in advance.

8 and 9 are explanatory views of an example of prediction of the second region to be accessed in the future.

As shown in FIG. 8, for example, it is assumed that the access information of the second area C3, which is the third from the start address in the first area in which the page number is defined in the entry E1, is updated by the update unit 24. At this time, it is assumed that the first second region C1 and the next second region C2 have been updated to "1" within a certain period T that goes back from the update timing of the second region C3.

In this case, the prediction unit 26 specifies a pattern in which accessed "1" are continuously arranged as a pattern represented by the access information updated within the immediately preceding fixed period T. Then, the prediction unit 26 predicts that a pattern similar to the specified pattern is also shown in the address information of the second region after the second region C4. That is, the prediction unit 26 predicts that the other second regions (second regions C4 to C16) continuous with the second region C3 will be continuously accessed "1" at the same intervals as the specified pattern. Therefore, the prediction unit 26 predicts the second region C4 to the second region C16 in the entry E1 as the second region to be accessed in the future.

Then, the prediction unit 26 updates the predicted access information of the second region to the accessed “1”. The access control information of the entry E'after the prediction is, for example, the state shown in FIG. 8 (see entry E1'in FIG. 8).

The prediction unit 26 does not have to make a prediction when there is no access information updated in a certain period of time.

For example, as shown in FIG. 9, it is assumed that the access information of the second area C3, which is the third from the start address, in the first area in which the page number is specified in the entry EY is updated by the update unit 24. .. At this time, the first second region C1 and the next second region C1 are in the (past) timing period T'before the fixed period T, instead of the fixed period T retroactive from the update timing of the second region C3. It is assumed that C2 has been updated to accessed "1".

In this case, the prediction unit 26 regards the access to the second region C1 and the second region C2 by the processing circuit 12 and the access to the second region C3 this time as different events. Then, the prediction unit 26 does not predict the second region C4 and subsequent regions of the entry EY as the second region to be accessed in the future at this point. Therefore, in this case, the access management information of the entry EY'after the prediction has the same contents as the entry EY before the prediction, as shown in FIG.

On the other hand, when making a prediction every predetermined period, the prediction unit 26 may make a prediction by the following method using the pattern indicated by the access information.

For example, the prediction unit 26 sets a number of second regions in the management table 31A that match or are close to the number, depending on the number of second regions that have been updated to “1” that have been accessed within a certain period of time. It is predicted as the second area to be accessed in the future.

Here, the prediction unit 26 specifies a plurality of fixed periods for the access management information in the management table 31A, and uses a pattern indicated by the access information for the fixed period at each specified fixed period to access in the future. The second region to be used may be predicted.

For example, the prediction unit 26 changes the pattern indicated by the access information updated in the first period in the access management information of the management table 31A by the access information updated in the second period of the timing before the first period. Priority is given to the pattern shown to predict a second region that the processing circuit 12 will access in the future.

In addition, the prediction unit 26 specifies a period in which more access information is updated to accessed "1" within a unit time within the first period and the second period. Then, the prediction unit 26 may predict the second region to be accessed in the future by preferentially using the pattern indicated by the access information of the specified period (first period or second period).

Note that preferential use means that the prediction or the prediction and the transfer of the predicted data in the second region to the other storage unit 14 are executed first. In addition, preferential use may mean that only the one with the higher priority is predicted and the one with the lower priority is not predicted. In addition, preferential use may mean that only the one with the higher priority is predicted and data is transferred, and the one with the lower priority is not predicted and the data is transferred. The predicted data transfer in the second region is performed by the transfer unit 28 described later (details will be described later).

This will be specifically described with reference to FIGS. 10 to 12. 10 to 12 are explanatory views of an example of prediction of the second region to be accessed in the future.

As shown in FIG. 10, for example, the access information of the second area C1 to the second area C3 in the first area in which the page number is defined in the entry E1 of the management table 31A has been accessed in the first period T1. Suppose it has been updated to "1". It is assumed that the timing at which the access information of each of the second regions C1 to the second region C3 is updated to the accessed "1" is the timings t3 to t5 within the first period T1.

On the other hand, as shown in FIG. 11, the access information of the second area C1 to the second area C3 in the first area in which the page number is defined in the entry EZ of the management table 31A has been accessed in the second period T2. Suppose it has been updated to "1". It is assumed that the timing at which the access information of each of the second regions C1 to the second region C3 is updated to the accessed "1" is the timings t0 to t2 within the second period T2.

These timings t0 to t5 are represented by the time series shown in FIG. That is, the timing t0 is the oldest, and it becomes closer to the current timing T0 toward the timing t5. Further, the second period represented by the timings t0 to t2 is longer than the first period represented by the timings t3 to t5. Therefore, the number of updates of access information per unit time in the first period T1 is larger than that in the second period T2. Further, the second period T2 is a timing before the first period T1.

In this case, first, the prediction unit 26 specifies a pattern indicated by the access information updated in each period for each of the first period T1 and the second period T2 in the access management information of the management table 31A. Then, the prediction unit 26 predicts the second region to be accessed in the future by preferentially using the pattern indicated by the access information of the first period T1 over the pattern indicated by the access information of the second period T2.

Specifically, as shown in FIG. 10, the prediction unit 26 has a second pattern according to the access information of the second region C1 to the second region C3 updated in the first period T1 in the entry E1. The three second regions C4 to C6 adjacent to the region C3 are predicted as the second regions to be accessed in the future.

Then, the prediction unit 26 updates the predicted access information of the second region to the accessed “1”. The access control information of the entry E1'after the prediction is in the state shown in FIG. 10 (see entry E1'in FIG. 10).

Next, as shown in FIG. 11, the prediction unit 26 receives the second region according to the pattern indicated by the access information of the second region C1 to the second region C3 updated in the second period T2 in the entry EZ. The second region C4 adjacent to C3 is predicted as the second region to be accessed in the future.

Then, the prediction unit 26 updates the predicted access information of the second region to the accessed “1”. The access control information of the entry EZ'after the prediction is in the state shown in FIG. 11 (see entry EZ'in FIG. 11).

Note that the prediction unit 26 does not have to use the access information of the second period T2, which has a low priority, as a pattern used for prediction. In this case, the prediction unit 26 does not have to predict the second region to be accessed in the future for the entry EZ shown in FIG.

Further, for example, the prediction unit 26 is stored in the storage unit 14 of a type in which the access speed by the processing circuit 12 is less than the first speed in the first region identified by each of the plurality of page numbers shown in the management table 31A. Regarding the second area in the first area in which data is stored, priority is given to the first area in which data is stored in the storage unit 14 having an access speed of the first speed or higher, and access is performed in the future. The second region may be predicted.

The processing circuit 12 gives priority to the data in the second area stored in the storage unit 14 having a slower access speed over the data in the second area stored in the storage unit 14 having a faster access speed. By predicting (or predicting and transferring) before accessing, a higher effect of reducing the stall time by the processing circuit 12 can be obtained.

The first speed may be predetermined. In the present embodiment, it is assumed that the access speed of the first storage unit 14A is equal to or higher than the first speed and the access speed of the second storage unit 14B is lower than the first speed.

For example, the prediction unit 26 gives priority to the first area in which the data is stored in the first storage unit 14A with respect to the second area in the first area in which the data is stored in the second storage unit 14B. , The second area to be accessed in the future may be predicted.

13 to 15 are explanatory views of an example of prediction of the second region to be accessed in the future.

As shown in FIG. 13, for example, it is assumed that the data in the first area in which the page number is specified in the entry E1 of the management table 31A is stored in the second storage unit 14B. Further, as shown in FIG. 14, it is assumed that the data in the first area in which the page number is defined in the entry EZ of the management table 31A is stored in the first storage unit 14A.

In this case, as shown in FIG. 13, the prediction unit 26 uses the access control information of the entry E1 that defines the page number of the first area in which the data is stored in the second storage unit 14B, and uses the access control information of the entry E1. The second region C4 is predicted as the second region to be accessed in the future (see entry E1'in FIG. 13). The method of predicting the second area to be accessed in the future from the access management information is the same as described above.

Next, as shown in FIG. 14, the prediction unit 26 uses the access control information of the entry EZ that defines the page number of the first area in which the data is stored in the first storage unit 14A, and uses the access control information of the entry EZ. The second area is predicted as the second area to be accessed in the future. The prediction unit 26 does not have to predict the second region to be accessed in the future for the entry EZ that defines the first region in which data is stored in the first storage unit 14A having a low priority. In this case, as shown in FIG. 14, the entry EZ'after the prediction has the same contents as the entry EZ before the prediction.

When the prediction unit 26 predicts the second area to be accessed in the future based on the priority according to the storage unit 14 in which the data is stored, the management table 31B (see FIG. 5) is used as the management table 31. It is preferable to use as.

FIG. 15 is an explanatory diagram of prediction using the management table 31B. In this case, the prediction unit 26 can easily search the management table 31B for the entry E (entry Ea, entry Eb, entry Ec, entry Ed) indicating the physical address of the second storage unit 14B. Therefore, the prediction unit 26 can easily identify the entry E that defines the page number of the first area in which the data is stored in the second storage unit 14B, and can use it for the prediction of the second area to be accessed in the future. ..

The explanation will be continued by returning to FIG. Next, the transfer unit 28 will be described. The transfer unit 28 transfers the data in the second region predicted by the prediction unit 26 to another type of storage unit 14 having a faster access speed by the processing circuit 12 than the storage unit 14 in which the data is stored. In the present embodiment, the “transfer” may mean a copy or a movement in which the original data is deleted.

For example, it is assumed that the data in the second region, which is predicted to be accessed in the future, is stored in the first storage unit 14A. In this case, the transfer unit 28 transfers the data in the second area stored in the first storage unit 14A to the cache memory 16.

Further, for example, it is assumed that the data in the second region predicted to be accessed in the future is stored in the second storage unit 14B. In this case, the transfer unit 28 transfers the data in the second area stored in the second storage unit 14B to the first storage unit 14A or the cache memory 16.

The basic unit of data transfer from the second storage unit 14B to the first storage unit 14A is a page (that is, a unit of the first area). Therefore, when the transfer destination is the first storage unit 14A, the transfer unit 28 transfers the data in the first area (page) including the data (cache line) in the second area to the first storage unit 14A.

On the other hand, the basic unit of data transfer from the second storage unit 14B or the first storage unit 14A to the cache memory 16 is a cache line unit (that is, a unit of the second area). Therefore, when the transfer destination is the cache memory 16, the transfer unit 28 transfers the data in the second area to the cache memory 16 in units of cache lines.

The timing at which the transfer unit 28 transfers the predicted data in the second region is not limited. For example, every time a new second area is predicted by the prediction unit 26, the transfer unit 28 transfers the data in the second area to the storage unit 14 or the cache memory 16 having a faster access speed.

Further, the transfer unit 28 stores the predicted data in the second region at a faster access speed at predetermined time intervals or at a predetermined timing after a predetermined time has elapsed since the prediction unit 26 last predicted. It may be transferred to the unit 14 or the cache memory 16. For example, the transfer unit 28 may transfer data during a period in which the processing circuit 12 has little access to the storage unit 14.

Then, when the data is transferred from the second storage unit 14B to the first storage unit 14A in page units, the transfer unit 28 transfers the physical address corresponding to the logical address of the transferred second region in the page table to the transfer destination. Update to the physical address indicating the position in the storage unit 14. Therefore, when the processing circuit 12 accesses the data, the processing circuit 12 can directly access the storage unit 14 of the transfer destination. The page table may be updated by the prediction unit 26.

Next, an example of the information processing procedure executed by the information processing apparatus 10 of the present embodiment will be described. FIG. 16 is a flowchart showing an example of the information processing procedure executed by the information processing apparatus 10.

First, the update unit 24 obtains an access target address from the memory access request received from the processing circuit 12 via the access control unit 20 (step S100).

Next, the update unit 24 is the second access target indicated in the memory access request received in step S100 in the entry E defining the page number indicated by the address information of the address obtained in step S100 in the management table 31A. The access information of the area is updated to the accessed "1" (step S102).

Next, the prediction unit 26 predicts the second region to be accessed in the future by the processing circuit 12 based on the access management information in the management table 31A (step S104).

Then, the prediction unit 26 updates the access information of the second region predicted in step S104 in the management table 31A to the accessed "1" (step S106).

Next, the transfer unit 28 transfers the data in the second region predicted in step S104 to another type of storage unit 14 or cache memory whose access speed by the processing circuit 12 is faster than that of the storage unit 14 in which the data is stored. Transfer to No. 16 (step S108).

Next, in the case of transfer from the second storage unit to the first storage unit, the transfer unit 28 stores the physical address corresponding to the logical address of the second region transferred in step S108 in the page table at the transfer destination. The physical address indicating the storage destination of the unit 14 is updated (step S110). Then, this routine is terminated.

As described above, the prediction unit 26 uses the access information updated in the second period T2, which is the timing before the first period T1, to change the pattern indicated by the access information updated in the first period T1. It may be used in preference to the pattern shown to predict a second region to be accessed in the future.

Further, the prediction unit 26 stores data in the second storage unit 14B of a type whose access speed is lower than the first speed in the first storage unit 14A having an access speed equal to or higher than the first speed. In some cases, the second area to be accessed in the future may be predicted in preference to the second area in which data is stored.

In these cases, as described above, in the information processing apparatus 10, only the prediction by the prediction unit 26 may be prioritized, or the prediction by the prediction unit 26 and the transfer by the transfer unit 28 may be prioritized. Good.

When the prediction by the prediction unit 26 and the transfer by the transfer unit 28 are prioritized, for example, the access speed of the second region preferentially predicted by the prediction unit 26 is higher than that of the second region having a lower priority. Transfer to the fast storage unit 14. Then, when the prediction unit 26 predicts the second region having a low priority, the data of the predicted second region may be transferred to the storage unit 14 having a high access speed.

At this time, when the transfer destination is the cache memory 16, the transfer unit 28 may transfer the data of the second region having a higher priority to the upper layer having a higher access speed in the cache memory 16. preferable.

As described above, the management device 18 of the present embodiment manages access to a plurality of types of storage units 14 by the processing circuit 12. The storage unit 14 includes a plurality of first regions, and the first region includes a plurality of second regions. The management device 18 includes a management unit (management information storage unit 30) and a prediction unit 26. The management unit (management information storage unit 30) manages the management table 31. The management table 31 defines the identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit 12 for each of the plurality of second areas included in the first area. It is a table in which the access control information is associated with the access control information. The prediction unit 26 predicts a second region to be accessed in the future by the processing circuit 12 based on the access management information.

As described above, in the management device 18 of the present embodiment, whether or not each of the plurality of types of storage units 14 has been accessed by the processing circuit 12 for each second area, which is a unit finer than the first area. Manage the access information shown. Therefore, for each of the plurality of types of storage units 14, it is possible to easily manage which second region in the first region is accessed by the processing circuit 12.

Then, in the management device 18 of the present embodiment, the second region to be accessed in the future by the processing circuit 12 is predicted based on the access management information that defines the access information of each of the second regions in the management table 31. Therefore, in the management device 18 of the present embodiment, the second region to be accessed in the future by the processing circuit 12 can be predicted according to the pattern of access to the second region by the processing circuit 12.

Therefore, the management device 18 can predict the data that the processing circuit 12 will access in the future with high accuracy.

Further, in the present embodiment, the transfer unit 28 uses the data in the second region predicted by the prediction unit 26 to access the data in the second region, which is faster than the storage unit 14 in which the data is stored, by the processing circuit 12. Is transferred to the storage unit 14.

Therefore, in the management device 18 of the present embodiment, the data in the second region predicted to be accessed in the future before being accessed by the processing circuit 12 is stored in the storage unit 14 (for example, the storage unit 14) in which the data is stored. It can be transferred to the storage unit 14 (for example, the first storage unit 14A or the cache memory 16) having a faster access speed than the second storage unit 14B).

Therefore, in the management device 18 of the present embodiment, in addition to the above effects, the access speed is improved by the processing circuit 12, the processing time is shortened, the processing performance is improved, and the power consumption is reduced by shortening the processing time. Can be planned.

(Modification example 1)
The prediction unit 26 may predict the second region to be accessed in the future based on the access management information in the management table 31, and the prediction method by the prediction unit 26 is not limited to the method described in the above embodiment.

For example, the prediction unit 26 may predict the second area in each of the plurality of first areas having adjacent logical addresses (page numbers) as the second area to be accessed in the future.

Here, the page number of the first area including the second area predicted to be accessed in the future may not be registered in the management table 31. In this case, the prediction unit 26 may add a new entry E that defines the page number of the first area including the second area that is predicted to be accessed in the future to the management table 31.

17 and 18 are explanatory views of an example of prediction in the second region. In this modification, a case where the management table 31B (see FIG. 5) is used as the management table 31 will be described.

For example, as shown in FIG. 17, it is assumed that the access information of the second area C16, which is the 16th from the start address in the first area in which the page number is specified in the entry _EZ , is updated by the update unit 24.

Then, as shown in FIG. 18, the prediction unit 26 has a second region in the first region of the next page number “0f064382” with respect to the page number “0f064381” of the first region defined in the entry Ez. It is assumed that C1 is predicted as a second region to be accessed in the future.

In this case, the prediction unit 26 creates a new entry E _{Z + 1} (hereinafter, may be referred to as a new entry E _{Z + 1} ) and registers it in the management table 31B. Here, there is an upper limit to the number of entries registered in the management table 31B. Therefore, when there is no empty entry E in the management table 31B, the prediction unit 26 may release any entry E registered in the management table 31B and register a new entry E _{Z + 1.} .. The release of the entry E may be performed in the same manner as the release of the entry E by the update unit 24.

Then, the prediction unit 26 registers the logical address, which is the page number, of the first area including the second area predicted to be accessed in the future in the new entry _{EZ + 1} in the management table 31B. Further, the prediction unit 26 searches the page table for the physical address corresponding to the logical address and registers it in the new entry _{EZ + 1} .

In this way, the management table 31A (see FIG. 4) and the TLB functioning as a page table cache are integrated and managed in the management table 31B (see FIG. 5), which is newly predicted by the prediction unit 26. register the new entry _{Z + 1} 2 regions, registers the logical addresses and physical addresses in該新entry _{Z + 1.}

Therefore, when the processing circuit 12 accesses the data in the second region, it is possible to prevent the entry E corresponding to the management table 31B, which also has a function as a TLB, from being present, and it is possible to suppress the occurrence of a TLB error. ..

Next, the prediction unit 26 updates the access information of the second region C1 predicted to be accessed in the future in the new entry _{EZ + 1} to the accessed “1”.

Then, as in the above embodiment, the transfer unit 28 transfers the data in the second area predicted by the prediction unit 26 to the cache memory 16. Further, the transfer unit 28 transfers the data to another type of storage unit 14 (for example, the first storage unit 14A) whose access speed by the processing circuit 12 is faster than that of the storage unit 14 in which the data is stored. May be good.

Then, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred second region in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14. At this time, if the transfer destination is the cache memory 16, it is not necessary to update the page table.

Next, an example of the information processing procedure executed by the information processing device 10 of this modification will be described. FIG. 19 is a flowchart showing an example of an information processing procedure executed by the information processing device 10 of this modified example.

First, the update unit 24 obtains an access target address from the memory access request received from the processing circuit 12 via the access control unit 20 (step S200).

Next, the update unit 24 is the second access target indicated in the memory access request received in step S200 in the entry E defining the page number indicated by the address information of the address obtained in step S200 in the management table 31A. The access information of the area is updated to the accessed "1" (step S202).

Next, the prediction unit 26 predicts the second region to be accessed in the future by the processing circuit 12 based on the access management information in the management table 31B (step S204).

Next, the prediction unit 26 indicates that the second area predicted in step S206 is in the first area identified by the next page number of the first area to be accessed indicated in the memory access request acquired in step S200. It is determined whether or not it is the second region (step S206).

If an affirmative decision is made in step S206 (step S206: Yes), the process proceeds to step S208.

In step S208, it is determined whether or not entry E, which defines the page number of the first area including the second area predicted in step S204, is registered in the management table 31B (step S208). If it is determined that the registration has not been performed (step S208: No), the process proceeds to step S210.

In step S210, the prediction unit 26 identifies the entry E to be released in the management table 31B (step S210) and releases the entry E (step S212).

Next, the prediction unit 26 creates a new entry _{EZ + 1} in the management table 31B, and registers the logical address (page number) of the first area including the second area predicted to be accessed in the future in step S204 (. Step S214). Next, the prediction unit 26 searches the page table for the physical address corresponding to the logical address and registers it in the new entry _{EZ + 1} (step S216).

Next, the prediction unit 26 updates the access information of the second region predicted to be accessed in the future in step S206 in the new entry _{EZ + 1} to the accessed “1” (step S218).

Next, the data in the second region predicted by the transfer unit 28 in step S206 is stored in another type of storage unit 14 or cache memory 16 having a faster access speed by the processing circuit 12 than the storage unit 14 in which the data is stored. Transfer to (step S220).

Then, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred second region in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14 (step S222). Then, this routine is terminated. The page table does not need to be updated at this timing, but may be updated at another timing.

On the other hand, if a negative determination is made in step S206 (step S206: No), the process proceeds to step S224. Even when the affirmative judgment is made in step S208 (step S208: Yes), the process proceeds to step S224.

In step S224, the prediction unit 26 updates the access information of the second region predicted in step S204 in the management table 31B to accessed “1” (step S224).

Next, the transfer unit 28 transfers the data in the second region predicted in step S206 to another type of storage unit 14 or cache memory whose access speed by the processing circuit 12 is faster than that of the storage unit 14 in which the data is stored. Transfer to 16 (step S226).

Next, the transfer unit 28 updates the physical address corresponding to the logical address of the second region transferred in step S226 in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14 (step S228). .. Then, this routine is terminated.

As described above, in the present modification, when the page number of the first area including the second area predicted to be accessed in the future is not registered in the management table 31B, the prediction unit 26 accesses the management table 31B in the future. Then, a new entry E that defines the page number of the first area including the predicted second area is added. Then, the prediction unit 26 registers the logical address and the physical address in the new entry E.

Therefore, when the processing circuit 12 accesses the data in the second region, it is possible to prevent the entry E corresponding to the management table 31B, which also has a function as a TLB, from being present, and it is possible to suppress the occurrence of a TLB error. ..

Therefore, in this modification, in addition to the effect of the above embodiment, the stall time of the processing circuit 12 can be shortened, and the access speed can be increased.

(Modification 2)
The prediction unit 26 corresponds to the identification information (page number) of another first area indicating the logical address (page number) within a predetermined range with respect to the logical address (page number) of the first area to be predicted. The second region to be accessed by the processing circuit 12 in the future may be predicted in the first region to be predicted based on the access management information to be used.

The first region of the prediction target is the first region of the target for predicting the second region to be accessed in the future by the processing circuit 12. The first region to be predicted is not limited. For example, the first area to be predicted is the first area in which the page number is specified in the entry E newly added to the management table 31B. The first region to be predicted is not limited to the newly added entry E.

The logical address within the predetermined range may be the logical address of the page adjacent to the first area to be predicted, or the logical address within the predetermined range with respect to the logical address of the first area to be predicted. It may be a logical address. Within the predetermined range, the difference in page numbers is equal to or less than a predetermined value.

Further, in the other first area indicating the logical address within the predetermined range, the data is stored in the same storage unit 14 as the data in the first area to be predicted, and the logical address of the first area to be predicted is stored. It may be the first area which shows the logical address of a predetermined range with respect to.

20 and 21 are explanatory views of an example of prediction of the second region to be accessed in the future. 20 and 21 show a case where the first region whose page number is defined in the newly registered new entry Ej is used as the first region to be predicted for the second region.

As shown in FIG. 20, for example, it is assumed that the update unit 24 newly registers the entry Ej of the page number “0f06438c” in the management table 31B based on the memory access request acquired from the processing circuit 12.

In this case, the update unit 24 registers the logical address (page number) indicated in the memory access request in the new entry Ej as in the above embodiment. Further, the update unit 24 reads the physical address corresponding to the logical address from the page table and registers it in the entry Ej. In the example shown in FIG. 20, the case where the physical address indicates the physical address of the second storage unit 14B will be described as an example.

Further, the update unit 24 obtains the access information of the access target second area indicated in the memory access request in the new entry Ej (hereinafter, may be referred to as the new entry Ej) in the same manner as in the above embodiment. Update to accessed "1".

When the new entry Ej is registered in the management table 31B, the prediction unit 26 identifies another entry E indicating a logical address within a predetermined range with respect to the logical address of the new entry Ej.

In this modification, it is assumed that the update unit 24 specifies the entry Eh1 and the entry Eh2 in which the physical addresses of the same storage unit 14 (second storage unit 14B in FIG. 20) as the new entry Ej are defined.

Then, the prediction unit 26 will access the second region included in the first region of the new entry Ej in the future according to the pattern indicated by the access information of these identified entries E (entry Eh1 and entry Eh2). Predict the second region.

Specifically, the prediction unit 26 determines whether or not the access management information of the other entries E (entries Eh1 and entry Eh2) indicating the logical addresses within the predetermined range satisfies the predetermined conditions.

Predetermined conditions may be determined in advance. For example, when the other entry E (entry Eh1 and entry Eh2) includes an entry E containing an access information indicating "1" that has been accessed "1" in a predetermined ratio or more, the prediction unit 26 sets a predetermined condition. Judge to meet.

The first threshold value and the predetermined ratio may be predetermined. For example, assume that the first threshold is "8". In this case, the access management information of each of the entry Eh1 and the entry Eh2 shown in FIG. 20 includes eight or more access information of the accessed “1”. Therefore, in this case, the prediction unit 26 determines that the predetermined condition is satisfied.

Then, when it is determined that the predetermined condition is satisfied, the prediction unit 26 determines that the second region of the new entry Ej is obtained from the pattern indicated by the access information defined in the access management information of the entry E (entry Eh1 and entry Eh2). Predict the second area that will be accessed in the future. The method of this prediction is the same as that of the above embodiment.

Then, the prediction unit 26 updates the predicted access information of the second region in the new entry Ej to the accessed "1" in the same manner as in the above embodiment. Therefore, the new entry Ej after being updated by the prediction unit 26 is, for example, as shown in FIG. For example, in the new entry Ej, the access information of the second area C1 is updated to the accessed "1" by the update unit 24, and at least one of the second areas C2 to C16 is updated to the accessed "1" by the prediction unit 26. Will be done.

Then, in this modification, when the prediction unit 26 determines that the predetermined condition is satisfied, the transfer unit 28 stores the data in the first region to be predicted in page units (units of the first region) in the second storage unit 14B. To the first storage unit 14A.

That is, it is assumed that the data in the first region shown in the new entry Ej is stored in the second storage unit 14B. In this case, for example, the transfer unit 28 transfers the data in the first region indicated by the new entry Ej from the second storage unit 14B to the first storage unit 14A in page units.

Further, the transfer unit 28 transfers the data of the second region to be accessed in the future predicted by the prediction unit 26 in the new entry Ej to the cache memory 16 in units of cache lines.

That is, in this modification, when the first area defined by the new entry Ej is first accessed, the prediction unit 26 indicates another accessed entry E (with entry Eh1) indicating a logical address within a predetermined range. If the access management information of the entry Eh2) satisfies the predetermined condition, it is predicted that the new entry Ej will be accessed more than the predetermined number of times. Then, the transfer unit 28 transfers the data of the new entry Ej from the second storage unit 14B to the first storage unit 14A in page units. At the same time, the transfer unit 28 transfers the data of the second region to be accessed in the future predicted by the prediction unit 26 in the new entry Ej to the cache memory 16 in units of cache lines.

Then, the transfer unit 28 updates the physical address shown in the new entry Ej in the management table 31B to the physical address indicating the first storage unit 14A of the transfer destination (in FIG. 21, the physical address of the new entry Ej'). reference). Further, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred first region in the page table to the physical address of the transfer destination first storage unit 14A.

When the prediction unit 26 determines that the above predetermined conditions are not satisfied, the transfer unit 28 transfers the data of the first area including the second area predicted to be accessed in the future in units of cache lines (units of the second area). , It may be transferred to the cache memory 16.

FIG. 22 is an explanatory diagram of an example of data transfer in this modified example. As shown in FIG. 22, in the present modification, with respect to the first area (for example, page A) defined by the entry predicted to have high memory access locality, the transfer unit 28 transfers the data of the page A in page units. Transfers from the second storage unit 14B to the first storage unit 14A. Further, the transfer unit 28 transfers the data of the second region predicted to be accessed in the future on the page A to the cache memory 16 in units of cache lines.

On the other hand, in this modification, for the first area (for example, page B) defined by the entry predicted to have low memory access locality, the transfer unit 28 stores the data of the page B in the second cache line unit. Transfer from unit 14B to cache memory 16.

That is, in this modification, the management device 18 executes the first process and the second process properly for the page A and the page B on the second storage unit 14B (SCM). In other words, the management device 18 executes the first process and the second process in a mixed manner.

The first process will be described. Of page A and page B on the second storage unit 14B (SCM), page A, which is expected to have high memory access locality, is transferred to the first storage unit 14A (DRAM) in page units. Then, the access information of the page A transferred to the first storage unit 14A (DRAM) in the management table 31B is the access information “1” indicating that the access has been completed by the access to the page A by the processing circuit 12 in units of cache lines. Will be updated to. Then, the prediction unit 26 predicts the second region (cash line) that the processing circuit 12 will access in the future according to the pattern indicated by the access information in the management table 31B. Then, the cache line predicted to be accessed in the future in the page A is transferred to the cache memory 16 in units of cache lines. This series of processes is referred to as a first process.

The second process will be described. In the management table 31B, the access information of the page B having low memory access locality that is not transferred to the first storage unit 14A (DRAM) and remains in the second storage unit 14B (SCM) is transferred to the page B by the processing circuit 12. By accessing the cache line unit, the access information "1" indicating that the access has been completed is updated. Then, the prediction unit 26 predicts the second region (cash line) that the processing circuit 12 will access in the future according to the pattern indicated by the access information in the management table 31B. Then, the cache line predicted to be accessed in the future in page B is transferred to the cache memory 16 in units of cache lines. This series of processes is referred to as a second process.

Next, an example of the information processing procedure executed by the information processing device 10 of this modification will be described. FIG. 23 is a flowchart showing an example of the information processing procedure executed by the information processing apparatus 10 of this modified example.

First, the update unit 24 obtains an access target address from the memory access request received from the processing circuit 12 via the access control unit 20 (step S300).

Next, the update unit 24 determines whether or not the entry E including the page number indicated by the address information of the first area indicated in the memory access request received in step S300 is in the management table 31B (step S302). ).

If the entry E is not in the management table 31B (step S302: No), the process proceeds to step S304. In step S304, the update unit 24 identifies and releases the entry to be released in the management table 30A (step S304). Then, the update unit 24 registers the new entry Ej in the management table 31B (step S306).

Next, the prediction unit 26 determines whether the access to the first area (that is, the page) including the second area of the access target shown in the memory access request received in step S300 is the first access to the first area. It is determined whether or not (step PS308). If a negative determination is made in step S308 (step S308: No), the process proceeds to step S326 described later. If an affirmative decision is made in step S308 (step S308: Yes), the process proceeds to step S310.

Next, the prediction unit 26 identifies another entry E (entry Eh1, entry Eh2) indicating a logical address within a predetermined range with respect to the logical address of the new entry Ej (step S310).

Next, the prediction unit 26 determines whether or not the access management information of these entries E (entries Eh1 and entry Eh2) identified in step S310 satisfies a predetermined condition (step S312). If the predetermined condition is not satisfied (step S312: No), the process proceeds to step S326 described later.

When the predetermined condition is satisfied (step S312: Yes), the process proceeds to step S314. In step S314, the prediction unit 26 uses the access control information of the entry E (entry Eh1 and entry Eh2) specified in step S310 to describe the second region in the first region shown in the new entry Ej in the future by the processing circuit 12. Predict the second region to be accessed (step S314).

Then, the prediction unit 26 updates the access information of the second region predicted in step S314 in the new entry Ej to the accessed “1” (step S316).

Next, the transfer unit 28 transfers the data in the first region indicated by the new entry Ej to the first storage unit 14A in page units (step S318). Next, the transfer unit 28 transfers the data in the second region, which is predicted to be accessed in the future in step S314, of the data in the first region to the cache memory 16 in units of cache lines (step S320).

Next, the transfer unit 28 updates the management table 31B and the page table (step S322). Specifically, the transfer unit 28 updates the physical address shown in the new entry Ej in the management table 31B to the physical address indicating the transfer destination storage unit 14 (for example, the first storage unit 14A) in step S318. .. Further, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred first region in the page table to the physical address of the transfer destination storage unit 14 (for example, the first storage unit 14A) in step S318. ..

Next, the update unit 24 is the second access target shown in the memory access request received in step S300 in the entry E that defines the page number indicated by the address information of the address obtained in step S300 in the management table 31B. The access information of the area is updated to the accessed "1" (step S326).

Next, the prediction unit 26 predicts the second region to be accessed in the future by the processing circuit 12 based on the access management information in the management table 31B (step S328).

Then, the prediction unit 26 updates the access information of the second region predicted in step S328 in the management table 31B to the accessed “1” (step S330).

Next, the transfer unit 28 transfers the data in the second area predicted in step S328 to the cache memory 16 in units of cache lines (step S332). That is, when the prediction unit 26 determines that the predetermined condition is not satisfied, the transfer unit 28 transfers the data in the second region predicted to be accessed by the processing circuit 12 in the future from the second storage unit 14B to the cache memory 16 in cache line units. Transfer directly to.

Next, the transfer unit 28 updates the physical address corresponding to the logical address of the second region transferred in step S332 in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14 (step S334). .. Then, this routine is terminated.

As described above, in the present modification, the prediction unit 26 manages access to the logical address of the first region to be predicted, which corresponds to the identification information of the other first region indicating the logical address within the predetermined range. Based on the information, the second region to be accessed by the processing circuit 12 in the future is predicted within the first region to be predicted.

Here, the access tendency by the processing circuit 12 between the first regions indicating the logical addresses within the predetermined range may be approximated. In particular, such a tendency occurs when a large amount of data spanning a plurality of first regions is stored in the storage unit 14.

Therefore, by performing the processing of this modification, the prediction unit 26 can predict the second region to be accessed in the future by the processing circuit 12 with higher accuracy in addition to the effect of the above-described embodiment.

(Modification 3)
FIG. 24 is a schematic view showing an example of the information processing device 10A of this modified example. As shown in FIG. 24, the processing circuit 12A of the information processing device 10A may be configured to include the cache memory 16 and the management device 18. The processing circuit 12A is the same as the processing circuit 12 of the above-described embodiment except that the cache memory 16 and the management device 18 are provided.

(Modification example 4)
FIG. 25 is a schematic view showing an example of the information processing device 10B of this modified example. As shown in FIG. 25, the management device 18A may be configured to include a cache memory 16, an access control unit 20, a management unit 22, and a storage unit 14.

Although the embodiments and modifications of the present invention have been described above, these embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. These novel embodiments and modifications can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

10, 10A, 10B Information processing device 12, 12A Processing circuit 14 Storage unit 16 Cache memory 18, 18A Management device 22 Management unit 24 Update unit 28 Transfer unit 30 Management information storage unit

Claims (23)

A management device that manages access to multiple types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management unit that manages a management table that associates access management information with
A prediction unit that predicts the second region that the processing circuit will access in the future based on the access management information.
When a memory access request is received from the processing circuit, the management table includes an update unit that updates the access information of the second area of the access target indicated in the memory access request to have been accessed.
The prediction unit
In the access management information, the pattern indicated by the access information updated in the first period has priority over the pattern indicated by the access information updated in the second period of the timing prior to the first period. To predict the second region that the processing circuit will access in the future.
Management apparatus. A management device that manages access to multiple types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management unit that manages a management table that associates access management information with
A prediction unit that predicts the second region to be accessed in the future by the processing circuit based on the access management information is provided.
The prediction unit
Among the first regions identified by each of the plurality of identification information shown in the management table, the data is stored in the storage unit of a type in which the access speed by the processing circuit is less than the first speed. With respect to the second region in the first region, the processing circuit will access the second region in the future in preference to the first region in which data is stored in the storage unit of the type of access speed equal to or higher than the first speed. Predict the second region to be
Management device. A management device that manages access to multiple types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management unit that manages a management table that associates access management information with
A prediction unit that predicts the second region that the processing circuit will access in the future based on the access management information.
A transfer unit for transferring the data in the second region predicted by the prediction unit to another type of storage unit having a faster access speed by the processing circuit than the storage unit in which the data is stored is provided. ,
The prediction unit
The processing circuit is based on the access management information corresponding to other identification information of the first region indicating a logical address within a predetermined range with respect to the identification information of the first region to be predicted in the management table. Predict the second area that will be accessed in the future,
Management apparatus. The plurality of types of the storage units are
Access speeds are different from each other,
The management device according to any one of claims 1 to 3 . The pattern is represented by a positional relationship in the storage unit of the second region in which the access information indicating access has been defined.
The management device according to claim 1 . The prediction unit
The second region to be accessed in the future by the processing circuit is predicted according to the pattern indicated by the plurality of access information including the access information updated immediately before by the update unit in the access management information.
The management device according to claim 1 . The prediction unit
According to the pattern indicated by the access information updated in a certain period of time in the access management information, the second region to be accessed in the future by the processing circuit is predicted.
The management device according to claim 1 . The prediction unit
When the predicted identification information of the first area including the second area is not registered in the management table,
A new entry including the identification information of the first area is added to the management table, and the identification information and the physical address of the first area are registered in the entry.
The management device according to any one of claims 1 to 3 . The prediction unit
The predicted access information of the second area in the management table is updated as accessed.
The management device according to any one of claims 1 to 8 . The plurality of types of the storage units include a first storage unit and a second storage unit having a slower access speed than the first storage unit.
The prediction unit
When the access management information corresponding to the other identification information of the first region indicating the logical address within the predetermined range with respect to the identification information of the first region to be predicted in the management table satisfies the predetermined condition, the said. Based on the access management information corresponding to the identification information, the second region to be accessed in the future by the processing circuit is predicted.
The transfer unit
When it is determined that the predetermined condition is satisfied, the data of the first region to be predicted is transferred from the second storage unit to the first storage unit in units of the first region.
The management device according to claim 3 . The prediction unit
The number of the second area in which the access information indicating that the access has been completed is defined in the other first area indicating the logical address within the predetermined range with respect to the identification information of the first area to be predicted is the first threshold value. When the above-mentioned first region is included in a predetermined ratio or more, it is determined that the predetermined condition is satisfied.
The management device according to claim 10 . The plurality of types of the storage units include a cache memory, the first storage unit having a slower access speed than the cache memory, and the second storage unit.
The transfer unit
When the prediction unit determines that the predetermined condition is satisfied, the data in the second region predicted to be accessed by the processing circuit in the future is transferred to the cache memory.
The management device according to claim 10 or 11 . The transfer unit
When the prediction unit determines that the predetermined condition is not satisfied, the data in the second region predicted to be accessed by the processing circuit in the future is directly transmitted from the second storage unit to the cache memory in units of the second region. Forward,
The management device according to claim 12 . The management table is
For each of the logical address as the identification information of the first region, the physical address of the first region in the storage unit, and the plurality of second regions included in the first region, the second region is described. The access management information that defines the access information indicating whether or not the access has been made by the processing circuit is associated with the access management information.
The management device according to any one of claims 1 to 13 . With the processing circuit
With multiple types of storage
A management device that manages access to a plurality of types of the storage units, and
With
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The management device is
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management unit that manages a management table that associates access management information with
A prediction unit that predicts the second region that the processing circuit will access in the future based on the access management information.
When a memory access request is received from the processing circuit, the management table includes an update unit that updates the access information of the second area of the access target indicated in the memory access request to have been accessed.
The prediction unit
In the access management information, the pattern indicated by the access information updated in the first period has priority over the pattern indicated by the access information updated in the second period of the timing prior to the first period. To predict the second region that the processing circuit will access in the future.
Information processing apparatus. With the processing circuit
With multiple types of storage
A management device that manages access to a plurality of types of the storage units, and
With
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The management device
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management unit that manages a management table that associates access management information with
A prediction unit that predicts the second region to be accessed in the future by the processing circuit based on the access management information is provided.
The prediction unit
Among the first regions identified by each of the plurality of identification information shown in the management table, the data is stored in the storage unit of a type in which the access speed by the processing circuit is less than the first speed. With respect to the second region in the first region, the processing circuit will access the second region in the future in preference to the first region in which data is stored in the storage unit of the type of access speed equal to or higher than the first speed. Predict the second region to be
Information processing device. With the processing circuit
With multiple types of storage
A management device that manages access to a plurality of types of the storage units, and
With
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The management device
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management unit that manages a management table that associates access management information with
A prediction unit that predicts the second region that the processing circuit will access in the future based on the access management information.
A transfer unit for transferring the data in the second region predicted by the prediction unit to another type of storage unit having a faster access speed by the processing circuit than the storage unit in which the data is stored is provided. ,
The prediction unit
The processing circuit is based on the access management information corresponding to other identification information of the first region indicating a logical address within a predetermined range with respect to the identification information of the first region to be predicted in the management table. Predict the second area that will be accessed in the future,
Information processing device. It is a management method in a management device that manages access to a plurality of types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management step that manages a management table that associates access management information with
A prediction step for predicting the second region to be accessed in the future by the processing circuit based on the access management information.
When a memory access request is received from the processing circuit, the management table includes an update step of updating the access information of the second region of the access target indicated in the memory access request to access.
The prediction step
In the access management information, the pattern indicated by the access information updated in the first period has priority over the pattern indicated by the access information updated in the second period of the timing prior to the first period. To predict the second region that the processing circuit will access in the future.
Management method. It is a management method in a management device that manages access to a plurality of types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management step that manages a management table that associates access management information with
Includes a prediction step that predicts the second region that the processing circuit will access in the future based on the access management information.
The prediction step
Among the first regions identified by each of the plurality of identification information shown in the management table, the data is stored in the storage unit of a type in which the access speed by the processing circuit is less than the first speed. With respect to the second region in the first region, the processing circuit will access the second region in the future in preference to the first region in which data is stored in the storage unit of the type of access speed equal to or higher than the first speed. Predict the second region to be
Management method. It is a management method in a management device that manages access to a plurality of types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management step that manages a management table that associates access management information with
A prediction step for predicting the second region to be accessed in the future by the processing circuit based on the access management information.
A transfer step of transferring the data in the second region predicted by the prediction step from the storage unit in which the data is stored to another type of storage unit having a faster access speed by the processing circuit is included. ,
The prediction step
The processing circuit is based on the access management information corresponding to other identification information of the first region indicating a logical address within a predetermined range with respect to the identification information of the first region to be predicted in the management table. Predict the second area that will be accessed in the future,
Management method. It is a program to be executed by a computer that manages access to multiple types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management step that manages a management table that associates access management information with
A prediction step for predicting the second region to be accessed in the future by the processing circuit based on the access management information.
When the memory access request is received from the processing circuit, the computer updates the access information of the second area of the access target indicated by the memory access request in the management table to be accessed. To run
The prediction step
In the access management information, the pattern indicated by the access information updated in the first period has priority over the pattern indicated by the access information updated in the second period of the timing prior to the first period. To predict the second region that the processing circuit will access in the future.
Program. It is a program to be executed by a computer that manages access to multiple types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management step that manages a management table that associates access management information with
Based on the access management information, the computer is made to perform a prediction step of predicting the second region to be accessed in the future by the processing circuit.
The prediction step
Among the first regions identified by each of the plurality of identification information shown in the management table, the data is stored in the storage unit of a type in which the access speed by the processing circuit is less than the first speed. With respect to the second region in the first region, the processing circuit will access the second region in the future in preference to the first region in which data is stored in the storage unit of the type of access speed equal to or higher than the first speed. Predict the second region to be
program. It is a program to be executed by a computer that manages access to multiple types of storage units by a processing circuit.
The storage unit includes a plurality of first regions, and the first region includes a plurality of second regions.
The identification information of the first region and the access information indicating whether or not the second region has been accessed by the processing circuit are defined for each of the plurality of second regions included in the first region. A management step that manages a management table that associates access management information with
A prediction step for predicting the second region to be accessed in the future by the processing circuit based on the access management information.
The transfer step of transferring the data in the second region predicted by the prediction step from the storage unit in which the data is stored to another type of storage unit having a faster access speed by the processing circuit. Let the computer run
The prediction step
The processing circuit is based on the access management information corresponding to other identification information of the first region indicating a logical address within a predetermined range with respect to the identification information of the first region to be predicted in the management table. Predict the second area that will be accessed in the future,
program.

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