JP2019164497A - Management device, information processing device, management method, and program - Google Patents

Abstract

To highly accurately predict data to be accessed by a processing circuit in the future.SOLUTION: A management device 18 manages accesses to a plurality of kinds of storage units 14 by a processing circuit 12. The storage unit 14 includes a plurality of first regions, and the first region includes a plurality of second regions. The management device 18 includes a management unit (management information storage unit 30)and a prediction unit 26. The management unit (management information storage unit 30) manages a management table 31. The management table 31 is a table associating identification information of the first region with access management information specifying access information indicating whether or not the processing circuit 12 has already accessed the second region for each of the plurality of second regions included in the first region. The prediction unit 26 predicts the second region to be accessed by the processing circuit 12 in the future on the basis of the access management information.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a management apparatus, an information processing apparatus, a management method, and a program.

  Various storage class memories (SCM) such as MRAM (Magnetic Resistive Random Access Memory), ReRAM (Resistive RAM), and PCM (Phase-Change Memory) have been developed. The SCM has a slower access speed than a DRAM (Dynamic Random Access Memory), but can be used as a large-capacity main memory due to its high degree of integration. When the SCM is installed in addition to the conventional DRAM as the main memory of the computer system, when the CPU accesses the SCM, the data arrival waiting time of the CPU becomes longer than when the DRAM is used, and the access speed is increased. This results in an increase in processing time.

  Therefore, it is conceivable to predict data to be accessed in the future by a processing circuit such as a CPU, and transfer the data to a memory that can be accessed at a higher speed before the access, thereby shortening the data arrival waiting time and speeding up the processing. However, conventionally, it has been difficult to predict with high accuracy the data that the processing circuit will access in the future. For example, conventionally, a method has been disclosed in which information indicating whether access has been completed is recorded in a page table in units of pages. However, which area in the page is accessed is not managed, and it has been difficult for the conventional technology to predict data to be accessed in the future by the processing circuit with high accuracy.

Computer Organization and Design RISC-V Edition, David A. Patterson & John L. Hennessy, Morgan Kaufmann Publishers, ISBN 978-0-12-812275-4, 5.7 Virtual Memory.

  The problem to be solved by the present invention is to provide a management device, an information processing device, a management method, and a program capable of accurately predicting data to be accessed in the future by a processing circuit.

  The management apparatus according to the embodiment manages access to a plurality of types of storage units by a processing circuit. The storage unit includes a plurality of first areas, and the first area includes a plurality of second areas. The management device includes a management unit and a prediction unit. The management unit manages the management table. The management table indicates whether the second area has been accessed by the processing circuit for each of the identification information of the first area and each of the plurality of second areas included in the first area. It is the table which matched the access management information which prescribed | regulated information. The prediction unit predicts the second area that the processing circuit will access in the future based on the access management information.

1 is a schematic diagram of an information processing apparatus. Explanatory drawing of the access to a memory | storage part. Schematic diagram of physical address space. The schematic diagram which shows the data structure of a management table. The schematic diagram which shows the data structure of a management table. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. The flowchart of the procedure of information processing. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. The flowchart of the procedure of information processing. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of prediction of a 2nd area | region. Explanatory drawing of data transfer. The flowchart of the procedure of information processing. 1 is a schematic diagram of an information processing apparatus. 1 is a schematic diagram of an information processing apparatus.

  Details of the present embodiment will be described below with reference to the accompanying drawings.

  FIG. 1 is a schematic diagram illustrating an example of the configuration of the information processing apparatus 10 according to the present embodiment. The information processing apparatus 10 includes a processing circuit 12, a storage unit 14, a cache memory 16, and a management device 18.

  The processing circuit 12 and the cache memory 16, the cache memory 16 and the management device 18, the processing circuit 12 and the management device 18, and the management device 18 and the storage unit 14 are connected so as to be able to exchange data and signals.

  The processing circuit 12 has one or more processors. The processor is, for example, a CPU (Central Processing Unit). The processor may include one or more CPU cores. The processing circuit 12 reads data from the storage unit 14 and writes data to the storage unit 14 in accordance with execution of the program.

  The processing circuit 12 and the management device 18 temporarily store the data stored in the storage unit 14 in the cache memory 16 and use it for processing.

  The storage unit 14 is a main memory used as a work area by the processing circuit 12. The information processing apparatus 10 according to the present embodiment includes a plurality of types of storage units 14. That is, the information processing apparatus 10 according to the present embodiment uses a plurality of types of storage units 14 as a main memory.

  The plurality of types of storage units 14 have different access speeds by the processing circuit 12. Hereinafter, the access speed by the processing circuit 12 may be simply referred to as an access speed.

  In the present embodiment, the information processing apparatus 10 includes a first storage unit 14A and a second storage unit 14B as a plurality of types of storage units 14 having different access speeds. Note that the information processing apparatus 10 may be configured to include three or more types of storage units 14.

  The first storage unit 14A is, for example, a volatile memory. Specifically, the first storage unit 14A is a DRAM (Dynamic Random Access Memory). The first storage unit 14A may be a non-volatile memory such as an MRAM (Magnetic Resistive Random Access Memory) that can be accessed at high speed.

  The second storage unit 14B has a slower access speed than the first storage unit 14A. The capacity of the second storage unit 14B is the same as or larger than the capacity of the first storage unit 14A.

  The second storage unit 14B is, for example, a nonvolatile memory. Specifically, the second storage unit 14B is a large-capacity high-speed non-volatile memory (Non-volatile Memory) having a higher degree of integration and a larger capacity than DRAM.

  More specifically, the second storage unit 14B is a memory called a storage class memory (SCM). For example, MRAM, PCM (Phase Change Memory), PRAM (Phase Random Access Memory), PCRAM (Phase Change Random Access Memory), ReRAM (Resistance Change Random Access Memory), FeRAM (Ferroelectric Random Access Memory), 3DXPoint or Memristor etc. is there.

  In the present embodiment, a case where the first storage unit 14A is a DRAM and the second storage unit 14B is an SCM will be described as an example. The access speed of the first storage unit 14A only needs to be higher than that of the second storage unit 14B, and these combinations are not limited to the form in which the first storage unit 14A is a DRAM and the second storage unit 14B is an SCM. For example, the first storage unit 14A may be an MRAM, and the second storage unit 14B may be a ReRAM.

  FIG. 2 is an explanatory diagram of a method of accessing the first storage unit 14A and the second storage unit 14B. When an SCM is installed as a main memory of a computer system in addition to a conventional DRAM, it is necessary to properly use both. In other words, the SCM has a larger capacity than the DRAM but has a slower access speed. For this reason, efficient data processing can be performed by well distributing the memory in which data is arranged in the DRAM and SCM in accordance with the characteristics of the data to be processed. That is, it is desirable that data with low access locality and large size is placed in the SCM, and the processor directly accesses the SCM in units of cache lines. Further, it is desirable that data with high access locality is transferred from the SCM to the DRAM in units of pages, and the processor accesses the data on the DRAM in units of cache lines.

  Returning to FIG. Note that when the first storage unit 14A and the second storage unit 14B are collectively described, they are simply referred to as the storage unit 14 for description.

  The storage unit 14 includes a plurality of first areas. In the present embodiment, a mode in which the first storage unit 14A and the second storage unit 14B include a plurality of first regions will be described. The first area includes a plurality of second areas. In other words, in the present embodiment, the processing circuit 12 and the management device 18 divide the first storage unit 14A and the second storage unit 14B into units of the first region or a second region obtained by further dividing the first region. Manage by unit.

  FIG. 3 is a schematic diagram showing a physical address space viewed from the processing circuit 12.

  As shown in FIG. 3, each of the first storage unit 14A and the second storage unit 14B includes a plurality of first regions.

  The first area is, for example, a data management unit (for example, page) by the processing circuit 12 or an OS (Operating System) operating on the processing circuit. For example, 4 KB. Note that the first area may be a unit of a predetermined number of data management units by the processing circuit 12 or the OS operating on the processing circuit. In the present embodiment, a case where the first region corresponds to a page will be described as an example.

  The second area is an area smaller than the first area. For example, the second area is a unit in which the processing circuit 12 reads and writes data on the storage unit 14. Specifically, the second area is a cache line unit. That is, the processing circuit 12 accesses the first storage unit 14A or the second storage unit 14B in units of cache lines.

  The cache line is, for example, 64 bytes. The second area may be a unit (for example, byte unit) smaller than the cache line.

  In the present embodiment, the processing circuit 12 and the management device 18 determine the area in the first storage unit 14A and the second storage unit 14B mapped in the physical address space 15 shown in FIG. , Page size). And the processing circuit 12 and the management apparatus 18 implement | achieve virtual memory by converting from a logical address to a physical address using a page table.

  Further, in the present embodiment, the processing circuit 12 and the management device 18 divide the first area into the size of the second area (for example, a cache line) and manage each of the second areas.

  As described above, the information processing apparatus 10 according to the present embodiment manages each of the plurality of types of storage units 14 for each second area (for example, cache line) that is a unit smaller than the first area (for example, page unit). It is configured to be possible.

  In addition, the information processing apparatus 10 of this Embodiment demonstrates as an example the case where it combines as 1st memory | storage part 14A and 2nd memory | storage part 14B, and is used as a main memory as multiple types of memory | storage parts used by this invention.

  Returning to FIG. 1, the description will be continued. The management device 18 manages access by the processing circuit 12 to a plurality of types of storage units 14. The management device 18 is, for example, a memory management unit (MMU: Memory Management Unit).

  The management device 18 includes an access control unit 20 and a management unit 22. The management unit 22 includes an update unit 24, a prediction unit 26, a transfer unit 28, and a management information storage unit 30.

  The access control unit 20 processes the memory access request received from the processing circuit 12. The memory access request is a memory access request for the storage unit 14. The memory access request indicates data writing to the storage unit 14 or data reading from the storage unit 14.

  The access control unit 20 accesses the storage unit 14 when the access target data indicated by the memory access request received from the processing circuit 12 is not stored in the cache memory 16. In this case, the access control unit 20 accesses the second area in the access target storage unit 14 indicated by the memory access request received from the processing circuit 12. Then, the management device 18 executes processing (write or read) indicated by the memory access request for the accessed second area.

  Next, the management unit 22 will be described. The management unit 22 manages the management table 31A. The management table 31A is an example of the management table 31. FIG. 4 is a schematic diagram illustrating an example of a data configuration of the management table 31A.

  The management table 31A is a table in which identification information of the first area is associated with access management information. That is, a plurality of entries E in which the identification information of the first area and the access management information are associated on a one-to-one basis are registered in the management table 31A.

  The identification information of the first area is information for identifying the first areas of the first storage unit 14A and the second storage unit 14B.

  In the present embodiment, as described above, a case where the first area corresponds to a page will be described. For this reason, in this Embodiment, the case where the identification information of a 1st area | region is a page number is demonstrated as an example. In the following description, the identification information of the first area may be referred to as a page number.

  In the present embodiment, the identification information of the first area registered in the management table 31A is represented by a logical address. That is, in the present embodiment, the identification information of the first area is represented by a page number in the logical address space. For this reason, in the information processing apparatus 10, by specifying the physical address corresponding to the logical address in the page table, the page number shown in the management table 31A can be stored in any type of storage unit 14 (the first storage unit 14A, the first storage unit 14A). 2) It is possible to specify whether to indicate the page number in the storage unit 14B).

  The access management information defines access information for each of a plurality of second areas included in the first area identified by the corresponding page number.

  The access information is a flag indicating whether or not the second area has been accessed by the processing circuit 12. In the example illustrated in FIG. 4, the access information “0” indicates a second area that has not been accessed by the processing circuit 12. The access information “1” indicates the second area that has been accessed by the processing circuit 12.

  FIG. 4 shows an example in which 16 cache lines as second areas are assigned to one page (one first area). For example, assume that the size of one page (first area) is 4K bytes. Further, it is assumed that the size of the cache line which is the second area is 64 bytes. In this case, one first region has 64 second regions. In the management table 31A, access management information that defines access information for each of the 64 second areas is defined for each first area identified by the page number.

  The management table 31B may be used instead of the management table 31A. The management table 31B is an example of the management table 31.

  FIG. 5 is a schematic diagram illustrating an example of a data configuration of the management table 31B. The management table 31B is obtained by further associating a physical address with the management table 31A. Specifically, the management table 31B has a configuration in which a logical address as identification information of the first area, a physical address of the first area in the storage unit 14, and access management information are associated with each other. In this case, the management information storage unit 30 may store the management table 31B instead of the management table 31A (see FIG. 1).

  By using the management table 31B having the data configuration shown in FIG. 5, the management table 31A (see FIG. 4) and the TLB (Translation Lookaside Buffer) functioning as a page table cache can be integrated and managed. That is, the processing circuit 12 can search both the physical address of the TLB and the access management information of each second area by using the logical address as a search key. Therefore, by using the management table 31B, it is possible to provide hardware for associative memory that searches the entry E using the page number represented by the logical address as a search key. The entry E in the management table 31B is a one-to-one correspondence between logical addresses, physical addresses, and access management information.

  Returning to FIG. The management unit 22 includes an update unit 24, a prediction unit 26, a transfer unit 28, and a management information storage unit 30.

  The management information storage unit 30 stores a management table 31A or a management table 31B. That is, the management information storage unit 30 is an example of a management unit of the present invention. In the present embodiment, a case where the management table 31A (see FIG. 4) is used as the management table 31 will be described as an example.

  The update unit 24 updates the management table 31 </ b> A when a memory access request is received from the processing circuit 12. More specifically, the update unit 24 accesses the access information of the second area to be accessed indicated by the memory access request corresponding to the page number indicating the first area to be accessed indicated by the memory access request in the management table 31A. Is updated to “1”. Note that the initial value of the access information in the management table 31A is “0” which is not accessed, and is updated to “1” which has been accessed by the updating unit 24.

  Specifically, it is assumed that the access target data indicated in the memory access request received from the processing circuit 12 is not stored in the cache memory 16. In this case, the access control unit 20 accesses the storage unit 14 based on the memory access request. Then, the update unit 24 receives the memory access request from the access control unit 20.

  Then, the update unit 24 updates the access information of the second area accessed by the processing circuit 12 from “0” not accessed to “1” accessed based on the received memory access request.

  Note that the update unit 24 changes the access information of the second area accessed by the processing circuit 12 from the unaccessed “0” to the accessed “1” only when the memory access request indicates data writing to the storage unit 14. May be updated. Also, the update unit 24 changes the access information of the second area accessed by the processing circuit 12 from the unaccessed “0” to the accessed “1” only when the memory access request indicates reading of data from the storage unit 14. May be updated. In addition, when the memory access request indicates data writing to the memory unit 14 or data reading from the memory unit 14, the update unit 24 sets the access information of the second area accessed by the processing circuit 12 to the access not “0”. "1" may be updated to "1" already accessed.

  In this way, the update unit 24 updates the access information in the management table 31A every time the processing circuit 12 performs an access such as reading data from the storage unit 14 or writing data.

  Therefore, the access management information in the management table 31A indicates what pattern the memory access request has issued to the second area in the first area identified by the page number. It will be.

  Note that the page number indicated by the logical address of the first area indicated in the memory access request may not exist in the management table 31A. That is, the entry E of the first area to be accessed indicated in the memory access request may not exist in the management table 31A.

  In this case, the update unit 24 needs to create a new entry E and register it in the management table 31A. Here, there is an upper limit to the number of entries registered in the management table 31A. For this reason, when there is no empty entry E in the management table 31A, the update unit 24 may release any entry E registered in the management table 31A and create a new entry E.

  A known method may be used as a method for specifying the entry E to be released. For example, the update unit 24 preferably specifies the entry E to be released using an algorithm such as LRU (Least Recently Used). By using this method, the updating unit 24 can specify the entry E that is least used, the entry E that has not been used for a long time, or the entry E that is not frequently referenced as the entry E to be released.

  Then, the update unit 24 registers the page number of the first area indicated in the accepted memory access request in the newly created entry E. Then, the updating unit 24 registers “0” as no access as the access information of all the second areas in the access management information corresponding to the page number in the entry E. Then, the update unit 24 may update the access information of the second area to be accessed indicated in the memory access request in the newly created entry E to “1” that has been accessed. In the following description, the newly created entry E may be simply referred to as a new entry E.

  The prediction unit 26 predicts a second area that the processing circuit 12 will access in the future based on the access management information in the management table 31A. The second area to be accessed in the future refers to a second area predicted to be accessed by the processing circuit 12 at a timing in the future (after the present) from the present.

  Then, the prediction unit 26 updates the access information of the second area predicted to be accessed in the management table 31A to “1” that has been accessed.

  Note that the timing of prediction by the prediction unit 26 is not limited.

  For example, the prediction unit 26 predicts a second region to be accessed in the future every time the update unit 24 updates the access information of the second region in the management table 31 </ b> A to the accessed “1”. In this case, for example, based on the access management information corresponding to the page number of the first area including the second area where the access information is updated, the predicting unit 26 sets the unaccessed “0” in the first area. Any one of the indicated second areas is predicted as a second area to be accessed in the future.

  In addition, for example, the prediction unit 26 may predict a second area that the processing circuit 12 will access in the future at every predetermined period.

  In this case, the prediction unit 26 determines that the access is not performed based on the access information of the second area included in each of the first areas identified by each of the page numbers defined in the management table 31A for each predetermined period. Any one of the second areas indicating “0” may be predicted as a second area to be accessed in the future.

  Further, the prediction unit 26 predicts the second area to be accessed in the future at both the timing when the access information in the management table 31A is updated to “1” that has been accessed by the update unit 24 and every predetermined period. Also good.

  The prediction by the prediction unit 26 will be specifically described.

  For example, the prediction unit 26 predicts the second area that the processing circuit 12 will access in the future, according to the pattern indicated by the access information in the management table 31A.

  The pattern indicated by the access information indicates an access pattern to the storage unit 14 by the processing circuit 12. Specifically, the pattern is represented by the positional relationship in the storage unit 14 of one or more second areas in which access information indicating accessed “1” is defined. For example, the pattern indicated by the access information indicates the regularity of the access information indicating “1” being accessed. Specifically, the pattern indicated by the access information is represented by at least one of the continuity of the arrangement of the access information indicating the accessed “1” and the arrangement interval. However, the present invention is not limited to this.

  For example, when prediction is performed every time the access information of the second area in the management table 31A is updated by the update unit 24, the prediction unit 26 uses the pattern indicated by the access information to perform prediction using the following method. Do.

  For example, in the access management information of the management table 31A, the prediction unit 26 is the first to be accessed in the future by the processing circuit 12 according to the pattern indicated by the plurality of access information including the access information updated immediately before by the update unit 24. Predict two regions.

  6 and 7 are explanatory diagrams of an example of prediction of the second area to be accessed in the future.

  As shown in FIG. 6, for example, it is assumed that the access information of the second area C3 that is third from the start address in the first area whose page number is defined in the entry E1 is updated by the updating unit 24. At this time, it is assumed that the access information is continuously accessed “1” from the first second area C1 to the second area C3 updated immediately before.

  In this case, the prediction unit 26 specifies a pattern in which accessed “1” s are continuously arranged from the first second area C1 toward the second area C3 updated immediately before. Then, the predicting unit 26 predicts that the same pattern as the identified pattern is also indicated in the address information of the second area after the second area C3. That is, the predicting unit 26 predicts that the accessed “1” is continued at the same interval as the specified pattern in the other second regions (second region C4 to second region C16) that are continuous to the second region C3. Therefore, the prediction unit 26 predicts the second region C4 to the second region C16 in the entry E1 as second regions that the processing circuit 12 will access in the future.

  Then, the prediction unit 26 updates the predicted access information of the second area to “1”. For example, the access management information of the entry E ′ after the prediction is in the state shown in FIG. 6 (see the entry E1 ′ in FIG. 6).

  In FIG. 6, the prediction unit 26 accesses all the second areas (second area C4 to second area C16) continuous after the second area C3 updated immediately before in the entry E1 in the future. The case of predicting as the second region is shown.

  However, the number of second regions predicted by the prediction unit 26 is not limited. For example, the prediction unit 26 may predict only one second region C4 adjacent to the second region C3 updated immediately before by the update unit 24 as a second region that the processing circuit 12 will access in the future. Further, the prediction unit 26 predicts a predetermined number of second regions (for example, the second region C4 to the second region C5) adjacent to the second region C3 as second regions that the processing circuit 12 will access in the future. Also good. Further, the prediction unit 26 may predict a second area that the processing circuit 12 will access in the future over a plurality of first areas.

  Further, as shown in FIG. 7, it is assumed that the updating unit 24 updates the access information of the second area C7, which is the seventh area from the top address, in the first area where the page number is defined in the entry EX of the management table 31A. Assume. At this time, it is assumed that every second access information is accessed “1” from the first second area C1 to the second area C7 updated immediately before.

  In this case, the predicting unit 26 specifies a pattern in which accessed “1” is arranged for each of the two second areas from the first second area C1 to the second area C7 updated immediately before. Then, the prediction unit 26 predicts that the same pattern as the identified pattern is also indicated in the address information of the second area after the second area C7. That is, the predicting unit 26 has already accessed the other second regions (second region C8 to second region C16) that follow the second region C7 every two second regions at the same interval as the specified pattern. Predict that “1” is placed. For this reason, in this case, the prediction unit 26 predicts the second area C10, the second area C13, and the second area C16 in the entry EX as a second area to be accessed in the future.

  Then, the prediction unit 26 updates the predicted access information of the second area to “1”. For example, the access management information of the entry E ′ after the prediction is in the state shown in FIG. 7 (see the entry EX ′ in FIG. 7).

  In addition, for example, the prediction unit 26 may predict the second area that the processing circuit 12 will access in the future according to the pattern indicated by the access information updated in a certain period in the access management information. The fixed period is a period from the timing at which the update unit 24 updates the access information to a timing that is a predetermined time later than the reference timing. This fixed period may be determined in advance.

  8 and 9 are explanatory diagrams of an example of predicting the second area to be accessed in the future.

  As shown in FIG. 8, for example, it is assumed that access information of the second area C3 that is the third from the start address in the first area whose page number is defined in the entry E1 is updated by the updating unit 24. At this time, it is assumed that the first second area C1 and the next second area C2 have been updated to “1” that has been accessed within a certain period T that goes back from the update timing of the second area C3.

  In this case, the prediction unit 26 identifies a pattern in which accessed “1” s are continuously arranged as a pattern represented by the access information updated within the immediately preceding fixed period T. Then, the prediction unit 26 predicts that the same pattern as the identified pattern is also indicated in the address information of the second area after the second area C4. That is, the predicting unit 26 predicts that the accessed “1” is continued at the same interval as the specified pattern in the other second regions (second region C4 to second region C16) that are continuous to the second region C3. Therefore, the prediction unit 26 predicts the second area C4 to the second area C16 in the entry E1 as second areas to be accessed in the future.

  Then, the prediction unit 26 updates the predicted access information of the second area to “1”. The access management information of the entry E ′ after the prediction is in the state shown in FIG. 8, for example (see the entry E1 ′ in FIG. 8).

  Note that the prediction unit 26 may not perform prediction when there is no access information updated in a certain period.

  For example, as illustrated in FIG. 9, it is assumed that, for example, the update unit 24 updates the access information of the second area C3 that is the third from the start address in the first area that is defined by the page number in the entry EY. . At this time, the first second area C1 and the next second area are not in a fixed period T that goes back from the update timing of the second area C3, but in a period T ′ that is earlier (past) timing than the fixed period T. Assume that C2 has been updated to accessed “1”.

  In this case, the prediction unit 26 regards the access by the processing circuit 12 to the second area C1 and the second area C2 and the current access to the second area C3 as separate events. Then, the prediction unit 26 does not predict the second area C4 and the subsequent entries of the entry EY as the second area to be accessed in the future. Therefore, in this case, the access management information of the entry EY ′ after prediction has the same contents as the entry EY before prediction, as shown in FIG.

  On the other hand, when the prediction is performed every predetermined period, the prediction unit 26 may perform the prediction by the following method using the pattern indicated by the access information.

  For example, in accordance with the number of second areas that have been updated to “1” that has been accessed within a certain period in the management table 31A, the prediction unit 26 determines the number of second areas that match or are close to the number. This is predicted as a second area to be accessed in the future.

  Here, the prediction unit 26 specifies a plurality of fixed periods for the access management information in the management table 31A, and uses the pattern indicated by the access information for the fixed periods for each specified fixed period to access in the future. The second region to be predicted may be predicted.

  For example, the prediction unit 26 uses the access information updated in the second period at a timing before the first period to change the pattern indicated by the access information updated in the first period in the access management information of the management table 31A. A second area to be accessed in the future by the processing circuit 12 is predicted by giving priority to the pattern shown.

  Further, the prediction unit 26 specifies a period in which more access information is updated to “1” that has been accessed within the unit time in the first period and the second period. Then, the prediction unit 26 may predict a second area to be accessed in the future by preferentially using the pattern indicated by the access information in the specified period (first period or second period).

  Note that using preferentially means that the prediction or the transfer of the predicted and predicted data in the second area to the other storage unit 14 is executed first. In addition, use with priority may mean that only the higher priority is predicted and the lower priority is not predicted. Further, using preferentially may mean that only a higher priority is predicted and data transferred, and a lower priority is not predicted and data transferred. Note that the transfer of the predicted data in the second area is performed by the transfer unit 28 described later (details will be described later).

  This will be specifically described with reference to FIGS. 10 to 12 are explanatory diagrams illustrating an example of prediction of the second area to be accessed in the future.

  As shown in FIG. 10, for example, the access information of the second area C1 to the second area C3 in the first area whose page number is defined in the entry E1 of the management table 31A has been accessed within the first period T1. Assume that it has been updated to “1”. It is assumed that the timing at which the access information of each of the second area C1 to the second area C3 is updated to the accessed “1” is the timing t3 to t5 in the first period T1.

  On the other hand, as shown in FIG. 11, the access information of the second area C1 to the second area C3 in the first area whose page number is defined in the entry EZ of the management table 31A has been accessed within the second period T2. Assume that it has been updated to “1”. It is assumed that the timing at which the access information of each of the second area C1 to the second area C3 is updated to “1” that has been accessed is the timing t0 to t2 in the second period T2.

  These timings t0 to t5 are represented by the time series shown in FIG. That is, the timing t0 is the oldest and approaches the current timing T0 toward the timing t5. In addition, the second period represented by the timings t0 to t2 is longer than the first period represented by the timings t3 to t5. For this reason, the number of updates of access information per unit time in the first period T1 is larger than that in the second period T2. The second period T2 is a timing before the first period T1.

  In this case, first, the prediction unit 26 specifies a pattern indicated by the access information updated in each period for each of the first period T1 and the second period T2 in the access management information of the management table 31A. Then, the prediction unit 26 predicts a second area to be accessed in the future by using the pattern indicated by the access information in the first period T1 with priority over the pattern indicated by the access information in the second period T2.

  Specifically, as illustrated in FIG. 10, the prediction unit 26 determines the second in accordance with the pattern indicated by the access information of the second area C1 to the second area C3 updated in the first period T1 in the entry E1. Three second regions C4 to C6 adjacent to the region C3 are predicted as second regions to be accessed in the future.

  Then, the prediction unit 26 updates the predicted access information of the second area to “1”. The access management information of the entry E1 'after the prediction is in the state shown in FIG. 10 (see entry E1' in FIG. 10).

  Next, as illustrated in FIG. 11, the prediction unit 26 determines whether the second area C2 corresponds to the pattern indicated by the access information of the second area C1 to the second area C3 updated in the second period T2 in the entry EZ. A second area C4 adjacent to C3 is predicted as a second area to be accessed in the future.

  Then, the prediction unit 26 updates the predicted access information of the second area to “1”. The access management information of the entry EZ ′ after the prediction is in the state shown in FIG. 11 (see the entry EZ ′ in FIG. 11).

  In addition, about the access information of 2nd period T2 with a low priority, the estimation part 26 does not need to use as a pattern used for prediction. In this case, the prediction unit 26 may not predict the second area to be accessed in the future for the entry EZ illustrated in FIG.

  Further, for example, the prediction unit 26 stores in the storage unit 14 of a type in which the access speed by the processing circuit 12 is less than the first speed in the first area identified by each of the plurality of page numbers shown in the management table 31A. For the second area in the first area in which data is stored, the first area in which data is stored in the storage unit 14 having the access speed type equal to or higher than the first speed is preferentially accessed in the future. The second region may be predicted.

  The processing circuit 12 gives priority to the data in the second area stored in the storage unit 14 having a slower access speed over the data in the second area stored in the storage unit 14 having a higher access speed. By performing prediction (or prediction and transfer) before access, a higher reduction effect of the stall time by the processing circuit 12 can be obtained.

  The first speed may be determined in advance. In the present embodiment, description will be made assuming that the access speed of the first storage unit 14A is equal to or higher than the first speed, and the access speed of the second storage unit 14B is lower than the first speed.

  For example, the prediction unit 26 gives priority to the second area in the first area in which data is stored in the second storage unit 14B over the first area in which data is stored in the first storage unit 14A. The second area to be accessed in the future may be predicted.

  13 to 15 are explanatory diagrams illustrating an example of prediction of the second area to be accessed in the future.

  As illustrated in FIG. 13, for example, it is assumed that data in the first area whose page number is defined in the entry E1 of the management table 31A is stored in the second storage unit 14B. Further, as shown in FIG. 14, it is assumed that the data in the first area whose page number is defined in the entry EZ of the management table 31A is stored in the first storage unit 14A.

  In this case, as shown in FIG. 13, the prediction unit 26 uses the access management information of the entry E1 that defines the page number of the first area in which data is stored in the second storage unit 14B. The second area C4 is predicted as a second area to be accessed in the future (see entry E1 ′ in FIG. 13). The method for predicting the second area to be accessed in the future from the access management information is the same as described above.

  Next, as illustrated in FIG. 14, the prediction unit 26 uses the access management information of the entry EZ that defines the page number of the first area in which data is stored in the first storage unit 14A. The second area is predicted as a second area to be accessed in the future. Note that the prediction unit 26 may not perform prediction of the second region to be accessed in the future for the entry EZ that defines the first region in which data is stored in the first storage unit 14A having low priority. In this case, as shown in FIG. 14, the post-prediction entry EZ 'has the same contents as the pre-prediction entry EZ.

  When the prediction unit 26 predicts a second area to be accessed in the future based on the priority according to the storage unit 14 in which data is stored, the management table 31B (see FIG. 5) is used as the management table 31. It is preferable to use as.

  FIG. 15 is an explanatory diagram of prediction using the management table 31B. In this case, the prediction unit 26 can easily retrieve the entry E (entry Ea, entry Eb, entry Ec, entry Ed) indicating the physical address of the second storage unit 14B from the management table 31B. For this reason, the prediction unit 26 can easily specify the entry E that defines the page number of the first area in which data is stored in the second storage unit 14B, and can use it for the prediction of the second area to be accessed in the future. .

  Returning to FIG. Next, the transfer unit 28 will be described. The transfer unit 28 transfers the data in the second area predicted by the prediction unit 26 to another type of storage unit 14 having a higher access speed by the processing circuit 12 than the storage unit 14 storing the data. In this embodiment, “transfer” may mean copying, or movement that deletes original data.

  For example, it is assumed that data in the second area predicted to be accessed in the future is stored in the first storage unit 14A. In this case, the transfer unit 28 transfers the data in the second area stored in the first storage unit 14 </ b> A to the cache memory 16.

  For example, it is assumed that data in the second area predicted to be accessed in the future is stored in the second storage unit 14B. In this case, the transfer unit 28 transfers the data in the second area stored in the second storage unit 14B to the first storage unit 14A or the cache memory 16.

  The basic unit of data transfer from the second storage unit 14B to the first storage unit 14A is a page (that is, a unit of the first area). Therefore, when the transfer destination is the first storage unit 14A, the transfer unit 28 transfers the data in the first area (page) including the data in the second area (cache line) to the first storage unit 14A.

  On the other hand, the basic unit of data transfer from the second storage unit 14B or the first storage unit 14A to the cache memory 16 is a cache line unit (that is, a unit of the second area). Therefore, when the transfer destination is the cache memory 16, the transfer unit 28 transfers the data in the second area to the cache memory 16 in units of cache lines.

  The timing at which the transfer unit 28 transfers the predicted data in the second area is not limited. For example, the transfer unit 28 transfers the data in the second area to the storage unit 14 or the cache memory 16 having a higher access speed each time a new second area is predicted by the prediction unit 26.

  In addition, the transfer unit 28 stores the predicted data in the second area at a higher access speed every predetermined time or at a predetermined timing after a predetermined time has elapsed since the prediction unit 26 last predicted. The data may be transferred to the unit 14 or the cache memory 16. For example, the transfer unit 28 may transfer data during a period in which the processing circuit 12 has little access to the storage unit 14.

  When the transfer unit 28 transfers data from the second storage unit 14B to the first storage unit 14A in units of pages, the transfer unit 28 sets the physical address corresponding to the logical address of the transferred second area in the page table to the transfer destination. To the physical address indicating the position in the storage unit 14. Therefore, the processing circuit 12 can directly access the transfer destination storage unit 14 when accessing the data. The page table may be updated by the prediction unit 26.

  Next, an example of an information processing procedure executed by the information processing apparatus 10 according to the present embodiment will be described. FIG. 16 is a flowchart illustrating an example of an information processing procedure executed by the information processing apparatus 10.

  First, the update unit 24 obtains an access target address from a memory access request received from the processing circuit 12 via the access control unit 20 (step S100).

  Next, in the entry E that defines the page number indicated by the address information of the address obtained in step S100 in the management table 31A, the update unit 24 specifies the second access target indicated by the memory access request accepted in step S100. The area access information is updated to “1” that has been accessed (step S102).

  Next, the prediction unit 26 predicts a second area that the processing circuit 12 will access in the future based on the access management information in the management table 31A (step S104).

  Then, the prediction unit 26 updates the access information of the second area predicted in step S104 in the management table 31A to “1” that has been accessed (step S106).

  Next, the transfer unit 28 stores the data in the second area predicted in step S104 in another type of storage unit 14 or cache memory that has a higher access speed by the processing circuit 12 than the storage unit 14 in which the data is stored. 16 (step S108).

  Next, in the case of transfer from the second storage unit to the first storage unit, the transfer unit 28 stores the physical address corresponding to the logical address of the second area transferred in step S108 in the page table as the transfer destination storage. The physical address indicating the storage destination of the unit 14 is updated (step S110). Then, this routine ends.

  Note that, as described above, the prediction unit 26 uses the access information updated in the second period T2, which is the timing before the first period T1, to change the pattern indicated by the access information updated in the first period T1. In some cases, the second area to be accessed in the future is predicted by giving priority to the pattern shown.

  In addition, the prediction unit 26 stores the second area in which data is stored in the second storage unit 14B whose access speed is less than the first speed, in the first storage unit 14A having an access speed equal to or higher than the first speed. A second area to be accessed in the future may be predicted in preference to the second area in which data is stored.

  In these cases, as described above, the information processing apparatus 10 may preferentially perform prediction by the prediction unit 26, or may preferentially perform prediction by the prediction unit 26 and transfer by the transfer unit 28. Good.

  In the case where the prediction by the prediction unit 26 and the transfer by the transfer unit 28 are performed with priority, for example, the second area predicted by the prediction unit 26 is preferentially accessed before the second area having a lower priority. To the fast storage unit 14. Next, when the prediction unit 26 predicts a second area with a low priority, the predicted data in the second area may be transferred to the storage unit 14 having a high access speed.

  At this time, when the transfer destination is the cache memory 16, the transfer unit 28 may transfer the data in the second area having a higher priority to the upper hierarchy having a higher access speed in the cache memory 16. preferable.

  As described above, the management device 18 according to the present embodiment manages access to a plurality of types of storage units 14 by the processing circuit 12. The storage unit 14 includes a plurality of first areas, and the first area includes a plurality of second areas. The management device 18 includes a management unit (management information storage unit 30) and a prediction unit 26. The management unit (management information storage unit 30) manages the management table 31. The management table 31 defines identification information of the first area and access information indicating whether or not the second area has been accessed by the processing circuit 12 for each of the plurality of second areas included in the first area. This is a table in which the access management information is associated. The prediction unit 26 predicts a second area that the processing circuit 12 will access in the future based on the access management information.

  As described above, in the management device 18 according to the present embodiment, whether or not each of the plurality of types of storage units 14 has been accessed by the processing circuit 12 for each second area that is a unit smaller than the first area. Manage the access information shown. Therefore, for each of the plurality of types of storage units 14, it is possible to easily manage which second area in the first area has been accessed by the processing circuit 12.

  In the management device 18 of the present embodiment, the second area that the processing circuit 12 will access in the future is predicted based on the access management information that defines each access information of the second area in the management table 31. Therefore, the management device 18 according to the present embodiment can predict the second area that the processing circuit 12 will access in the future, according to the pattern of access to the second area by the processing circuit 12.

  Therefore, the management device 18 can predict data to be accessed in the future by the processing circuit 12 with high accuracy.

  In the present embodiment, the transfer unit 28 uses other types of data in the second area predicted by the prediction unit 26 that have a higher access speed by the processing circuit 12 than the storage unit 14 in which the data is stored. To the storage unit 14.

  Therefore, in the management device 18 of the present embodiment, before being accessed by the processing circuit 12, the data in the second area predicted to be accessed in the future is stored in the storage unit 14 (for example, the data is stored) The data can be transferred to the storage unit 14 (for example, the first storage unit 14A or the cache memory 16) having a higher access speed than the second storage unit 14B).

  For this reason, in addition to the above effects, the management device 18 according to the present embodiment improves the access speed by the processing circuit 12, shortens the processing time, improves the processing performance, and reduces the power consumption by shortening the processing time. Can be achieved.

(Modification 1)
The prediction unit 26 only needs to predict the second area to be accessed in the future based on the access management information in the management table 31, and the prediction method by the prediction unit 26 is not limited to the method described in the above embodiment.

  For example, the prediction unit 26 may predict a second area in each of a plurality of first areas adjacent to each other with a logical address (page number) as a second area to be accessed in the future.

  Here, the page number of the first area including the second area predicted to be accessed in the future may not be registered in the management table 31. In this case, the prediction unit 26 may add a new entry E that defines the page number of the first area including the second area predicted to be accessed in the future to the management table 31.

  17 and 18 are explanatory diagrams illustrating an example of prediction of the second region. In this modification, a case where the management table 31B (see FIG. 5) is used as the management table 31 will be described.

For example, as shown in FIG. 17, it is assumed that in the first region defined page number in the entry E _Z, 16 th access information of the second region C16 of the start address, is updated by the update unit 24.

  Then, as illustrated in FIG. 18, the prediction unit 26 performs the second area in the first area of the next page number “0f064382” with respect to the page number “0f064381” of the first area defined in the entry Ez. Assume that C1 is predicted as a second area to be accessed in the future.

In this case, the prediction unit 26 creates a new entry E _{Z + 1} (hereinafter may be referred to as a new entry E _{Z + 1} ) and registers it in the management table 31B. Here, there is an upper limit to the number of entries registered in the management table 31B. For this reason, when there is no empty entry E in the management table 31B, the prediction unit 26 may release any entry E registered in the management table 31B and register a new entry E _{Z + 1.} . The release of the entry E may be performed by the same method as the release of the entry E by the update unit 24.

Then, the prediction unit 26 registers the logical address, which is the page number, of the first area including the second area predicted to be accessed in the future in the new entry E _{Z + 1} in the management table 31B. Also, the prediction unit 26 searches the physical address corresponding to the logical address from the page table and registers it in the new entry E _{Z + 1} .

As described above, the management unit 31A (see FIG. 4) and the management table 31B (see FIG. 5) that integrates and manages the management table 31A (see FIG. 5) and the TLB that functions as the page table cache are newly predicted by register the new entry _{Z + 1} 2 regions, it registers the logical addresses and physical addresses in該新entry _{Z + 1.}

  For this reason, when the processing circuit 12 accesses the data in the second area, it can be avoided that the entry E corresponding to the management table 31B having the function as the TLB does not exist, and the occurrence of the TLB miss can be suppressed. .

Next, the predicting unit 26 updates the access information of the second area C1 predicted to be accessed in the future in the new entry E _{Z + 1 to} “1”.

  Then, as in the above embodiment, the transfer unit 28 transfers the data in the second area predicted by the prediction unit 26 to the cache memory 16. In addition, the transfer unit 28 transfers the data to another type of storage unit 14 (for example, the first storage unit 14A) having a higher access speed by the processing circuit 12 than the storage unit 14 in which the data is stored. Also good.

  Then, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred second area in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14. At this time, if the transfer destination is the cache memory 16, the page table need not be updated.

  Next, an example of an information processing procedure executed by the information processing apparatus 10 according to the present modification will be described. FIG. 19 is a flowchart illustrating an example of an information processing procedure executed by the information processing apparatus 10 according to the present modification.

  First, the update unit 24 obtains an access target address from a memory access request received from the processing circuit 12 via the access control unit 20 (step S200).

  Next, the update unit 24 in the entry E that defines the page number indicated by the address information of the address obtained in step S200 in the management table 31A is the second access target indicated by the memory access request accepted in step S200. The access information of the area is updated to “1” that has been accessed (step S202).

  Next, the prediction unit 26 predicts a second area that the processing circuit 12 will access in the future based on the access management information in the management table 31B (step S204).

  Next, the prediction unit 26 determines that the second area predicted in step S206 is in the first area identified by the next page number of the first area to be accessed indicated in the memory access request acquired in step S200. It is determined whether it is the second area (step S206).

  If a positive determination is made in step S206 (step S206: Yes), the process proceeds to step S208.

  In step S208, it is determined whether or not entry E defining the page number of the first area including the second area predicted in step S204 is registered in the management table 31B (step S208). When it is determined that it is not registered (step S208: No), the process proceeds to step S210.

  In step S210, the prediction unit 26 specifies the entry E to be released in the management table 31B (step S210), and releases the entry E (step S212).

Next, the prediction unit 26 creates a new entry E _{Z + 1} in the management table 31B and registers the logical address (page number) of the first area including the second area predicted to be accessed in the future in step S204 ( Step S214). Next, the prediction unit 26 searches the physical address corresponding to the logical address from the page table and registers it in the new entry E _{Z + 1} (step S216).

Next, the prediction unit 26 updates the access information of the second area predicted to be accessed in step S206 in the new entry E _{Z + 1 to} “1” that has been accessed (step S218).

  Next, the data in the second area predicted by the transfer unit 28 in step S206 is stored in another type of storage unit 14 or cache memory 16 having a higher access speed by the processing circuit 12 than the storage unit 14 storing the data. (Step S220).

  Then, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred second area in the page table to the physical address indicating the storage destination of the transfer destination storage unit 14 (step S222). Then, this routine ends. Note that the page table update need not be performed at this timing, but may be performed at another timing.

  On the other hand, if a negative determination is made in step S206 (step S206: No), the process proceeds to step S224. Also in the case where an affirmative determination is made in step S208 (step S208: Yes), the process proceeds to step S224.

  In step S224, the prediction unit 26 updates the access information of the second area predicted in step S204 in the management table 31B to “1” that has been accessed (step S224).

  Next, the transfer unit 28 stores the data in the second area predicted in step S206 in another type of storage unit 14 or cache memory that is faster in access speed by the processing circuit 12 than the storage unit 14 in which the data is stored. 16 (step S226).

  Next, the transfer unit 28 updates the physical address corresponding to the logical address of the second area transferred in step S226 in the page table to a physical address indicating the storage destination of the transfer destination storage unit 14 (step S228). . Then, this routine ends.

  As described above, in this modification, the prediction unit 26 accesses the management table 31B in the future when the page number of the first area including the second area predicted to be accessed in the future is not registered in the management table 31B. Then, a new entry E defining the page number of the first area including the predicted second area is added. Then, the prediction unit 26 registers a logical address and a physical address in the new entry E.

  For this reason, when the processing circuit 12 accesses the data in the second area, it can be avoided that the entry E corresponding to the management table 31B having the function as the TLB does not exist, and the occurrence of the TLB miss can be suppressed. .

  Therefore, in this modification, in addition to the effects of the above embodiment, the stall time of the processing circuit 12 can be shortened, and the access speed can be increased.

(Modification 2)
The prediction unit 26 corresponds to the identification information (page number) of the other first area indicating the logical address (page number) within a predetermined range with respect to the logical address (page number) of the first area to be predicted. Based on the access management information to be processed, the second area that the processing circuit 12 will access in the future may be predicted in the first area to be predicted.

  The first area to be predicted is the first area to be predicted for the second area to be accessed in the future by the processing circuit 12. The first region to be predicted is not limited. For example, the first area to be predicted is the first area in which the page number is defined for the entry E newly added to the management table 31B. The first region to be predicted is not limited to the newly added entry E.

  The logical address within the predetermined range may be a logical address of a page adjacent to the first area to be predicted, or within a predetermined range with respect to the logical address of the first area to be predicted. It may be a logical address. “Within a predetermined range” means that the page number difference is equal to or less than a predetermined value.

  In the other first area indicating the logical address within the predetermined range, data is stored in the same storage unit 14 as the data in the first area to be predicted, and the logical address of the first area to be predicted The first area may indicate a predetermined range of logical addresses.

  20 and 21 are explanatory diagrams of an example of predicting the second area to be accessed in the future. FIG. 20 and FIG. 21 show a case where the first area in which the page number is defined in the newly registered new entry Ej is used as the first area to be predicted for the second area.

  As illustrated in FIG. 20, for example, it is assumed that the updating unit 24 newly registers an entry Ej of the page number “0f06438c” in the management table 31B based on the memory access request acquired from the processing circuit 12.

  In this case, the update unit 24 registers the logical address (page number) indicated in the memory access request in the new entry Ej, as in the above embodiment. Further, the update unit 24 reads the physical address corresponding to the logical address from the page table and registers it in the entry Ej. In the example illustrated in FIG. 20, a case where the physical address indicates the physical address of the second storage unit 14B will be described as an example.

  Similarly to the above-described embodiment, the update unit 24 stores the access information of the second area to be accessed indicated in the memory access request in the new entry Ej (hereinafter sometimes referred to as a new entry Ej). Updated to “1” already accessed.

  When the new entry Ej is registered in the management table 31B, the prediction unit 26 specifies another entry E indicating a logical address within a predetermined range with respect to the logical address of the new entry Ej.

  In the present modification, it is assumed that the update unit 24 has specified the entry Eh1 and the entry Eh2 in which the physical addresses of the same storage unit 14 (the second storage unit 14B in FIG. 20) as the new entry Ej are defined.

  Then, the prediction unit 26 accesses the second area included in the first area of the new entry Ej in the future in accordance with the pattern indicated by the access information of these specified entries E (entry Eh1 and entry Eh2). Predict the second region.

  Specifically, the prediction unit 26 determines whether or not the access management information of another entry E (entry Eh1 and entry Eh2) indicating a logical address within a predetermined range satisfies a predetermined condition.

  The predetermined condition may be determined in advance. For example, when the other entry E (entry Eh1 and entry Eh2) includes an entry E that includes access information indicating “1” that is already accessed at a first threshold value or more, the prediction unit 26 sets a predetermined condition. Judging to meet.

  The first threshold value and the predetermined ratio may be determined in advance. For example, it is assumed that the first threshold is “8”. In this case, the access management information of each of the entry Eh1 and the entry Eh2 shown in FIG. For this reason, in this case, the prediction unit 26 determines that the predetermined condition is satisfied.

  If the prediction unit 26 determines that the predetermined condition is satisfied, the prediction unit 26 uses the second area of the new entry Ej from the pattern indicated by the access information defined in the access management information of these entries E (entry Eh1 and entry Eh2). The second area to be accessed in the future is predicted. This prediction method is the same as in the above embodiment.

  Then, similarly to the above embodiment, the prediction unit 26 updates the predicted access information of the second area in the new entry Ej to “1”. Therefore, the new entry Ej after being updated by the prediction unit 26 is, for example, as shown in FIG. For example, the access information of the second area C1 in the new entry Ej is updated to “1” accessed by the update unit 24, and at least one of the second areas C2 to C16 is updated to “1” accessed by the prediction unit 26 Is done.

  Then, in this modification, when the prediction unit 26 determines that the predetermined condition is satisfied, the transfer unit 28 stores the data of the first region to be predicted in page units (units of the first region) in the second storage unit 14B. To the first storage unit 14A.

  That is, it is assumed that the data in the first area indicated by the new entry Ej is stored in the second storage unit 14B. In this case, for example, the transfer unit 28 transfers the data in the first area indicated by the new entry Ej from the second storage unit 14B to the first storage unit 14A in units of pages.

  In addition, the transfer unit 28 transfers the data in the second area to be accessed in the future predicted by the prediction unit 26 in the new entry Ej to the cache memory 16 in units of cache lines.

  In other words, in the present modification, when the first area defined by the new entry Ej is accessed for the first time, the predicting unit 26 selects another accessed entry E (entry Eh1 that indicates a logical address within a predetermined range). When the access management information of the entry Eh2) satisfies the predetermined condition, it is predicted that the new entry Ej is also accessed more than a predetermined number of times. Then, the transfer unit 28 transfers the data of the new entry Ej from the second storage unit 14B to the first storage unit 14A in page units. At the same time, the transfer unit 28 transfers the data of the second area accessed in the future predicted by the prediction unit 26 in the new entry Ej to the cache memory 16 in units of cache lines.

  Then, the transfer unit 28 updates the physical address indicated by the new entry Ej in the management table 31B to the physical address indicated by the transfer destination first storage unit 14A (in FIG. 21, the physical address of the new entry Ej ′). reference). In addition, the transfer unit 28 updates the physical address corresponding to the logical address of the transferred first area in the page table to the physical address of the first storage unit 14A that is the transfer destination.

  If the prediction unit 26 determines that the predetermined condition is not satisfied, the transfer unit 28 stores the data in the first area including the second area predicted to be accessed in the future in units of cache lines (units of the second area). Transfer to the cache memory 16 is sufficient.

  FIG. 22 is an explanatory diagram of an example of data transfer in the present modification. As shown in FIG. 22, in the present modification, for the first area (for example, page A) defined by the entry predicted to have high memory access locality, the transfer unit 28 transfers the data of page A in units of pages. Then, the data is transferred from the second storage unit 14B to the first storage unit 14A. Further, the transfer unit 28 transfers the data in the second area predicted to be accessed in the future in the page A to the cache memory 16 in units of cache lines.

  On the other hand, in the present modification, for the first area (for example, page B) defined by the entry predicted to have low memory access locality, the transfer unit 28 stores the data of page B in the second storage in units of cache lines. The data is transferred from the unit 14B to the cache memory 16.

  That is, in the present modification, the management device 18 executes the first process and the second process separately for page A and page B on the second storage unit 14B (SCM). In other words, the management device 18 executes the first process and the second process in a mixed manner.

  The first process will be described. Of page A and page B on the second storage unit 14B (SCM), page A, which is expected to have high memory access locality, is transferred to the first storage unit 14A (DRAM) on a page basis. Then, the access information of page A transferred to the first storage unit 14A (DRAM) in the management table 31B is access information “1” indicating that access has been made by the processing circuit 12 accessing the page A in units of cache lines. Updated to Then, the prediction unit 26 predicts a second area (cache line) to be accessed in the future by the processing circuit 12 in accordance with the pattern indicated by the access information in the management table 31B. Then, the cache line predicted to be accessed in the future in page A is transferred to the cache memory 16 in units of cache lines. This series of processes is referred to as a first process.

  The second process will be described. In the management table 31B, the access information of the page B having a low memory access locality that is not transferred to the first storage unit 14A (DRAM) and remains in the second storage unit 14B (SCM) is transferred to the page B by the processing circuit 12. Is updated to access information “1” indicating that access has been completed. Then, the prediction unit 26 predicts a second area (cache line) to be accessed in the future by the processing circuit 12 in accordance with the pattern indicated by the access information in the management table 31B. Then, the cache line predicted to be accessed in the future in page B is transferred to the cache memory 16 in units of cache lines. This series of processing is referred to as second processing.

  Next, an example of an information processing procedure executed by the information processing apparatus 10 according to the present modification will be described. FIG. 23 is a flowchart illustrating an example of an information processing procedure executed by the information processing apparatus 10 according to the present modification.

  First, the updating unit 24 obtains an access target address from a memory access request received from the processing circuit 12 via the access control unit 20 (step S300).

  Next, the updating unit 24 determines whether or not the entry E including the page number indicated by the address information of the first area indicated in the memory access request received in step S300 is in the management table 31B (step S302). ).

  When the entry E is not in the management table 31B (step S302: No), the process proceeds to step S304. In step S304, the update unit 24 identifies and releases the entry to be released in the management table 30A (step S304). Then, the update unit 24 registers the new entry Ej in the management table 31B (Step S306).

  Next, the prediction unit 26 determines whether the access to the first area (that is, the page) including the second area to be accessed indicated in the memory access request received in step S300 is the first access to the first area. It is determined whether or not (step PS308). If a negative determination is made in step S308 (step S308: No), the process proceeds to step S326 described later. If an affirmative determination is made in step S308 (step S308: Yes), the process proceeds to step S310.

  Next, the prediction unit 26 identifies another entry E (entry Eh1, entry Eh2) indicating a logical address within a predetermined range with respect to the logical address of the new entry Ej (step S310).

  Next, the prediction unit 26 determines whether or not the access management information of these entries E (entry Eh1 and entry Eh2) specified in step S310 satisfies a predetermined condition (step S312). If the predetermined condition is not satisfied (step S312: NO), the process proceeds to step S326 described later.

  If the predetermined condition is satisfied (step S312: YES), the process proceeds to step S314. In step S314, the prediction unit 26 uses the access management information of the entry E (entry Eh1 and entry Eh2) identified in step S310 to process the second area in the first area indicated by the new entry Ej by the processing circuit 12 in the future. A second area to be accessed is predicted (step S314).

  Then, the prediction unit 26 updates the access information of the second area predicted in Step S314 in the new entry Ej to “1” that has been accessed (Step S316).

  Next, the transfer unit 28 transfers the data in the first area indicated by the new entry Ej to the first storage unit 14A in units of pages (step S318). Next, the transfer unit 28 transfers the data in the second area predicted to be accessed in the future in step S314 in the data in the first area to the cache memory 16 in units of cache lines (step S320).

  Next, the transfer unit 28 updates the management table 31B and the page table (step S322). Specifically, the transfer unit 28 updates the physical address indicated by the new entry Ej in the management table 31B to a physical address indicating the transfer destination storage unit 14 (for example, the first storage unit 14A) in step S318. . Also, the transfer unit 28 updates the physical address corresponding to the transferred logical address of the first area in the page table to the physical address of the transfer destination storage unit 14 (for example, the first storage unit 14A) in step S318. .

  Next, the update unit 24 stores the second access target indicated by the memory access request received in step S300 in the entry E that defines the page number indicated by the address information of the address obtained in step S300 in the management table 31B. The access information of the area is updated to “1” that has been accessed (step S326).

  Next, the prediction unit 26 predicts a second area that the processing circuit 12 will access in the future based on the access management information in the management table 31B (step S328).

  Then, the prediction unit 26 updates the access information of the second area predicted in step S328 in the management table 31B to “1” that has been accessed (step S330).

  Next, the transfer unit 28 transfers the data in the second area predicted in step S328 to the cache memory 16 in units of cache lines (step S332). That is, when the prediction unit 26 determines that the predetermined condition is not satisfied, the transfer unit 28 transfers the data in the second area predicted to be accessed in the future by the processing circuit 12 from the second storage unit 14B to the cache memory 16 in units of cache lines. Direct transfer to

  Next, the transfer unit 28 updates the physical address corresponding to the logical address of the second area transferred in step S332 in the page table to a physical address indicating the storage destination of the transfer destination storage unit 14 (step S334). . Then, this routine ends.

  As described above, in the present modification, the prediction unit 26 performs access management corresponding to the identification information of the other first area indicating the logical address within the predetermined range with respect to the logical address of the first area to be predicted. Based on the information, the second area that the processing circuit 12 will access in the future is predicted in the first area to be predicted.

  Here, the access tendency by the processing circuit 12 between the first areas indicating the logical addresses within a predetermined range may be approximated. In particular, such a tendency occurs when a large amount of data extending over a plurality of first areas is stored in the storage unit 14.

  For this reason, the prediction unit 26 can predict the second region that the processing circuit 12 will access in the future with higher accuracy in addition to the effects of the above-described embodiment by performing the processing of this modification.

(Modification 3)
FIG. 24 is a schematic diagram illustrating an example of an information processing apparatus 10A according to the present modification. As illustrated in FIG. 24, the processing circuit 12A of the information processing apparatus 10A may include a cache memory 16 and a management device 18. The processing circuit 12A is the same as the processing circuit 12 of the above embodiment except that the processing circuit 12A includes the cache memory 16 and the management device 18.

(Modification 4)
FIG. 25 is a schematic diagram illustrating an example of an information processing apparatus 10B according to the present modification. As illustrated in FIG. 25, the management device 18 </ b> A may include a cache memory 16, an access control unit 20, a management unit 22, and a storage unit 14.

  As mentioned above, although embodiment and the modification of this invention were demonstrated, these embodiment and the modification are shown as an example, and are not intending limiting the range of invention. These novel embodiments and modifications can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 10A, 10B Information processing device 12, 12A Processing circuit 14 Storage unit 16 Cache memory 18, 18A Management device 22 Management unit 24 Update unit 28 Transfer unit 30 Management information storage unit

Claims (21)

A management device for managing access to a plurality of types of storage units by a processing circuit,
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. A management unit for managing a management table in which access management information is associated;
Based on the access management information, a prediction unit that predicts the second area to be accessed in the future by the processing circuit;
A management device comprising: The plurality of types of storage units are
Access speeds are different from each other,
The management apparatus according to claim 1. The prediction unit
Predicting the second region to be accessed in the future by the processing circuit according to a pattern indicated by the access information;
The management apparatus according to claim 1 or 2. The pattern is represented by a positional relationship in the storage unit of the second area in which the access information indicating accessed is defined.
The management device according to claim 3. An update unit that updates the access information of the second area to be accessed indicated by the memory access request in the management table when the memory access request is received from the processing circuit;
The management device according to claim 3 or 4. The prediction unit
Predicting the second region to be accessed in the future by the processing circuit according to the pattern indicated by a plurality of the access information including the access information updated immediately by the update unit in the access management information;
The management device according to claim 5. The prediction unit
Predicting the second area to be accessed in the future by the processing circuit according to the pattern indicated by the access information updated in a certain period in the access management information;
The management device according to claim 5. The prediction unit
In the access management information, the pattern indicated by the access information updated in the first period is compared with the pattern indicated by the access information updated in the second period at a timing earlier than the first period. Preferentially used to predict the second area that the processing circuit will access in the future,
The management device according to claim 5. The prediction unit
When the identification information of the first area including the predicted second area is not registered in the management table,
Adding a new entry including identification information of the first area to the management table, and registering the identification information and physical address of the first area in the entry;
The management apparatus of any one of Claims 1-5. The prediction unit
In the first area identified by each of the plurality of identification information shown in the management table, data is stored in the storage unit whose access speed by the processing circuit is less than the first speed. The processing circuit accesses the second area in the first area in the future with priority over the first area in which data is stored in the storage unit of the access speed type higher than the first speed. Predicting the second region to be
The management apparatus of any one of Claims 1-5. The prediction unit
Updating the access information of the predicted second area in the management table to be accessed;
The management apparatus of any one of Claims 1-10. A transfer unit that transfers the data in the second region predicted by the prediction unit to another type of the storage unit having a higher access speed by the processing circuit than the storage unit in which the data is stored;
The management apparatus according to any one of claims 1 to 11. The prediction unit
Based on the access management information corresponding to the identification information of the other first area indicating a logical address within a predetermined range with respect to the identification information of the first area to be predicted in the management table, the processing circuit Predicting the second area to be accessed in the future,
The management apparatus according to claim 12. The plurality of types of storage units include a first storage unit and a second storage unit having a lower access speed than the first storage unit,
The prediction unit
In the management table, when the access management information corresponding to the identification information of another first area indicating a logical address within a predetermined range with respect to the identification information of the first area to be predicted satisfies a predetermined condition, Based on the access management information corresponding to the identification information, the processing circuit predicts the second area to be accessed in the future,
The transfer unit
When it is determined that the predetermined condition is satisfied, the data of the first region to be predicted is transferred from the second storage unit to the first storage unit in units of the first region.
The management apparatus according to claim 13. The prediction unit
The number of the second areas in which the access information indicating that access has been made to the other first areas indicating logical addresses within a predetermined range with respect to the identification information of the first area to be predicted is the first threshold value. When the above first region is included in a predetermined ratio or more, it is determined that the predetermined condition is satisfied.
The management device according to claim 14. The plurality of types of storage units include a cache memory, the first storage unit having a lower access speed than the cache memory, and the second storage unit,
The transfer unit
When the prediction unit determines that the predetermined condition is satisfied, the data of the second area predicted to be accessed in the future by the processing circuit is transferred to the cache memory.
The management apparatus according to claim 14 or 15. The transfer unit
When the prediction unit determines that the predetermined condition is not satisfied, the data in the second area predicted to be accessed in the future by the processing circuit is directly transferred from the second storage unit to the cache memory in units of the second area. Forward,
The management apparatus according to claim 16. The management table is
For each of the logical address as identification information of the first area, the physical address of the first area in the storage unit, and the plurality of second areas included in the first area, the second area is the Corresponding access management information that defines access information indicating whether or not it has been accessed by the processing circuit,
The management apparatus of any one of Claims 1-17. A processing circuit;
Multiple types of storage units;
A management device for managing access to a plurality of types of the storage units;
With
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The management device
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. A management unit for managing a management table in which access management information is associated;
Based on the access management information, a prediction unit that predicts the second area to be accessed in the future by the processing circuit;
An information processing apparatus comprising: A management method in a management device for managing access to a plurality of types of storage units by a processing circuit,
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. A management step for managing a management table in which access management information is associated;
A predicting step of predicting the second area to be accessed in the future by the processing circuit based on the access management information;
Management method. A program for causing a computer to manage access to a plurality of types of storage units by a processing circuit,
The storage unit includes a plurality of first areas, the first area includes a plurality of second areas,
The identification information of the first area and the access information indicating whether or not the second area has been accessed by the processing circuit are defined for each of the plurality of second areas included in the first area. A management step for managing a management table in which access management information is associated;
A predicting step of predicting the second area to be accessed in the future by the processing circuit based on the access management information;
Including the program.

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