JP6326835B2 - Information processing apparatus, IC card, command processing method, and command processing program - Google Patents

Description

  The present invention relates to a technical field such as an IC (Integrated Circuit) chip constituted by a multi-core processor.

  Conventionally, an attack such as DFA (Differential Fault Analysis) is performed on an IC chip by a malicious third party. As a countermeasure against such a problem, for example, Patent Document 1 discloses a technique for gradually increasing the strength of a security countermeasure every time an attack is detected.

JP 2012-203800 A

  By the way, in the technique of Patent Document 1, priority can be given to speed during normal times, but in this case, the operation is performed in a security-sensitive state. On the other hand, in recent years, IC cards are increasingly used in various situations, and the number and types of commands to be mounted are increasing. Each command is divided into one in which security is given priority and one in which speed is given priority, but there is no known technique for switching between security priority and speed priority according to the command.

  Therefore, the present invention has been made in view of the above problems and the like, and includes an information processing apparatus, an IC card, a command processing method, and a command processing program capable of switching between security priority and speed priority according to a command. The purpose is to provide.

In order to solve the above-described problem, the invention according to claim 1 is an information processing apparatus including a plurality of CPUs and a controller that controls the CPU, and the controller receives a command from an external terminal. A determination means for determining whether the received command is security priority or speed priority based on an instruction code included in a header of the command, and when the determination means determines that the security priority is given, Control means for causing the plurality of CPUs to execute the same processing according to the command at the same timing.

  According to a second aspect of the present invention, in the information processing apparatus according to the first aspect, when the determination unit determines that the security is not prioritized, the plurality of processes in a series of processes according to the command are performed. CPUs are executed at the same timing.

According to a third aspect of the present invention, in the information processing device according to the first or second aspect, the information processing device stores in advance a table in which an instruction code is associated with security priority or speed priority. When the command is received, the determination means refers to the table stored in the nonvolatile memory to determine whether the received command is security priority or speed priority. It is characterized by that.

The invention according to claim 4 is an IC card comprising a plurality of CPUs and a controller for controlling the CPU, and the controller receives the received command when the command is received from an external terminal. A determination unit that determines whether security priority or speed priority is based on an instruction code included in a header of the command, and when the determination unit determines that security priority is given, the same processing according to the command is performed. Control means for causing the plurality of CPUs to execute at the same timing .

The invention according to claim 5 is a command processing method in an information processing apparatus including a plurality of CPUs and a controller that controls the CPUs, and when the controller receives a command from an external terminal, the reception is performed. Determining whether the given command is security priority or speed priority based on an instruction code included in a header of the command, and when the controller determines that the security priority is given, the same according to the command And a step of causing the plurality of CPUs to execute the process at the same timing.

According to the sixth aspect of the present invention, when a command is received from an external terminal, the received command is a security priority or speed when the controller in the processor including a plurality of CPUs and a controller that controls the CPU is received. A determination unit that determines whether priority is given based on an instruction code included in a header of the command, and the determination unit that performs the same processing according to the command when the determination unit determines that the security priority is given. It functions as a control means to be executed at the same timing.

  According to the present invention, security priority and speed priority can be switched according to a command.

FIG. 2A is a diagram illustrating a schematic configuration example of the IC card 1. (B) is a figure which shows an example of a command table. It is a flowchart which shows the process of the controller 10e. It is a conceptual diagram which shows an example of the execution timing of CPU10a-10d.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, an IC card according to the present embodiment will be described with reference to FIG. FIG. 1A is a diagram illustrating a schematic configuration example of the IC card 1. The IC card 1 is used as a cash card, credit card, employee card or the like. Alternatively, the IC card 1 is incorporated into a communication device such as a smartphone or a mobile phone. The IC chip 1a may be configured by being directly incorporated on a circuit board of a communication device.

  An IC chip 1a is mounted on the IC card 1 as shown in FIG. Specifically, the IC chip 1 a includes a multi-core processor 10, a RAM (Random Access Memory) 11, a ROM (Read Only Memory) 12, a nonvolatile memory 13, and an I / O circuit 14. The I / O circuit 14 serves as an interface with the external terminal 2. The I / O circuit 14 is provided with eight terminals C1 to C8 defined by, for example, ISO / IEC7816. For example, the C1 terminal is a power supply terminal, the C2 terminal is a reset terminal, the C3 terminal is a clock terminal, the C5 terminal is a ground terminal, and the C7 terminal is a terminal that performs data communication with the external terminal 2. Examples of the external terminal 2 include an IC card issuing machine, ATM, ticket gate, and authentication gate. Alternatively, when the IC card 1 is incorporated in a communication device, the external terminal 2 corresponds to a control unit responsible for the function of the communication device.

  The multi-core processor 10 includes a plurality of CPUs (cores) 10a to 10d and a controller 10e that controls the CPUs 10a to 10d. When a command is received from the external terminal 2, the CPU (core) 10a to 10d executes a process according to the command according to a program stored in the ROM 12 or the nonvolatile memory 13 under the control of the controller 10e. . Here, the command received from the external terminal 2 is composed of a data string called APDU including a header and a body. The command header includes CLA (instruction class), INS (instruction code), P1 (instruction parameter 1), and P2 (instruction parameter 2). The commands include a security priority command and a speed priority command. Security priority means that security is given priority over speed in processing according to a command. On the other hand, speed priority means that processing according to a command is given priority over speed.

  The controller 10e functions as a determination unit and a control unit in the present invention according to a command processing program stored in the nonvolatile memory 13, for example. Specifically, when a command is received from the external terminal 2, the controller 10e determines whether the received command has security priority or speed priority. For example, the controller 10 e refers to a command table stored in advance in the non-volatile memory 13 and makes the above determination. FIG. 1B is a diagram illustrating an example of a command table. As shown in FIG. 1B, an INS value indicating a command and security priority or speed priority are registered in association with each command in the command table. In the command table, INS values indicating all commands that can be received from the external terminal 2 need not be registered. For example, only an INS value indicating a security priority command may be registered in the command table, or only an INS value indicating a speed priority command may be registered in the command table.

  If the controller 10e determines that security is a priority (in other words, a speed is not a priority), the controller 10e causes a plurality of CPUs to execute the same processing (commands such as MOV and ADD) according to the command at the same timing. On the other hand, if the controller 10e determines that security is not a priority (in other words, speed is a priority), separate processing (commands such as MOV and ADD) in a series of processes corresponding to the command is given to a plurality of CPUs. Execute at the same timing. As a result, the operation of the plurality of CPUs in the multi-core processor 10 can be switched to the optimum operation for each command. Therefore, the speed of the command requiring speed is given priority to the speed, and the command requiring security is given priority to security. The operation can be switched.

  Next, the operation of the multi-core processor 10 when receiving a command will be described with reference to FIGS. FIG. 2 is a flowchart illustrating an example of processing of the controller 10e. FIG. 3 is a conceptual diagram illustrating an example of execution timing of the CPUs 10a to 10d. In the example of FIG. 3, a series of processes a to d including an MOV (data movement) process and a plurality of ADD (addition) processes are taken as an example of the process according to the command.

  The process shown in FIG. 2 is started when a command is received from the external terminal 2. Then, the controller 10e determines whether or not the received command is a speed priority command with reference to, for example, a command table (step S1). When it is determined that the command is a speed priority command (step S1: YES), the process proceeds to step S2. On the other hand, if it is determined that the command is not speed priority (step S1: NO), the process proceeds to step S3. In step S1, the controller 10e may be configured to determine whether the received command is a security command.

  In step S2, the controller 10e causes a plurality of CPUs to execute different (different) processes in the series of processes according to the received command at the same timing. Thus, for example, at timing 1 (t = 1) shown in FIG. 3A, the CPU 10a executes the process a, the CPU 10b executes the process b, and the CPU 10c executes the process c (that is, different processes are executed in parallel). Will be executed). In this case, the CPU 10d does not perform processing. Thereafter, at timing 2 (t = 2) shown in FIG. 3A, the CPU 10a executes the process d. That is, since the process d can be executed only after the processes a and b are finished, the process d is executed at the timing 2. As described above, in the case of speed priority, the process according to the command ends at the timing 2, and the process is completed faster than the security priority. Then, the controller 10e transmits (responds) the processing result by the CPU (in the example of FIG. 3A, the result of the processing d by the CPU 10a) to the external terminal 2 (step S5).

  On the other hand, in step S3, the controller 10e causes a plurality of CPUs to execute the same processing according to the received command at the same timing. As a result, for example, at timing 1 (t = 1) shown in FIG. 3B, the CPUs 10a to 10d each execute the process a (that is, the same process is executed in parallel), and FIG. ) At timing 2 (t = 2) shown in FIG. 3B, the CPUs 10a to 10d each execute processing b, and at timing 3 (t = 3) shown in FIG. 3B, the CPUs 10a to 10d execute processing c, respectively. At timing 4 (t = 4) shown in FIG. 3B, each of the CPUs 10a to 10d executes the process d.

  Next, in step S4, the controller 10e determines whether or not the processing results of a plurality of CPUs (results of processing d by the CPUs 10a to 10d in the example of FIG. 3B) match (verification at timing 5). To do. If the controller 10e determines that the processing results match (step S4: YES), the controller 10e transmits (responds) the processing result of any CPU to the external terminal 2 (step S5). On the other hand, if it is determined that the processing results do not match (step S4: NO), an error response is sent to the external terminal 2 or the operation of the controller 10e is stopped (step S6). In this way, in the case of security priority, it takes time until timing 5, but the same processing is executed in parallel by a plurality of CPUs, and the result is verified, so the data is altered by an external attack or the like Can be detected with high probability.

  As described above, according to the above-described embodiment, the multi-core processor 10 determines whether the received command is security priority or speed priority. The processing is executed at the same timing by a plurality of CPUs, and when it is determined that security is not a priority, the processing is performed at the same timing by a plurality of CPUs in a series of processing corresponding to the command. Therefore, it is possible to switch between security priority and speed priority according to the command, so that an optimum operation can be performed for each command. That is, a command with priority given to speed can operate at high speed, and a command with priority given to security can ensure high security.

  In the above embodiment, the controller 10e is configured to determine whether security priority or speed priority is used using the command table. However, other than this, security priority or speed priority is determined using a determination flag. It may be configured to determine whether or not. In this case, the controller 10e determines the security priority or the speed priority according to the result of the process according to the received command (for example, when the determination flag is “1”, the security priority and the determination flag is “0”). In case of ", speed priority" is maintained. For example, when the IC chip 1a is activated, the determination flag is set (held) to indicate speed priority. When the process according to the specific command is normally executed, the determination flag is set so as to indicate the security priority according to the result. On the other hand, when the process according to the specific command fails, the determination flag is set to indicate speed priority according to the result. Thus, the value of the determination flag is switched according to a certain condition. As a result, speed priority or security priority can be dynamically switched according to a specific situation. Then, when the next command is received, the controller 10e refers to the determination flag held to determine whether the received command is security priority or speed priority, and according to the determination result. As described above, a plurality of CPUs are operated.

1 IC card 1a IC chip 10 Multi-core processor 10a to 10d CPU
10e Controller 11 RAM
12 ROM
13 Non-volatile memory 14 I / O circuit

Claims (6)

An information processing apparatus comprising a plurality of CPUs and a controller that controls the CPUs,
The controller is
When a command is received from an external terminal, determination means for determining whether the received command is security priority or speed priority based on an instruction code included in the header of the command ;
Control means for causing the plurality of CPUs to execute the same processing according to the command at the same timing when the determination means determines that security is given priority;
An information processing apparatus comprising:   2. The information according to claim 1, wherein if the determination unit determines that security is not a priority, the CPUs execute different processes in a series of processes corresponding to the command at the same timing. Processing equipment. The information processing apparatus includes a nonvolatile memory that stores in advance a table in which instruction codes are associated with security priority or speed priority,
When the command is received, the determination means refers to the table stored in the nonvolatile memory and determines whether the received command is security priority or speed priority. The information processing apparatus according to claim 1 or 2. An IC card comprising a plurality of CPUs and a controller for controlling the CPUs,
The controller is
When a command is received from an external terminal, determination means for determining whether the received command is security priority or speed priority based on an instruction code included in the header of the command;
Control means for causing the plurality of CPUs to execute the same processing according to the command at the same timing when the determination means determines that security is given priority;
An IC card comprising: A command processing method in an information processing apparatus comprising a plurality of CPUs and a controller for controlling the CPUs,
When the controller receives a command from an external terminal, determining whether the received command is security priority or speed priority based on an instruction code included in a header of the command ;
When the controller determines that the security is prioritized, causing the plurality of CPUs to execute the same processing according to the command at the same timing;
A command processing method comprising: The controller in a processor comprising a plurality of CPUs and a controller for controlling the CPUs.
When a command is received from an external terminal, determination means for determining whether the received command is security priority or speed priority based on an instruction code included in the header of the command ;
A command processing program for causing a plurality of CPUs to execute the same processing according to the command at the same timing when the determination unit determines that security is a priority.

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