JP7206942B2 - Electronic information storage medium, IC chip, initial setting method, and initial setting program - Google Patents

Description

The present invention relates to technical fields such as IC cards having multiple interfaces.

2. Description of the Related Art Conventionally, an IC card having multiple interfaces is known. For example, the memory card disclosed in Patent Document 1 has a plurality of interfaces and is configured to be able to communicate simultaneously with a host using the plurality of interfaces. In the manufacturing process of an IC chip mounted on such an IC card, when writing large-capacity data such as an OS to the non-volatile memory in the IC chip from the outside, a fast communication speed, such as a SWP (Single Wire Protocol) interface can be used to speed up production.

JP 2014-182776 A

However, in some services in the market, for example, the SWP interface is not used, and an interface other than this interface, such as an ISO7816 interface, is used. In this case, the availability of SWP interfaces that are not used by the service may contribute to unauthorized use or unintended behavior. Conversely, in market services, only the SWP interface is used, but depending on the IC chip manufacturing facility, there are cases where only the ISO7816 interface is available. On the other hand, preparing OSs with different interface correspondences for each product also reduces the applicability of software, which is a factor in lowering development efficiency.

Therefore, the present invention has been made in view of such points and the like, and provides an electronic information storage medium, an IC chip, and an electronic information storage medium capable of preventing unauthorized use and unintended operation of an unused interface among a plurality of interfaces. An object of the present invention is to provide an initial setting method and an initial setting program.

In order to solve the above problems, the invention according to claim 1 is an electronic information storage medium having a plurality of interfaces, wherein a first interface for performing initial setting for operating one or more interfaces among the plurality of interfaces is provided. a storage means for storing one program and a second program for performing initial settings for operating some of the interfaces; and when the electronic information storage medium is started, the electronic determining whether or not the information storage medium is in a specific state, selecting one of the first program and the second program based on the result of the determination, and performing at least the above according to the selected program and setting means for performing initial settings for operating some of the interfaces, wherein the interfaces subject to the initial settings by the first program include interfaces not subject to the initial settings by the second program. It is characterized by

According to a second aspect of the present invention, there is provided an electronic information storage medium having a plurality of interfaces, wherein the storage means stores operability information indicating whether or not to operate at least one of the plurality of interfaces; setting means for performing initial setting for operating a part of the interface based on the operability information when the electronic information storage medium is activated.

The invention according to claim 3 is the electronic information storage medium according to claim 2, wherein the setting means determines whether or not the electronic information storage medium is in a specific state when the electronic information storage medium is activated. If it is determined that the electronic information storage medium is in the specific state, initial setting is performed to operate the part of the interface based on the operation propriety information.

The invention according to claim 4 is the electronic information storage medium according to claim 2 or 3, wherein the operability information is stored in the storage means for each of the plurality of interfaces, and the setting means It is characterized in that whether or not to operate each interface is determined based on the operability information stored for each interface, and initial setting is performed to operate the interface determined to be operated.

The invention according to claim 5 is the electronic information storage medium according to any one of claims 2 to 4, wherein the operability information is updated from an external device via any one of the interfaces in an operating state. It is characterized by further comprising update means for updating the operation enable/disable information stored in the storage means when a command is received.

The invention according to claim 6 is an IC chip having a plurality of interfaces, wherein a first program for performing initial settings for operating one or more interfaces among the plurality of interfaces; a storage means for storing a second program for performing initial settings for operating a portion of the interface; and determination as to whether or not the IC chip is in a specific state when the IC chip is activated. setting means for selecting either one of the first program and the second program based on the result of the determination, and performing initial setting for operating at least the part of the interface according to the selected program; , wherein interfaces to be initialized by the first program include interfaces not to be initialized by the second program.

According to a seventh aspect of the present invention, there is provided an IC chip having a plurality of interfaces, comprising storage means for storing operability information indicating whether or not at least one of the plurality of interfaces should be operated; setting means for performing initial setting to operate a part of the interface based on the operation propriety information when the chip is activated.

According to an eighth aspect of the invention, there is provided an initialization method executed by a computer included in an electronic information storage medium having a plurality of interfaces, wherein initialization is performed to operate one or more of the plurality of interfaces. and a second program for performing initial settings for operating some of the plurality of interfaces; and when the electronic information storage medium is activated, determining whether the electronic information storage medium is in a specific state, selecting one of the first program and the second program based on the result of the determination, and performing processing according to the selected program and performing initial settings for operating at least some of the interfaces, wherein the interfaces subject to the initial settings by the first program include interfaces not subject to the initial settings by the second program. characterized by being

According to a ninth aspect of the invention, there is provided an initialization method executed by a computer included in an electronic information storage medium having a plurality of interfaces, wherein whether or not to operate at least one of the plurality of interfaces is determined. and a step of initializing a portion of the interface to operate based on the operability information when the electronic information storage medium is activated. .

A tenth aspect of the invention provides a computer included in an electronic information storage medium having a plurality of interfaces; a second program for performing initial settings for operating some of the interfaces of the electronic information storage medium; selects either the first program or the second program based on the result of the determination, and operates at least the part of the interface according to the selected program and an initial setting program for executing an initial setting step, wherein interfaces to be initialized by the first program include interfaces not to be initialized by the second program. characterized by

The invention according to claim 11 is a step of storing, in a computer included in an electronic information storage medium having a plurality of interfaces, operability information indicating whether or not at least one of the plurality of interfaces is to be operated. and performing initial setting for operating a part of the interface based on the operability information when the electronic information storage medium is activated.

According to the present invention, unauthorized use and unintended operation of an unused interface among a plurality of interfaces can be prevented.

2 is a diagram showing an example of functional blocks of the IC chip 1; FIG. 4A and 4B are diagrams showing an example of contents stored in the NVM 13 in the first embodiment; FIG. (A) is a flowchart showing an example of processing of the CPU 10 when the IC chip 1 is activated in the first embodiment, and (B) is a flow chart in which the IC chip 1 updates interface operability information in the first embodiment 4 is a flow chart showing an example of processing of the CPU 10 when a command is received; FIG. 12 is a diagram showing an example of contents stored in the NVM 13 in the second embodiment; FIG. 10 is a flow chart showing an example of processing of the CPU 10 when the IC chip 1 is activated in the second embodiment; (A) and (B) are diagrams showing an example of contents stored in the NVM 13 in the third embodiment. (A) is a flowchart showing an example of processing of the CPU 10 when the IC chip 1 is activated in the third embodiment, and (B) is a flow chart in which the IC chip 1 updates interface operability information in the third embodiment. 4 is a flow chart showing an example of processing of the CPU 10 when a command is received;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below are embodiments in which the present invention is applied to an IC chip having a plurality of interfaces.

[1. General configuration and function of IC chip]
First, the general configuration and functions of the IC chip 1 will be described with reference to FIG. FIG. 1 is a diagram showing an example of functional blocks of an IC chip 1. As shown in FIG. As shown in FIG. 1, the IC chip 1 includes a CPU (Central Processing Unit) 10, ROM (Read Only Memory) 11, RAM (Random Access Memory) 12, NVM (Nonvolatile Memory) 13, and first to fourth interfaces 14a to 14d and the like. Here, the CPU 10 is a processor that executes various programs stored in the ROM 11 or NVM 13 . The ROM 11 can be applied as an example of storage means, but it may not be provided in the IC chip 1 in some cases. The NVM 13 is an example of storage means, such as a non-volatile memory such as a flash memory. The NVM 13 may be "Electrically Erasable Programmable Read-Only Memory". The ROM 11 or NVM 13 stores an OS (Operating System) and application programs. The OS includes an initial setting program of the present invention, driver programs corresponding to the first to fourth interfaces 14a to 14d, and the like. The initial setting program of the present invention causes the CPU 10 to function as setting means and updating means.

Note that the IC chip 1 is an example of an electronic information storage medium of the present invention, and is sometimes called a secure microcomputer. The IC chip 1 is used by being mounted on IC cards such as cash cards, credit cards, and employee cards. Alternatively, the IC chip 1 may be mounted on an IC card as a SIM (Subscriber Identity Module), for example, and mounted on a terminal device such as a smart phone or a mobile phone. Alternatively, the IC chip 1 may be mounted on an embedded substrate as eUICC (Embedded Universal Integrated Circuit Card), for example, so that it cannot be easily removed or replaced from a terminal device such as IoT (Internet of Things) (that is, integrated with the terminal device). may be formed).

The first to fourth interfaces 14a to 14d are for the CPU 10 to communicate with an external device (not shown). Although the IC chip 1 has four interfaces 14a to 14d in the example of FIG. 1, the IC chip 1 may have two or three interfaces, or five interfaces. It may have more than one interface. The first interface 14a is an interface (that is, an ISO7816 interface) for performing communication according to the T=1 protocol (start-stop half-duplex block transmission protocol) defined by ISO7816, for example. The second interface 14b is, for example, an interface for performing communication according to SWP (that is, an SWP interface). The third interface 14c is an interface for serial communication by, for example, I ² C (Inter-Integrated Circuit). The fourth interface 14d is an interface for serial communication by SPI (Serial Peripheral Interface), for example. Any one of the interfaces 14a-14d may be an interface such as GPIO (General Purpose Input Output).

If the IC chip 1 has eight terminals C1 to C8 defined by the international standard ISO7816 or the like, for example, the C1 terminal is used to supply power, and the C2 terminal is used for resetting from an external device. (reset signal) is input, the C6 terminal is used for the SWP interface, and the C7 terminal is used for the ISO7816 interface. Examples of external devices include IC chip issuing machines (IC card issuing machines), ATMs, ticket gates, authentication gates, and the like. Alternatively, when the IC chip 1 is mounted on a terminal device, the external device corresponds to a control unit that controls the terminal device or a server that communicates with the terminal device via a network.

In the above configuration, when the IC chip 1 is activated, the CPU 10 operates some of the first to fourth interfaces 14a to 14d according to the initial setting program and based on the operability information of the interfaces. Make initial settings. By configuring in this way, it is possible to prevent unauthorized use and unintended operation of an unused interface among a plurality of interfaces. Here, the interface operability information is information indicating whether or not at least one of the first to fourth interfaces 14a to 14d should be operated (that is, permitted or not permitted). can be updated by When the IC chip 1 is activated, the CPU 10 determines whether the IC chip 1 is in a specific state. An initial setting may be made to operate some of the first to fourth interfaces 14a to 14d based on the operability information.

Here, whether or not the IC chip 1 is in a specific state is determined by a state management variable stored in the NVM 13, for example. Examples of the specific state include a manufacturing completion state of the IC chip 1 and a service entry state of the IC chip 1, but other states may be used. For example, when the manufacture of the IC chip 1 is completed, a predetermined device rewrites the state management variable stored in the NVM 13 to a value indicating the manufacture completion state. Alternatively, when a service using the IC chip 1 is started, a predetermined device rewrites the state management variable stored in the NVM 13 to a value indicating the service input state.

On the other hand, it is also possible to perform initial setting for operating some of the first to fourth interfaces 14a to 14d without storing the interface operability information in the NVM 13. FIG. In this case, the NVM 13 includes a first program for performing initial settings for operating one or more of the first to fourth interfaces 14a to 14d, and a part of the first to fourth interfaces 14a to 14d. and a second program for performing initial settings for operating the interface.

Here, interfaces to be initialized by the first program include interfaces not to be initialized by the second program. As an example, the interfaces to be initialized by the first program are the first to fourth interfaces 14a to 14d (that is, all interfaces), and the interface to be initialized by the second program is the second interface. A possible case is the interface 14b and the third interface 14c. In this case, interfaces to be initialized by the first program include interfaces not to be initialized by the second program (that is, the first interface 14a and the fourth interface 14d).

However, in the present application, while using a high-speed interface in the manufacturing process of the IC chip 1 (for example, when issuing the IC chip 1), security is improved in the service in the market (for example, when operating the IC chip 1). is one of the purposes, the interfaces to be initialized by the first program do not necessarily have to be all the interfaces. Therefore, there may be a case where the interface to be initialized by the first program is the second interface 14b and the interface to be initialized by the second program is the first interface 14a. In this case, the interfaces to be initialized by the first program include an interface not to be initialized by the second program (that is, the second interface 14b). Alternatively, as another example, the interfaces to be initialized by the first program are the second interface 14b and the fourth interface 14d, and the interfaces to be initialized by the second program are the first interface 14a and the fourth interface 14d. A case of being the interface 14d is also conceivable. In this case as well, the interfaces to be initialized by the first program include the interfaces not to be initialized by the second program (that is, the second interface 14b).

Then, when the IC chip 1 is activated, the CPU 10 determines whether or not the IC chip 1 is in a specific state, and based on the determination result, either the first program or the second program is executed. Selecting a program and initializing at least a portion of the interface to operate according to the selected program. Even with this configuration, it is possible to prevent unauthorized use and unintended operation of unused interfaces among a plurality of interfaces.

[2. Operation of IC chip 1]
Next, the operation of the IC chip 1 will be described separately for Examples 1 to 3. FIG.

(Example 1)
First, the operation of the IC chip 1 according to the first embodiment will be described with reference to FIGS. 2 and 3. FIG. In addition, in the first embodiment, it is assumed that the interface operability information is stored in the NVM 13 in the form of a permission flag. 2A and 2B are diagrams showing an example of contents stored in the NVM 13 in the first embodiment. FIG. 3A is a flowchart showing an example of processing of the CPU 10 when the IC chip 1 is activated in the first embodiment, and FIG. 4 is a flow chart showing an example of processing of the CPU 10 when a command for updating information is received; The processes shown in FIGS. 3A and 3B are executed according to an initial setting program or the like in the OS.

In the example of ^FIG . 2A, the ISO7816 permission flag F1, the SWP permission flag F2, the I2C permission flag F3, and the SPI permission flag F4 are stored in a predetermined area of the NVM 13 (for example, an area specified by the interface identifier). It is The ISO7816 permission flag F1 is a flag indicating whether or not to operate the first interface 14a, and is "1" indicating permission in the example of FIG. 2(A). The SWP permission flag F2 is a flag indicating whether or not to operate the second interface 14b, and is set to "0" indicating non-permission in the example of FIG. 2(A). ^The I2C permission flag F3 is a flag indicating whether or not to operate the third interface 14c, and is set to "0" indicating non-permission in the example of FIG. 2(A). The SPI permission flag F4 is a flag indicating whether or not to operate the fourth interface 14d, and is "0" indicating disapproval in the example of FIG. 2(A). Thus, in the example of FIG. 2A, permission flags are stored in the NVM 13 for each of the first to fourth interfaces 14a to 14d. However, if, for example, there is an interface whose life cycle must continue to operate, the permission flag for this interface may not be stored in NVM 13 . In the example of ^FIG . 2B, the SWP permission flag F2, the I2C permission flag F3, and the SPI permission flag F4 are stored in a predetermined area of the NVM 13, but the first interface 14a must continue to operate during its life cycle. The ISO7816 permission flag F1 is not stored because it is an interface that must be used.

The processing shown in FIG. 3A is started when the IC chip 1 is activated. The IC chip 1 is activated when the IC chip 1 receives a reset signal or when power is supplied to the IC chip 1 . At step S1 shown in FIG. 3A, the CPU 10 selects one of the first to fourth interfaces 14a to 14d for which a permission flag is stored. For example, first, the first interface 14a is selected. Note that if there is an interface for which the permission flag is not stored, that is, an interface that must continue to operate in terms of its life cycle, for example, immediately before step S1, that interface (in the example of FIG. 2B, the first interface 14a is applicable) is executed. Interfaces for which the permission flag is not stored are described in the program so that initialization processing is always performed.

Next, the CPU 10 determines whether or not the permission flag of the interface selected in step S1 indicates "permitted" (step S2). When the CPU 10 determines that the permission flag of the selected interface indicates "permitted" (step S2: YES), the CPU 10 executes initialization processing of the interface selected in step S1 (step S3), and proceeds to step S5. . In this initialization process, initial setting for operating the selected interface, for example, setting of the communication speed of the interface is performed. Note that in this initialization process, the potential of terminals used for the interface may be set (for example, set to a high level).

On the other hand, when the CPU 10 determines that the permission flag of the interface selected in step S1 does not indicate "permitted" (step S2: NO), the CPU 10 executes stop processing of the interface selected in step S1 (step S4). , go to step S5. In this stop processing, initial setting for not operating the selected interface, for example, setting for cutting off the power supply to the terminal used for the interface is performed. It should be noted that in this stop processing, the potential of the terminal used for the interface may be set (for example, set to low level). Alternatively, when the CPU 10 determines that the permission flag of the selected interface does not indicate "permitted" (step S2: NO), the CPU 10 proceeds to step S5 without performing the stop processing (that is, without proceeding to step S4). It may be configured as

In step S5, the CPU 10 determines whether or not there is an interface that has not been selected in step S1 among the interfaces for which permission flags are stored. When the CPU 10 determines that there is an interface that has not yet been selected (step S5: YES), the process returns to step S1 and selects an interface that has not yet been selected. Then, the CPU 10 performs the processes after step S2 for the selected interface. In this way, when the IC chip 1 is activated, the CPU 10 determines whether or not to operate each interface based on the permission flag stored for each interface. flag is "1") to initialize the interface to operate.

On the other hand, when the CPU 10 determines that there is no interface that has not been selected yet (step S5: NO), the process shown in FIG. 3(A) ends. Here, in a case where the IC chip 1 is activated by receiving a reset and the processing shown in FIG. After the process shown in FIG. 3A is completed, the system waits for a command from an external device (the same applies to the second and third embodiments). On the other hand, in the case where the IC chip 1 is activated by power supply and the processing shown in FIG. 3A is started, after the processing shown in FIG. (The same applies to Examples 2 and 3).

The interface operability information may be stored in the NVM 13 in the form of a permission list. In this case, identifiers of interfaces to be operated are registered in the permission list. Then, when the IC chip 1 is activated, the CPU 10 selects a part of the first to fourth interfaces 14a to 14d (that is, the identifiers are registered in the permission list) based on the stored permission list. You will need to make initial settings to operate the Alternatively, the interface operability information may be stored in the NVM 13 in the form of a disapproval list. In this case, identifiers of interfaces that are not to be operated are registered in the disapproval list. Then, when the IC chip 1 is activated, the CPU 10 selects some of the first to fourth interfaces 14a to 14d (that is, interfaces whose identifiers are not registered in the non-permission list) based on the stored non-permission list. ) to operate the interface.

Next, the processing shown in FIG. 3B is started when a command to update the operability information of the interface is received from an external device via any interface in the operating state. This command is composed of, for example, an APDU (Application Protocol Data Unit), and the APDU is composed of, for example, a header including CLA, INS, P1 and P2, and a body including Lc and Data. Here, CLA indicates a command class (instruction class), INS indicates a command code (instruction code), and P1 and P2 indicate command parameters (instruction parameters). Lc indicates the length of Data, and Data indicates updated data of the interface operability information.

At step S6 shown in FIG. 3B, the CPU 10 identifies the permission flag stored in the NVM 13 based on the update data included in the received command. For example, if the update data includes an interface identifier, the CPU 10 identifies the permission flag on the NVM 13 from the identifier indicated by the update data. Note that the update data may include updated permission flags corresponding to all interfaces in a predetermined order. In this case, the CPU 10 identifies each permission flag on the NVM 13 .

Next, the CPU 10 updates the permission flag specified in step S6 (that is, the permission flag stored in the NVM 13) (for example, rewrites "1" to "0") (step S7). Note that when the interface operability information is stored in the form of a permission list, the update data includes, for example, the permission list after the update. In this case, the CPU 10 updates the permission list on the NVM 13 based on the permission list indicated by the update data included in the received command (overwrites the permission list indicated by the update data). Next, the CPU 10 transmits a response to the command (including, for example, a status word indicating normal termination) to the external device (step S8), and terminates the processing shown in FIG. 3B.

As described above, according to the first embodiment, the NVM 13 stores operability information for each interface. Since it is configured to be able to set whether or not, for example, it is used in the manufacturing process (for example, it has a high utility value in terms of speed, or it has to be used depending on the manufacturing equipment), but it is not used in the service in the market. prevent unintended use and unintended operation. In addition, since it is not necessary to prepare an OS having different interface correspondences for each product on which the IC chip 1 is mounted, it is possible to improve development efficiency without lowering the reusability of software. Moreover, since the operability information of the interface is configured to be updated by a command from an external device, the operability of each interface can be flexibly updated in accordance with the change in the situation after the service is started.

(Example 2)
Next, the operation of the IC chip 1 according to the second embodiment will be described with reference to FIGS. 4 and 5. FIG. Note that, in the second embodiment, the permission flag of the interface is not used. FIG. 4 is a diagram showing an example of contents stored in the NVM 13 in the second embodiment. In the example of FIG. 4, the state management variables are stored in a predetermined area of NVM13. The initial setting programs stored in the NVM 13 include a first program for performing initial settings for operating all interfaces and a second program for performing initial settings for operating some interfaces. include. FIG. 5 is a flow chart showing an example of processing of the CPU 10 when the IC chip 1 is activated in the second embodiment. Note that the processing shown in FIG. 5 is executed according to an initial setting program or the like in the OS.

The processing shown in FIG. 5 is started when the IC chip 1 is activated. At step S11 shown in FIG. 5, the CPU 10 refers to the state management variables stored in the NVM 13 to determine whether the IC chip 1 is in a specific state. For example, if the state management variable is a value indicating the manufacturing completed state, it is determined that the IC chip 1 is in a specific state (for example, manufacturing completed state). When the CPU 10 determines that the IC chip 1 is not in the specific state (step S11: NO), the CPU 10 selects the first program (in other words, selects the storage start address of the first program), and selects the first program ( In other words, the first to fourth interfaces 14a to 14d (that is, all interfaces) are initialized according to the first program from the storage start address (step S12), and the process shown in FIG. 5 is terminated. do. The contents of this initialization process are the same as in the first embodiment.

On the other hand, when the CPU 10 determines that the IC chip 1 is in the specific state (step S11: YES), the CPU 10 selects the second program, and according to the selected second program, controls the first to fourth interfaces 14a to 14d. A specific interface (that is, a part of the interface) is initialized (step S13), and the process shown in FIG. 5 is terminated. Identifiers of, for example, the second interface 14b and the third interface 14c are described in the second program as specific interfaces to be initialized. It should be noted that, as in the first embodiment, interfaces that are not subject to the initialization process are either stopped or are not processed at all.

As described above, according to the second embodiment, the first program for performing initial settings for operating all interfaces and the second program for performing initial settings for operating some interfaces are provided. A program (a first program or a second Since it is possible to set whether or not to operate each interface according to the program), it is used in the manufacturing process (for example, it has high utility value in terms of speed, or it has to be used depending on the manufacturing equipment) can prevent unauthorized use and unintended operation of interfaces that are not used in services on the market. In addition, since it is not necessary to prepare an OS having different interface correspondences for each product on which the IC chip 1 is mounted, it is possible to improve development efficiency without lowering the reusability of software. Moreover, since the configuration is such that the first program or the second program can be selected based on the state management variables stored in the NVM 13, the initialization of either one can be performed more efficiently. In the second embodiment, the first to fourth interfaces 14a to 14d (that is, all interfaces) are used as examples of interfaces to be initialized by the first program. The interface may be a part of the first to fourth interfaces 14a to 14d (that is, it may not be all of the interfaces).

(Example 3)
Next, the operation of the IC chip 1 according to the third embodiment will be described with reference to FIGS. 6 and 7. FIG. In addition, in the third embodiment, it is assumed that interface operability information is stored in the NVM 13 in the form of a permission flag. 6A and 6B are diagrams showing an example of contents stored in the NVM 13 in the third embodiment. In the example of ^FIG . 6A, state management variables, ISO7816 permission flag F1, SWP permission flag F2, I2C permission flag F3, and SPI permission flag F4 are stored in a predetermined area of NVM13. On the other hand, in the example of ^FIG . 6B, the state management variables, the SWP permission flag F2, the I2C permission flag F3, and the SPI permission flag F4 are stored in a predetermined area of the NVM13. FIG. 7A is a flow chart showing an example of processing of the CPU 10 when the IC chip 1 is activated in the third embodiment, and FIG. 4 is a flow chart showing an example of processing of the CPU 10 when a command for updating information is received; The processes shown in FIGS. 7A and 7B are executed according to an initial setting program or the like in the OS. The processing (steps S31 to S33) shown in FIG. 7B is the same as the processing (steps S6 to S8) shown in FIG. 3B, so redundant description will be omitted.

The processing shown in FIG. 7A is started when the IC chip 1 is activated. At step S21 shown in FIG. 7A, the CPU 10 refers to the state management variables stored in the NVM 13 to determine whether the IC chip 1 is in a specific state. For example, if the state management variable is a value indicating a service-on state, it is determined that the IC chip 1 is in a specific state (eg, service-on state). When the CPU 10 determines that the IC chip 1 is not in the specific state (step S21: NO), the CPU 10 executes initialization processing of the first to fourth interfaces 14a to 14d (step S22). Terminate the indicated process.

On the other hand, when the CPU 10 determines that the IC chip 1 is in a specific state (step S21: YES), it selects one interface for which a permission flag is stored, from among the first to fourth interfaces 14a to 14d. (Step S23). If there is an interface for which the permission flag is not stored, for example, the initialization process for that interface (the first interface 14a in the example of FIG. 6B) is executed immediately before step S23.

Next, the CPU 10 determines whether or not the permission flag of the interface selected in step S23 indicates "permitted" (step S24). When the CPU 10 determines that the permission flag of the selected interface indicates "permitted" (step S24: YES), the CPU 10 executes initialization processing of the interface selected in step S23 (step S25), and proceeds to step S27. . The contents of this initialization process are the same as in the first embodiment.

On the other hand, when the CPU 10 determines that the permission flag of the interface selected in step S23 does not indicate "permitted" (step S24: NO), the CPU 10 executes stop processing of the interface selected in step S23 (step S26). , the process proceeds to step S27. The contents of this stop processing are the same as in the first embodiment. As in the first embodiment, if it is determined that the permission flag of the selected interface does not indicate "permitted", the processing may proceed to step S27 without performing the stop processing.

In step S27, the CPU 10 determines whether or not there is an interface that has not been selected in step S23 among the interfaces for which permission flags are stored. When the CPU 10 determines that there is an interface that has not yet been selected (step S27: YES), the process returns to step S23 to select an interface that has not yet been selected. Then, the CPU 10 performs the processes after step S24 for the selected interface. On the other hand, when the CPU 10 determines that there is no interface that has not been selected yet (step S27: NO), it ends the processing shown in FIG. 7A.

As described above, according to the third embodiment, whether or not to perform initial setting referring to interface operability information is determined according to the state of the IC chip 1 (for example, manufacturing completed state or service input state). Therefore, it is possible to avoid the initial setting referring to the operability information of the interface, for example, before entering the manufacturing completion state or the service input state, and as a result, perform the initial setting to operate the interface more efficiently. can do.

1 IC chip 10 CPU
11 ROMs
12 RAMs
13 NVM
14a to 14d 1st to 4th interfaces

Claims (11)

An electronic information storage medium comprising a plurality of interfaces,
a first program for performing initial settings for operating one or more of the plurality of interfaces; a second program for performing initial settings for operating some of the plurality of interfaces; a storage means for storing
When the electronic information storage medium is activated, it is determined whether or not the electronic information storage medium is in a specific state, and one of the first program and the second program is selected based on the result of the determination. setting means for selecting a program of and performing initial setting for operating at least the part of the interface according to the selected program;
with
An electronic information storage medium, wherein the interface to be initialized by the first program includes an interface not to be initialized by the second program. An electronic information storage medium comprising a plurality of interfaces,
storage means for storing operability information indicating whether or not to operate at least one interface among the plurality of interfaces;
setting means for performing initial setting for operating a part of the interface based on the operability information when the electronic information storage medium is activated;
An electronic information storage medium comprising: The setting means determines whether or not the electronic information storage medium is in a specific state when the electronic information storage medium is activated, and if it is determined that the electronic information storage medium is in the specific state 3. The electronic information storage medium according to claim 2, wherein an initial setting for operating said part of the interfaces is performed based on said operation propriety information. the operability information is stored in the storage means for each of the plurality of interfaces;
The setting means determines whether or not to operate each interface based on the operability information stored for each interface, and performs initial setting to operate the interface determined to be operated. 4. The electronic information storage medium according to claim 2 or 3. further comprising update means for updating the operability information stored in the storage means when a command for updating the operability information is received from an external device via any of the interfaces in an operating state. 5. The electronic information storage medium according to any one of claims 2 to 4, characterized by: An IC chip comprising a plurality of interfaces,
a first program for performing initial settings for operating one or more of the plurality of interfaces; a second program for performing initial settings for operating some of the plurality of interfaces; a storage means for storing
When the IC chip is activated, it is determined whether or not the IC chip is in a specific state, and one of the first program and the second program is selected based on the result of the determination. and setting means for performing initial setting for operating at least the part of the interface according to the selected program;
with
An IC chip, wherein the interfaces to be initialized by the first program include interfaces not to be initialized by the second program. An IC chip comprising a plurality of interfaces,
storage means for storing operability information indicating whether or not to operate at least one interface among the plurality of interfaces;
setting means for performing initial setting for operating a part of the interface based on the operability information when the IC chip is activated;
An IC chip comprising: An initialization method executed by a computer contained in an electronic information storage medium having multiple interfaces, comprising:
a first program for performing initial settings for operating one or more of the plurality of interfaces; a second program for performing initial settings for operating some of the plurality of interfaces; and storing
When the electronic information storage medium is activated, it is determined whether or not the electronic information storage medium is in a specific state, and one of the first program and the second program is selected based on the result of the determination. selecting a program for and initializing at least the portion of the interface to operate according to the selected program;
including
The initial setting method, wherein the interfaces to be initialized by the first program include interfaces not to be initialized by the second program. An initialization method executed by a computer contained in an electronic information storage medium having multiple interfaces, comprising:
storing operability information indicating whether or not to operate at least one interface among the plurality of interfaces;
performing initial setting for operating a part of the interface based on the operability information when the electronic information storage medium is activated;
An initial setting method, comprising: A computer contained in an electronic information storage medium having multiple interfaces,
a first program for performing initial settings for operating one or more of the plurality of interfaces; a second program for performing initial settings for operating some of the plurality of interfaces; and storing
When the electronic information storage medium is activated, it is determined whether or not the electronic information storage medium is in a specific state, and one of the first program and the second program is selected based on the result of the determination. selecting a program for and initializing at least the portion of the interface to operate according to the selected program;
An initialization program that causes the execution of
The initial setting program, wherein the interfaces to be initialized by the first program include interfaces not to be initialized by the second program. A computer contained in an electronic information storage medium having multiple interfaces,
storing operability information indicating whether or not to operate at least one interface among the plurality of interfaces;
performing initial setting for operating a part of the interface based on the operability information when the electronic information storage medium is activated;
An initial setting program characterized by executing

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