JP6324494B2 - 記憶システムおよびエイリアス・メモリ - Google Patents
記憶システムおよびエイリアス・メモリ Download PDFInfo
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- JP6324494B2 JP6324494B2 JP2016516745A JP2016516745A JP6324494B2 JP 6324494 B2 JP6324494 B2 JP 6324494B2 JP 2016516745 A JP2016516745 A JP 2016516745A JP 2016516745 A JP2016516745 A JP 2016516745A JP 6324494 B2 JP6324494 B2 JP 6324494B2
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- JP
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- Prior art keywords
- memory
- block
- data
- request
- alias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/065—Replication mechanisms
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361828636P | 2013-05-29 | 2013-05-29 | |
| US61/828,636 | 2013-05-29 | ||
| US14/036,298 | 2013-09-25 | ||
| US14/036,298 US9678689B2 (en) | 2013-05-29 | 2013-09-25 | Storage systems and aliased memory |
| PCT/US2014/039634 WO2014193862A2 (en) | 2013-05-29 | 2014-05-28 | Storage systems and aliased memory |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016524228A JP2016524228A (ja) | 2016-08-12 |
| JP2016524228A5 JP2016524228A5 (enExample) | 2017-07-06 |
| JP6324494B2 true JP6324494B2 (ja) | 2018-05-16 |
Family
ID=51986493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016516745A Active JP6324494B2 (ja) | 2013-05-29 | 2014-05-28 | 記憶システムおよびエイリアス・メモリ |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US9678689B2 (enExample) |
| EP (1) | EP3005126B1 (enExample) |
| JP (1) | JP6324494B2 (enExample) |
| CN (1) | CN105339909B (enExample) |
| BR (1) | BR112015029108B1 (enExample) |
| ES (1) | ES2865575T3 (enExample) |
| RU (1) | RU2669008C2 (enExample) |
| WO (1) | WO2014193862A2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9678689B2 (en) * | 2013-05-29 | 2017-06-13 | Microsoft Technology Licensing, Llc | Storage systems and aliased memory |
| US10049052B2 (en) * | 2014-10-27 | 2018-08-14 | Nxp Usa, Inc. | Device having a cache memory |
| US9740414B2 (en) | 2015-10-29 | 2017-08-22 | Pure Storage, Inc. | Optimizing copy operations |
| KR20170076878A (ko) * | 2015-12-24 | 2017-07-05 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
| US10210088B2 (en) | 2015-12-28 | 2019-02-19 | Nxp Usa, Inc. | Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache invalidation unit in a computing system |
| US11237758B2 (en) * | 2016-08-06 | 2022-02-01 | Wolley Inc. | Apparatus and method of wear leveling for storage class memory using address cache |
| US10387304B2 (en) * | 2017-12-28 | 2019-08-20 | Intel Corporation | Virtual transfer of data between memory and storage domains |
| TWI771926B (zh) * | 2021-02-25 | 2022-07-21 | 慧榮科技股份有限公司 | 資料儲存裝置以及非揮發式記憶體控制方法 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5119290A (en) * | 1987-10-02 | 1992-06-02 | Sun Microsystems, Inc. | Alias address support |
| JPH05158782A (ja) * | 1991-12-06 | 1993-06-25 | Hitachi Ltd | 記憶装置 |
| US6438672B1 (en) * | 1999-06-03 | 2002-08-20 | Agere Systems Guardian Corp. | Memory aliasing method and apparatus |
| RU2257609C2 (ru) * | 1999-10-21 | 2005-07-27 | Мацусита Электрик Индастриал Ко., Лтд. | Устройство доступа к полупроводниковой карте памяти, компьютерно-считываемый носитель записи, способ инициализации и полупроводниковая карта памяти |
| US6625725B1 (en) * | 1999-12-22 | 2003-09-23 | Intel Corporation | Speculative reuse of code regions |
| GB2372589B (en) * | 2001-02-21 | 2003-01-22 | 3Com Corp | Memory aliasing in a processor system |
| US7900017B2 (en) * | 2002-12-27 | 2011-03-01 | Intel Corporation | Mechanism for remapping post virtual machine memory pages |
| JP2004362464A (ja) * | 2003-06-06 | 2004-12-24 | Sony Corp | 不揮発メモリを利用したコンピュータシステム |
| US20050138307A1 (en) * | 2003-12-18 | 2005-06-23 | Grimsrud Knut S. | Storage performance improvement using data replication on a disk |
| US20110029723A1 (en) | 2004-08-06 | 2011-02-03 | Super Talent Electronics, Inc. | Non-Volatile Memory Based Computer Systems |
| US8417915B2 (en) * | 2005-08-05 | 2013-04-09 | Arm Limited | Alias management within a virtually indexed and physically tagged cache memory |
| US7872657B1 (en) * | 2006-06-16 | 2011-01-18 | Nvidia Corporation | Memory addressing scheme using partition strides |
| US7747817B2 (en) * | 2006-06-28 | 2010-06-29 | Unity Semiconductor Corporation | Performing data operations using non-volatile third dimension memory |
| JP4783229B2 (ja) * | 2006-07-19 | 2011-09-28 | パナソニック株式会社 | キャッシュメモリシステム |
| JP2009009665A (ja) * | 2007-06-29 | 2009-01-15 | Elpida Memory Inc | 半導体記憶装置 |
| US8074034B2 (en) * | 2007-07-25 | 2011-12-06 | Agiga Tech Inc. | Hybrid nonvolatile ram |
| US7855916B2 (en) | 2007-10-24 | 2010-12-21 | Rao G R Mohan | Nonvolatile memory systems with embedded fast read and write memories |
| US8250282B2 (en) * | 2009-05-14 | 2012-08-21 | Micron Technology, Inc. | PCM memories for storage bus interfaces |
| US8412987B2 (en) * | 2009-06-30 | 2013-04-02 | Micron Technology, Inc. | Non-volatile memory to store memory remap information |
| US20130033957A1 (en) * | 2011-08-04 | 2013-02-07 | Spar Food Machinery Manufacturing Co., Ltd. | Stirrer having Programmable Stirring Mode Control |
| CN103946810B (zh) * | 2011-09-30 | 2017-06-20 | 英特尔公司 | 配置非易失性随机访问存储器内分区的方法及计算机系统 |
| KR101767359B1 (ko) * | 2011-12-29 | 2017-08-10 | 인텔 코포레이션 | 다이렉트 액세스를 갖는 다중-레벨 메모리 |
| US9552176B2 (en) | 2013-04-12 | 2017-01-24 | Microsoft Technology Licensing, Llc | Block storage using a hybrid memory device |
| US9678689B2 (en) * | 2013-05-29 | 2017-06-13 | Microsoft Technology Licensing, Llc | Storage systems and aliased memory |
-
2013
- 2013-09-25 US US14/036,298 patent/US9678689B2/en active Active
-
2014
- 2014-05-28 WO PCT/US2014/039634 patent/WO2014193862A2/en not_active Ceased
- 2014-05-28 EP EP14802963.0A patent/EP3005126B1/en active Active
- 2014-05-28 ES ES14802963T patent/ES2865575T3/es active Active
- 2014-05-28 CN CN201480030762.4A patent/CN105339909B/zh active Active
- 2014-05-28 RU RU2015151012A patent/RU2669008C2/ru active
- 2014-05-28 JP JP2016516745A patent/JP6324494B2/ja active Active
- 2014-05-28 BR BR112015029108-2A patent/BR112015029108B1/pt active IP Right Grant
-
2017
- 2017-05-30 US US15/608,690 patent/US10216437B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| BR112015029108B1 (pt) | 2022-05-17 |
| BR112015029108A2 (pt) | 2017-07-25 |
| RU2015151012A (ru) | 2017-06-01 |
| US20170262207A1 (en) | 2017-09-14 |
| EP3005126A2 (en) | 2016-04-13 |
| ES2865575T3 (es) | 2021-10-15 |
| WO2014193862A3 (en) | 2015-04-09 |
| CN105339909A (zh) | 2016-02-17 |
| JP2016524228A (ja) | 2016-08-12 |
| RU2669008C2 (ru) | 2018-10-05 |
| CN105339909B (zh) | 2018-08-24 |
| US9678689B2 (en) | 2017-06-13 |
| US20140359203A1 (en) | 2014-12-04 |
| US10216437B2 (en) | 2019-02-26 |
| WO2014193862A2 (en) | 2014-12-04 |
| EP3005126B1 (en) | 2021-03-31 |
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