JP6312201B2 - Current signal generation circuit, current signal generation IC chip - Google Patents

Description

  The present invention relates to a current signal generation circuit that controls characteristics of an output current and a current signal generation IC chip using the current signal generation circuit.

  2. Description of the Related Art Conventionally, a control device that determines a vehicle sensor and a vehicle state and a system using the vehicle sensor are known. A wireless sensor used for this vehicle sensor is also known. The vehicle sensor measures the rotational speed of the vehicle wheel or vehicle tire, and the measurement value recorded by the vehicle sensor is processed into a data message representing the rotational speed of the wheel. Send wirelessly.

  For example, Patent Document 1 describes a configuration related to a system having a vehicle sensor, a control device for determining a vehicle state, and at least one vehicle sensor. The vehicle sensor described in Patent Document 1 has an interface for cable connection data transmission, and the interface transmits data between the vehicle sensor and the control device by a cable that can be implemented electrically or optically. To connect for. In such cable connection data transmission, so-called PSI5 (Peripheral Sensor Interface 5) is applied. According to PS15, other cable connection transmission is also possible depending on the required data transmission rate, installation conditions and cost. Also, cable connection data transmission can be performed unidirectionally or bidirectionally.

Patent Document 2 describes a sensor device and a method for supplying a signal for a rotation angle and a signal for a rotation torque. In the method described in Patent Document 2, the PSI5 protocol for digital interface is used for the sensor element.
In addition to the rotation speed sensor, there is a form in which an in-vehicle linear Hall IC using a magnetic sensor similarly performs PSI5 communication. In communication such as PSI5, a circuit that outputs a sensor signal is required to output a current as an output signal. Particularly, in recent years, when the communication is carried in a vehicle, the rise and fall of the output current is required. It is required to control the inclination of the image with high accuracy.

In addition to PSI5, DSI (Distributed System Interface) is also required to output current as an output signal.
In the conventional technique, a voltage having a certain slope is generated, and the generated voltage is converted into a current. FIG. 10 is a diagram illustrating a known low-pass filter circuit that generates a voltage having a certain slope. Circuit shown in FIG. 10, the resistive element 901 and a capacitor 902 connected between the terminal 903 and the terminal 904 is configured by connecting the other end of the capacitor 902 to the reference voltage _{V ss.} Circuit shown in FIG. 10, the output signal _{V out} having a time constant RC against the current output instruction signal _{V in} input from terminal 903 is output from the terminal 904.

Special table 2012-528032 gazette JP 2013-142699 A

However, elements such as the resistance element 901 and the capacitor 902 provided in the circuit shown in FIG. 10 have variations in characteristics. Variations in the characteristics of the resistance element 901 and the capacitor 902 cause variations in the characteristics of circuits that output current. For this reason, the circuit shown in FIG. 10 has a problem in controlling the output characteristics of the output current.
The present invention has been made in view of the above points, and provides a current signal generation circuit and a current signal generation IC chip capable of controlling current output characteristics regardless of variations in element characteristics. For the purpose.

In order to solve the above problems, an aspect of the current signal generation circuit of the present invention includes a reference current source that generates a reference current, a plurality of output current sources that generate and output an output current based on the reference current , A plurality of switching circuits provided in the output current source, for switching whether or not to output the output current, and a control for instructing the switching circuits of each of the plurality of output current sources to output or stop the output current; A control circuit that outputs a signal; and an output terminal that merges the output currents output from the plurality of output current sources in accordance with an instruction from the control circuit and outputs a sum of the plurality of output currents. The circuit sequentially outputs the control signals to the switching circuits of the plurality of output current sources, and at least some of the plurality of output current sources are generated by the other output current sources based on the control signals. Delayed a predetermined time than output said output current before rising, the than the output current outputted immediately before outputting the output current falls behind certain time, the switching circuit includes first A gate terminal of the first semiconductor transistor is connected to the reference current source via the resistance element; and the switching circuit further includes the resistance element and a ground potential. A first state in which a gate terminal of the first semiconductor transistor is connected to the reference current source via the resistance element; and a first state in which the gate terminal of the first semiconductor transistor is connected to the reference current source via the resistance element; A second state in which a gate terminal of the semiconductor transistor is connected to a ground potential via the resistance element and the second semiconductor transistor, and a gate of the first semiconductor transistor A third state in which a child is connected to the ground potential via the resistance element without passing through the second semiconductor transistor, and is in the first state at the time of rising, and the second state at the time of falling. After entering the state of 2, the state shifts to the third state.

Also, an aspect of the current signal generation circuit of the present invention, in the above-said reference current source, and a plurality of said output current source is in a mirror relationship.

An aspect of the current signal generation IC chip of the present invention includes: the current signal generation circuit according to any one of claims 1 to 10; and an input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage. An input power supply PAD and a detection circuit for detecting the trigger signal are provided, and the current signal generation circuit outputs an output current to the power supply PAD based on the trigger signal.
Further, according to an aspect of the current signal generation IC chip of the present invention, in the above aspect, the trigger detected by the detection circuit is input from the power supply PAD, an input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage. Based on the signal, the current signal generation circuit performs PSI5 communication or DSI communication for outputting an output current to the power supply PAD.

  It is possible to provide a current signal generation circuit and a current signal generation IC chip that can control current output characteristics regardless of variations in element characteristics.

It is a figure for demonstrating the current signal generation circuit of 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating a configuration of an output current source illustrated in FIG. 1. It is a figure for demonstrating the control signal shown in FIG. It is a figure for demonstrating the output current output according to the control signal shown in FIG. It is a figure for demonstrating the current signal generation circuit of 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a configuration of the output current source shown in FIG. 5. It is a figure for demonstrating the control signal shown in FIG. FIG. 6 is a diagram for explaining an output current output according to the control signal shown in FIG. 5. It is a figure for demonstrating the current signal generation IC chip of this invention. It is the figure which showed the well-known circuit which produces | generates the voltage with a fixed inclination.

Hereinafter, a first embodiment and a second embodiment of the current signal generation circuit of the present invention will be described.
[First Embodiment]
FIG. 1 is a diagram for explaining a current signal generation circuit according to a first embodiment of the present invention. The current signal generation circuit according to the first embodiment includes a reference current source 121, an N-type MOS transistor 122 in which a reference current I _REF supplied from the reference current source 121 flows between a source and a drain, and a current flowing in the MOS transistor 122. A plurality (k) of output current sources 101 to 10k that generate a mirror current of the output, and a control circuit 123 that outputs a plurality (k) of control signals ON1 to ONk for switching on and off the output current sources 101 to 10k. ,have.

The source terminal of the MOS transistor 122 is connected to the reference current source 121, and the drain terminal is grounded. A node connecting the reference current source 121 and the MOS transistor 122 and the plurality of output current sources 101 to 10k is referred to as a node N1. The gate terminal and the source terminal of the node N1 and the MOS transistor 122 are kept at the same potential.
The control circuit 123 includes a terminal 112 that the main clock signal MCLK is inputted, and a terminal 111 which is the current output instruction signal _{V in} is input, the. The control circuit 123 outputs k control signals ON1 to ONk, and each of the control signals ON1 to ONk is input to any one of the corresponding output current sources 101 to 10k. When the input control signals ON1 to ONk are at a high level, the output current sources 101 to 10k output current. The sum of the output currents I _{out — 1} to I _{out — k} output from the output current sources 101 to _{10 k} is output from the terminal 113 as the output current I _out .

FIG. 2 is a diagram for explaining the output current source 101. The output current sources 101 to 10k all have the same configuration. For this reason, in the first embodiment, only the configuration of the output current source 101 will be described, and the description of the other output current sources will be substituted.
The output current source 101 includes a NOT circuit 204, switches 201 and 202, and a MOS transistor 203. The switches 201 and 202 are connected in series, and the switch 201 is connected to the node N1. The control signal ON1 is input from the terminal 211 and controls the switch 201. Further, the control signal ON 1 is branched and controls the switch 202 via the NOT circuit 204. A gate terminal of the MOS transistor 203 is connected between the switches 201 and 202.

In the output current source 101 shown in FIG. 2, when the control signal ON1 is at a high level, the switch 201 is turned on and the switch 202 is turned off. When the switch 201 is turned on, the node N1 and the gate terminal of the MOS transistor 203 are connected and the MOS transistor 203 is turned on. When the MOS transistor 203 is turned on, the output current I _{out — 1} is output from the drain terminal of the MOS transistor 203 to the terminal 213. When the control signal ON1 is at the low level, the switch 201 is turned off and the switch 202 is turned on. When the switch 201 is turned off, the node N1 and the gate terminal of the MOS transistor 203 are disconnected, and the MOS transistor 203 is turned off. When the MOS transistor 203 is turned off, the output of the output current _{Iout_1} is stopped.

3, in the first embodiment, and a current output instruction signal _{V in} input to the control circuit 123, a main clock signal MCLK, a diagram showing a timing chart of control signals ON1～ONk. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates the level of each signal. The main clock signal MCLK is a pulse signal having a constant cycle and a pulse width. Current output instruction signal V _in is the main clock signal MCLK of a certain number (k-number in the first embodiment) is turned on, a signal which is turned while being turned off.

The control circuit 123 that operates in this way can be realized by a shift register, for example. In the first embodiment, the current output instruction signal V _in is up standing in synchronism with the falling edge of the main clock signal MCLK, the first embodiment is not limited to such a configuration .
Level of the control signal ON1 becomes a High level in synchronism with the rising edge of the main clock signal MCLK immediately after the current output instruction signal V _in is climbed standing, the main clock immediately after the current output instruction signal V _in fell standing It goes low in synchronization with the rising edge of signal MCLK. Further, the control signal ON2 becomes a high level in synchronization with the rising edge of the main clock signal MCLK immediately after the control signal ON1 rises, and at the rising edge of the main clock signal MCLK immediately after the control signal ON1 falls. Synchronously goes low. As described above, the control signal ON1 to the control signal ONk of this embodiment sequentially rises and falls at a timing shifted by one period of the main clock signal MCLK. Therefore, the control signal ONk changes at a timing delayed by (k−1) cycles of the main clock signal MCLK from the control signal ON1.

With such an operation, the output current sources 101 to _10k sequentially output the output currents _{Iout_1 to Iout_k} at a timing shifted by one cycle of the main clock signal MCLK, and the output stops. The output current I _out increases with a constant slope, and decreases with a constant slope equal to the slope when increasing.
FIG. 4 is a diagram for explaining a change in the output current _Iout output in response to the control signal shown in FIG. 4, and a current output instruction signal _{V in} input to the control circuit 123, a main clock signal MCLK and the output current is outputted from each of the output current source _{101~10k I} out_1 _~I out_k and the output current _{I out_1} ~ it is a diagram showing a timing chart for explaining the output current _{I out} is the sum of _I out_k. The horizontal axis in FIG. 4 indicates time, and the vertical axis indicates the signal level as an absolute value. Output current source 101~10k outputs each output current _I out_1 _{~I out_k} at the timing when the control signal ON1~ONk shown in FIG. 3 is output. Output current _I out_1 _{~I out_k} merges at one node, the sum of the output current _I out_1 _{~I out_k} is output as the output current _{I out} from the terminal 113.

The output current sources 101 to 10k all have the same configuration, and the output currents _{Iout_1 to Iout_k} all have the same value. Such an output current _I out_1 _{~I out_k} are sequentially output at predetermined time intervals, by the total of the output currents _I out_1 _{~I out_k} is the output current _{I out,} the output current _{I out} is increased with a constant gradient To do. Then, the output of the output current _I out_1 _{~I out_k} is sequentially stopped at a predetermined time interval, the output current _{I out} is lowered with a constant slope. For this reason, the current signal generation circuit of the first embodiment can control the characteristics of the output current, particularly the rate of change, with sufficiently high accuracy, regardless of variations in the characteristics of the resistance elements and capacitors.

In the first embodiment, since the output current _Iout shown in FIG. 4 is changed more gradually, a filter can be provided in the current signal generation circuit shown in FIG. Further, by connecting a resistance element to a node to which the gate of the MOS transistor 203 is connected, the resistance value of the resistance element and the parasitic capacitance of the gate of the MOS transistor 203 itself (hereinafter referred to as “gate capacitance”) It is charged with the time constant. For this reason, the output current _{Iout_1} flowing out from the MOS transistor 203 can be gradually increased.

[Second Embodiment]
Next, a current signal generation circuit according to a second embodiment of the present invention will be described. The current signal generation circuit of the second embodiment aims to change the output current _Iout shown in FIG. 4 more gradually.
FIG. 5 is a diagram for explaining the current signal generation circuit of the second embodiment. Note that in the second embodiment, components similar to those described in the first embodiment are denoted by the same reference numerals, and description thereof is partially omitted.

Current signal generation circuit of the second embodiment, the reference current source 121 for outputting a reference current _{I REF,} and MOS transistor 122 and the output current source 501~50k to mirror the reference current _{I REF,} the output current source 101~10k Is provided with a control circuit 523 for outputting control signals ON1 to ONk. The second embodiment is different from the first embodiment in that the control circuit 523 outputs the control signals OFF1 to OFFk together with the control signals ON1 to ONk.

FIG. 6 is a diagram for explaining a portion functioning as a switching circuit in the output current source 501. The output current sources 501 to 50k all have the same configuration. For this reason, in the second embodiment, only the configuration of the output current source 501 will be described, and the description of another output current source will be given.
The output current source 501 includes a NOT circuit 204, switches 201 and 202, and a MOS transistor 203. Further, in the output current source 501, one end of the resistance element 604 is connected to the gate terminal of the MOS transistor 203. The output current source 501 includes an N-type MOS transistor 603 having a drain terminal and a gate terminal connected to the other end of the resistance element 604. The switch 202 connects the source terminal of the MOS transistor 603 to the reference voltage V _{ss in} accordance with a signal output from the NOT circuit 204.

The output current source 501 includes a switch 605. The switch 605 is a switch that is turned on / off in accordance with the control signal OFF1, and when the switch 605 is turned on, a closed circuit including the MOS transistor 203 and the resistance element 604 is completed.
The output current source 501 shown in FIG. 6 can take the following three states a, b, and c.
State a: Switch 201 on, Switch 202 off, Switch 605 off State b: Switch 201 off, Switch 202 on, Switch 605 off State c: Switch 201 off, Switch 202 on, Switch 605 on In state a, the MOS transistor 203 The gate terminal is connected to the node N1 through the resistance element 604. At this time, the gate of the MOS transistor 203 is charged with a time constant based on the resistance value of the resistance element 604 and the parasitic capacitance of the gate of the MOS transistor 203 itself. For this reason, the output current _{Iout_1} flowing out from the MOS transistor 203 rises more slowly than in the first embodiment.

In the state b, the gate terminal of the MOS transistor 203 is connected to the reference voltage V _ss through the resistance element 604. At this time, since the electric charge accumulated in the gate capacitance of the MOS transistor 203 is gently discharged through the MOS transistor 603, the output current I _{out_1} flowing out from the MOS transistor 203 falls more slowly than in the first embodiment. .

In the second embodiment, even when the Vth of the MOS transistor 203 varies, the MOS transistor 603 can realize the output current I _{out_1} having a gentle slope.
In the state b, the MOS transistor 203 and the MOS transistor 603 are of the same N type, so that the second embodiment has the following merit. That is, given the rate at which the output current _{I out_1} outputted from MOS transistor 203 is removed from the output current _{I out,} stored in the gate capacitance of MOS transistors having a threshold voltage is not correlated with the threshold voltage _{V th} of the MOS transistor 203 When the discharged charges are discharged, the discharge time constant varies among the output current sources 101 to 10k due to variations in the threshold voltage in the process.

As shown in FIG. 6, the charge accumulated in the gate capacitance of the diode-connected MOS transistor 603 is discharged in a short time until V _gs reaches the threshold voltage V _th of the MOS transistor 603, and then the relative The discharge current converges to 0 over a long time. In other words, if the MOS transistors 203 and 603 are transistors of the same type (N-type in the second embodiment), the influence of variations in the threshold voltage _Vth of the MOS transistors in the output current source 101 is offset and accurate shut-off is performed. You can get time.

In the state c, the gate terminal of the MOS transistor 203 is connected to the reference voltage V _ss through the resistance element 604. At this time, a path is formed in which the gate terminal of the MOS transistor 203 is connected to the reference voltage V _ss without passing through the MOS transistor 603. For this reason, the output current I _{out_1} output from the MOS transistor 203 is completely removed from the output current I _out .

7, in the second embodiment, and a current output instruction signal _{V in} input to the control circuit 523 is a diagram showing a main clock signal MCLK, a timing chart of control signals ON1~ONk and OFF1～OFFk. In FIG. 7, the horizontal axis indicates time, and the vertical axis indicates the level of each signal. The relationship between the main clock signal MCLK and the control signals ON1 to ONk is the same as that in the first embodiment. The control signals OFF1 to OFFk are at a low level while the control signals ON1 to ONk are at a high level, and are at a high level while the control signals ON1 to ONk are at a low level.

FIG. 8 is a diagram for explaining a change in the output current _Iout output in response to the control signal shown in FIG. 7, and a current output instruction signal _{V in} input to the control circuit 523, a main clock signal MCLK and the output current is outputted from each of the output current source _{101~10k I} out_1 _~I out_k and the output current _{I out_1} ~ it is a diagram showing a timing chart for explaining the output current _{I out} is the sum of _I out_k. In FIG. 8, the horizontal axis indicates time, and the vertical axis indicates the signal level. As shown in FIG. 8, the second embodiment, the output current _I out_1 _{~I out_k} than the first embodiment is slowly rising, slowly falls. For this reason, the output current I _out of the second embodiment changes more slowly at the rise and fall than in the first embodiment.

  FIG. 9 is a circuit configuration diagram for explaining a current signal generation IC chip including the current signal generation circuit of the present invention. The IC chip shown in FIG. 9 includes a power supply PAD 21, a regulator circuit 22, a detection circuit 24, a digital circuit 25, and a current signal generation circuit 26. The current signal generation circuit 26 may be either the current signal generation circuit of the first embodiment or the current signal generation circuit of the second embodiment.

The power supply PAD 21 receives an input signal in which a trigger signal _Str having a pulse waveform is superimposed on the power supply voltage VDD. Further, the detection circuit 24 detects the trigger signal S _tr . The detected trigger signal S _tr is calculated by the digital circuit 25. The current signal generation circuit 26 outputs an output current to the power supply PAD 21 based on the output signal of the digital circuit 25. The regulator circuit 22 is connected to the power supply PAD21.

That is, the current signal generation IC chip shown in FIG. 9 includes a power supply PAD21 to which an input signal in which a trigger signal _Str having a pulse waveform is superimposed on a power supply voltage, and a detection circuit 24 that detects the trigger signal _Str. And a current signal generation circuit 26 that outputs a predetermined signal as a current to the power supply PAD 21 based on the detected trigger signal _Str .
According to such a current signal generation IC chip, it is possible to control the current output characteristics regardless of variations in element characteristics. Therefore, the current output from the power supply PAD21 can be accurately performed in PSI5 communication or DSI communication. Can communicate. A regulator circuit 22 is connected to the power supply PAD 21 and generates a voltage for operating the detection circuit 24 and the like.

  In addition, this invention is not limited to the said 1st Embodiment and 2nd Embodiment. For example, in the first embodiment and the second embodiment, all of the output current sources operate according to the control signal and output the output current, but only some of the plurality of output current sources are based on the control signal, The output current source may output an output current that rises after a certain time delay from the output current output immediately before and falls after a certain time delay from the output current output immediately before. In addition to the configuration in which the output current constituted by the NMOS transistor is drawn from the Iout terminal, a configuration in which the output current is constituted by the PMOS transistor and flows into the Iout terminal may be employed. In the case of a PMOS transistor, the voltage range of the external VDD at the IOUT terminal is set appropriately so that the PMOS transistor that drives the output is turned on.

  The present invention can be applied to any circuit that outputs current. In particular, the present invention is suitable for a circuit in which the output current is required to change with a constant slope with high accuracy.

21 Power PAD
22 regulator circuit 24 detection circuit 25 digital circuit 26 current signal generation circuit 101-10k, 501-50k output current source 111, 112, 113, 211, 213 terminal 121 reference current source 122, 203, 603 MOS transistor 123, 523 control circuit 201, 202, 605 switch 204 NOT circuit 604 resistance element N1 node

Claims (4)

A reference current source for generating a reference current;
A plurality of output current sources for generating and outputting an output current based on the reference current ;
A plurality of switching circuits provided in the output current source, for switching whether to output the output current;
A control circuit that outputs a control signal that instructs the switching circuit of each of the plurality of output current sources to output or stop the output current;
An output terminal that merges the output currents output from the plurality of output current sources according to an instruction of the control circuit, and outputs a sum of the plurality of output currents;
With
The control circuit sequentially outputs the control signal to the switching circuit of the plurality of output current sources,
At least some of the plurality of output current sources rise based on the control signal with a certain time delay from the output current output immediately before by the other output current source, and the output current output immediately before Output the output current falling after a certain time delay from the output current ,
The switching circuit includes a first semiconductor transistor and a resistance element, and a gate terminal of the first semiconductor transistor is connected to the reference current source via the resistance element, and the switching circuit The circuit includes a second semiconductor transistor that is diode-connected between the resistance element and a ground potential;
A first state in which a gate terminal of the first semiconductor transistor is connected to the reference current source through the resistance element; and a gate terminal of the first semiconductor transistor is the resistance element and the second semiconductor transistor. And a third state in which the gate terminal of the first semiconductor transistor is connected to the ground potential via the resistance element without going through the second semiconductor transistor. And take
A current signal generation circuit configured to shift to the third state after the first state at the time of rising and the second state at the time of falling .   The current signal generation circuit according to claim 1, wherein the reference current source and the plurality of output current sources are in a mirror relationship. A current signal generation circuit according to claim 1 or 2 ,
A power supply PAD that receives an input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage;
A detection circuit for detecting the trigger signal;
With
The current signal generation circuit is a current signal generation IC chip that outputs an output current to the power supply PAD based on the trigger signal. An input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage is input from the power supply PAD, and the current signal generation circuit outputs an output current to the power supply PAD based on the trigger signal detected by the detection circuit The current signal generation IC chip according to claim 3 , which performs PSI5 communication or DSI communication.

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