JP6302837B2 - スプリアス相殺を備えた統合された位相ロック及び乗算遅延ロックループ - Google Patents
スプリアス相殺を備えた統合された位相ロック及び乗算遅延ロックループ Download PDFInfo
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- JP6302837B2 JP6302837B2 JP2014542557A JP2014542557A JP6302837B2 JP 6302837 B2 JP6302837 B2 JP 6302837B2 JP 2014542557 A JP2014542557 A JP 2014542557A JP 2014542557 A JP2014542557 A JP 2014542557A JP 6302837 B2 JP6302837 B2 JP 6302837B2
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- 239000003990 capacitor Substances 0.000 claims description 17
- 230000003068 static effect Effects 0.000 claims description 15
- 230000006870 function Effects 0.000 claims description 9
- 238000013459 approach Methods 0.000 description 6
- 230000003111 delayed effect Effects 0.000 description 6
- 101000739577 Homo sapiens Selenocysteine-specific elongation factor Proteins 0.000 description 5
- 102100037498 Selenocysteine-specific elongation factor Human genes 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000596 photon cross correlation spectroscopy Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
Description
"A DLL-Based Programmable Clock Multiplier in 0.18um CMOS with -70dBc Reference Spur" P.C. Maulik, et al. IEEE JSSC, Vol. 42, No. I, August 2007
Claims (7)
- 装置であって、
マルチプレクサと、
前記マルチプレクサの出力と第1の入力とに結合される位相遅延回路と、
前記マルチプレクサの第2の入力に結合されるクロック参照ラインと、
前記マルチプレクサのセレクタ入力に結合される選択信号ラインを有するセレクタと、
前記位相遅延回路の出力に結合される信号分周器要素と、
可変遅延コントローラであって、前記位相遅延回路の出力と、前記信号分周器要素の第1の出力とに結合される、前記可変遅延コントローラと、
統合された位相検出器及びチャージポンプ要素(PDCHP)であって、少なくとも、前記可変遅延コントローラの出力と、前記セレクタの選択信号ラインと、前記信号分周器要素の第2の出力とに結合される、前記PDCHPと、
前記PDCHPの出力と、前記位相遅延回路のコントロール入力とに結合されるキャパシタと、
を含む、装置。 - 請求項1に記載の装置であって、
前記位相遅延回路が、各々が前記キャパシタの電圧により制御される、直列に結合される複数の位相遅延要素を含む、装置。 - 請求項1に記載の装置であって、
前記セレクタが、論理高に結合される第1の入力と、信号分周されたラインに結合されるクロック入力とを有するセレクタメモリを更に含み、
前記セレクタメモリが前記選択信号ラインで搬送される信号によりリセットされる、装置。 - 請求項1に記載の装置であって、
前記セレクタの出力が、選択信号ライン上の選択信号を生成するために、前記信号分周器要素の少なくとも1つの出力と組み合わされる、装置。 - 請求項1に記載の装置であって、
前記PDCHPが、
位相比較器要素と、
前記位相比較器要素の少なくとも1つの出力に結合され、前記位相比較器要素により制御される電流源と、
を含み、
前記位相遅延回路の位相遅延が前記電流源により生成される電流の関数である、装置。 - 請求項5に記載の装置であって、
前記可変遅延コントローラと前記セレクタとに結合される位相ロックループモードラインを更に含み、
前記セレクタが位相ロック出力を選択する、装置。 - 請求項1に記載の装置であって、
前記セレクタが前記クロック参照ラインを選択し、それにより、前記位相遅延回路の出力信号の静的位相オフセットが低減される、装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/300,143 | 2011-11-18 | ||
US13/300,143 US8384456B1 (en) | 2011-11-18 | 2011-11-18 | Integrated phase-locked and multiplying delay-locked loop with spur cancellation |
PCT/US2012/065903 WO2013075121A1 (en) | 2011-11-18 | 2012-11-19 | Integrated phase-locked and multiplying delay-locked loop with spur cancellation |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2017235017A Division JP6450825B2 (ja) | 2011-11-18 | 2017-12-07 | スプリアス相殺を備えた統合された位相ロック及び乗算遅延ロックループ |
Publications (2)
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JP2014533913A JP2014533913A (ja) | 2014-12-15 |
JP6302837B2 true JP6302837B2 (ja) | 2018-03-28 |
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JP2014542557A Active JP6302837B2 (ja) | 2011-11-18 | 2012-11-19 | スプリアス相殺を備えた統合された位相ロック及び乗算遅延ロックループ |
JP2017235017A Active JP6450825B2 (ja) | 2011-11-18 | 2017-12-07 | スプリアス相殺を備えた統合された位相ロック及び乗算遅延ロックループ |
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JP2017235017A Active JP6450825B2 (ja) | 2011-11-18 | 2017-12-07 | スプリアス相殺を備えた統合された位相ロック及び乗算遅延ロックループ |
Country Status (4)
Country | Link |
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US (1) | US8384456B1 (ja) |
JP (2) | JP6302837B2 (ja) |
CN (1) | CN103931103B (ja) |
WO (1) | WO2013075121A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6440481B2 (ja) | 2014-12-15 | 2018-12-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN106549664B (zh) * | 2015-09-22 | 2019-11-22 | 澜起科技股份有限公司 | 一种数字延迟锁相环及其锁定方法 |
US9787466B2 (en) | 2016-03-09 | 2017-10-10 | Ciena Corporation | High order hybrid phase locked loop with digital scheme for jitter suppression |
US10250264B2 (en) * | 2016-06-21 | 2019-04-02 | Marvell World Trade Ltd. | Multiplying delay-locked loop using sampling time-to-digital converter |
US10177772B2 (en) * | 2016-07-15 | 2019-01-08 | Qualcomm Incorporated | Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation |
US10281523B2 (en) | 2017-09-19 | 2019-05-07 | Ciena Corporation | Techniques and circuits for on-chip jitter and phase noise measurement in a digital test environment |
US10340902B1 (en) * | 2018-04-30 | 2019-07-02 | Analog Devices Global Unlimited Company | Multiplying delay locked loops with compensation for realignment error |
JP7420537B2 (ja) * | 2019-11-26 | 2024-01-23 | ローム株式会社 | 位相ロックループ回路 |
US11411569B2 (en) * | 2020-06-30 | 2022-08-09 | Qualcomm Incorporated | Calibration of sampling-based multiplying delay-locked loop (MDLL) |
KR20220039111A (ko) | 2020-09-21 | 2022-03-29 | 삼성전자주식회사 | 위상 고정 루프 장치 및 이의 동작 방법 |
CN112953867A (zh) * | 2021-01-29 | 2021-06-11 | 北京紫光展锐通信技术有限公司 | 基于延迟环的谐波调整方法及相关产品 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000036728A (ja) * | 1998-05-12 | 2000-02-02 | Mitsubishi Electric Corp | クロック生成回路及びクロック生成方法 |
US6208183B1 (en) * | 1999-04-30 | 2001-03-27 | Conexant Systems, Inc. | Gated delay-locked loop for clock generation applications |
US6952431B1 (en) * | 1999-10-28 | 2005-10-04 | Rambus Inc. | Clock multiplying delay-locked loop for data communications |
US6674772B1 (en) * | 1999-10-28 | 2004-01-06 | Velio Communicaitons, Inc. | Data communications circuit with multi-stage multiplexing |
CN1120572C (zh) * | 2000-02-12 | 2003-09-03 | 威盛电子股份有限公司 | 使用锁相环路调校的延迟装置及其调校方法 |
US6930524B2 (en) * | 2001-10-09 | 2005-08-16 | Micron Technology, Inc. | Dual-phase delay-locked loop circuit and method |
US6784707B2 (en) * | 2002-07-10 | 2004-08-31 | The Board Of Trustees Of The University Of Illinois | Delay locked loop clock generator |
US6982579B2 (en) * | 2003-12-11 | 2006-01-03 | Micron Technology, Inc. | Digital frequency-multiplying DLLs |
US6995554B2 (en) * | 2004-06-16 | 2006-02-07 | Agilent Technologies, Inc. | Delay-locked loop and a method of testing a delay-locked loop |
KR100732760B1 (ko) * | 2005-06-29 | 2007-06-27 | 주식회사 하이닉스반도체 | 지연고정루프회로 |
EP1913696B1 (en) * | 2005-08-03 | 2011-11-02 | Philips Intellectual Property & Standards GmbH | Delay-locked loop |
US7405604B2 (en) * | 2006-04-20 | 2008-07-29 | Realtek Semiconductor Corp. | Variable delay clock circuit and method thereof |
US7999585B2 (en) * | 2009-06-25 | 2011-08-16 | Analog Devices, Inc. | Calibrating multiplying-delay-locked-loops (MDLLS) |
KR20110002144A (ko) * | 2009-07-01 | 2011-01-07 | 칭화대학교 | 하이브리드 fir 필터링 기법이 적용된 지연 동기 루프 및 이를 포함하는 반도체 메모리 장치 |
US7994832B2 (en) * | 2009-11-06 | 2011-08-09 | Oracle America, Inc. | Aperture generating circuit for a multiplying delay-locked loop |
US8134393B1 (en) * | 2010-09-29 | 2012-03-13 | Motorola Solutions, Inc. | Method and apparatus for correcting phase offset errors in a communication device |
-
2011
- 2011-11-18 US US13/300,143 patent/US8384456B1/en active Active
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2012
- 2012-11-19 WO PCT/US2012/065903 patent/WO2013075121A1/en active Application Filing
- 2012-11-19 JP JP2014542557A patent/JP6302837B2/ja active Active
- 2012-11-19 CN CN201280055458.6A patent/CN103931103B/zh active Active
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Also Published As
Publication number | Publication date |
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US8384456B1 (en) | 2013-02-26 |
CN103931103B (zh) | 2018-02-16 |
CN103931103A (zh) | 2014-07-16 |
JP6450825B2 (ja) | 2019-01-09 |
JP2018082444A (ja) | 2018-05-24 |
JP2014533913A (ja) | 2014-12-15 |
WO2013075121A1 (en) | 2013-05-23 |
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