JP6302639B2 - Current monitoring circuit - Google Patents

Description

  The present invention relates to a current monitoring circuit.

  Semiconductor devices that handle a relatively large current, such as motor driver ICs and switching power supply ICs, are often equipped with overcurrent protection devices.

  FIG. 10 shows a conventional circuit for monitoring whether a monitoring target current such as a motor driving current is in an overcurrent state (see, for example, Patent Document 1). Constant currents 903 and 904 are supplied to the collectors of the transistors 901 and 902 forming the current mirror, and a sense resistor 905 in which a sense current Is corresponding to a monitored current (motor drive current or the like) flows is used as an emitter of the transistors 901 and 902. Connect between. Then, the transistor 906 is turned on or off through a change in the current flowing through the transistor 902 in accordance with the change in the monitoring target current (and hence the change in the sense current Is). Therefore, the overcurrent protection signal 907 corresponding to the magnitude of the monitoring target current can be obtained from the transistor 906. The logical value of the overcurrent protection signal 907 changes according to the magnitude relationship between the monitoring target current and the threshold current.

JP 2009-156835 A

  When an integrated circuit including the circuit of FIG. 10 is formed, the sense resistor 905 is formed as a polysilicon resistor or a diffused resistor on the integrated circuit, but the resistance value of the polysilicon resistor or the like varies relatively depending on the temperature. Further, the on-resistance of an output transistor (not shown) through which the monitoring target current flows also changes relatively greatly depending on the temperature. Furthermore, the absolute accuracy of the sense resistor 905 and the on-resistance is not high. On the other hand, the value of the threshold current described above depends on the sense resistor 905 and the on-resistance (this point will be apparent from the following description). Therefore, in the circuit of FIG. 10, a relatively large variation occurs in the threshold current. An increase in the variation of the threshold current hinders the high accuracy of the state monitoring of the monitoring target current.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a current monitoring circuit that contributes to higher accuracy of state monitoring of a current to be monitored.

  A current monitoring circuit according to the present invention includes first and second mirror transistors forming a current mirror, a constant current supply circuit for supplying a constant current to one end of each of the first and second mirror transistors, and a current to be monitored. Is connected in parallel to the target transistor, a series circuit of first and second sense transistors through which a sense current corresponding to the monitoring target current flows, and a third sense connected in series to the first mirror transistor A transistor and a monitoring output circuit for outputting a monitoring result signal corresponding to the current flowing through the second mirror transistor, and in series between the other ends of the first and second mirror transistors, the second and second mirror transistors. Three sense transistors are provided.

  For example, at least one of the first to third sense transistors may be an adjustable transistor formed such that its own on-resistance is variable.

  Specifically, for example, the adjustable transistor is formed by connecting a plurality of element transistors including one or more transistors in parallel, and turns on one or more element transistors that are turned on among the plurality of element transistors. The on-resistance of the adjustable transistor is formed by a resistor, and the on-resistance of the adjustable transistor may be controlled by controlling on / off of each element transistor.

  Further, for example, the logic of the monitoring result signal changes depending on the magnitude relationship between the monitoring target current and the threshold current, and the threshold current includes the on-resistance of the target transistor and the on-resistances of the first to third sense transistors. It can have a value according to the ratio.

  Further, for example, a constant current supplied to one end of the second mirror transistor is divided into the second mirror transistor and the monitoring output circuit according to the monitoring target current, and the monitoring output circuit is connected to the monitoring output circuit. The monitoring result signal may be output in accordance with the divided current.

  In addition, for example, a control circuit that determines whether the current to be monitored is in an overcurrent state based on the monitoring result signal and performs a predetermined protection operation based on the determination result is further provided in the current monitoring circuit. May be.

  A semiconductor device including an integrated circuit in which the current monitoring circuit is integrated may be formed.

  The semiconductor device may include a constant current generation circuit that generates the constant current using a reference voltage source and a resistance element. At this time, the resistance element is preferably provided outside the integrated circuit.

  For example, the reference voltage source may be formed using a semiconductor bandgap voltage.

  Further, an electric device including the above semiconductor device may be formed.

  ADVANTAGE OF THE INVENTION According to this invention, it is possible to provide the current monitoring circuit which contributes to the high precision of the state monitoring of the monitoring object current.

1 is a schematic block diagram of a motor drive system according to an embodiment of the present invention. It is a figure which shows the OCP circuit (overcurrent protection circuit) which concerns on a reference Example, and its peripheral circuit. It is a figure for demonstrating the resistance value in a part of circuit of FIG. 1 is a diagram illustrating an OCP circuit and its peripheral circuits according to a first embodiment of the present invention. FIG. 5 is a diagram for explaining resistance values in a part of the circuit of FIG. 4. FIG. 6 is a circuit diagram of a constant current generation circuit according to a second example of the present invention. FIG. 10 is a diagram illustrating a part of an OCP circuit according to a third embodiment of the present invention. It is a figure which concerns on 3rd Example of this invention and shows the other example of a part of OCP circuit. 1 is an external view of a printing apparatus according to the present invention. It is a conventional circuit diagram for performing current monitoring.

  Hereinafter, an example of an embodiment of the present invention will be specifically described with reference to the drawings. In each of the drawings to be referred to, the same part is denoted by the same reference numeral, and redundant description regarding the same part is omitted in principle. In this specification, for the sake of simplification, information, signals, physical quantities, and state quantities corresponding to the symbols or signs are described by writing symbols or signs that refer to information, signals, physical quantities, state quantities, or members. Or names of members, etc. may be omitted or abbreviated.

  FIG. 1 is a schematic block diagram of a motor drive system 1 according to an embodiment of the present invention. The motor drive system 1 includes a motor driver IC 10 (hereinafter simply referred to as “IC 10”) and a motor 20. The IC 10 is a semiconductor integrated circuit having a control circuit 11, a pre-driver 12, a driver 13, and an overcurrent protection circuit 14 (hereinafter referred to as OCP circuit 14), and is formed by integrating them.

  The control circuit 11 generates a pre-drive control signal that instructs to rotate the motor 20 in a desired state, and controls the operation of the IC 10 as a whole. The pre-driver 12 generates a drive control signal for the driver 13 by performing level shift and waveform shaping on the pre-drive control signal from the control circuit 11. The driver 13 supplies a drive current to the coils constituting the motor 20 based on the drive control signal from the pre-driver 12. This drive current is supplied to the motor 20 via an output stage provided in the driver 13. The output stage includes, for example, a high-side switch and a low-side switch connected in series with each other, and a predetermined DC voltage is applied to the output stage. The OCP circuit 14 monitors the drive current flowing through the coil of the motor 20 and generates an overcurrent protection signal Socp corresponding to the magnitude of the drive current.

  Although not shown in FIG. 1, the IC 10 includes a regulator that generates a predetermined internal voltage Vreg from the power supply voltage Vcc of the IC 10, an overvoltage protection circuit that monitors the occurrence of an overvoltage state of the power supply voltage Vcc, and the IC 10. Various circuit blocks such as a temperature protection circuit for monitoring whether or not an abnormal temperature state is generated are integrated.

  The control circuit 11 has an overcurrent protection function as a function particularly related to the present invention. In the overcurrent protection function, the control circuit 11 determines whether or not the drive current to the motor 20 is in an overcurrent state based on the overcurrent protection signal Socp from the OCP circuit 14, and determines a predetermined value based on the determination result. Perform protective actions. The signal Socp is a digital signal having a logical value of “1” or “0”, and a protection operation is performed when the logical value of the signal Socp is “1”. The protection operation includes, for example, stopping driving of the motor 20 and transmitting a predetermined abnormality signal to a host device (not shown) connected to the IC 10.

  Hereinafter, a specific configuration example of the OCP circuit 14 and a configuration example of a related circuit of the OCP circuit 14 will be described in detail in a plurality of embodiments. In the following description, a potential of 0 V (volt) serving as a reference for each voltage such as the internal voltage Vref is referred to as a reference potential, and a wiring, a metal layer, or a point having the reference potential is referred to as a ground.

<Reference Example>
First, a reference embodiment will be described with reference to FIG. FIG. 2 shows the OCP circuit 14Z as the OCP circuit 14 according to the reference embodiment, and also shows a part of the circuit in the driver 13. The transistor M0 functions as the low-side switch, and the drive current I2 of the motor 20 flows between the drain and source of the transistor M0. A sense current I1 corresponding to the drive current I2 flows through the transistor M1. The on-resistance of the transistor M1 is set to N times the on-resistance of the transistor M0. FIG. 2 is a circuit diagram used for comparison with FIG. 4 described later, and the operation and function of the circuit of FIG. 2 are clarified by referring to the description of FIG. 4 described later.

  In the circuit of FIG. 2, a calculation formula for a circuit portion including transistors M0 and M1 and a resistor R0 is considered (see also FIG. 3). The on-resistance of the transistor M0 is represented by R2, and the drain-source voltage of the transistor M0 is represented by Vo. Then, for this circuit portion, the following expressions (1) and (2) are established, and expression (3) is derived from expressions (1) and (2).

  Next, in the current balanced state of the current mirror composed of the transistors Q1 and Q2, that is, in the state where the constant current Iref from the transistor M12 flows through the emitter of the transistor Q2, the circuit portion composed of the transistors Q1 and Q2 and the resistors R0 and R1. Consider the formula for. In the current equilibrium state, Equation (4) is established for the circuit portion. Solving equation (4) for I1, equation (5) is obtained. Substituting equation (5) into equation (3) yields equation (6).

  For example, the constant current Iref is 30 μA (microamperes), N = 2410, and the resistors R0, R1, and R2 are 500Ω (ohms), 4.5 kΩ (kiloohms), and 0.22Ω, respectively. In some cases, the drive current I2 shown in Equation (6) is 1.12 A (ampere).

  In FIG. 2, when the actual driving current I2 exceeds the threshold current having the value on the right side of the equation (6), the sense current I1 becomes larger than the value on the right side of the equation (5). Part or all of Iref is supplied to the base of the transistor Q4 via the transistor Q3. As a result, the transistor Q4 is turned on and the signal Socp is at a low level. If the drive current I2 is smaller than the threshold current, the constant current Iref from the transistor M12 flows through the transistor Q2 without being supplied to the base of the transistor Q4, so that the transistor Q4 is turned off and the signal Socp becomes high level.

  In the circuit of FIG. 2, the threshold current depends on the on-resistance R2 of the transistor M0 and the resistors R0 and R1. The resistance value of the on-resistance R2 varies relatively depending on the temperature. The resistors R0 and R1 are formed as polysilicon resistors or diffused resistors on the integrated circuit, but the resistance value of such resistors also changes relatively greatly depending on the temperature. Further, the absolute accuracy of the on-resistance R2 and the resistors R0 and R1 is not high. Therefore, in the circuit of FIG. 2, a relatively large variation occurs in the threshold current. The variation here includes variation in threshold current due to temperature change and variation in threshold current due to resistance value errors of the resistors R0 to R2.

<< First Example >>
As a first embodiment, a specific configuration example of the OCP circuit 14 will be described. FIG. 4 shows an OCP circuit 14A as the OCP circuit 14 according to the first embodiment, and a partial circuit in the driver 13 is shown.

  The driver 13 is provided with a transistor M0, and the OCP circuit 14A is provided with transistors M1 to M3. The transistors M0 to M3 are each formed of an N-channel MOSFET (metal field oxide transistor (MOS field effect transistor)). The OCP circuit 14A is further provided with transistors Q1 to Q4 that are NPN bipolar transistors, transistors M10 to M12 that are P-channel MOSFETs, and a resistor 41. Monitor output circuit 50 is formed by transistors Q3 and Q4 and resistor 41. A constant current generation circuit 42 included in the components of the motor drive system 1 is connected to the OCP circuit 14A. Although the entire constant current generation circuit 42 can be provided in the IC 10, all or a part of the constant current generation circuit 42 can be provided outside the IC 10.

  The constant current generation circuit 42 generates a constant current Iref. The output terminal of the constant current generation circuit 42 is connected to the drain of the transistor M10, and the constant current Iref generated by the constant current generation circuit 42 flows to the drain of the transistor M10. The drain of the transistor M10 is commonly connected to the gates of the transistors M10, M11, and M12, and the sources of the transistors M10, M11, and M12 are commonly connected to the terminal 43 to which the internal voltage Vreg is applied. Therefore, the transistors M10 to M12 form a current mirror having the transistor M10 as the current input side and the transistors M11 and M12 as the current output side. As a result, a constant current Iref flows through the drains of the transistors M11 and M12. On the other hand, the drains of the transistors M11 and M12 are connected to the collectors of the transistors Q1 and Q2, respectively. Therefore, the transistors M11 and M12 function as first and second constant current sources that supply the constant current Iref to the collectors of the transistors Q1 and Q2, respectively.

  The base of the transistor Q1 is commonly connected to the collector of the transistor Q1 and the base of the transistor Q2, and a series circuit of transistors M2 and M3 is provided between the emitters of the transistors Q1 and Q2. As described above, the transistors Q1 and Q2 form a current mirror in a state where the voltage drop in the transistors M2 and M3 is applied between the emitters of the transistors Q1 and Q2. More specifically, the emitter of the transistor Q1 is connected to the drain of the transistor M3, the emitter of the transistor Q2 is connected to the drain of the transistor M2, and the sources of the transistors M2 and M3 are commonly connected to the ground.

  The drains of the transistors M0 and M1 are commonly connected to a terminal 44 to be connected to the coil of the motor 20. The source of the transistor M0 is connected to the ground. The source of the transistor M1 and the drain of the transistor M2 are commonly connected to the emitter of the transistor Q2.

  The collector and base of the transistor Q3 are connected in common to each other, and are also connected to the collector of the transistor Q2. The emitter of the transistor Q3 is connected to the base of the transistor Q4. The collector of the transistor Q4 is connected to the terminal 43 via the resistor 41, and the emitter of the transistor Q4 is connected to the ground. The collector potential of the transistor Q4 is the potential of the overcurrent protection signal Socp. When the transistor Q4 is on, the voltage level of the signal Socp is low, and when the transistor Q4 is off, the voltage level of the signal Socp is high. The low level signal Socp has a logical value “1” for which the above-described protection operation is to be performed, and the high level signal Socp has a logical value “0” for which the protection operation is not performed.

  As is well known, an arbitrary transistor has a first end, a second end, and a control end, and ON means a state where the first end and the second end of the transistor are conductive, and OFF means the first end of the transistor. It refers to a state where the first end and the second end are non-conductive (blocked). When the transistor is a bipolar transistor, one of the first end and the second end is a collector, the other is an emitter, and the control end is a base. When the transistor is a field effect transistor, one of the first end and the second end is a drain, the other is a source, and the control end is a gate.

  The gate voltage supply circuit 51 provided in the OCP circuit 14A applies the gate voltage Vgate1 to the gates of the transistors M0 and M1, applies the gate voltage Vgate2 to the gate of the transistor M2, and gates the gate of the transistor M3. A voltage Vgate3 is applied. Each of the transistors M0 to M3 functions as a switch. When the transistors M0 and M1 are turned on, the gate voltages Vgate1 to Vgate3 are generated and applied so that the transistors M2 and M3 are also turned on. The gate voltages Vgate1 to Vgate3 have the same potential (that is, for example, the gates of the transistors M0 to M3 are commonly connected). However, the gate voltages Vgate1 to Vgate3 may be different from each other. Of the gate voltages Vgate1 to Vgate3, only two voltages (for example, Vgate2 and Vgate3) may be common to each other. The signal Socp when the transistor M0 is off is invalid. Therefore, in the following, a state where the transistor M0 is on is considered.

  The transistor M0 functions as the low-side switch, and the drive current I2 of the motor 20 flows between the drain and source of the transistor M0. A sense current I1 corresponding to the drive current I2 flows between the source and drain of the transistor M1. As described above, the on-resistance of the transistor M0 is represented by R2. In this case, the transistors M0 to M3 are formed so that the on-resistances of the transistors M1, M2, and M3 are “N · R2”, “M · R2”, and “L · R2”, respectively. In order to realize this, the transistor M0 on the IC 10 is configured such that the source areas of the transistors M1, M2, and M3 are 1 / N times, 1 / M times, and 1 / L times the source area of the transistor M0, respectively. ˜M3 may be formed. N, M, and L have predetermined values, for example, values of several hundred to several thousand. Of course, the on-resistance of the transistor M0 refers to the resistance between the source and drain of the transistor M0 when the transistor M0 is on (the same applies to other field-effect transistors).

  The operation of the circuit of FIG. 4 will be described. First, consider the calculation formula for the first circuit portion comprising the transistors M0 to M2 (see also FIG. 5). For the first circuit portion, the following expressions (1A) and (2A) are established, and the expression (3A) is derived from the expressions (1A) and (2A). That is, “I2 = (N + M) · I1” is established.

  Next, the transistors Q1, Q2, M2, and M3 are formed in a current balanced state of the current mirror including the transistors Q1 and Q2, that is, in a state where the constant current Iref from the transistor M12 flows between the collector and the emitter of the transistor Q2. Consider the calculation formula for the second circuit portion. In the current balance state, Expression (4A) is established for the second circuit portion. Solving equation (4A) for I1, equation (5A) is obtained. Substituting equation (5A) into equation (3A) yields equation (6A).

  For example, when the constant current Iref is 31.9 μA (microamperes) and N = 2410, M = 2410, and L = 2690, the drive current I2 shown in the equation (6A) is 1.23 A (ampere). It becomes.

The value on the right side of the equation (6A) functions as a predetermined threshold current I _TH that distinguishes whether or not the drive current I2 is in an overcurrent state. When the driving current I2 is greater than the threshold current I _TH, since the sense current I1 becomes larger than the right side value of the formula (5A), a part or all of the constant current Iref from the transistor M12 through the transistor Q3 transistor As a result, the transistor Q4 is turned on and the signal Socp becomes low level. If the driving current I2 is smaller than the threshold current _{I TH,} a constant current Iref from the transistor M12 is to flow the transistor Q2 is not supplied to the base of the transistors Q4, transistor Q4 is a signal Socp a high level in the OFF .

Thus, the monitor output circuit 50 outputs a signal corresponding to the current flowing between the collector and emitter of the transistor Q2 as the overcurrent protection signal Socp. At this time, the logic of the overcurrent protection signal Socp changes in the magnitude relation between the driving current I2 and threshold current I _TH. More specifically, the constant current Iref supplied from the transistor M12 toward the collector of the transistor Q2 is divided into the transistor Q2 and the monitoring output circuit 50 in accordance with the drive current I2, and is divided into the monitoring output circuit 50. Accordingly, the logic of the overcurrent protection signal Socp changes. When receiving the low level signal Socp, the control circuit 11 determines that the drive current I2 is in an overcurrent state and performs the above-described protection operation.

According to the first embodiment, the threshold is determined by the ratio of the on-resistance of the transistor M0 and the on-resistances of the transistors M1 to M3 (in other words, the source area ratio between the transistors M0 and M1 to M3). The current I _TH can be set, and unlike the circuit of FIG. 2, the threshold current I _TH depends on the on-resistance R2 and the integrated circuit resistance (polysilicon resistance, etc .: R0 and R1 in FIG. 2). And are not affected by the resistance value error. Therefore, it is possible to suppress the variation in the threshold current I _TH. Further, an external resistor (Patent Document 1; resistor RNF in FIG. 2) for the IC as shown in Patent Document 1 is also unnecessary.

Note that when considering the calculation formula for the first circuit portion composed of the transistors M0 to M2, since the emitter current of the transistor Q2 actually flows into the transistor M2, the calculation formula is strictly the one described above (formula ( 2A) and (3A)). In the above description, when considering the equation for the first circuit portion, the emitter current of the transistor Q2 in I2 ≒ I _TH is assumed to sufficiently smaller than the sense current I1, ignoring the emitter current of transistor Q2. Even if this assumption was not, threshold current I _TH is, (such as polysilicon resistors: R0 and R1 in FIG. 2) integrated circuit resistor remains that is not influenced by the temperature characteristics of not.

<< Second Example >>
A second embodiment will be described. The matters described in the second embodiment are combined with the first embodiment.

The constant current generation circuit 42 of FIG. 4 can be configured as shown in FIG. The constant current generation circuit 42 of FIG. 6 includes a reference voltage source 61 that generates and outputs a reference voltage Vref, a resistor 62, an amplifier 63, and a transistor 64 formed as an NPN-type bipolar transistor. A current is generated as a constant current Iref. Therefore, the collector of the transistor 64 is connected to the drain of the transistor M10 (see also FIG. 4). A reference voltage Vref is applied to the non-inverting input terminal of the amplifier 63. The emitter of the transistor 64 is connected to the ground via the resistor 62, and the connection point between the emitter of the transistor 64 and the resistor 62 is connected to the inverting input terminal of the amplifier 63. The output terminal of the amplifier 63 is connected to the base of the transistor 64. As a result, when the resistance value of the resistor ₆₂ is represented by R ₆₂ , Iref = (Vref / R ₆₂ ) (however, the base current of the transistor 64 is ignored). Since the drain currents of the transistors M11 and M12 in FIG. 4 are determined by the collector current of the transistor 64, the constant current generation circuit 42 has a function of setting the value of the constant current Iref supplied from the transistors M11 and M12.

Here, a pad (not shown) for externally attaching the resistor 62 is provided on the IC 10, and the resistor 62 is formed by a resistor element (metal film resistor or the like) provided outside the IC 10. Thus, the temperature characteristics of the constant current Iref can be improved in the circuits of FIGS. 4 and 6 as compared with the circuit of FIG. 2 (in the circuit of FIG. 2, the polysilicon resistance formed on the IC 10 is reduced). Since the constant current Iref is generated by using this, the temperature variation of the constant current Iref is large). In addition, the reference voltage source 61 may be formed using a semiconductor band gap voltage (ie, the reference voltage source 61 may be a band gap reference). Thereby, the temperature characteristic of the constant current Iref can be further improved. Since threshold current I _TH with a value of the right side of the equation (6A) depends on the constant current Iref, by improving the temperature characteristics of the constant current Iref, it can be further reduced temperature variations in threshold current I _TH. The reference voltage source 61, the amplifier 63, and the transistor 64 may be formed on the IC 10.

  When the temperature characteristics of the threshold current were evaluated between the circuit of FIG. 2 and the circuit of FIG. 4, the following results were obtained. In the circuit of FIG. 2, the threshold current, which was 3.3 A when the ambient temperature of the IC 10 was −60 ° C., decreased to 1.76 A when the ambient temperature reached 150 ° C. (the variation amount was 1.54 A). On the other hand, in the case where the circuits of FIGS. 4 and 6 are used, the threshold current which was 1.673 A when the ambient temperature of the IC 10 was −60 ° C. was 1.635 A when the ambient temperature was 150 ° C. (Variation amount is 0.0301A). As described above, in the circuit configuration of FIG. 2, it is necessary to allow about ± 1 A as the temperature variation of the threshold current. However, the temperature variation of the threshold current is reduced to ± 0.1 A or less by the techniques of the first and second embodiments. I was able to suppress it. Further, if the constant current Iref can be adjusted toward the target value by forming the resistor 62 with a variable resistor, the accuracy of the threshold current can be further improved.

<< Third Example >>
A third embodiment will be described. The matters described in the third embodiment are combined with the first or second embodiment.

  The transistor M3 in FIG. 4 may be configured as shown in FIG. FIG. 7 is a partial circuit diagram of the IC 10 according to the third embodiment. In FIG. 7, the transistor M3 is formed by transistors 101 to 103 which are N-channel MOSFETs. The drains of the transistors 101 and 102 are commonly connected to the emitter of the transistor Q1, and the sources of the transistors 101 and 103 are commonly connected to the ground. The source of the transistor 102 and the drain of the transistor 103 are connected to each other. It is possible to make the on-resistances different between the transistors 101 to 103 by making the source areas different between the transistors 101 to 103. Here, the source areas of the transistors 101 to 103 are the transistor M0 ( 4), the on-resistance of each of the transistors 101 to 103 is assumed to be L ′ times the on-resistance R2 of the transistor M0.

  The gate voltage supply circuit 51 controls the on / off of each of the transistors 101 to 103 by supplying a gate voltage to each of the transistors 101 to 103. At this time, when the transistor M0 in FIG. 4 is turned on, the gate voltage supply circuit 51 can selectively perform the first on control, the second on control, or the third on control on the transistor M3. In the first on control, only the transistor 101 among the transistors 101 to 103 is turned on. In the second on control, only the transistors 102 and 103 among the transistors 101 to 103 are turned on. In the third on control, all of the transistors 101 to 103 are turned on.

Accordingly, the on-resistance (L · R2) of the transistor M3 becomes “L ′ · R2” when the first on-control is executed, and becomes “2 · L ′ · R2” when the second on-control is executed. When the on control is executed, “(2/3) · L ′ · R2”. In other words, it is possible to variably up to 3 stages on-resistance of the transistor M3, the result can be variably set up to 3 stages threshold current I _TH. If the threshold current I _TH can be varied, for example, an appropriate threshold current I _TH can be set according to the type of the motor 20 and the operation mode of the motor 20.

  In this way, the transistor M3 can be formed by connecting a plurality of element transistors in parallel. In the example of FIG. 7, the first element transistor is the transistor 101 itself, and the second element transistor includes the transistors 102 and 103. The on-resistance of the transistor M3 is formed by the on-resistance of one or more element transistors that are turned on among the plurality of element transistors. Therefore, the gate voltage supply circuit 51 can control the on-resistance of the transistor M3 by controlling on / off of each element transistor.

The number of element transistors forming the transistor M3 may be three or more. For example, as shown in FIG. 8, a third element transistor may be added to the transistor M3 in addition to the first and second element transistors described above. The third element transistor is composed of a series circuit of transistors 104 to 106 each having the same structure as that of the transistor 101, and is interposed in series between the emitter of the transistor Q1 and the ground, like the first and second element transistors. The gate voltage supply circuit 51 can individually control on / off of each element transistor by supplying a gate voltage to each element transistor. Note that the ON state of a certain element transistor means a state in which all the transistors in the element transistor are turned on, and the OFF state of a certain element transistor means a state in which all the transistors in the element transistor are turned off. Point to. When using the circuit of Figure 8, can be varied up to 7 stages on-resistance of the transistor M3, the result can be variable up to 7 stages threshold current I _TH.

  A transistor whose on-resistance is variable by using the configuration of FIG. 7 or FIG. 8 is referred to as an adjustable transistor (on-resistance variable transistor). In the example of FIGS. 7 and 8, the transistor M3 is an adjustable transistor. However, the transistor M1 or M2 has the same circuit configuration as the transistor M3 of FIG. It may be formed as an adjustable transistor. When the transistor M1 is formed as an adjustable transistor, the transistor M1 may be formed by connecting a plurality of element transistors in parallel like the transistor M3 in FIG. 7 or FIG. The transistor is formed by the on resistance of one or more element transistors that are turned on. The gate voltage supply circuit 51 can control the on-resistance of the transistor M1 by controlling on / off of each element transistor. The same applies when the transistor M2 is an adjustable transistor. Of the transistors M1, M2, and M3, any two or more transistors may be adjustable transistors.

<< Deformation, etc. >>
The embodiment of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiment is merely an example of the embodiment of the present invention, and the meaning of the term of the present invention or each constituent element is not limited to that described in the above embodiment. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

  A current monitoring circuit is included in the IC 10 described above. The IC 10 is a semiconductor device including an integrated circuit in which a current monitoring circuit is integrated. In the above-described embodiment, the current monitoring circuit includes the OCP circuit 14 as a component. The gate voltage supply circuit 51 may also be included in the current monitoring circuit. A part or all of the control circuit 11 may be included in the current monitoring circuit. A part or all of the constant current generation circuit 42 may be included in the current monitoring circuit.

  The current monitoring circuit includes first and second mirror transistors (Q1, Q2) that form a current mirror, and constant current supply circuits (M10 to M12) that supply a constant current to one end of each of the first and second mirror transistors. ), A target transistor (M0) through which a monitoring target current (I2) flows, and a first and second sense transistors (M1, M2) connected in parallel to the target transistor and through which a sense current (I1) corresponding to the monitoring target current flows. M2) series circuit, a third sense transistor (M3) connected in series to the first mirror transistor, and a monitoring output circuit (Socp) for outputting a monitoring result signal (Socp) corresponding to the current flowing through the second mirror transistor 50), and the second and third sense transistors are connected in series between the other ends of the first and second mirror transistors. Data is provided.

  In the above-described embodiment, the transistor M0 as the low-side switch in the driver 13 is the target transistor, but the target transistor may be a high-side switch in the driver 13. In addition, any transistor may be the target transistor.

  Each transistor forming the IC 10 or the current monitoring circuit may be any type of transistor. Therefore, the MOSFET in each circuit described above may be replaced with a junction FET or a bipolar transistor, or the bipolar transistor in each circuit described above may be replaced with a junction FET or MOSFET. In addition, each circuit described above may be modified such that a transistor formed as an N-channel FET is formed as a P-channel FET, and vice versa. Similarly, each circuit described above may be modified so that a transistor formed as an NPN bipolar transistor is formed as a PNP bipolar transistor.

  The above-described IC 10 or the motor drive system 1 including the IC 10 can be mounted on any electric device. The current I2 may be a current that flows through any electrical component in the electrical device. The motor 20 may be any type of motor, for example, a stepping motor, a motor with a brush, or a brushless motor (including a three-phase brushless motor). The electric device equipped with the motor drive system 1 is an arbitrary device that uses the motor 20, and includes, for example, a printing device (printer or copier) as shown in FIG. 9, a scanner, a hard disk device, and a hard disk device. Personal computers, air conditioners, and surveillance cameras. In the printing apparatus, the motor 20 is used when the paper is moved (that is, when paper is fed). In the surveillance camera, the motor 20 is used as power for swinging the camera.

  The monitoring target current may be other than the drive current of the motor 20. Therefore, it is not always necessary to mount the motor 20 on the electric device, and a switching regulator, an LED device, or the like using the target transistor may be formed. That is, for example, the target transistor may be a switching transistor that forms a switching regulator or an output transistor that supplies current to an LED (Light Emitting Diode). In this case, the current that flows in the switching transistor or the output transistor is the monitoring target current. Become.

1 Motor drive system
10 Motor driver IC
11 Control circuit 12 Pre-driver 13 Driver 14, 14A, 14Z Overcurrent protection circuit (OCP circuit)
20 motor 42 constant current generation circuit 50 monitoring output circuit M0 to M3 transistor (N-channel type MOSFET)
M10 to M12 transistor (P-channel type MOSFET)
Q1-Q4 transistors (NPN type bipolar transistors)

Claims (10)

First and second mirror transistors forming a current mirror;
A constant current supply circuit for supplying a constant current as a current flowing through the resistance element based on a reference voltage to one end of each of the first and second mirror transistors;
A target transistor through which a monitoring target current flows; and
A series circuit of first and second sense transistors connected in parallel to the target transistor and through which a sense current corresponding to the monitored current flows;
A third sense transistor connected in series to the first mirror transistor;
A monitoring output circuit that outputs a monitoring result signal according to the magnitude relationship between the monitoring target current and the threshold current based on the current flowing through the second mirror transistor;
The second and third sense transistors are provided in series between the other ends of the first and second mirror transistors , the reference voltage is Vref, the resistance value of the resistance element is R, and the constant current is Iref. The source areas of the first, second and third sense transistors are 1 / N times, 1 / M times and 1 / L times the source area of the target transistor, respectively, and the threshold current is I _TH . A current monitoring circuit characterized by satisfying the following equations :

2. The current monitoring circuit according to claim 1, wherein at least one of the first to third sense transistors is an adjustable transistor formed such that its own on-resistance is variable. . The adjustable transistor is formed by connecting in parallel a plurality of element transistors composed of one or more transistors, and the adjustment is possible by the on-resistance of one or more element transistors that are turned on among the plurality of element transistors. The on-resistance of the transistor is formed,
The current monitoring circuit according to claim 2, wherein an on-resistance of the adjustable transistor is controlled by controlling on / off of each element transistor. 4. The current according to claim 1, wherein the threshold current has a value corresponding to a ratio between an on-resistance of the target transistor and an on-resistance of the first to third sense transistors. Supervisory circuit. A constant current supplied to one end of the second mirror transistor is shunted to the second mirror transistor and the monitoring output circuit according to the monitoring target current, and the monitoring output circuit is shunted to the monitoring output circuit. The current monitoring circuit according to claim 1, wherein the monitoring result signal is output in accordance with a current. 6. A control circuit for determining whether or not the current to be monitored is in an overcurrent state based on the monitoring result signal and further performing a predetermined protection operation based on the determination result. The current monitoring circuit according to any one of the above. A semiconductor device comprising an integrated circuit in which the current monitoring circuit according to claim 1 is integrated. The resistance element is external to the integrated circuit ,
The semiconductor device according to claim 7, further comprising a pad for externally attaching the resistance element . 9. The semiconductor device according to claim 7 , wherein the reference voltage source for supplying the reference voltage is formed by using a semiconductor bandgap voltage. An electrical apparatus comprising the semiconductor device according to claim 7.

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