JP6270398B2 - Imaging device - Google Patents

Description

The present invention relates to an imaging equipment.

  2. Description of the Related Art Imaging devices that capture an image using an image sensor and store the captured image as digital data, such as a digital still camera and a digital video camera, are widely used. An image pickup element used in such an image pickup apparatus is generally a CCD (Charge Coupled Device) type image sensor (hereinafter referred to as a CCD sensor). In recent years, CMOS (Complementary Metal Oxide Semiconductor) type image sensors (hereinafter referred to as CMOS sensors) have attracted attention as the number of pixels in an image sensor increases.

  The CMOS sensor has features such that random access of pixel signals is possible, readout is faster than CCD sensors, high sensitivity, and low power consumption. As a method for realizing a high frame rate by operating a CMOS sensor at high speed, a method having a plurality of means from reading a pixel signal to outputting it to the outside has been proposed (see, for example, FIG. 5 of Patent Document 1). According to this method, for example, it is possible to simultaneously output two rows of signals using different readout means and different output means for the pixels of the first row and the pixels of the second row. A frame rate can be realized.

  With the increase in pixels and resolution of CMOS sensors, there is a strong demand for reduction in pixel size, and it becomes extremely difficult to have multiple readout means while maintaining characteristics such as saturation and sensitivity, especially in pixels. Yes. On the other hand, a method has been proposed in which a signal line for reading out pixel signals in the column direction is used in common and a plurality of output means are provided thereafter (see, for example, FIG. 1 of Patent Document 1).

  In this method, first, the signal of the pixel in the first row is read out to the first circuit portion outside the pixel region through a common signal line in the column direction. The read signal of the pixels in the first row is subjected to a predetermined process in the first circuit unit and then output as a digital signal from the first output means. Further, after reading the signal of the pixel in the first row to the first circuit portion, the signal of the pixel in the second row is read out to the second circuit portion outside the pixel region through a common signal line in the column direction. The read pixel signals in the second row are subjected to predetermined processing in the second circuit unit, and then output as digital signals from the second output means. According to this method, it is possible to output the signals of the pixels in the first row and the signals of the pixels in the second row separately from the common readout means, and to output the signals in the two rows separately. The frame rate can be realized.

  However, this method can output two rows of signals in parallel, but cannot output them simultaneously. That is, after reading the signal of the pixel in the first row to the first circuit portion, the signal of the pixel in the second row is read out to the second circuit portion. Therefore, the signal of the pixel in the first row is the first pixel signal between the signal of the pixel in the first row output from the first output means and the signal of the pixel in the second row output from the second output means. This causes a delay corresponding to the time for reading out to the circuit section.

  When a signal processing circuit such as a DSP (Digital Signal Processor) receives a signal output from the image sensor, if there are two rows simultaneously, the signal of the first pixel in the first row and the signal of the first pixel in the second row In many cases, synchronization is easier to process. As a method of eliminating this delay, a method of eliminating a time difference between signals by providing a FIFO (First In First Out) memory in the subsequent stage of a plurality of output means (for example, FIG. 12 of Patent Document 2) can be considered. Another possible method is to eliminate the time difference between signals by providing a delay line in the subsequent stage of the output means that outputs first. However, these methods require a special circuit for eliminating the delay.

JP 2005-347932 A JP 2001-45378 A

  In the CMOS sensor, in order to achieve both the reduction in the pixel size and the high-speed readout operation, a method of outputting the signals of the two rows in parallel using the output means different from the common readout means is used. In some cases, there is a problem that a time difference occurs between signals in two rows. Further, in order to eliminate this time difference, when a FIFO memory or a delay line is provided at the subsequent stage of the plurality of output means, there is a problem that a circuit for that purpose is required. An object of the present invention is to provide an imaging apparatus and a control method therefor that enable high-speed reading operation of an imaging element without providing a special circuit.

An imaging apparatus according to the present invention includes a plurality of pixels arranged in a matrix each having photoelectric conversion means, a column signal line for outputting a signal from the plurality of pixels for each column, and the plurality of pixels in one row. by a run査means you select, a plurality of column signal processing means for processing signals read from pixels connected to the column signal lines, respectively, provided corresponding to said plurality of column signal processing means, said column A plurality of output means for adding and outputting a synchronization signal to the signal processed by the signal processing means , and before the output from the output means of the signal of the pixel read out before is completed The readout of the pixel signal of the next row to the column signal processing means different from the column signal processing means corresponding to the output means is started, and the signal from the column signal processing means is sent following the synchronization signal. Output means And a control means for controlling said image sensor to output, the synchronization signal, and characterized in that it comprises a signal for recognizing whether output from one of the output means of said plurality of output means To do.

  According to the present invention, the pixel signal is output following the synchronization signal from the output means, so that when the image signal of the pixels in a plurality of rows is output in parallel in the image sensor, the row is not provided even if a special circuit is not provided. Synchronous control of a plurality of output signals output at different timings is possible. As a result, a high-speed readout operation in the imaging apparatus can be realized without providing a special circuit.

It is a figure which shows the structural example of the imaging device which concerns on embodiment of this invention. It is a figure showing an example of composition of an image sensor concerning a 1st embodiment. It is a figure which shows the structural example of the output part which concerns on 1st Embodiment. 3 is a timing chart illustrating an operation example of the image sensor according to the first embodiment. It is a figure which shows the structural example of the input part of the signal processing part which concerns on 1st Embodiment. 10 is a timing chart illustrating an operation example of the image sensor according to the second embodiment. 10 is a timing chart illustrating an operation example of an image sensor according to a third embodiment. It is a figure which shows the structural example of the image pick-up element which concerns on 4th Embodiment. It is a figure which shows the structural example of the output part which concerns on 4th Embodiment. 10 is a timing chart illustrating an operation example of an image sensor according to a fourth embodiment. It is a figure which shows the structural example of the input part of the signal processing part which concerns on 4th Embodiment. 10 is a timing chart illustrating an operation example of an image sensor according to a fifth embodiment. 16 is a timing chart illustrating an operation example of an image sensor according to a sixth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment described below is an example as means for realizing the present invention, and should be appropriately modified or changed according to the configuration and various conditions of the apparatus to which the present invention is applied. It is not limited to the embodiment.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to the present embodiment. The imaging device of this embodiment can be applied to a digital still camera, a digital video camera, and the like. As shown in FIG. 1, the imaging apparatus according to the present embodiment includes an optical system 11, an imaging element 12, a signal processing unit 13, a compression / decompression unit 14, a synchronization control unit 15, an operation unit 16, an image display unit 17, and an image recording. Part 18.

  The optical system 11 includes a lens for condensing light from a subject on the image sensor 12, a drive mechanism for moving the lens to perform zooming and focusing, a mechanical shutter mechanism, an aperture mechanism, and the like. Among these, the movable part is driven based on a control signal from the synchronization control part 15.

  The image sensor 12 includes a CMOS image sensor (CMOS sensor), a CDS (Correlated Double Sampling) circuit, an AGC (Auto Gain Control) circuit, an AD (Analog Digital) converter, and the like. The image sensor 12 is controlled by a control signal from the synchronization control unit 15. Here, the CMOS sensor reads an image signal by an XY address method. Further, the CMOS sensor performs an imaging operation by controlling operation timings such as exposure, signal readout, and reset in accordance with a control signal from the synchronization control unit 15. A digitized image signal is output through noise removal by the CDS circuit, gain control by the AGC circuit, and analog-digital conversion by the AD converter.

  The signal processing unit 13 performs white balance adjustment processing, color correction processing, AF (Auto Focus) processing, AE on the digitized image signal input from the image sensor 12 under the control of the synchronization control unit 15. Perform signal processing such as (Auto Exposure) processing. The compression / decompression unit 14 operates under the control of the synchronization control unit 15, and performs compression encoding processing on the image signal from the signal processing unit 13 in a predetermined still image data format. The predetermined still image data format is, for example, a JPEG (Joint Photographic Coding Experts Group) system. The compression / decompression unit 14 performs decompression / decoding processing on the encoded data of the still image supplied from the synchronization control unit 15. Further, the moving picture compression coding process and the expansion decoding process may be executed by a moving picture experts group (MPEG) method or the like.

  The synchronization control unit 15 is a microcontroller including, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The synchronization control unit 15 performs overall control of each unit of the imaging apparatus by the CPU executing a program stored in the ROM or the like. The operation unit 16 includes various operation keys such as a shutter release button, a lever, a dial, and the like, and outputs a control signal corresponding to an input operation by the user to the synchronization control unit 15.

  The image display unit 17 includes a display device such as an LCD (Liquid Crystal Display) and an interface circuit for the display device. The image display unit 17 generates an image signal to be displayed on the display device from the image signal supplied from the synchronization control unit 15, and supplies the signal to the display device to display an image. The image recording unit 18 is realized as, for example, a portable semiconductor memory, an optical disc, an HDD (Hard Disk Drive), a magnetic tape, or the like, and receives an image data file encoded by the compression / decompression unit 14 from the synchronization control unit 15. Remember. Further, the image recording unit 18 reads out the data designated by the control signal from the synchronization control unit 15 and outputs the data to the synchronization control unit 15.

Here, a basic operation in the imaging apparatus of the present embodiment will be described.
Prior to capturing a still image, image signals output from the image sensor 12 are sequentially supplied to the signal processing unit 13. The signal processing unit 13 performs image quality correction processing on the digital image signal from the image sensor 12 and supplies the image display unit 17 through the synchronization control unit 15 as a camera-through image signal. As a result, the camera-through image is displayed, and the user can adjust the angle of view while viewing the display image.

  In this state, when the shutter release button of the operation unit 16 is pressed, an image signal for one frame from the image sensor 12 is taken into the signal processing unit 13 under the control of the synchronization control unit 15. The signal processing unit 13 performs image quality correction processing on the captured image signal for one frame, and supplies the processed image signal to the compression / decompression unit 14. The compression / decompression unit 14 compresses and encodes the input image signal, and supplies the generated encoded data to the image recording unit 18 through the synchronization control unit 15. As a result, the data file of the captured still image is recorded in the image recording unit 18.

  When reproducing the still image data file recorded in the image recording unit 18, the synchronization control unit 15 reads the selected data file from the image recording unit 18 in response to an operation input from the operation unit 16. The data is supplied to the compression / decompression unit 14 to execute decompression decoding processing. The decoded image signal is supplied to the image display unit 17 via the synchronization control unit 15, whereby a still image is reproduced and displayed.

  When recording a moving image, the image signal sequentially processed by the signal processing unit 13 is subjected to compression encoding processing by the compression / decompression unit 14, and the encoded data of the generated moving image is sequentially converted into the image recording unit 18. Transfer to and record. The moving image data file is read from the image recording unit 18 and supplied to the compression / decompression unit 14, decompressed and decoded, and supplied to the image display unit 17, thereby displaying the moving image.

  FIG. 2 is a diagram showing a schematic configuration of the image sensor (CMOS sensor) 12 according to the present embodiment. The image sensor 12 includes a pixel region 101 in which a plurality of pixels 100 are arranged, a vertical scanning unit 102, a first signal selection unit 105a and a second signal selection unit 105b, a first column signal processing unit 106a, and a second column signal processing unit. 106b, a first column AD unit 107a and a second column AD unit 107b. The image sensor 12 includes a first horizontal memory unit 108a and a second horizontal memory unit 108b, a first horizontal scanning unit 109a and a second horizontal scanning unit 109b, a first output unit 110a and a second output unit 110b, and a signal generation unit. (TG: Timing Generator) 112.

  In the pixel region 101, as indicated by P11 to P44 in FIG. 2, a plurality of pixels 100 are arranged in a matrix (matrix) in the row direction (horizontal direction) and the column direction (vertical direction). Each pixel 100 includes a photoelectric conversion unit (not shown) and a transistor. In the present embodiment, a pixel area 101 having a 4 × 4 array (4 columns and 4 rows) will be described as an example. However, the pixel array in the image area 101 is not limited to this number.

  The vertical scanning unit 102 selects pixels arranged in the pixel region 101 one row at a time, and drives and controls the reset operation and readout operation of the selected pixel row. The pixel control line 103 is arranged for each pixel row and is commonly connected to pixels in the same row, and transmits a drive control signal in units of rows by the vertical scanning unit 102.

  The vertical signal lines 104 are arranged for each pixel column and commonly connected to pixels in the same column, and signals of pixels in a row selected by the pixel control line 103 are read out to the corresponding vertical signal lines 104, respectively. The vertical signal line 104 can be connected to the first column signal processing unit 106a through the first signal selection unit 105a and can be connected to the second column signal processing unit 106b through the second signal selection unit 105b. . That is, the signal selection units 105a and 105b function as switches that selectively connect the vertical signal line 104 to either the first column signal processing unit 106a or the second column signal processing unit 106b.

  The column signal processing units 106 a and 106 b have a CDS circuit and an AGC circuit (not shown) provided for each vertical signal line 104. The column signal processing units 106a and 106b remove fixed pattern noise by CDS processing on the signal of each column of pixels sent through the vertical signal line 104 and perform S / N (Signal / Noise). Sample and hold to keep the ratio good. Fixed pattern noise is noise resulting from variations in threshold values of transistors in the pixel circuit. Further, the column signal processing units 106a and 106b perform gain control by an AGC circuit if necessary.

  The column AD units 107 a and 107 b have AD converters provided for each vertical signal line 104. The column AD units 107a and 107b perform analog-to-digital conversion on each pixel signal of each column sent from the corresponding column signal processing units 106a and 106b. Here, the column AD units 107a and 107b of the present embodiment all have AD converters with an 8-bit precision, but the bit precision is even higher, such as 10 bits, 12 bits, and 14 bits. An accurate AD converter may be used.

  The horizontal memory units 108a and 108b store the pixel signals of the respective columns in units of rows digitized by the corresponding column AD units 107a and 107b, respectively. Here, the horizontal memory units 108a and 108b of this embodiment can store 8-bit digital signals for each column in accordance with the corresponding column AD units 107a and 107b. It is only necessary to store a digital signal having a corresponding number of bits.

  The horizontal scanning units 109a and 109b select and transfer the digitized pixel signals stored in the corresponding horizontal memory units 108a and 108b to the corresponding output units 110a and 110b, respectively, for each column. The horizontal memory units 108a and 108b are controlled.

  The output units 110a and 110b add a synchronization signal before or after the digitized row-unit pixel signal. The output units 110a and 110b output digital pixel signals with synchronization signals to the signal processing unit 13 from the corresponding output terminals 111a and 111b, respectively. The signal generation unit (TG) 112 outputs various clock signals and control signals necessary for the operation of each unit of the image sensor 12 based on the control signal from the synchronization control unit 15 via the control terminal 113.

  The output units 110a and 110b according to the present embodiment will be described. Hereinafter, the first output unit 110a will be described, but the same applies to the second output unit 110b. FIG. 3 is a diagram illustrating a configuration of the output unit 110a according to the present embodiment. The first output unit 110a includes a first signal conversion unit 201a, a first synchronization signal addition unit 202a, and a first differential transmission buffer 203a.

  The first signal conversion unit 201a receives pixel signals D0a, D1a, D2a, D3a, D4a, D5a, and D6a transmitted from the first horizontal memory unit 108a via eight horizontal signal lines corresponding to 8 bits. And D7a are input. In addition, the pixel clock signal Skka transmitted from the TG 112 as a clock signal is input to the first signal conversion unit 201a. The pixel clock signal Skca is a signal having the same cycle as the transfer of the first horizontal scanning unit 109a. The first signal conversion unit 201a adjusts the phases of the 8-bit pixel signals D0a to D7a so as to be synchronized with the phase of the pixel clock signal Skca.

  The first signal conversion unit 201a may further perform, for example, black level adjustment, column variation correction, signal amplification, color relation processing, and the like. The black level adjustment is performed so that the signal levels of all the pixel signals are the same so that the signal levels of light-shielded pixels (not shown) arranged in the periphery of the pixel region 101 become the levels set in advance by the synchronization control unit 15. It is a function to shift. In the column variation correction, variation correction data in the column direction is created from signals of light-shielded pixels (not shown) arranged above or below the pixel region 101, and the pixels generated in the column signal processing unit 106 and the column AD unit 107 are generated. This is a function for correcting variations in the column direction of signals. The signal amplification is a function that applies a gain to the pixel signal so that an appropriate signal level is obtained in image processing. For example, it is possible to perform control such that the signal processing unit 13 calculates an appropriate gain amount from an image captured in advance, and the synchronization control unit 15 sets the gain. The color related process is, for example, a white balance (WB) process. For each pixel 100 in the pixel region 101, an RGB color filter (not shown) is provided according to an array such as a Bayer array. For example, it is possible to perform control such that the signal processing unit 13 calculates a gain amount for each color on which appropriate WB processing is performed from an image captured in advance, and the synchronization control unit 15 sets the gain for each color.

  The first synchronization signal adding unit 202a adds a start synchronization signal and, if necessary, an end synchronization signal to each of the pixel signals D0a to D7a in a state synchronized with the phase of the pixel clock signal Skca. Here, the timing of adding the synchronization signal is controlled by the control signal output from the TG 112 based on the control signal from the synchronization control unit 15.

  The first differential transmission buffer 203a is provided for each of the pixel signals D0a to D7a and the pixel clock signal Skca to which a synchronization signal is added, and a normal rotation signal having the same polarity as each pulse signal and an inverted signal having a reverse polarity. Are output simultaneously. In the present embodiment, the normal pixel signal is D0Pa to D7Pa, the inverted pixel signal is D0Na to D7Na, the normal pixel clock signal is SckPa, and the inverted pixel clock signal is SckNa.

  Here, the pixel clock signal input to the output units 110a and 110b is assumed to be sent from the TG 112, but a delay corresponding to the distance from the TG 112 to each of the output units 110a and 110b occurs. . For this reason, the pixel clock signals Skca and Sckb input to the output units 110a and 110b, respectively, are distinguished from each other.

  In addition, the first differential transmission buffer 203a of the first output unit 110a illustrated in FIG. 3 can use LVDS (Low Voltage Differential Signaling) that performs differential operation in a current mode. This is advantageous for noise resistance and unwanted radiation problems.

  That is, in the single-phase (single) output of only the pulse signal corresponding to the normal rotation signal, components such as blunting and ringing are more likely to occur in the pulse waveform as the speed increases, and the influence is directly affected. On the other hand, in the LVDS that performs the differential operation, it is possible to reproduce the waveform by using both differential outputs, so that the noise resistance is improved. In this respect, the same effect can be obtained not only for pixel signals but also for pixel clock signals.

  Furthermore, in the single-phase output of only the pulse signal corresponding to the normal rotation signal, current flows back and forth between the output circuit on the transmission side and the input circuit on the reception side in response to the change of the pulse, so it is unnecessary each time. An electromagnetic field that causes radiation is generated, which affects the peripheral circuits and the outside of the solid-state imaging device. On the other hand, in LVDS that performs differential operation in the current mode, although current flows back and forth between the transmission side output circuit and the reception side input circuit, the switching timing of the normal signal and the inverted signal is always the same. Yes, the directions of the generated electromagnetic fields are opposite to each other. Therefore, the electromagnetic fields generated by both parties cancel each other, and the generation of electromagnetic fields that cause unnecessary radiation is greatly reduced. In order to further enhance this effect, the two output lines of the normal signal and the inverted signal in the differential signal are arranged close to each other, and the connection distance between the differential transmission buffer and the differential reception buffer is the same as much as possible. It is necessary to design the circuit so that

  Next, the operation in the first embodiment will be described with reference to FIG. FIG. 4 is a timing chart illustrating an operation example of the image sensor 12 according to the first embodiment. In FIG. 4, Opr1 indicates a first read operation when the first signal selection unit 105a is selected, and Opr2 indicates a second read operation when the second signal selection unit 105b is selected. Among the pixels arranged in the pixel region 101, signals of pixels in odd-numbered rows are read using the first readout operation Opr1, and signals of pixels in even-numbered rows are read out using the second readout operation Opr2. To.

  In the first read operation Opr1, first, in the period Read1r, the first signal selection unit 105a is selected, and the vertical row corresponding to the signals of the pixels in the first row by the drive control signal from the vertical scanning unit 102 respectively. Read out to the signal line 104 (time t00 to t01). At this time, the N signal in the state in which the pixels are first reset is sampled and held by the first column signal processing unit 106a, and the S signal in the state in which the signal of the photoelectric conversion unit is subsequently read out is the first column signal processing unit 106a. Is sampled and held.

  Next, in the period CDS1r, the first column signal processing unit 106a performs noise removal by CDS processing by subtracting the N signal from the S signal in the CDS circuit, and performs gain control by the AGC circuit if necessary. (After time t01). Then, in the period AD1r, the first column AD unit 107a performs analog-to-digital conversion on the pixel signal of the first row from which noise has been removed, and stores the signal in the first horizontal memory unit 108a (until time t03). The processing at time t00 to t03 so far is parallel processing for each column with respect to the signal of each pixel in the first row.

  Subsequently, in the period SD1r, the first synchronization signal adding unit 202a in the first output unit 110a is synchronized with the phase of the pixel clock signal Skka, and the start synchronization signal is transmitted before the 8-bit pixel signal is sent. It is added (after time t03). At this time, the start synchronization signal needs to be set to a combination of values that cannot be taken by the 8-bit pixel signal. When the black level after black level adjustment is set to a value higher than 0, for example, “11110000” is added as a start synchronization signal to each 8-bit signal constituting the pixel signal. realizable.

  Specifically, 8 clocks of the pixel clock signal Skca are assigned as the period SD1r. During the period SD1r, D0Pa to D7Pa, which are 8-bit normal pixel signals, output D0Pa = 11110000 to D7Pa = 11110000. Similarly, during the period SD1r, D0Na to D7Na, which are 8-bit inverted pixel signals, output D0Na = 00001111 to D7Na = 00001111. At this time, the start synchronization signal is not added to the normal pixel clock signal SckPa and the inverted pixel clock signal SckNa.

  Next, in the period SigOut1r, the first horizontal scanning unit 109a selects the first horizontal memory unit 108a for each column, and digitized 8-bit pixel signals D0a to D7a stored in the first horizontal memory unit 108a. Is transferred to the first output unit 110a. Then, the first signal conversion unit 201a adjusts the phases of the 8-bit pixel signals D0a to D7a so as to be synchronized with the phase of the pixel clock signal Skca sent from the TG 112. Thereafter, the first differential transmission buffer 203a converts the signal into a normal signal and an inverted signal corresponding to each 8-bit signal, and outputs the signal from the first output terminal 111a.

  Further, in the period ED1r, after the 8-bit pixel signal is sent out in a state where the first synchronization signal adding unit 202a in the first output unit 110a is synchronized with the phase of the pixel clock signal Skca, the end synchronization signal is output. Add (until time t05). At this time, the end synchronization signal needs to be set to a combination of values that cannot be taken by the 8-bit pixel signal. Further, in order to distinguish from the start synchronization signal, it can be realized by adding “11001100” as an end synchronization signal, for example, to each 8-bit signal constituting the pixel signal.

  Specifically, 8 clocks of the pixel clock signal Skca are assigned as the period ED1r. Then, during the period ED1r, D0Pa to D7Pa, which are 8-bit normal pixel signals, output D0Pa = 1001100 to D7Pa = 1001100. Similarly, during the period ED1r, D0Na to D7Na, which are 8-bit inverted pixel signals, output D0Na = 00110011 to D7Na = 00110011. At this time, the end synchronization signal is not added to the normal pixel clock signal SckPa and the inverted pixel clock signal SckNa. The period from time t03 to t05 so far is the signal output period of each pixel in the first row to which the start synchronization signal and end synchronization signal are added.

  In the first read operation Opr1, after the pixel signal of the first row is output, the signal of the pixel of the third row is output continuously. A period from time t05 to t07 is a period in which parallel processing for each column such as readout for each column, CDS processing, analog-digital conversion, and storage in the horizontal memory unit is performed for the signal of each pixel in the third row. A period from time t07 to t09 is an output period of the signal of each pixel in the third row to which the start synchronization signal and the end synchronization signal are added. Furthermore, in the first embodiment, since the pixels 100 arranged in the pixel region 101 have four rows, the signal readout operation for the pixels in the first row is started again after time t09.

  Next, in the second readout operation Opr2, since the vertical signal line 104 is wired in common with the vertical pixel column, the operation is started after the end of the period Read1r for reading the signal of the pixel in the first row (after time t01) ). First, in the period Read2r, the signals of the pixels in the second row are read out to the corresponding vertical signal lines 104 by the drive control signal from the vertical scanning unit 102 in a state where the second signal selection unit 105b is selected. That is, the N signal and S signal of the signals of the pixels in the second row are read out to the second column signal processing unit 106b via the corresponding vertical signal lines 104 (time t01 to t02).

  Next, in the period CDS2r, the second column signal processing unit 106b performs noise removal by CDS processing in the CDS circuit, and performs gain control by the AGC circuit if necessary (after time t02). Then, in the period AD2r, the second column AD unit 107b performs analog-digital conversion on the signals of the pixels in the second row and stores them in the second horizontal memory unit 108b (until time t04). The processing at times t01 to t04 so far is parallel processing for each column with respect to the signal of each pixel in the second row.

  Subsequently, in a period SD2r, start synchronization is performed before an 8-bit pixel signal is sent in a state where a second synchronization signal adding unit (not shown) in the second output unit 110b is synchronized with the phase of the pixel clock signal Skkb. A signal is added (after time t04). At this time, it is necessary to set the start synchronization signal to a combination of values that cannot be taken by the 8-bit pixel signal. For example, for each 8-bit signal constituting the pixel signal, “ This can be realized by adding 11110000 ″. Since the specific start synchronization signal for each 8-bit signal is the same as the start synchronization signal in the first read operation Opr1, description thereof is omitted.

  Here, in the second readout operation Opr2, since the readout operation of the pixel signal of the second row is started after the end of the period Read1r, the period SD2r to which the start synchronization signal is added also starts with a time delay corresponding to the period Read1r. There is a need to.

  Next, in the period SigOut2r, the second horizontal scanning unit 109b selects the second horizontal memory unit 108b for each column, and digitized 8-bit pixel signals D0b to D7b stored in the second horizontal memory unit 108b. Is transferred to the second output unit 110b. Then, a second signal conversion unit (not shown) of the second output unit 110b adjusts the phases of the 8-bit pixel signals D0b to D7b so as to be synchronized with the phase of the pixel clock signal Skkb sent from the TG 112. Thereafter, a second differential transmission buffer (not shown) of the second output unit 110b converts the signal into a normal signal and an inverted signal corresponding to each 8-bit signal, and outputs the converted signal from the second output terminal 111b.

  Further, subsequently, in the period ED2r, the end synchronization signal is added after the 8-bit pixel signal is sent out while the second synchronization signal addition unit in the second output unit 110b is synchronized with the phase of the pixel clock signal Skkb. (Until time t06). At this time, the end synchronization signal needs to be set to a combination of values that cannot be taken by the 8-bit pixel signal. Further, in order to distinguish from the start synchronization signal, it can be realized by adding “11001100” as an end synchronization signal, for example, to each 8-bit signal constituting the pixel signal. Since the end synchronization signal for each specific 8-bit signal is the same as the end synchronization signal in the first read operation Opr1, description thereof will be omitted. The period from time t04 to t06 so far is the signal output period of each pixel in the second row to which the start synchronization signal and end synchronization signal are added.

  In the second read operation Opr2, after the pixel signal of the second row is output, the signal of the pixel of the fourth row is output continuously. A period from time t06 to t08 is a period for executing parallel processing for each column such as readout for each column, CDS processing, analog-digital conversion, and storage in the horizontal memory unit for the signals of the pixels in the fourth row. A period from time t08 to t10 is an output period of the signal of each pixel in the fourth row to which the start synchronization signal and the end synchronization signal are added. Furthermore, in the first embodiment, since the pixels 100 arranged in the pixel region 101 have four rows, the signal readout operation for the pixels in the second row is started again after time t10.

  Thus, in the first embodiment, it is necessary to operate the first read operation Opr1 and the second read operation Opr2 while being shifted by the period Read1r. For this reason, the TG 112 controls the parallel processing operation for each column from the readout of the pixel signal of the first row performed during the period Read1r, the period CDS1r, and the period AD1r to the storage in the first horizontal memory unit 108a. Is possible. In addition, the TG 112 shifts by the period Read1r, and performs column-by-column parallel processing from reading the pixel signal of the second row performed during the period Read2r, the period CDS2r, and the period AD2r to storage in the second horizontal memory unit 108b. It is possible to control the processing operation.

  Here, the difference between the start times of the first read operation Opr1 and the second read operation Opr2 is that the signal of the pixel in the first row is read because the vertical signal line 104 is wired in common to the vertical pixel column. This is because reading of the signals of the pixels in the second row cannot be started until the processing is completed. Therefore, the start time of the second read operation Opr2 may be after a predetermined time has elapsed after the end of the period Read1r.

  Furthermore, the TG 112 controls the output operation of the pixel signal of the first row and the signal of the pixel of the second row to which the start synchronization signal and the end synchronization signal are added separately from the parallel processing operation for each column described above. Is possible. Here, the start timing of the output operation of the start synchronization signal added to the signal of the pixel in the first row may be after a predetermined time has elapsed after the parallel processing operation of the signal of the pixel in the first row. The start timing of the output operation of the start synchronization signal added to the pixel signal of the second row may also be after a predetermined time has elapsed after the parallel processing operation of the signal of the second row pixel. Further, the difference between the output start timings of the start synchronization signal added to the pixel signal of the first row and the start synchronization signal added to the signal of the pixel of the second row may be longer than the period Read1r.

  The start timing of the period Read1r, the start timing of the period Read2r, the start timing of the period SD1r, and the start timing of the period SD2r can be individually and appropriately set based on the control signal from the synchronization control unit 15.

  The above description describes the relationship between the first read operation Opr1 and the second read operation Opr2. When the readout operation is repeated, the same applies to the relationship between the second readout operation Opr2 that reads out the signals of the pixels in the second row and the first readout operation Opr1 that reads out the signals of the pixels in the third row.

  In this embodiment, the start synchronization signal and the end synchronization signal are set to “11110000” and “11001100”, respectively, but the present invention is not limited to this. Since the start synchronization signal and the end synchronization signal can be distinguished from each other, and any combination of values that cannot be taken by the 8-bit pixel signal is acceptable, for example, the start synchronization signal is “11001100” and the end synchronization signal is “11110000”. It may be reversed. In addition, for example, the length may be increased such that the start synchronization signal is “1111111100000000” and the end synchronization signal is “1111000011110000”.

  Further, the start synchronization signal of the first row is “11001100”, the start synchronization signal of the second row is “111000011”, the start synchronization signal of the third row is “11000000”, and the start synchronization signal of the fourth row is “11000011”. Suppose that it is set. In this case, it can be shown that the first row of the pixel signal is set by setting only the start synchronization signal of the first row to 1 for both the fifth clock and the sixth clock. Further, when both the seventh clock and the eighth clock are set to 0, it can be indicated that the signal is an odd row pixel signal output from the first output unit 110a. Further, when both the seventh clock and the eighth clock are set to 1, it can be indicated that the signals are pixels of even rows output from the second output unit 110b. At this time, if all end synchronization signals are set to “11001111”, they can be distinguished from any start synchronization signal.

  Alternatively, the start synchronization signal of the first row is “11000001”, the start synchronization signal of the second row is “11000010”, the start synchronization signal of the third row is “11000011”, and the start synchronization signal of the fourth row is “11000100”. Suppose that it is set. In this way, the 6th clock to the 8th clock may represent binary numbers of row numbers. At this time, if all end synchronization signals are set to “11000000”, they can be distinguished from any start synchronization signal.

When the number of rows in the pixel area increases, the number of start synchronization signals may be set to a necessary number in advance.
Here, since the number of pixels of the output signal of the image sensor 12 is determined in advance, if the synchronization control unit 15 can control the signal processing unit 13 to perform processing corresponding to pixels for one row. The end synchronization signal can be omitted.

  FIG. 5 is a diagram illustrating a configuration of an input portion of the signal processing unit 13 according to the present embodiment, and timing is performed in units of rows output from the image sensor 12 so that signal processing in the signal processing unit 13 is possible. It is possible to receive digital pixel signals that are shifted from each other. The signal processing unit 13 includes a first input unit 401 a, a second input unit 401 b, a synchronization signal decoding unit 403, and an internal memory 404.

  Pixel signals from the first output unit 110a and the second output unit 110b are input to the first input unit 401a and the second input unit 401b via the first input terminal 402a and the second input terminal 402b, respectively. . Since the signal input to the signal processing unit 13 is a differential signal composed of a normal pixel signal and an inverted pixel signal as described with reference to FIG. 3, the signal is received by a differential reception buffer (not shown). To convert it into a normal pulse signal. At this time, the phase of the pixel clock signal input at the same time and the phase of the signal processing clock signal of the signal processing unit 13 are compared, and the process of synchronizing the phase of the digital pixel signal with the phase of the signal processing clock signal of the signal processing unit 13 is also performed. .

  The synchronization signal decoding unit 403 decodes the synchronization signal of the row-unit pixel signal with the synchronization signal, and stores the row-unit pixel signal sandwiched between the start synchronization signal and the end synchronization signal in the internal memory 404. The internal memory 404 stores pixel signals in units of rows. The areas for storing the pixel signals from the first row to the eighth row are indicated as mP1r to mP8r for convenience.

When the pixel signal of the first row is input from the first input unit 401a to the synchronization signal decoding unit 403, the row unit sandwiched between the start synchronization signal and the end synchronization signal based on the control signal from the synchronization control unit 15 Are stored in the area mP1r of the internal memory 404. Next, when the pixel signal in the second row is input from the second input unit 401 b to the synchronization signal decoding unit 403, it is sandwiched between the start synchronization signal and the end synchronization signal based on the control signal from the synchronization control unit 15. The row-by-row pixel signal is stored in the area mP2r of the internal memory 404.

  At this time, for the internal memory 404, the signal operation for the pixels in the first row and the signal operation for the pixels in the second row are performed simultaneously. Can be controlled. After the operation of storing the signals of the pixels in the first and second rows, the operation of storing the signals of the pixels in the third and fourth rows is performed in the same manner.

  Then, the signals of the pixels in the first to fourth rows stored in the areas mP1r to mP4r of the internal memory 404 are processed for each row from the internal memory terminal 405 based on the control signal from the synchronization control unit 15. It will be done. After that, when the signal of the pixel in the first row is continuously input, it may be stored in the area mP1r from the beginning. Alternatively, in odd-numbered imaging, the signals of the pixels in the first to fourth rows are stored in the areas mP1r to mP4r, respectively, and in even-numbered imaging, the signals of the pixels in the first to fourth rows are respectively stored. You may make it memorize | store in area | region mP5r-mP8r. In such a case, it is possible to secure time required for subsequent signal processing.

  As described above, in the present embodiment, it is possible to provide a means for controlling the synchronization of output signals by individually setting the start synchronization signal for each of the signals of the plurality of output means in accordance with the read time difference. it can. Then, by assigning a memory area for storing a pixel signal corresponding to the decoded synchronization signal at the input portion of the signal processing unit, synchronization control corresponding to the readout time difference can be realized. As a result, it is not necessary to provide a FIFO memory or a delay line after the output unit of the image sensor, and signals of a plurality of pixels can be output separately using an output unit different from the common readout unit. A high-speed reading operation in the imaging apparatus can be realized.

  Furthermore, when a signal that can be recognized as a signal read out as a start synchronization signal is a pixel signal in the first row, the signal processing unit starts the signal processing operation without going through the synchronization control means. Can do. In addition, when a signal that can be recognized from which output means signal is added as a start synchronization signal, the signal processing section performs signal processing operations such as correction according to a specific row without going through the synchronization control means. Can be implemented. Further, when a signal for recognizing the order of the rows read out as the start synchronization signal is added, the synchronization signal decoding means can allocate a memory area for storing the pixel signal without going through the synchronization control means.

(Second Embodiment)
Next, the second embodiment of the present invention will be described with reference to FIG. 6 in addition to FIGS. In the second embodiment, the basic configuration and operation of the imaging apparatus and the basic configuration and operation of the imaging element are the same as those in the first embodiment. . The signal processing unit 13 according to the first embodiment is configured to be able to receive digital pixel signals that are out of timing in units of rows that are output from the image sensor 12. In general, when a signal processing circuit such as a DSP receives a signal output from an image sensor, the signal of the first pixel in the first row and the signal of the first pixel in the second row are synchronized if there are two rows simultaneously. May be easier to process. Therefore, in the second embodiment, the first pixel signal of the first row and the first pixel signal of the second row are synchronously output without providing a FIFO memory or a delay line after the output unit of the image sensor. A method for enabling this will be described.

  FIG. 6 is a timing chart illustrating an operation example of the image sensor 12 according to the second embodiment. In FIG. 6, Opr1 indicates a first read operation when the first signal selection unit 105a is selected, and Opr2 indicates a second read operation when the second signal selection unit 105b is selected.

  In the second embodiment, the start of the period SD1r of the first row in the first read operation Opr1 is not the time t23 that is the end of the period AD1r but the time t24 that is the start of the period SD2r of the second row. This is different from the first embodiment. Also, the start of the period SD3r in the third row is not the time t28 at which the period AD3r ends, but the time t29 at the start of the period SD4r in the fourth line, which is different from the first embodiment. That is, in the second embodiment, the period SD1r for the first row and the period SD2r for the second row start simultaneously, and the period SD3r for the third row and the period SD4r for the fourth row start simultaneously.

  At time t23, which is the end of the period AD1r in the first read operation Opr1, the pixel signal of the first row is stored in the first horizontal memory unit 108a as a digitized pixel signal in units of rows. Since the pixel signal stored in the first horizontal memory unit 108a is digital data, unlike the analog signal, it can be held without deterioration. Therefore, the TG 112 delays the start of the operation of the first horizontal scanning unit 109a based on the control signal from the synchronization control unit 15. Next, the period SD1r and the period SD2r are synchronized by starting the period SD1r of the first line at time t24, which is the start of the period SD2r of the second line.

  Subsequently, the period SigOut1r of the first row is started simultaneously with the start of the period SigOut2r of the second row. That is, simultaneously with the start of the period SigOut2r of the second row, the first horizontal scanning unit 109a selects the first horizontal memory unit 108a for each column, and the digitized 8-bit stored in the first horizontal memory unit 108a The pixel signals D0a to D7a are transferred to the first output unit 110a. Thereby, the signal of the first pixel in the first row and the signal of the first pixel in the second row can be synchronized. Further, the period ED1r of the first row is started in synchronization with the period ED2r of the second row.

  As described above, the synchronization control unit 15 is configured so that the entire output period of the signals of the pixels in the first row to which the start synchronization signal and the end synchronization signal are added is delayed by a time corresponding to the period Read2r (time t23 to t24). Controls the image sensor 12. Thereby, the signal of the pixel of the 1st row and the signal of the pixel of the 2nd row can be synchronized and outputted. The same operation is performed for the signals of the pixels in the third row and the signals of the pixels in the fourth row.

  As described above, in this embodiment, the output signal can be synchronized by individually setting the start synchronization signal for each of the signals of the plurality of output means. However, the output period of the pixel signal of the first row to which the start synchronization signal and the end synchronization signal are added is delayed by a time corresponding to the period Read2r. Therefore, the read time for each row in the first read operation Opr1 becomes longer by a time corresponding to the period Read2r. However, this makes it possible to separately output signals from a plurality of pixels by using output means different from the common readout means without providing a FIFO memory or a delay line after the output means of the image sensor. A high-speed reading operation in the imaging apparatus can be realized.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. 7 in addition to FIGS. In the third embodiment, the basic configuration and operation of the imaging apparatus and the basic configuration and operation of the imaging element are the same as those in the first embodiment. . In the first embodiment, a high-speed readout operation in the imaging apparatus is realized by separately outputting signals of a plurality of pixels using an output unit different from the common readout unit. In the third embodiment, a method for realizing a further high-speed reading operation by simultaneously operating a parallel processing for each column and a part of an output period of a pixel signal will be described.

  FIG. 7 is a timing chart illustrating an operation example of the image sensor 12 according to the third embodiment. In FIG. 7, Opr1 indicates a first read operation when the first signal selection unit 105a is selected, and Opr2 indicates a second read operation when the second signal selection unit 105b is selected.

  The third embodiment is different from the first embodiment in the following points. The end of the period SD1r of the first row in the first read operation Opr1 is the same as the end of the period AD1r of the first row at time t43. The start of the period ED1r in the first row is simultaneously with the start of the period Read3r in the third row at time t45. Further, the end of the period SD2r of the second row in the second read operation Opr2 is the same as the end of the period AD2r of the second row at time t44. The start of the period ED2r in the second row is simultaneously with the start of the period Read4r in the fourth row at time t46.

  At time t43, which is the end of the period AD1r in the first readout operation Opr1, the pixel signal of the first row is stored in the first horizontal memory unit 108a as a digitized pixel unit pixel signal. Therefore, the period SigOut1r of the first row can be started after time t43. Therefore, the TG 112 causes the first synchronization signal adding unit 202a to output a start synchronization signal based on the control signal from the synchronization control unit 15 so that the period AD1r ends and the period SD1r ends at the same time. Then, after the period SD1r ends, the period SigOut1r in the first row starts.

  Further, an end synchronization signal is output following time t45, which is the end of the period SigOut1r. At the same time, a period Read3r for reading out the signals of the pixels in the third row is started, and thereafter, the same operation as that of the signals of the pixels in the first row is performed.

  Next, also in the second readout operation Opr2, at time t44, which is the end of the period AD2r, the pixel signal of the second row is stored in the second horizontal memory unit 108b as a digitized pixel unit pixel signal. Has been. Therefore, the period SigOut2r in the second row can be started after time t44. Therefore, the TG 112 outputs the start synchronization signal from the second synchronization signal adding unit 202b based on the control signal from the synchronization control unit 15 so that the period AD2r and the period SD2r end at the same time. Then, after the period SD2r ends, the period SigOut2r in the second row is started.

  Further, the end synchronization signal is output following time t46, which is the end of the period SigOut2r. At the same time, a period Read4r for reading out the signals of the pixels in the fourth row is started, and thereafter, the same operation as the signals of the pixels in the second row is performed.

  As described above, in the present embodiment, it is possible to provide a means for controlling the synchronization of output signals by individually setting the start synchronization signal for each of the signals of the plurality of output means in accordance with the read time difference. it can. Then, by assigning a memory area for storing a pixel signal corresponding to the decoded synchronization signal at the input portion of the signal processing unit, synchronization control corresponding to the readout time difference can be realized. As a result, it is not necessary to provide a FIFO memory or a delay line after the output unit of the image sensor, and signals of a plurality of pixels can be output separately using an output unit different from the common readout unit. A high-speed reading operation in the imaging apparatus can be realized.

  Further, in the present embodiment, the first row period AD1r and the first row period SD1r are overlapped, and the first row period ED1r and the third row period SD3r are overlapped, so that a higher-speed read operation is performed. Can be realized. Similarly, by overlapping the period AD2r in the second row and the period SD2r in the second row, and by overlapping the period ED2r in the second row and the period SD4r in the fourth row, a higher-speed read operation can be realized. it can.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. 1 and FIGS. Note that in the fourth embodiment, the basic configuration and operation of the imaging apparatus are the same as those in the first embodiment, and therefore, description will be made with reference to the drawings and symbols. The image sensor 12 according to the first embodiment includes two sets of horizontal memory units and output units, thereby realizing a high-speed read operation by simultaneous output of two rows. In the fourth embodiment described below, four sets of horizontal memory units and output units are provided, thereby realizing further high-speed read operation.

  FIG. 8 is a diagram illustrating a schematic configuration of the image sensor 12 according to the present embodiment. The image sensor 12 includes a pixel region 101 in which a plurality of pixels 100 are arranged, a vertical scanning unit 102, a first signal selection unit 105a and a second signal selection unit 105b, a first column signal processing unit 106a, and a second column signal processing unit. 106b, a first column AD unit 107a and a second column AD unit 107b. Further, the imaging device 12 includes a first memory selection unit 114a and a second memory selection unit 114b, a first horizontal memory unit 108a, a second horizontal memory unit 108b, a third horizontal memory unit 108c, and a fourth horizontal memory unit 108d. . The image sensor 12 includes a first horizontal scanning unit 109a and a second horizontal scanning unit 109b, a first output unit 110a, a second output unit 110b, a third output unit 110c, a fourth output unit 110d, and a TG (Timing Generator). ) 112.

  In the pixel region 101, as indicated by P11 to P84 in FIG. 8, a plurality of pixels 100 are arranged in a matrix (matrix) in the row direction (horizontal direction) and the column direction (vertical direction). Each pixel 100 includes a photoelectric conversion unit (not shown) and a transistor. Here, for example, P11 to P14 indicate four pixels in the first row, and P81 to P84 indicate four pixels in the eighth row. In the present embodiment, a pixel area 101 having a 4 × 8 array (4 columns and 8 rows) will be described as an example. However, the pixel array in the image area 101 is not limited to this number.

  The vertical scanning unit 102, the pixel control line 103, the vertical signal line 104, the signal selection units 105a and 105b, the column signal processing units 106a and 106b, and the column AD units 107a and 107b are the same as those in the first embodiment shown in FIG. Since the same operation as that of the image sensor is performed, the description is omitted.

  The first memory selection unit 114a selectively connects the row-by-row pixel signals analog-digital converted in the first column AD unit 107a to either the first horizontal memory unit 108a or the third horizontal memory unit 108c. It is a switch to do. The second memory selection unit 114b selectively connects the row-by-row pixel signals analog-digital converted in the second column AD unit 107b to either the second horizontal memory unit 108b or the fourth horizontal memory unit 108d. It is a switch to do.

  The first horizontal memory unit 108a and the third horizontal memory unit 108c store pixel signals of each column in units of rows digitized by the first column AD unit 107a. The second horizontal memory unit 108b and the fourth horizontal memory unit 108d store pixel signals of each column in units of rows digitized by the second column AD unit 107b. Here, the horizontal memory units 108a, 108b, 108c, and 108d can store an 8-bit digital signal for each column in accordance with the corresponding column AD units 107a and 107b. It is only necessary to store a digital signal having a corresponding number of bits.

  The first horizontal scanning unit 109a selects and transfers the digitized pixel signals stored in the horizontal memory units 108a and 108c to the corresponding output units 110a and 110c, respectively, for each column. 108a and 108b are controlled. The second horizontal scanning unit 109b is configured to select and transfer the digitized pixel signals stored in the horizontal memory units 108b and 108d to the corresponding output units 110b and 110d for each column, respectively. 108b and 108d are controlled.

  The output units 110a, 110b, 110c, and 110d add a synchronization signal before or after the digitized row unit pixel signal. The output units 110a, 110b, 110c, and 110d output digital pixel signals with synchronization signals to the signal processing unit 13 from the corresponding output terminals 111a, 111b, 111c, and 111d, respectively. The TG 112 outputs various clock signals and control signals necessary for the operation of each unit of the image sensor 12 based on the control signal from the synchronization control unit 15 via the control terminal 113.

  The output units 110a, 110b, 110c, and 110d according to the present embodiment will be described. The first output unit 110a will be described below, but the same applies to the second output unit 110b, the third output unit 110c, and the fourth output unit 110d. FIG. 9 is a diagram illustrating a configuration of the output unit 110a according to the present embodiment. The first output unit 110a includes a first signal conversion unit 201a, a first parallel-serial conversion unit 204a, a first synchronization signal addition unit 202a, and a first differential transmission buffer 203a.

  The first signal conversion unit 201a receives pixel signals D0a, D1a, D2a, D3a, D4a, D5a, and D6a transmitted from the first horizontal memory unit 108a via eight horizontal signal lines corresponding to 8 bits. And D7a are input. In addition, the pixel clock signal Skka transmitted from the TG 112 as a clock signal is input to the first signal conversion unit 201a. The pixel clock signal Skca is a signal having the same cycle as the transfer of the first horizontal scanning unit 109a. The first signal conversion unit 201a adjusts the phases of the 8-bit pixel signals D0a to D7a so as to be synchronized with the phase of the pixel clock signal Skca. The first signal conversion unit 201a may further perform the black level adjustment, column variation correction, signal amplification, color relation processing, and the like described in the first signal conversion unit in the first embodiment shown in FIG. .

  The first parallel-serial conversion unit 204a includes 8-bit pixel signals D0a to D7a synchronized with the phase of the pixel clock signal Skka and a multiplied clock having a frequency twice that of the pixel clock signal Skka sent from the TG 112 as a clock signal. The signal H2cka is input. Using the multiplied clock signal H2cka, the first parallel-serial conversion unit 204a performs parallel / serial conversion on the pixel signals D0a to D7a in which 8 bits each are input in parallel. For example, the pixel signals D0a to D7a are arranged in parallel in a 2-bit series synchronized with the multiplied clock signal H2cka such as the pixel signals D0a and D1a, the pixel signals D2a and D3a, the pixel signals D4a and D5a, and the pixel signals D6a and D7a. The converted pixel signal is output. Here, since the multiplied clock signal H2cka has a frequency twice that of the pixel clock signal Skka, the data transfer amount per pixel clock signal Skka does not change.

  The first synchronization signal adding unit 202a is synchronized with the phase of the multiplied clock signal H2cka, and the start synchronization signal and necessary for each of the pixel signals D0a / D1a, D2a / D3a, D4a / D5a, and D6a / D7a. The end synchronization signal is added according to the above. Here, the timing of adding the synchronization signal is controlled by the control signal output from the TG 112 based on the control signal from the synchronization control unit 15.

  The first differential transmission buffer 203a is provided for each of the pixel signals D0a · D1a, D2a · D3a, D4a · D5a, D6a · D7a, and the multiplied clock signal H2cka to which the synchronization signal is added. The first differential transmission buffer 203a simultaneously outputs a normal rotation signal having the same polarity as each pulse signal and an inverted signal having a reverse polarity. In this embodiment, the normal pixel signal is D0Pa to D7Pa, the inverted pixel signal is D0Na to D7Na, the normal multiplication clock signal is H2ckPa, and the inverted multiplication clock signal is H2ckNa.

  Here, it is assumed that the same signal is transmitted from the TG 112 as the pixel clock signal and the multiplied clock signal input to the output units 110a, 110b, 110c, and 110d. However, a delay corresponding to the distance from the TG 112 to each of the output units 110a, 110b, 110c, and 110d occurs. Therefore, the pixel clock signals Skka, Sckb, Sckc, Sckd and the multiplied clock signals H2cka, H2ckb, H2ckc, and H2ckd that are respectively input to the output units 110a, 110b, 110c, and 110d are used separately.

  Next, the operation in the fourth embodiment will be described with reference to FIG. FIG. 10 is a timing chart illustrating an operation example of the image sensor 12 according to the fourth embodiment. In FIG. 10, Opr1 indicates a first read operation when the first signal selection unit 105a is selected and the first memory selection unit 114a is connected to the first horizontal memory unit 108a. Opr2 indicates a second read operation when the second signal selection unit 105b is selected and the second memory selection unit 114b is connected to the second horizontal memory unit 108b. Opr3 indicates a third read operation when the first signal selection unit 105a is selected and the first memory selection unit 114a is connected to the third horizontal memory unit 108c. Opr4 indicates a fourth read operation when the second signal selection unit 105b is selected and the second memory selection unit 114b is connected to the fourth horizontal memory unit 108d.

  Among the pixels arranged in the pixel region 101, the signals of the pixels in the first row and the fifth row are read using the first read operation Opr1, and the signals of the pixels in the second row and the sixth row are read as the second signal. Reading is performed using the reading operation Opr2. Further, the signals of the pixels in the third and seventh rows are read out using the third readout operation Opr3, and the signals of the pixels in the fourth and eighth rows are read out using the fourth readout operation Opr4. .

  In the first read operation Opr1, first, in the period Read1r, the first signal selection unit 105a is selected, and the vertical row corresponding to the signals of the pixels in the first row by the drive control signal from the vertical scanning unit 102 respectively. Read out to the signal line 104 (time t60 to t61). At this time, the N signal in the state in which the pixels are first reset is sampled and held by the first column signal processing unit 106a, and the S signal in the state in which the signal of the photoelectric conversion unit is subsequently read out is the first column signal processing unit 106a. Is sampled and held.

  Next, in the period CDS1r, the first column signal processing unit 106a performs noise removal by CDS processing by subtracting the N signal from the S signal in the CDS circuit, and performs gain control by the AGC circuit if necessary. (After time t61). Then, in the period AD1r, the first column AD unit 107a performs analog-to-digital conversion on the pixel signal of the first row from which noise is removed. In the first read operation Opr1, since the first memory selection unit 114a is connected to the first horizontal memory unit 108a, the signal of the pixel in the first row converted into the digital signal is the first horizontal memory unit 108a. (Until time t63). Processing at time t60 to t63 so far is parallel processing for each column with respect to the signal of each pixel in the first row.

  Subsequently, in the period SD1r, before the pixel signal in which four 2-bit serially parallel pixels are sent in a state where the first synchronizing signal adding unit 202a in the first output unit 110a is synchronized with the phase of the multiplied clock signal H2cka. A start synchronization signal is added (after time t63). Since the start synchronization signal added here can be the same as the start synchronization signal in the first embodiment for each of the two 2-bit serially parallel pixel signals, description thereof will be omitted. At this time, the start synchronization signal is not added to the forward multiplied clock signal H2ckPa and the inverted multiplied clock signal H2ckNa.

  Next, in the period SigOut1r, the first horizontal scanning unit 109a selects the first horizontal memory unit 108a for each column, and digitized 8-bit pixel signals D0a to D7a stored in the first horizontal memory unit 108a. Is transferred to the first output unit 110a. Then, the first signal conversion unit 201a adjusts the phases of the 8-bit pixel signals D0a to D7a so as to be synchronized with the phase of the pixel clock signal Skca sent from the TG 112. In addition, the first parallel-serial conversion unit 204a converts the pixel signals D0a to D7a input in parallel in which the phase is adjusted into four 2-bit serial pixel signals in synchronization with the multiplied clock signal H2cka. Thereafter, the first differential transmission buffer 203a converts the signal into a normal signal and an inverted signal corresponding to each of the two 2-bit serially parallel signals, and outputs them from the first output terminal 111a.

  Further, continuously, in the period ED1r, four parallel pixel signals of 2 bits in series are sent out in a state where the first synchronization signal adding unit 202a in the first output unit 110a is synchronized with the phase of the multiplied clock signal H2cka. An end synchronization signal is added later (until time t67). Since the end synchronization signal added here can be the same as the end synchronization signal in the first embodiment for each of the four parallel pixel signals of 2-bit series, description thereof will be omitted. At this time, the end synchronization signal ED1r is not added to the forward multiplied clock signal H2ckPa and the inverted multiplied clock signal H2ckNa. The period from time t63 to t67 so far is the signal output period of each pixel in the first row to which the start synchronization signal and end synchronization signal are added.

  In the first read operation Opr1, after the pixel signal of the first row is output, the signal of the pixel of the fifth row is output continuously. A period from time t67 to t70 is a period in which parallel processing for each column such as readout for each column, CDS processing, analog-digital conversion, and storage in the horizontal memory unit is performed for the signal of each pixel in the fifth row. A period from time t70 to t71 is an output period of the signal of each pixel in the fifth row to which the start synchronization signal and the end synchronization signal are added. Furthermore, in the second embodiment, since the pixels 100 arranged in the pixel region 101 have 8 rows, the signal readout operation for the pixels in the first row is started again after time t71.

  Next, in the second readout operation Opr2, since the vertical signal line 104 is wired in common to the vertical pixel column, the operation starts after the end of the period Read1r for reading the signal of the pixel in the first row (time). After t61). First, in the period Read2r, the signals of the pixels in the second row are read out to the corresponding vertical signal lines 104 by the drive control signal from the vertical scanning unit 102 in a state where the second signal selection unit 105a is selected. That is, the N signal and the S signal of the pixel signals in the second row are read out to the second column signal processing unit 106b via the corresponding vertical signal lines 104 (time t61 to t62).

  Next, in the period CDS2r, the second column signal processing unit 106b performs noise removal by CDS processing in the CDS circuit, and performs gain control by the AGC circuit if necessary (after time t62). Then, in the period AD2r, the second column AD unit 107b performs analog-digital conversion on the signals of the pixels in the second row. In the second read operation Opr2, since the second memory selection unit 114b is connected to the second horizontal memory unit 108b, the pixel signal of the second row converted into a digital signal is the second horizontal memory unit 108b. (Until time t64). The processing at time t61 to t64 so far is parallel processing for each column with respect to the signal of each pixel in the second row.

  Subsequently, in the period SD2r, two parallel 2-bit pixel signals are sent in a state where a second synchronization signal adding unit (not shown) in the second output unit 110b is synchronized with the phase of the multiplied clock signal H2ckb. A start synchronization signal is added before coming (after time t64). Since the start synchronization signal added here is the same as the start synchronization signal in the first read operation Opr1, description thereof will be omitted.

  Here, in the second readout operation Opr2, since the signal readout operation of the pixels in the second row is started after the end of the period Read1r, the period SD2r to which the start synchronization signal is added also starts with a time delay corresponding to the period Read1r. There is a need.

  Next, in the period SigOut2r, the second horizontal scanning unit 109b selects the second horizontal memory unit 108b for each column, and digitized 8-bit pixel signals D0b to D7b stored in the second horizontal memory unit 108b. Is transferred to the second output unit 110b. Then, a second signal conversion unit (not shown) of the second output unit 110b adjusts the phases of the 8-bit pixel signals D0b to D7b so as to be synchronized with the phase of the pixel clock signal Skkb sent from the TG 112. In addition, a second parallel-serial conversion unit (not shown) of the second output unit 110b has four parallel 2-bit serial signals in which the pixel signals D0b to D7b that are input in parallel with the phase adjusted are synchronized with the multiplied clock signal H2ckb. Converted to a pixel signal. Thereafter, a second differential transmission buffer (not shown) of the second output unit 110b converts the signal into a normal signal and an inverted signal corresponding to each of the four parallel 2-bit signals, and from the second output terminal 111b. Output.

  Further, continuously, after a pixel signal in which four 2-bit serially parallel pixels are sent out in a period ED2r in a state where the second synchronization signal adding unit in the second output unit 110b is synchronized with the phase of the multiplied clock signal H2ckb. An end synchronization signal is added (until time t68). Since the end synchronization signal added here is the same as the end synchronization signal in the first read operation Opr1, description thereof will be omitted. The period from time t64 to t68 so far is the signal output period of each pixel in the second row to which the start synchronization signal and end synchronization signal are added.

  In the second readout operation Opr2, after the pixel signal of the second row is output, the pixel signal of the sixth row is output continuously. The description of the pixel signal output of the sixth row after time t68 is omitted because it may be performed in the same manner as the signal output of the pixel of the second row. In the second embodiment, since the pixels 100 arranged in the pixel region 101 are 8 rows, the pixel signal of the second row is read again after the pixel signals of the sixth row are output. Is started.

  Next, in the third readout operation Opr3, since the vertical signal line 104 is wired in common to the vertical pixel column, the operation starts after the end of the period Read2r for reading out the signals of the pixels in the second row (time). After t62).

  The period from time t62 to t65 is a period in which parallel processing for each column such as readout for each column, CDS processing, analog-digital conversion, and storage in the horizontal memory unit is performed for the signal of each pixel in the third row. The period from time t65 to t69 is the signal output period of each pixel in the third row to which the start synchronization signal and end synchronization signal are added. The description of the output of the pixel signal of the seventh row after time t69 may be performed in the same manner as the output of the signal of the pixel of the third row, and is therefore omitted. In the fourth embodiment, since the pixels 100 arranged in the pixel region 101 have eight rows, the signal readout operation of the pixels in the third row is performed again after the pixel signals in the seventh row are output. Is started.

  Next, in the fourth readout operation Opr4, since the vertical signal line 104 is wired in common to the vertical pixel column, the operation starts after the end of the period Read3r for reading out the signals of the pixels in the third row (time). after t63).

  A period from time t63 to t66 is a period in which parallel processing for each column such as readout for each column, CDS processing, analog-digital conversion, and storage in the horizontal memory unit is performed for the signals of the pixels in the fourth row. A period from time t66 to t70 is an output period of the signal of each pixel in the fourth row to which the start synchronization signal and the end synchronization signal are added. The description of the signal output from the pixels in the eighth row after time t70 is omitted because it may be performed in the same manner as the signal output from the pixels in the fourth row. In the second embodiment, since the pixels 100 arranged in the pixel region 101 have eight rows, the pixel signal readout operation for the fourth row is performed again after the output of the pixel signals for the eighth row. Is started.

  As described above, in the fourth embodiment, it is necessary to operate the first read operation Opr1 and the second read operation Opr2 while being shifted by the period Read1r. For this reason, the TG 112 controls the parallel processing operation for each column from the readout of the pixel signal of the first row performed during the period Read1r, the period CDS1r, and the period AD1r to the storage in the first horizontal memory unit 108a. Is possible. Further, the TG 112 shifts by the period Read1r, and reads out the signals of the pixels in the second row performed during the period Read2r, the period CDS2r, and the period AD2r, and stores them in the second horizontal memory unit 108b for each column. It is possible to control parallel processing operations.

  Here, the difference between the start times of the first readout operation Opr1 and the second readout operation Opr2 is that the readout of the signals of the pixels in the first row is completed because the vertical signal line 104 is wired in common with the vertical pixel column. This is because reading of the signals of the pixels in the second row cannot be started. Therefore, the start time of the second read operation Opr2 may be after a predetermined time has elapsed after the end of the period Read1r.

  Further, the TG 112 can control the output operation of the pixel signals in each row to which the start synchronization signal and the end synchronization signal are added, in addition to the above-described parallel processing operation for each column. Here, the output operation start timing of the start synchronization signal added to the signal of the pixel in the first row may be after a predetermined time has elapsed after the parallel processing operation of the signal of the pixel in the first row. Further, for example, the start timing of the output operation of the start synchronization signal added to the signal of the pixel in the second row may be after a predetermined time has elapsed after the parallel processing operation of the signal of the pixel in the second row. Further, the difference between the output start timings of the start synchronization signal added to the pixel signal of the first row and the start synchronization signal added to the signal of the pixel of the second row may be longer than the period Read1r.

  The start timing of the period Read1r, the start timing of the period Read2r, the start timing of the period SD1r, and the start timing of the period SD2r can be individually and appropriately set based on the control signal from the synchronization control unit 15.

  The above description has described only the relationship between the first read operation Opr1 and the second read operation Opr2. The same applies to the relationship between the second read operation Opr2 and the third read operation Opr3, and the relationship between the third read operation Opr3 and the fourth read operation Opr4. Further, when the readout operation is repeated, the same applies to the relationship between the fourth readout operation Opr4 that reads out the pixel signal of the fourth row and the first readout operation Opr1 that reads out the pixel signal of the fifth row. The same applies to the relationship between the fourth readout operation Opr4 that reads out the pixel signal in the eighth row and the first readout operation Opr1 that reads out the pixel signal in the first row.

  Here, since the number of pixels of the output signal of the image sensor 12 is determined in advance, if the synchronization control unit 15 can control the signal processing unit 13 to perform processing corresponding to pixels for one row. The end synchronization signal can be omitted.

  FIG. 11 is a diagram illustrating a configuration of an input portion of the signal processing unit 13 according to the present embodiment, and timing is performed in units of rows output from the image sensor 12 so that signal processing in the signal processing unit 13 is possible. It is possible to receive digital pixel signals that are shifted from each other. The signal processing unit 13 includes a first input unit 401 a, a second input unit 401 b, a third input unit 401 c, a fourth input unit 401 d, a synchronization signal decoding unit 403, a serial-parallel conversion unit 406, and an internal memory 404.

  Pixel signals from the first output unit 110a and the second output unit 110b are input to the first input unit 401a and the second input unit 401b via the first input terminal 402a and the second input terminal 402b, respectively. . In addition, pixel signals from the third output unit 110c and the fourth output unit 110d are input to the third input unit 401c and the fourth input unit 401d via the third input terminal 402c and the fourth input terminal 402d, respectively. Is done.

  Since the signal input to the signal processing unit 13 is a differential signal composed of a normal pixel signal and an inverted pixel signal as described with reference to FIG. 9, it is received by a differential reception buffer (not shown). To convert it into a normal pulse signal. At this time, the phase of the multiplied clock signal input at the same time and the phase of the signal processing clock signal of the signal processing unit 13 are compared, and the process of synchronizing the phase of the digital pixel signal with the phase of the signal processing clock signal of the signal processing unit 13 is also performed. .

  The synchronization signal decoding unit 403 decodes the synchronization signal of the row-unit pixel signal with the synchronization signal, and outputs the row-unit pixel signal sandwiched between the start synchronization signal and the end synchronization signal. The serial-parallel converter 406 is a pixel in which four 2-bit serial pixel signals sent from the first output unit 110a, the second output unit 110b, the third output unit 110c, and the fourth output unit 110d are paralleled by 8 bits. The signal is serial-parallel converted and stored in the internal memory 404. For example, four 2-bit serial pixel signals D0a and D1a, D2a and D3a, D4a and D5a, and D6a and D7a sent from the first output unit 110a are converted into 8-bit parallel pixel signals D0a to D7a. Is done. The internal memory 404 stores pixel signals in units of rows. In FIG. 11, regions for storing pixel signals from the first row to the eighth row are indicated as mP1r to mP8r for convenience.

  Here, a case where the operation shown in FIG. 10 is performed will be described. When the pixel signal of the first row is input from the first input unit 401a to the synchronization signal decoding unit 403, the row unit sandwiched between the start synchronization signal and the end synchronization signal based on the control signal from the synchronization control unit 15 Are sent to the serial-parallel converter 406. The signal of the pixel in the first row is converted into a pixel signal in which 8 bits are paralleled by the serial-parallel conversion unit 406 and stored in the area mP1r of the internal memory 404. Next, when the pixel signal in the second row is input from the second input unit 401 b to the synchronization signal decoding unit 403, it is sandwiched between the start synchronization signal and the end synchronization signal based on the control signal from the synchronization control unit 15. The row-by-row pixel signal is sent to the serial-parallel converter 406. The pixel signals in the second row are converted into 8-bit parallel pixel signals by the serial-parallel converter 406 and stored in the area mP2r of the internal memory 404.

  Subsequently, a pixel signal of the third row is input from the third input unit 401 c, converted into a pixel signal parallel to 8 bits, and stored in the area mP <b> 3 r of the internal memory 404. Subsequently, the pixel signal of the fourth row is input from the fourth input unit 401d, is converted into a pixel signal parallel to 8 bits, and is stored in the area mP4r of the internal memory 404.

  At this time, with respect to the internal memory 404, the pixel storing operation of the first row pixel, the signal storing operation of the pixel of the second row, the signal storing operation of the pixel of the third row, and the pixel storing operation of the pixel of the fourth row A timing at which a part of the signal storing operation overlaps occurs. However, since it is a storage operation for different areas of the internal memory 404, it can be controlled. After the signal storage operation for the pixels in the first row, the second row, the third row, and the fourth row is completed, the signal storage operation for the pixels in the fifth row and thereafter is similarly performed.

  Then, the signals of the pixels in the first to eighth rows stored in the areas mP1r to mP8r of the internal memory 404 are processed for each row from the internal memory terminal 405 based on the control signal from the synchronization control unit 15. It will be done. After that, when the signal of the pixel in the first row is continuously input, it may be stored in the area mP1r from the beginning.

  As described above, in the present embodiment, it is possible to provide a means for controlling the synchronization of output signals by individually setting the start synchronization signal for each of the signals of the plurality of output means in accordance with the read time difference. it can. Then, by assigning a memory area for storing a pixel signal in accordance with the decoded synchronization signal at the input portion of the signal processing unit, synchronization control corresponding to the reading time difference can be realized. As a result, it is not necessary to provide a FIFO memory or a delay line after the output unit of the image sensor, and signals of a plurality of pixels can be output separately using an output unit different from the common readout unit. A high-speed reading operation in the imaging apparatus can be realized. In the present embodiment, since it is possible to output four rows simultaneously, a four times higher frame rate can be realized.

  Further, since the parallel-serial conversion unit 204 in the output unit 110 converts the pixel signals that are input in parallel with 8 bits each into 8 pixel signals that are 2 bits in series and outputs them, 4 outputs The number of differential transmission buffers 203 in all the units 110 is halved. As a result, the effect of reducing the circuit scale and power consumption can be expected, and the number of output terminals from the image sensor is also reduced, so that the package of the image sensor can be reduced.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIG. 1, FIG. 8, FIG. 9, FIG. In the fifth embodiment, the basic configuration and operation of the imaging apparatus and the basic configuration and operation of the imaging element are the same as those in the fourth embodiment. . The signal processing unit 13 according to the fourth embodiment is configured to be able to receive digital pixel signals that are out of timing in units of rows that are output from the image sensor 12. In the fifth embodiment, a method for enabling the synchronous output of the signals of the first pixels from the first row to the fourth row without providing a FIFO memory or delay line in the subsequent stage of the output means of the image sensor will be described. To do.

  FIG. 12 is a timing chart illustrating an operation example of the image sensor 12 according to the fifth embodiment. In FIG. 12, Opr1 indicates a first read operation when the first signal selection unit 105a is selected and the first memory selection unit 114a is connected to the first horizontal memory unit 108a. Opr2 indicates a second read operation when the second signal selection unit 105b is selected and the second memory selection unit 114b is connected to the second horizontal memory unit 108b. Opr3 indicates a third read operation when the first signal selection unit 105a is selected and the first memory selection unit 114a is connected to the third horizontal memory unit 108c. Opr4 indicates a fourth read operation when the second signal selection unit 105b is selected and the second memory selection unit 114b is connected to the fourth horizontal memory unit 108d.

  In the fifth embodiment, the start of the period SD1r of the first row in the first read operation Opr1 is time t86, which is the start of the period SD4r of the fourth row in the fourth read operation Opr4. This is different from the fourth embodiment. Similarly, at the time t86 when the start of the second row period SD2r in the second read operation Opr2 and the start of the third row period SD3r in the third read operation Opr3 are the start of the fourth row period SD4r. This is different from the fourth embodiment.

  At time t83, which is the end of the period AD1r in the first read operation Opr1, the pixel signal of the first row is stored in the first horizontal memory unit 108a as a digitized pixel signal in units of rows. Similarly, the pixel signal of the second row in the second readout operation Opr2 and the pixel signal of the third row in the third readout operation Opr3 are also digitized row-unit pixel signals, respectively, in the second horizontal memory unit. 108b and the third horizontal memory unit 108c. Since the stored pixel signal is digital data, it can be held without being degraded unlike an analog signal. Therefore, based on the control signal from the synchronization control unit 15, the TG 112 delays the start of the operations of the first horizontal scanning unit 109a and the second horizontal scanning unit 109b. Next, at time t86, which is the start of the period SD4r in the fourth row, the period SD1r in the first row, the period SD2r in the second row, and the period SD3r in the third row are started, so that the period SD1r, the period SD2r, SD3r and period SD4r are synchronized.

  Subsequently, simultaneously with the start of the period SigOut4r of the fourth row, the period SigOut1r of the first row, the period SigOut2r of the second row, and the period SigOut3r of the third row are started. That is, simultaneously with the start of the period SigOut4r in the fourth row, the first horizontal scanning unit 109a selects the first horizontal memory unit 108a and the third horizontal memory unit 108c for each column, and stores the stored 8-bit pixel signal. Transfer to the first output unit 110a and the third output unit 110c. Similarly, simultaneously with the start of the period SigOut4r in the fourth row, the second horizontal scanning unit 109b selects the second horizontal memory unit 108b and the fourth horizontal memory unit 108d for each column, and stores the 8-bit pixel signal. Are transferred to the second output unit 110b and the fourth output unit 110d. Thereby, the signal of the first pixel in the first row, the signal of the first pixel in the second row, the signal of the first pixel in the third row, and the signal of the first pixel in the fourth row can be synchronized. Further, the period ED1r of the first row, the period ED2r of the second row, and the period ED3r of the third row are started in synchronization with the period ED4r of the fourth row.

  Synchronous control is performed so that the entire output period of the signal of the pixel in the first row to which the start synchronization signal and the end synchronization signal are added is delayed by a time corresponding to the period Read2r, the period Read3r, and the period Read4r (time t83 to t86). The unit 15 controls the image sensor 12. Thereby, the signal of the pixel in the first row and the signal of the pixel in the fourth row can be output in synchronization. Similarly, the synchronization control unit is configured to delay the entire output period of the pixel signal of the second row to which the start synchronization signal and the end synchronization signal are added by a time corresponding to the period Read3r and the period Read4r (time t84 to t86). 15 controls the image sensor 12. Thereby, the signal of the pixel of the 2nd row and the signal of the pixel of the 4th row can be synchronized and output.

  Similarly, the synchronization control unit 15 is configured to delay the entire output period of the pixel signals of the third row to which the start synchronization signal and the end synchronization signal are added by a time corresponding to the period Read4r (time t85 to t86). Controls the image sensor 12. Thereby, the signal of the pixel of the 3rd row and the signal of the pixel of the 4th row can be synchronized and output. Therefore, the pixel signal of the first row, the signal of the pixel of the second row, and the signal of the pixel of the third row can be output in synchronization with the signal of the pixel of the fourth row. The same operation is performed on the signals of the pixels on the fifth row to the pixels on the eighth row.

  As described above, in this embodiment, the output signal can be synchronized by individually setting the start synchronization signal for each of the signals of the plurality of output means. However, the signal output period of the pixels in the first row to which the start synchronization signal and the end synchronization signal are added is delayed by a time corresponding to the sum of the period Read2r, the period Read3r, and the period Read4r. Therefore, the read time for each row in the first read operation Opr1 becomes longer by a time corresponding to the sum of the period Read2r, the period Read3r, and the period Read4r. However, this makes it possible to separately output signals from a plurality of pixels by using output means different from the common readout means without providing a FIFO memory or a delay line after the output means of the image sensor. A high-speed reading operation in the imaging apparatus can be realized. In this embodiment, since it is possible to output four rows simultaneously, a frame rate close to four times can be realized.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described with reference to FIG. 1, FIG. 8, FIG. 9, FIG. In the sixth embodiment, the basic configuration and operation of the imaging apparatus and the basic configuration and operation of the imaging element are the same as those in the fourth embodiment. . In the fourth embodiment, a high-speed readout operation in the imaging apparatus is realized by separately outputting signals of a plurality of pixels using an output unit different from the common readout unit. In the sixth embodiment, a method for realizing a further high-speed reading operation by simultaneously operating a parallel processing for each column and a part of an output period of a pixel signal will be described.

  FIG. 13 is a timing chart illustrating an operation example of the image sensor 12 according to the sixth embodiment. In FIG. 13, Opr1 indicates a first read operation when the first signal selection unit 105a is selected and the first memory selection unit 114a is connected to the first horizontal memory unit 108a. Opr2 indicates a second read operation when the second signal selection unit 105b is selected and the second memory selection unit 114b is connected to the second horizontal memory unit 108b. Opr3 indicates a third read operation when the first signal selection unit 105a is selected and the first memory selection unit 114a is connected to the third horizontal memory unit 108c. Opr4 indicates a fourth read operation when the second signal selection unit 105b is selected and the second memory selection unit 114b is connected to the fourth horizontal memory unit 108d.

  The sixth embodiment differs from the fourth embodiment in the following points. The end of the period SD for adding the start synchronization signal in each read operation Opr is the same as the end of the period AD for analog-digital conversion. In addition, the start of the period ED for adding the end synchronization signal in each read operation Opr is simultaneously with the start of the period Read of the next read row.

  At time t103, which is the end of the period AD1r in the first read operation Opr1, the pixel signal of the first row is stored in the first horizontal memory unit 108a as a digitized pixel unit pixel signal. Therefore, the period SigOut1r in the first row can be started after time t103. Therefore, the TG 112 causes the first synchronization signal adding unit 202a to output a start synchronization signal based on the control signal from the synchronization control unit 15 so that the period AD1r ends and the period SD1r ends at the same time. Then, after the period SD1r ends, the period SigOut1r in the first row starts.

  Further, an end synchronization signal is output following time t105 when the period SigOut1r ends. At the same time, a period Read5r for reading out the signals of the pixels in the fifth row is started, and thereafter, the same operation as the signals of the pixels in the first row is performed.

  Similarly, in the second to fourth read operations Opr, the TG 112 starts from the synchronization signal adding unit based on the control signal from the synchronization control unit 15 so that the period AD and the period SD end simultaneously. Output sync signal. Then, after the period SD ends, the period SigOut of the corresponding row is started. Next, after the end of the period SigOut, the end synchronization signal of the corresponding row is continuously output. At the same time, the period Read of the next read row is started, and the same operation is performed thereafter.

  As described above, in the present embodiment, it is possible to provide a means for controlling the synchronization of output signals by individually setting the start synchronization signal for each of the signals of the plurality of output means in accordance with the read time difference. it can. Then, by assigning a memory area for storing a pixel signal corresponding to the decoded synchronization signal at the input portion of the signal processing unit, synchronization control corresponding to the readout time difference can be realized. As a result, it is not necessary to provide a FIFO memory or a delay line after the output unit of the image sensor, and signals of a plurality of pixels can be output separately using an output unit different from the common readout unit. A high-speed reading operation in the imaging apparatus can be realized. In the present embodiment, since it is possible to output four rows simultaneously, a four times higher frame rate can be realized. Furthermore, in the present embodiment, a higher-speed read operation can be realized by overlapping the period AD and the period SD and overlapping the period ED and the period Read.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 11: Optical system 12: Image pick-up element 13: Signal processing part 15: Synchronization control part 100: Pixel 101: Pixel area 102: Vertical scanning part 103: Pixel control line 104: Vertical signal line 105: Signal selection part 106: Column signal processing Unit 107: column AD unit 108: horizontal memory unit 109: horizontal scanning unit 110: output unit 112: signal generation unit (TG) 114: memory selection unit 201: first signal conversion unit 202: first synchronization signal addition unit 403: Sync signal decoder

Claims (3)

A plurality of pixels arranged in a matrix having a photoelectric conversion means, respectively, and a column signal line for outputting a signal from the plurality of pixels in each column, and run査means you select one row of the plurality of pixels A plurality of column signal processing means for processing signals read from the pixels connected to the column signal lines, and signals provided respectively corresponding to the plurality of column signal processing means and processed by the column signal processing means an imaging device having a plurality of output means, the outputting by adding a synchronization signal to,
Before the output of the signal of the previously read pixel from the output means is completed, the signal of the pixel of the next row is read to the column signal processing means different from the column signal processing means corresponding to the output means. Control means for controlling the image sensor so that the output means outputs a signal from the column signal processing means following the synchronization signal ;
With
2. The imaging apparatus according to claim 1, wherein the synchronization signal includes a signal for recognizing from which output means of the plurality of output means .   2. The imaging apparatus according to claim 1, wherein the control unit controls the plurality of output units to simultaneously output the synchronization signal and simultaneously output signals from the column signal processing unit.   The control means controls the output means corresponding to the column signal processing means to output the synchronization signal while reading out a pixel signal to the column signal processing means. The imaging apparatus according to 1.

Images