JP4284577B2 - Imaging apparatus and solid-state imaging device driving method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image pickup apparatus and a solid-state image pickup device driving method, and is suitable for application to, for example, a digital still camera.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a digital still camera that converts a captured image of an object into digital data, and stores the converted digital data in a memory. This digital still camera employs, for example, a solid-state image sensor (CCD: Charge Coupled Device) as an image sensor.
[0003]
[Problems to be solved by the invention]
By the way, in this digital still camera, since it is necessary to read out all pixels constituting one screen every time imaging is performed, imaging at intervals of several tens [ms] is the limit. For example, when the horizontal drive frequency is 14.3 [MHz] and the number of pixels is 330,000, images can be captured only at intervals of 23 [ms], and high-speed continuous imaging cannot be realized.
[0004]
Therefore, as a method for realizing high-speed continuous imaging, a method of increasing the frame rate (that is, the number of images that can be acquired per second) by reducing the number of pixels that read signals out of each pixel constituting the CCD, or horizontal transfer A method of increasing the frame rate by increasing the register reading frequency (that is, the reading speed) is conceivable.
[0005]
However, in the method of increasing the frame rate by reducing the number of pixels to be read, the number of pixels itself is reduced. Therefore, it is inevitable that the image quality is deteriorated, and the frame is read by increasing the reading frequency of the horizontal transfer register. In the method of increasing the rate, there are problems that transfer efficiency in the horizontal transfer register is deteriorated and a clock margin used in a signal processing circuit provided in the subsequent stage of the CCD is insufficient.
[0006]
The present invention has been made in consideration of the above points, and an object of the present invention is to propose an imaging apparatus and a solid-state imaging element driving method capable of performing continuous imaging at high speed with a simple configuration.
[0007]
[Means for Solving the Problems]
In order to solve such a problem, in the present invention, a pixel unit that is arranged in a matrix and has a photoelectric conversion unit that photoelectrically converts received light, and a vertical charge transfer unit that transfers charges read from the pixel unit in the vertical direction, A drive unit that controls the pixel unit and the vertical charge transfer unit so as to alternately perform decimation readout for thinning out some pixel rows and reading out charges to the vertical charge transfer unit and one-stage vertical transfer in the vertical charge transfer unit by providing the bets may fast imaging with shortened iMAGING intervals than conventional.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0009]
In FIG. 1, reference numeral 1 denotes a configuration of a digital still camera as a whole, and incident light L1 incident from the subject side is incident on a solid-state imaging device (CCD: Charge Coupled Device) 3 through an optical lens 2. Based on the signal supplied from the timing generation circuit 4, the CCD 3 photoelectrically converts the received incident light L 1 to generate an image signal S 1 and sends it to the sample hold (S / H) circuit 5.
[0010]
That is, as shown in FIG. 2A, the CCD 3 receives the incident light L1 by the photosensor unit 10. The photo sensor unit 10 obtains electric charges by photoelectrically converting the received incident light L1, and accumulates the electric charges. The charges accumulated in the photosensor unit 10 are transferred from the photosensor unit 10 to the vertical transfer register 11 at a timing based on the read pulse signal S2 supplied from the timing generation circuit 4.
[0011]
Subsequently, the charges transferred to the vertical transfer register 11 are transferred from the vertical transfer register 11 to the horizontal transfer register 12 line by line at a timing based on the vertical transfer clock signal S3 supplied from the timing generation circuit 4. .
[0012]
Then, the charges transferred to the horizontal transfer register 12 are transferred from the horizontal transfer register 12 to the output unit 13 at a timing based on the horizontal transfer clock signal S4 supplied from the timing generation circuit 4, and from the output unit 13 to the image signal S1. Are output for each line.
[0013]
The S / H circuit 5 generates an image signal S10 of an analog signal based on the image signal S1 supplied from the CCD 3, and sends this to the analog / digital (A / D) conversion circuit 20. The A / D conversion circuit 20 performs analog-digital conversion on the image signal S10 and sends the image data S11 obtained as a result to the camera signal processing circuit 21.
[0014]
The camera signal processing circuit 21 obtains image data S12 by performing data processing such as gamma correction and gain control on the image data S11, and obtains the image data S12 via a switching circuit 22, which is a liquid crystal display (LCD). 23 and displayed on the LCD 23.
[0015]
In this state, when the user performs an operation for recording the image data S12 on the operation unit 30, the operation unit 30 sends a command signal S14 for performing a recording operation to the controller 31. The controller 31 generates a recording control signal S15 for controlling the recording of the image data S12 based on the supplied command signal S14, and sends the recording control signal S15 to the memory control 32 and the switching circuit 22.
[0016]
Based on this recording control signal S15, the switching circuit 22 sends the image data S12 supplied from the camera signal processing circuit 21 to a DRAM (Dynamic Random Access memory) 33 via the data bus BUS.
[0017]
By the way, the memory control 32 is supplied with the horizontal synchronizing signal H and the vertical synchronizing signal V from the timing generating circuit 4 via the camera signal processing circuit 21, and the memory control 32 is supplied with the recording control signal supplied from the controller 31. Based on S15, the horizontal synchronization signal H and the vertical synchronization signal V are added to the image data S12, and the image data S12 is once written in the DRAM 33.
[0018]
Thereafter, the memory control 32 reads the image data S12 from the DRAM 33 and sends the read image data S12 to the compression / decompression circuit 34 via the data bus BUS. The compression / decompression circuit 34 generates compressed image data S17 by compressing and encoding the image data S12 by an encoding method based on the JPEG (Joint Photographic Coding Experts Group) standard, and writes and stores this in the flash memory 35. .
[0019]
In this state, when the user performs an operation for reproducing the compressed image data S17 in the operation unit 30, the operation unit 30 sends a command signal S14 for performing a reproduction operation to the controller 31. The controller 31 generates a reproduction control signal S20 for reproducing the compressed image data S17 on the basis of the supplied command signal S14, and reads the compressed image data S17 from the flash memory 35 by sending it to the flash memory 35. To the compression / decompression circuit 34.
[0020]
The compression / decompression circuit 34 decompresses and decodes the compressed image data S17 supplied from the flash memory 35, and sends the resulting image data S21 to the switching circuit 22 via the data bus BUS. The switching circuit 22 is supplied with a reproduction control signal S20 generated based on the command signal S15 in the controller 31, and the switching circuit 22 is supplied from the compression / expansion circuit 34 based on the reproduction control signal S20. The image data S21 sent to the LCD 23 is displayed on the LCD 23.
[0021]
By the way, in the digital still camera 1, high-speed imaging can be performed. When a user performs an operation for performing high-speed imaging in the operation unit 30, a command for performing high-speed imaging from the operation unit 30. The signal S14 is sent to the controller 31. The controller 31 generates a high-speed imaging control signal S25 based on the supplied command signal S14 and sends it to the timing generation circuit 4, the camera signal processing circuit 21, the switching circuit 22, and the memory control 32.
[0022]
The timing generation circuit 4 constitutes a solid-state image sensor driving means together with the controller 31, and generates a read pulse signal S2, a vertical transfer clock signal S3, and a horizontal transfer clock signal S4 based on the supplied high-speed imaging control signal S25. These are sent to the CCD 3. Based on the readout pulse signal S2 supplied from the timing generation circuit 4, the CCD 3 performs so-called thinning readout for reading out charges from only a part of the pixel rows in the vertical direction among all the pixels.
[0023]
The CCD 3 performs this thinning-out reading and transfers the charge to the vertical transfer register 11, and then horizontally transfers the charge from the vertical transfer register 11 at a timing based on the vertical transfer clock signal S 3 supplied from the timing generation circuit 4. Vertical transfer is performed for transfer to the register 12. As described above, the CCD 3 can perform high-speed imaging by alternately performing thinning readout and vertical transfer.
[0024]
Specifically, as shown in FIG. 2B, the CCD 3 reads out charges from only one-eighth of the photosensor units 10 provided corresponding to each pixel, and vertically Transfer to the transfer register 11. That is, only the charges accumulated in the photosensor unit 10 of one line (for example, the first line, the ninth line,...) Out of the eight lines are read out.
[0025]
The charge transferred to the vertical transfer register 11 is one stage (ie, one line) from the vertical transfer register 11 to the horizontal transfer register 12 at a timing based on the vertical transfer clock signal S3 supplied from the timing generation circuit 4. ) Transferred.
[0026]
Then, after a predetermined exposure time elapses, the CCD 3 performs charge thinning out again and executes vertical transfer. In this manner, the CCD 3 obtains eight images (i to h) having different exposure timings by repeatedly performing thinning readout and vertical transfer 8 times alternately.
[0027]
In this case, the charge transferred to the horizontal transfer register 12 is transferred from the horizontal transfer register 12 to the output unit 13 at a timing based on the horizontal transfer clock signal S4 supplied from the timing generation circuit 4, and the image is output from the output unit 13 to the image. The signal S30 is output for each line.
[0028]
FIG. 3 shows a timing chart when executing high-speed imaging. 3A shows the read pulse signal S2, and FIG. 3B shows the vertical transfer clock signal S3. FIG. 3C shows the exposure time, which is determined by the read pulse signal S2. FIG. 3D shows the output timing for each line of the image signal S30 output from the output unit 13, that is, the CCD 3, and the image signal S30 is output in synchronization with the vertical transfer clock signal S3 for each line. Yes.
[0029]
Incidentally, in this case, since the CCD 3 cannot output the image signals S30 of all the captured lines during the imaging period, the image signals S30 of the remaining lines that could not be output during the imaging period even during the readout period after the end of the imaging period. The output is made (FIG. 3D).
[0030]
The image signal S30 output from the CCD 3 in this way is converted into image data S31 through the S / H circuit 5, the A / D conversion circuit 20 and the camera signal processing circuit 21 in order, and then the switching circuit 22 and the data bus. The data is written in the DRAM 33 sequentially through the BUS.
[0031]
By the way, the image signal S30 is generated by alternately executing decimation readout and vertical transfer in the CCD 3, so that the order of transfer from the vertical transfer register 11 to the horizontal transfer register 12 is independent of the order of exposure timing. Is output for each line.
[0032]
Accordingly, the memory control 32 rearranges the image data S31 on the DRAM 33 based on the high-speed imaging control signal S25 supplied from the controller 31, thereby generating eight correct images for each exposure timing. The image data S32 is sent to the camera signal processing circuit 21 via the data bus BUS.
[0033]
Since the data amount of the image data S32 is reduced to 1/8 in the vertical direction, the camera signal processing circuit 21 performs the interpolation processing in the vertical direction on the image data S32, and the interpolated image obtained as a result thereof. Data S33 is sent to the compression / decompression circuit 34 via the data bus BUS. The compression / decompression circuit 34 compresses and encodes the interpolated image data S33 to generate compressed image data S34, which is written and stored in the flash memory 35.
[0034]
In this state, when the user performs an operation for reproducing the compressed image data S34 on the operation unit 30, the controller 31 reads the compressed image data S34 from the flash memory 35, and the compressed image data S34 is compressed / decompressed by the compression / decompression circuit 34. The data bus BUS and the switching circuit 22 are sequentially sent to the LCD 23 for display.
[0035]
In the above configuration, the CCD 3 reads charges from only one-eighth of the total pixels of the photosensor unit 10 during high-speed imaging. Then, the CCD 3 performs this thinning-out reading and transfers charges to the vertical transfer register 11, and then performs one-stage vertical transfer. In this way, the CCD 3 can perform high-speed imaging by alternately executing thinning readout and vertical transfer.
[0036]
That is, the minimum interval between imaging is the sum of the time required to transfer charges to the vertical transfer register 11 and the time required for one stage of vertical transfer, and imaging can be performed at intervals of several tens [μs]. Become. As a result, the imaging interval can be further reduced as compared with the conventional case. For example, if the time required for transfer to the vertical transfer register 11 is 3.5 [μs] and the time required for one-stage vertical transfer is 15 [μs], continuous imaging can be performed at intervals of about 19 [μs]. Become.
[0037]
Further, since this CCD 3 does not require a special structure and a general-purpose CCD can be used, high-speed imaging can be performed with a simple configuration without changing the design of the CCD 3. Further, in the digital still camera 1, the number of pixels of 1/8 of all the pixels is read out at the time of high-speed imaging, whereas high-speed imaging can be performed while suppressing deterioration of image quality by reading out all the pixels at the normal time.
[0038]
According to the above configuration, after performing thinning readout for reading out charges from only some of the pixel rows in the vertical direction among all the pixels formed by the photosensor unit 10 formed on the imaging surface of the CCD 3, the charges are transferred vertically. By transferring to the register 11 and performing one-stage vertical transfer, and alternately performing this thinning readout and one-stage vertical transfer, the imaging interval is further shortened as compared with the prior art without changing the design of the CCD 3. Thus, high-speed imaging can be performed with a simple configuration.
[0039]
In the above-described embodiment, the case where the charge is read from only 1/8 of all the pixels has been described. However, the present invention is not limited to this, and for example, 1/10 of all the pixels. The charge may be read from only the pixels. In short, the charge may be read from only a part of the pixel rows in the vertical direction among all the pixels.
[0040]
In the above-described embodiment, the case where one-stage vertical transfer is performed after the charge is transferred to the vertical transfer register 11 is described. However, the present invention is not limited to this. For example, two-stage vertical transfer is performed. In short, it is only necessary to perform vertical transfer by the number of stages (that is, the number of lines) corresponding to the number of pixels to be read out.
[0041]
In the above-described embodiment, the case where the exposure time is adjusted by reading the charge from the photosensor unit 10 at the timing based on the read pulse signal S2 supplied from the timing generation circuit 4 has been described. However, the charge accumulated in the photosensor section 10 of the CCD 3 is swept away at the timing based on the sub-pulse signal as shown in FIG. 3E (FIG. 3F), thereby generating the sub-pulse signal generation timing. The exposure time can be adjusted more finely by controlling.
[0042]
In the above-described embodiment, the case where the charge is read from the photosensor unit 10 at the timing based on the read pulse signal S2 supplied from the timing generation circuit 4 has been described. However, the present invention is not limited to this and each exposure is performed. The exposure time and the imaging interval may be set every time, and the imaging may be performed, or the imaging may be performed with the exposure time and the imaging interval set in advance for one trigger.
[0043]
In the above-described embodiment, the case where the present invention is applied to the CCD 3 has been described. However, the present invention is not limited to this, and other various solid-state imaging devices such as a CMOS (Complementary Metal Oxide Semiconductor) are used. You may make it apply to invention.
[0044]
Further, in the above-described embodiment, the case where the present invention is applied to the digital still camera 1 has been described. However, the present invention is not limited to this, and in short, the present invention is applied to an imaging apparatus that captures an object with a solid-state imaging device. Can be widely applied.
[0045]
【The invention's effect】
As described above, according to the present invention, a pixel unit that is arranged in a matrix and has a photoelectric conversion unit that photoelectrically converts received light, a vertical charge transfer unit that transfers charges read from the pixel unit in a vertical direction, The pixel unit and the vertical charge transfer unit are controlled so as to alternately perform the thinning readout for reading out charges to the vertical charge transfer unit from a part of the pixel rows and the one-stage vertical transfer in the vertical charge transfer unit. it allows the imaging interval required for the imaging and subsequent image capturing can be shortened further than conventional and can realize an imaging apparatus capable of performing high-speed imaging hidden.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an imaging apparatus according to the present invention.
FIG. 2 is a schematic diagram illustrating a configuration of a CCD.
FIG. 3 is a schematic diagram illustrating a timing chart during high-speed imaging.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Digital still camera, 2 ... Optical lens, 3 ... CCD, 4 ... Timing generation circuit, 5 ... S / H circuit, 10 ... Photo sensor part, 11 ... Vertical transfer register, 12 ... Horizontal transfer register, 13 ... output unit, 20 ... A / D conversion circuit, 21 ... camera signal processing circuit, 22 ... switching circuit, 23 ... LCD, 30 ... operation unit, 31 ... controller, 32 ... Memory control, 33 ... DRAM, 34 ... Compression / decompression circuit, 35 ... Flash memory.

Claims (4)

A pixel unit that is arranged in a matrix and has a photoelectric conversion unit that photoelectrically converts received light;
A vertical charge transfer unit that transfers charges read from the pixel unit in the vertical direction;
The pixel unit and the vertical charge transfer unit are controlled so as to alternately perform the thinning readout for reading out the charges to the vertical charge transfer unit by thinning out from some pixel rows and the one-stage vertical transfer in the vertical charge transfer unit. that comprises a drive unit for an imaging device. The driving unit can adjust an exposure time by controlling a generation timing of a sub-pulse signal for sweeping away the electric charge accumulated in the photoelectric conversion unit.
The imaging device according to claim 1. The drive unit is
Adaptively switch the thinning readout mode for reading by thinning out the charge for each predetermined pixel row from the all-pixel reading mode and the all pixel rows for reading the charge from the all the pixel rows in response to a user's input operation
The imaging apparatus according to 請 Motomeko 1. A pixel unit that is arranged in a matrix and has a photoelectric conversion unit that photoelectrically converts received light;
A vertical charge transfer unit that transfers charges read from the pixel unit in the vertical direction;
The pixel unit and the vertical charge transfer unit are controlled so as to alternately perform the thinning readout for reading out the charges to the vertical charge transfer unit by thinning out from some pixel rows and the one-stage vertical transfer in the vertical charge transfer unit. Method for driving a solid-state imaging device.

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