JP2008103992A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the operation speed of a solid-state imaging apparatus having an AD converter circuit for each column without increasing the operation speed of the AD converter circuits themselves. <P>SOLUTION: The solid-state imaging apparatus comprises: a plurality of pixel circuits 30 which are arranged in a matrix form and perform photoelectric conversion individually; a plurality of AD converter circuits 16 and 17 which are arranged on respective columns and convert analog signals obtained by photoelectric conversion by the pixel circuits in each column into digital signals; a plurality of data buses 19 and 20 for transmitting the plurality of digital signals independently; a plurality of switches 27 which are installed in correspondence with respective AD converter circuits and connect the output of the corresponding AD converter circuit and one of the data buses; and a horizontal scanning circuit 18 which transmits the digital signals in parallel by the plurality of data buses by supplying a selection signal 33 for simultaneously turning the plurality of switches on to those switches connected to the different data buses. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging system, and in particular, a MOS-type solid-state imaging device capable of high-speed operation including one or more analog-digital conversion circuits (ADC) in each column of a matrix in which a plurality of pixel circuits are arranged The present invention also relates to an imaging system using such a solid-state imaging device.

  In recent years, in a MOS type solid-state imaging device, a configuration including an ADC for each column has been proposed for speeding up.

  The MOS type solid-state imaging device having this configuration includes a pixel unit in which pixel circuits including a photoelectric conversion unit are arranged in a matrix, and an ADC provided in two or more in each column of the array. The output from a plurality of pixel circuits is processed in parallel by the two or more ADCs, so that the operation speed can be increased. Furthermore, a method has been proposed in which a plurality of vertical signal lines are provided in each column, and signals are taken out from a plurality of pixel circuits at the same time to further increase the speed.

  Hereinafter, a MOS type solid-state imaging device provided with two ADCs for each column shown in Patent Document 1 will be described with reference to FIGS. 13, 14, 15, and 16.

  FIG. 13 is a diagram showing a basic circuit configuration of a conventional solid-state imaging device. In the figure, for the sake of simplification, description is made using a pixel portion 100 including pixel circuits 101 arranged in 3 rows and 3 columns.

  The outputs of the pixel circuits 101 in one column are connected to, for example, correlated double sampling circuits (hereinafter referred to as CDS) 102a and 102b through a common vertical signal line 107. The analog output from the pixel circuit in the row selected according to the readout signal from the vertical scanning circuit 105 is sampled by the CDSs 102 a and 102 b through the vertical signal line 107.

  Next, the analog signals sampled by the CDSs 102a and 102b in the columns are converted into digital signals by the ADCs 103a and 103b in the columns, respectively. The converted digital signals are sequentially output to the outside via the data buses 106a and 106b for each column in response to the selection signals from the horizontal scanning circuits 104a and 104b. Since the converted digital signal is transmitted, high-speed operation can be performed.

  FIG. 14 is a diagram for explaining the operation of the conventional solid-state imaging device. FIG. 14 shows two columns of the solid-state imaging device of FIG. When a readout signal is supplied from the vertical scanning circuit 105 to a pixel circuit in one row, a switch such as a MOS (Metal Oxide Semiconductor) transistor of the CDS 102a on the lower side of each column is controlled to be turned on. As a result, the CDS 102a An analog signal from the pixel circuit in that row is sampled. Further, when a readout signal is supplied to the pixel circuit in another row, similarly, the analog signal from the pixel circuit in that row is sampled by the CDS 102b on the upper side of each column.

  In this way, analog signals from pixel circuits in different rows are divided up and down and converted into digital signals by the ADCs 103a and 103b, respectively.

  FIG. 15 is a timing chart for explaining the operation timing. Each of the two bands indicates a time when a series of operations related to different rows, that is, analog signal readout from the pixel circuit, noise removal by CDS, analog-digital conversion of the signal by ADC, and output of the converted digital signal are performed. Show. The right direction of the drawing corresponds to the passage of time.

  Since there is only one vertical signal line 107 in each column, the read operation is sequentially processed for each row, but the other operations are executed in parallel for two rows by double CDS, ADC, and data bus. It is possible, so that high speed operation is possible.

  In order to further increase the speed, the solid-state imaging device shown in FIG. 16 is provided with two vertical signal lines 107a and 107b in each column. The vertical signal line 107a connects the output of the odd-numbered pixel circuit and the CDS 102a, and the vertical signal line 107b connects the output of the even-numbered pixel circuit and the CDS 102b. The vertical scanning circuit 105 supplies readout signals simultaneously to one odd-numbered pixel circuit and one even-numbered pixel circuit.

According to this configuration, since all the operations for two rows including the reading of the analog signal from the pixel circuit can be executed simultaneously, the operation speed can be further increased.
JP 2005-347932 A

  Although the conventional solid-state imaging device has a certain effect on the speeding up of the operation as described above, the demand for the high-speed operation of the solid-state imaging device is expected to further increase in the future as the number of pixels increases. Is done. However, it is difficult to meet such a demand only with the conventional technology.

  In order to achieve even higher speeds, for example, it is conceivable to use a technique such as increasing the operating speed of the ADC, but it is easy to realize an ADC that operates at high speed while maintaining conversion accuracy and stability. is not.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a two-dimensional solid-state imaging device capable of operating at a higher speed than before without increasing the operating speed of the ADC.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a pixel unit in which a plurality of pixel circuits each performing photoelectric conversion are arranged in a matrix, and each column includes a pixel circuit. Corresponding to each of the plurality of conversion circuits for converting the analog signals obtained by photoelectric conversion into digital signals, the plurality of data buses for independently transmitting the plurality of digital signals, and the plurality of conversion circuits, respectively. By providing a plurality of switches that connect the output of the corresponding conversion circuit and one of the data buses, and supply a selection signal that simultaneously turns on the plurality of switches that are connected to different data buses A horizontal scanning circuit for transmitting the digital signals in parallel through the plurality of data buses.

  According to this configuration, since digital signals obtained in a plurality of columns can be transmitted in parallel on different data buses, the time required for digital signal transmission is reduced, and solid-state imaging capable of operating at higher speed than before A device can be realized.

  The first switch in each column of the left portion of the switches is divided into the output of the corresponding conversion circuit and one of the switches obtained by dividing the pixel portion into two parts in the column direction. A second switch in each column of the right portion of the switches connects an output of a corresponding conversion circuit and another common data bus, and the horizontal scanning circuit May supply a selection signal for simultaneously turning on one of the first switches and one of the second switches.

  According to this configuration, since only one set of data buses is provided in each of the left part and the right part, the area of the data bus on the semiconductor chip can be suppressed.

  The first switch in each odd column among the switches connects the output of the corresponding conversion circuit and one common data bus, and the second switch in each even column among the switches corresponds. The output of the conversion circuit is connected to another common data bus, and the horizontal scanning circuit simultaneously turns on one of the first switch and one of the second switch adjacent to each other. A selection signal may be supplied.

  According to this configuration, digital signals obtained in two adjacent columns are simultaneously output via different data buses. For example, when each pixel circuit is provided with a Bayer color filter, digital signals related to different colors can be obtained at the same time, so there is no need to provide an external circuit for rearranging data. Useful for realizing an imaging system.

  In addition, a plurality of sets of the plurality of data buses are provided, a plurality of the conversion circuits are provided in each column, and a plurality of conversion circuits in each column independently provide analog signals obtained by pixel circuits in different rows of the column. The switches corresponding to the different conversion circuits in the same column connect the output of the corresponding conversion circuit and one of the data buses of a different set, and the horizontal scanning circuit is connected to the data bus. For each set, a plurality of switches connected to one set of different data buses may be supplied with a selection signal for simultaneously turning them on, so that the digital signals may be transmitted through a plurality of sets of the data buses. Good.

  The solid-state imaging device is further provided with a first vertical signal line provided in each column, connecting each pixel circuit in an odd row of the column and one of the plurality of conversion circuits in the column, and each column. And a second vertical signal line connecting each pixel circuit in the even-numbered row of the column and the other one of the plurality of conversion circuits in the column, the plurality of conversion circuits including the first conversion circuit The analog signal transmitted through the vertical signal line and the analog signal transmitted through the second vertical signal line are each converted into a digital signal in parallel, and the horizontal scanning circuit simultaneously selects the data bus for each set of the data buses. By supplying signals, the digital signals may be transmitted in parallel through a plurality of sets of the data buses.

  The solid-state imaging device may further include a pixel circuit divided into two in the row direction, each having an upper portion and a lower portion, and provided in each column, and a pixel circuit in each row in the upper portion of the column And a first vertical signal line connecting each of the plurality of conversion circuits in the column, a pixel circuit provided in each column and in each row in the lower portion of the column, and the plurality of conversion circuits in the column A second vertical signal line for connecting to the other one, and the plurality of conversion circuits each receive an analog signal transmitted by the first vertical signal line and an analog signal transmitted by the second vertical signal line, respectively. In parallel, the signals are converted into digital signals, and the horizontal scanning circuit simultaneously supplies the selection signals to each set of the data buses so that the digital signals are transmitted in parallel on a plurality of sets of the data buses. Even .

  According to these configurations, processing of analog signals obtained by a plurality of pixel circuits in one column can be executed completely simultaneously including reading from the pixel circuits, so that a solid-state imaging device that operates at higher speed can be obtained. can get.

  Further, by making the conversion circuit a single slope integration type analog-digital conversion circuit, a high-performance conversion circuit with a simple circuit configuration can be realized.

  Furthermore, a solid-state imaging device with less noise can be realized by providing a noise removal circuit provided in each column and connected between the pixel circuit and the conversion circuit in that column.

  In addition, the present invention can be realized not only as a solid-state imaging device but also as an imaging system including the solid-state imaging device as described above.

  According to the solid-state imaging device according to the present invention, digital signals obtained in a plurality of columns can be transmitted in parallel on different data buses, so that the time required for transmitting the digital signals is shortened. As a result, a solid-state imaging device capable of operating at a higher speed than before can be realized without providing a high-speed ADC.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a basic circuit configuration of a solid-state imaging device 10 according to the present embodiment.

  In the present embodiment, an example of a solid-state imaging device including pixel circuits 30 arranged in 6 rows and 3 columns will be described for the sake of simplicity. For convenience of explanation, portions obtained by dividing a pixel portion in which the pixel circuits 30 are arranged into two in the column direction (that is, with a dividing line parallel to the column) are referred to as a left portion 11 and a right portion 12, respectively.

  The vertical scanning circuit 21 sequentially supplies a readout signal to the pixel circuit in the row for each row. An analog signal obtained as a result of photoelectric conversion in each pixel circuit in the row to which the readout signal is given is input to the CDSs 14 and 15. The conversion control circuit 28 outputs a control signal for analog-digital conversion, and the ADCs 16 and 17 for each column convert the analog signal of each column into a digital signal according to the control signal.

  The horizontal scanning circuit 18 sequentially outputs selection signals of half the number of columns one by one and supplies one selection signal to one column in the left portion 11 and one column in the right portion 12 simultaneously. The digital signal of the column of the left portion 11 supplied with the selection signal is output to the data bus 19, and the digital signal of the column of the right portion 12 supplied with the selection signal is output to the data bus 20.

  As a result, the time required for transmitting the digital signals of all the columns is half as compared with the case of transferring and outputting using one data bus as in the prior art, and the operation speed can be increased.

  Here, since the signal for each column is transmitted after being converted into a digital signal, the data can be easily handled. That is, signal degradation during high-speed transfer is unlikely to occur, and even when data is transferred via a plurality of data buses, the influence of differences in characteristics between data buses (for example, parasitic capacitance of signal lines constituting the data bus) can be ignored. As a result, a merit is obtained in which signal variations between the data buses hardly occur.

  FIG. 2 is a diagram illustrating an example of a main part of the solid-state imaging device 10, and illustrates an example of a circuit configuration of the ADCs 16 and 17 and the data buses 19 and 20. FIG. 2 shows an example in which the ADCs 16 and 17 are single slope integration type analog-digital conversion circuits and the digital signal is represented by 3 bits for each of the ADCs 16 and 17.

  A portion corresponding to one column of the ADC 16 includes a comparator 22 which is an arithmetic unit, a transfer switch 25 including three MOS transistors whose gates are connected to the output side of the comparator 22, and three MOS transistors of the transfer switch 25. The memory 26 includes three capacitors connected to each other, and the read switch 27 includes three MOS transistors respectively connected to the three capacitors of the memory 26.

  The ADC 16 includes a similar circuit corresponding to each column of the left portion 11 of the pixel portion. The ADC 17 also includes a similar circuit corresponding to each column of the right portion 12 of the pixel portion.

  The conversion control circuit 28 supplies to the ADCs 16 and 17 via the signal lines 23 and 24 a single slope ramp signal and a count signal that counts a 3-bit value while the ramp signal rises or falls.

FIG. 3 is a diagram for explaining the operation of the solid-state imaging device 10.
When a readout signal is supplied from the vertical scanning circuit 21 to a pixel circuit in one row, the pixel circuit in that row outputs an analog signal obtained by photoelectric conversion to the vertical signal line 32 in each column. The CDSs 14 and 15 sample analog signals from the vertical signal lines 32 of each column and output them to the ADCs 16 and 17.

  Note that the CDS generally has a function of removing noise from an analog signal by sampling the analog signal. That is, the CDSs 14 and 15 are an example of a noise removal circuit.

  The CDSs 14 and 15 output the analog signals of the respective columns to the comparators 22 of the ADCs 16 and 17. The ADCs 16 and 17 convert the analog signal of each column into a digital signal according to the ramp wave signal and the count signal from the conversion control circuit 28, and store the converted digital signal in the memory 26.

The operation so far is performed simultaneously for all the columns in one row.
Next, the horizontal scanning circuit 18 supplies the selection signal 33 simultaneously to the readout switches 27 in one column of the ADCs 16 and 17 respectively. As a result, the digital signals converted in the two columns are simultaneously transmitted via the data buses 19 and 20, respectively.

  When the horizontal scanning circuit 18 sequentially supplies selection signals to two different columns, the digital signals of each column are output to the outside via the data buses 19 and 20 simultaneously for two columns. As a result, as shown in the timing chart of FIG. 4, the time required to transmit the digital signals of all the columns is halved compared to the case of transferring and outputting using one data bus as in the prior art. , It is possible to speed up the operation.

  Heretofore, an example in which a digital signal obtained in one column of the left portion 11 of the pixel portion and a digital signal obtained in one column of the right portion 12 are simultaneously transmitted through the data buses 19 and 20, respectively. Although described, the present invention is not limited to the case where the pixel portion is divided into two.

  For example, it is of course possible to further increase the number of divisions of the pixel portion to 3 and 4 and transmit a digital signal of one column from each divided portion simultaneously using the same number of data buses as the number of divisions. . In that case, it is possible to further increase the speed.

  In addition to simultaneously outputting the digital signal of the left portion 11 and the digital signal of the right portion 12 of the pixel portion, a modification in which the adjacent odd-numbered digital signal and even-numbered digital signal are simultaneously output may be considered. it can.

  FIG. 5 is a diagram illustrating a basic circuit configuration of a solid-state imaging device according to such a modification. Compared to the configuration of FIG. 1, the division of the left part 11 and the right part 12 of the pixel part is no longer taken into account, the ADC 16 and the data bus 19 process the signals of each odd column, and the ADC 17 and the data bus 20 are each even column. Modified to process the signal.

  In the configuration in which the pixel portion is divided into the left portion 11 and the right portion 12 as shown in FIG. 1, only the data bus 19 is routed through the left portion 11 and only the data bus 20 is routed through the right portion 12. By passing, the area occupied by the data bus on the semiconductor chip can be suppressed. This is useful for downsizing the semiconductor chip that realizes the solid-state imaging device.

  On the other hand, in the configuration according to this modification, digital signals obtained in two adjacent columns are simultaneously output via different data buses. For example, when each pixel circuit is provided with a Bayer color filter, digital signals related to different colors can be obtained at the same time, so there is no need to provide an external circuit for rearranging data. Useful for realizing an imaging system.

(Second Embodiment)
FIG. 6 is a diagram illustrating a basic circuit configuration of the solid-state imaging device according to the second embodiment.

  In response to the readout signal for each row from the vertical scanning circuit 21, analog signals from the pixel circuits in the odd rows are sampled by the CDSs 14a and 15a and converted into digital signals by the ADCs 16a and 17a. Further, analog signals from the pixel circuits in even rows are sampled by the CDSs 14b and 15b and converted into digital signals by the ADCs 16b and 17b.

  The horizontal scanning circuits 18a and 18b sequentially output selection signals of half the number of columns one by one, and use one selection signal for selecting digital signals of two columns.

  Odd-row digital signals are output by two columns via data buses 19a and 20a in accordance with control by horizontal scanning circuit 18a, and even-row digital signals are transmitted through data buses 19b and 20b according to control by horizontal scanning circuit 18b. Are output every two columns.

  As a result, the processing speed is increased by distributing the signals up and down, and the time for transferring and outputting the pixel signals of each row is halved compared to the conventional method, thereby further increasing the speed. Here, since the signal for each column is transmitted after being converted to a digital signal, the data can be easily handled. The specific merit in this case is as described in the first embodiment.

FIG. 7 is a diagram for explaining the operation of the solid-state imaging device according to the present embodiment.
When a readout signal is supplied from the vertical scanning circuit 21 to a pixel circuit in one odd row, the pixel circuit in that row outputs an analog signal obtained by photoelectric conversion to the vertical signal line 32 in each column, and the CDSs 14a and 15a. Samples an analog signal from the vertical signal line 32 of each column.

  Thereafter, when a readout signal is supplied from the vertical scanning circuit 21 to the pixel circuit of one even row, the pixel circuit of that row outputs an analog signal obtained by photoelectric conversion to the vertical signal line 32 of each column, The CDSs 14b and 15b sample analog signals from the vertical signal lines 32 in each column.

  The ADCs 16a and 17a convert the analog signals sampled by the CDSs 14a and 15a into digital signals. The converted digital signals are simultaneously transmitted through the data buses 19a and 20a for two columns in accordance with the selection signals simultaneously supplied to the two columns from the horizontal scanning circuit 18a, and are output to the outside.

  On the other hand, the ADCs 16b and 17b convert the analog signals sampled by the CDSs 14b and 15b into digital signals. The converted digital signals are simultaneously transmitted for two columns via the data buses 19b and 20b in accordance with selection signals simultaneously supplied to the two columns from the horizontal scanning circuit 18b, and are output to the outside.

  As a result, as shown in the timing chart of FIG. 8, the time required to transmit the digital signals of all the columns in each row is half that in the case of transferring and outputting using one data bus as in the conventional case. become.

  In addition, regarding a series of operations related to different rows, analog signal readout from the pixel circuit cannot be performed simultaneously, but noise removal by CDS, analog-to-digital conversion of the signal by ADC, and output of the converted digital signal are respectively duplexed. Since it can be executed in parallel by the CDS, ADC, and data bus, the operation can be significantly faster than in the first embodiment.

  As described in the first embodiment, the number of divisions of the pixel portion may be 3 or more, and digital signals in adjacent odd and even columns may be transmitted simultaneously.

(Third embodiment)
FIG. 9 is a diagram illustrating a basic circuit configuration of the solid-state imaging device according to the third embodiment.

  Compared with the solid-state imaging device shown in FIG. 6, the difference is that two vertical signal lines 32a and 32b are provided for each column.

  The vertical signal line 32a connects the output of each pixel circuit in the odd row and the CDS 14a, 15a, and the vertical signal line 32b connects the output of each pixel circuit in the even row and the CDS 14b, 15b. The vertical scanning circuit 21 supplies read signals to two adjacent rows simultaneously.

  According to this configuration, as shown in the timing chart of FIG. 10, all operations for two adjacent rows including the reading of the analog signal from the pixel circuit can be performed simultaneously, so that even higher speed operation is possible. Become.

  Further, a modification in which the vertical signal lines 32a and 32b provided in each column are respectively provided in the upper part and the lower part of the pixel portion can be considered. Here, the upper portion and the lower portion refer to a portion obtained by dividing the pixel portion into two in the row direction (that is, by a dividing line parallel to the row).

  FIG. 11 is a diagram illustrating a basic circuit configuration of a solid-state imaging device according to such a modification. Compared to the configuration of FIG. 9, the following points are different. That is, the vertical signal line 32a connects the output of the pixel circuit in each lower row of the pixel portion and the CDS 14a, 15a, and the vertical signal line 32b connects the output of the pixel circuit in each upper row of the pixel portion to the CDS 14b, 15b. The vertical scanning circuit 21 supplies a readout signal simultaneously to one row in the lower part and one row in the upper part.

  According to this configuration, only the vertical signal line 32a is passed through the lower part of the pixel portion, and only the vertical signal line 32b is passed through the upper part, thereby suppressing the area occupied by the vertical signal line on the semiconductor chip. be able to. Thereby, since the area occupied by the pixel circuit can be relatively large, it is useful for improving the aperture ratio which is one of the characteristics required for the solid-state imaging device.

(Fourth embodiment)
The present invention can be realized not only as the solid-state imaging device described so far, but also as a solid-state imaging system using such a solid-state imaging device.

  FIG. 12 is a block diagram illustrating an example of a functional configuration of a solid-state imaging system according to the fourth embodiment.

  This solid-state imaging system is a system for imaging a subject using the solid-state imaging device described so far, and includes a lens 51, a diaphragm 52, a solid-state imaging device 10, an overall control unit 53, a timing generation unit 54, and a signal processing unit 55. , A memory unit 56, an external I / F (Interface) 57, a recording medium I / F 58, and a recording medium 59.

  The lens 51 and the diaphragm 52 are an optical system that forms an object image on the solid-state imaging device 10. The solid-state imaging device 10 is the solid-state imaging device shown in FIG. 1, and outputs a digital signal of each pixel obtained by capturing a subject image to the signal processing unit 55. The digital signal is transmitted from the solid-state imaging device 10 to the signal processing unit 55 simultaneously for two pixels by two data buses.

  The signal processing unit 55 uses the memory unit 56 as a work memory to generate image data representing a subject image from the digital signal of each pixel.

  The overall control unit 53 comprehensively controls these operations. That is, by adjusting the lens 51 and the diaphragm 52 according to the spatial high-frequency component and light amount included in the subject image, a preferable focus and exposure are obtained, and the timing generator 54 is controlled to control the solid-state imaging device 10 and the signal processing. A timing signal for driving the unit 55 is generated.

  The generated image data is output from the external I / F 57 to an external device via, for example, a USB (Universal Serial Bus) cable or a wireless LAN (Local Area Network), and attached to the recording medium I / F 58. For example, it is stored in a recording medium 59 such as an SD (Secure Digital) memory card. The overall control unit also controls these operations.

  According to this configuration, since the digital signal of each pixel is simultaneously transmitted by two pixels from the solid-state imaging device 10 to the signal processing unit 55, the operation can be speeded up as described above.

  It is obvious that the solid-state imaging device 10 may use not only the solid-state imaging device shown in FIG. 1 but also other solid-state imaging devices described so far.

  As described above, the solid-state imaging device of the present invention has been described based on the embodiment, but the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

  The present invention is useful for a solid-state imaging device having an ADC for each column for speeding up, and can be used for a digital camera, a digital video camera, and the like that support moving images.

It is a figure which shows the basic circuit structure of the solid-state imaging device of the 1st Embodiment of this invention. It is a figure which shows an example of the principal part of the solid-state imaging device of the embodiment. It is a figure for demonstrating the operation | movement of the embodiment. It is a timing chart which shows the operation timing of the embodiment. It is a figure which shows the basic circuit structure of the solid-state imaging device which concerns on the modification of the embodiment. It is a figure which shows the basic circuit structure of the solid-state imaging device of the 2nd Embodiment of this invention. It is a figure for demonstrating the operation | movement of the embodiment. It is a timing chart which shows the operation timing of the embodiment. It is a figure which shows the basic circuit structure of the solid-state imaging device of the 3rd Embodiment of this invention. It is a timing chart which shows the operation timing of the embodiment. It is a figure which shows the basic circuit structure of the solid-state imaging device which concerns on the modification of the embodiment. It is a block diagram which shows an example of a functional structure of the solid-state imaging system of the 4th Embodiment of this invention. It is a figure which shows the basic circuit structure of the conventional solid-state imaging device. It is a figure for demonstrating operation | movement of the conventional solid-state imaging device. It is a timing chart which shows the operation timing of the conventional solid-state imaging device. It is a figure which shows the improved circuit structure of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Solid-state imaging device 11 Left part 12 Right part 14, 14a, 14b CDS
16, 16a, 16b, 17, 17a, 17b ADC
18, 18a, 18b Horizontal scanning circuit 19, 19a, 19b, 20, 20a, 20b Data bus 21 Vertical scanning circuit 22 Comparator 23, 24 Signal line 25 Transfer switch 26 Memory 27 Switch 28 Conversion control circuit 30 Pixel circuit 32, 32a , 32b Vertical signal line 33 Selection signal 51 Lens 52 Aperture 53 Overall control unit 54 Timing generation unit 55 Signal processing unit 56 Memory unit 57 External I / F
58 Recording medium I / F
59 Recording medium 100 Pixel unit 101 Pixel circuit 102a, 102b CDS
103a, 103b ADC
104a, 104b Horizontal scanning circuit 105 Vertical scanning circuit 106a, 106b Data bus 107, 107a, 107b Vertical signal line

Claims (9)

A pixel portion in which a plurality of pixel circuits each performing photoelectric conversion are arranged in a matrix;
A plurality of conversion circuits that are provided in each column and convert an analog signal obtained by photoelectric conversion in the pixel circuit of the column into a digital signal;
A plurality of data buses for independently transmitting a plurality of the digital signals;
A plurality of switches provided corresponding to each of the plurality of conversion circuits, and connecting the output of the corresponding conversion circuit and one of the data buses;
A horizontal scanning circuit for transmitting the digital signals in parallel on the plurality of data buses by supplying selection signals for simultaneously turning on the plurality of switches connected to different data buses. A solid-state imaging device. A portion formed by dividing the pixel portion into two in the column direction is defined as a left portion and a right portion, respectively.
The first switch in each column of the left portion of the switches connects the output of the corresponding conversion circuit and one common data bus,
The second switch in each column of the right portion of the switches connects the output of the corresponding conversion circuit and another common data bus,
The solid-state imaging device according to claim 1, wherein the horizontal scanning circuit supplies a selection signal for simultaneously turning on one of the first switch and one of the second switch. The first switch in each odd column among the switches connects the output of the corresponding conversion circuit and one common data bus,
The second switch in each even column of the switches connects the output of the corresponding converter circuit and another common data bus,
2. The solid-state imaging according to claim 1, wherein the horizontal scanning circuit supplies a selection signal for simultaneously turning on one of the first switch and one of the second switches adjacent to each other. apparatus. A plurality of sets of the plurality of data buses are provided,
A plurality of the conversion circuits are provided in each column,
The plurality of conversion circuits in each column independently convert the analog signals obtained by the pixel circuits in different rows of the column into digital signals,
The switches corresponding to different conversion circuits in the same column connect the output of the corresponding conversion circuit and one of the data buses of a different set,
The horizontal scanning circuit supplies a plurality of sets of the data buses by supplying a selection signal for simultaneously turning on the plurality of switches connected to one set of different data buses for each set of the data buses. The solid-state imaging device according to claim 1, wherein the digital signal is transmitted by a bus. The solid-state imaging device further includes:
A first vertical signal line provided in each column and connecting each pixel circuit in an odd row of the column and one of the plurality of conversion circuits in the column;
A second vertical signal line provided in each column and connecting each pixel circuit in an even row of the column and the other one of the plurality of conversion circuits in the column;
The plurality of conversion circuits convert an analog signal transmitted through the first vertical signal line and an analog signal transmitted through the second vertical signal line into digital signals in parallel,
5. The horizontal scanning circuit transmits the digital signals in parallel on a plurality of sets of data buses by supplying the selection signals simultaneously to each set of the data buses. The solid-state imaging device described. In the solid-state imaging device, the pixel unit is divided into two parts in a row direction, and an upper part and a lower part, respectively,
A first vertical signal line provided in each column and connecting a pixel circuit in each row of the upper portion of the column to one of the plurality of conversion circuits in the column;
A second vertical signal line provided in each column and connecting a pixel circuit in each row in the lower part of the column and the other one of the plurality of conversion circuits in the column;
The plurality of conversion circuits convert an analog signal transmitted through the first vertical signal line and an analog signal transmitted through the second vertical signal line into digital signals in parallel,
5. The horizontal scanning circuit transmits the digital signals in parallel on a plurality of sets of data buses by supplying the selection signals simultaneously to each set of the data buses. The solid-state imaging device described. The solid-state imaging device according to claim 1, wherein the conversion circuit is a single slope integration type analog-digital conversion circuit. The solid-state imaging device further includes:
The solid-state imaging device according to claim 1, further comprising a noise removal circuit provided in each column and connected between a pixel circuit and a conversion circuit in the column. A solid-state imaging device according to any one of claims 1 to 8,
An optical system for forming a subject image on the solid-state imaging device;
An imaging system comprising: a signal processing unit that processes an output signal from the solid-state imaging device.

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