JP6265872B2 - Semiconductor test apparatus and semiconductor test method - Google Patents

Description

The present invention relates to a semiconductor test apparatus and a semiconductor test method for a chip-like semiconductor device, and more particularly to an energization evaluation apparatus that applies a large direct current to a power semiconductor device as a semiconductor device.

  Evaluation of a semiconductor device is performed by using an electrode member such as a stage connected to a measuring instrument and a probe needle, and bringing the electrode member into contact with a surface electrode (upper surface electrode) of a chip-like semiconductor device placed on the stage. It is common.

  In recent years, the capacity of power semiconductor devices has been increasing, and the value of the energization current during testing has been increasing. However, in the evaluation method as described above, the surface electrode is destroyed when the heat treatment (measures) of the semiconductor device is not sufficient or the initial contact resistance in the surface of the surface electrode is not uniform during energization with a large current. There is a problem to do.

  As a semiconductor test apparatus for solving the above problems, for example, Patent Document 1 discloses a pressure contact type semiconductor apparatus having a structure in which a metal foil or powder metal is disposed between an electrode member and a semiconductor device.

JP 2006-337247 A

  However, in the above-described pressure contact type semiconductor device, a phenomenon such as a scratch on the surface electrode of the semiconductor device or an intrusion of powder metal occurs, and when the pressure between the semiconductor device and the electrode member is increased, the semiconductor device itself is destroyed. There was a problem of doing.

  The present invention has been made to solve the above-described problems, and can maintain good electrical contact with the electrodes of the semiconductor device from the initial stage of the energization process without adversely affecting the semiconductor device to be tested. An object is to obtain a semiconductor test apparatus.

According to a first aspect of the present invention, there is provided a semiconductor test apparatus for testing the semiconductor device by passing a current between one electrode and the other electrode in a semiconductor device having one electrode and the other electrode on one main surface and the other main surface. a semiconductor test apparatus, and placing the semiconductor device while electrically connected to the other electrode of said semiconductor device, a cooling plate having conductivity and cooling, that is provided on one electrode of said semiconductor device A laminated metal foil formed by laminating a plurality of partial metal foils, and a pressurizing portion that is disposed above one main surface of the semiconductor device, has a pressure surface facing the one main surface, and has conductivity, In operation, a direct current is applied between the cooling plate and the pressurizing unit, and a pressurizing mechanism that executes a pressurizing process that pressurizes the pressurizing unit in a first direction toward one main surface of the semiconductor device. The It characterized the Turkey and a current supply unit for executing to energization process.

The semiconductor test apparatus according to claim 5, wherein according to the present invention, among of claims 1 to 3, a semiconductor test apparatus according to any one, before asked pressure part, before Symbol pressure surface characterized in that it has a recess structure recessed in a second direction of the first direction and the opposite direction.

In the semiconductor test apparatus according to the first aspect of the present invention, at least a partial region in the edge region of the metal foil is disposed on the electrode exposed region.

  For this reason, during the pressure treatment of the present invention, a relatively small scratch that breaks through the natural oxide film formed on the surface of the one electrode of the semiconductor device by applying a concentrated load to the edge region of the metal foil. (Scratches at the level of natural oxide film destruction) can be applied to the surface of one electrode. As a result, it is possible to maintain a good electrical contact between the pressurizing part and the one electrode via the metal foil in a situation where the resistance value is uniform in the plane of the one electrode. The test accuracy can be improved.

  In addition, the scratches at the natural oxide film destruction level are scratches at a level that does not affect the semiconductor device at all, and thus do not adversely affect the semiconductor device to be tested during the energization process.

In the second aspect of the present invention, since the pressing surface of the pressing portion has the above-described concave structure, no load is applied to the protective film formation region on the electrode of the protective film during the pressing process. There is an effect of reliably avoiding the phenomenon of sometimes damaging the protective film.

It is explanatory drawing which shows the structure of the electricity supply evaluation apparatus which is Embodiment 1 of this invention. It is a perspective view which shows the structure of the pressurization plate shown in FIG. It is explanatory drawing which shows the structure of the semiconductor device shown in FIG. It is explanatory drawing which shows the structure (1st aspect) of the laminated metal foil shown in FIG. It is explanatory drawing which shows the structure of the electricity supply evaluation apparatus used as the modification of Embodiment 1. 6 is a top view showing a second mode of the laminated metal foil used in Embodiment 1. FIG. 6 is a top view showing a third aspect of the laminated metal foil used in Embodiment 1. FIG. 6 is a top view showing fourth to ninth aspects of the laminated metal foil used in Embodiment 1. FIG. It is a top view which shows the 10th-13th aspect of the laminated metal foil used in Embodiment 1. It is a top view which shows the 14th-16th aspect of the laminated metal foil used in Embodiment 1. It is a top view which shows the 17th-18th aspect of the laminated metal foil used in Embodiment 1. It is explanatory drawing which shows the 1st aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 2nd aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 3rd aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. 10 is a cross-sectional view schematically showing a back surface structure of a pressure plate in a fourth mode of Embodiment 2. FIG. It is explanatory drawing which shows the 5th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 6th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 7th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 8th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 9th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 10th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 11th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 12th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 13th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the 14th aspect of the pressurization board in the electricity supply evaluation apparatus of Embodiment 2. FIG. It is explanatory drawing which shows the structure of the electricity supply evaluation apparatus which is a 15th aspect of Embodiment 2. FIG.

<Embodiment 1>
(Electrification evaluation device)
FIG. 1 is an explanatory diagram showing the configuration of an energization evaluation apparatus according to Embodiment 1 of the present invention. As shown in the figure, a current-carrying evaluation apparatus 101, which is a semiconductor test apparatus, includes a cooling plate 2, a pressure plate 3, a pressure shaft 4, a current-carrying portion 8, a pressure plate holding plate 10, a shaft 11, a positioning plate 13, and a laminated metal. It consists of a foil 20 and a lower buffer plate 21.

  The semiconductor device 1 is an object to be evaluated (tested), and has a surface electrode (one electrode) and a back electrode (the other electrode) on at least the front surface (one main surface) and the back surface (the other main surface). As the semiconductor device 1, for example, a Schottky barrier diode or MOSFET using silicon carbide can be considered. With respect to such a semiconductor device 1, a direct current is passed between the front surface electrode and the back surface electrode of the semiconductor device 1 from the energizing portion 8 through the pressure plate 3 and the cooling plate 2 to evaluate the electrical characteristics of the semiconductor device 1. It is the energization evaluation apparatus 101 that does.

  The cooling plate 2 is provided on the back electrode side of the semiconductor device 1, and the semiconductor device 1 is placed so that the surface thereof is in contact with the back surface (including the back electrode) of the semiconductor device 1, and the electrode terminal P <b> 2 of the current-carrying unit 8. (A terminal to which one of the positive electrode and the negative electrode of the power source is connected). The cooling plate 2 has a cooling function for cooling the semiconductor device 1 from the back electrode when energized by the energization unit 8.

  The material of the cooling plate 2 may be a material having a high thermal conductivity such as a metal such as copper or aluminum or carbon and having conductivity. Further, a water channel may be provided inside the cooling plate 2 so that heat exchange can be performed by flowing a medium such as cooling water with a chiller or the like, or a surface in contact with the back surface of the semiconductor device 1 (upper surface in the figure). A structure that efficiently exchanges heat with air, such as a slit-like structure, may be provided on the back surface (the lower surface in the drawing) opposite to the surface, and heat exchange may be performed by flowing air or the like with a fan or the like.

  Further, the surface of the cooling plate 2 in contact with the back surface of the semiconductor device 1 is polished so as to make uniform contact with the chip-like semiconductor device 1 so that the surface roughness Ra is 5 μm or less, particularly 2 μm. The following is desirable.

  As shown in FIG. 1, a positioning plate 13 having an opening at the center is provided on the surface of the cooling plate 2 via a lower buffer plate 21. The positioning plate 13 has an opening so that the semiconductor device 1 can be placed at an appropriate position on the surface of the cooling plate 2. The lower buffer plate 21 is preferably a copper or aluminum plate having a thickness of 10 to 500 μm, gold, or an alloy containing these as main components.

  Therefore, the semiconductor device 1 can be placed on the surface of the cooling plate 2 while being positioned in the opening of the positioning plate 13 at the time of energization evaluation accompanying the energization process. On the surface of the semiconductor device 1, a laminated metal foil 20 formed by laminating a plurality of metal foils is provided.

  Further, the shaft 11 is erected on the surface of the cooling plate 2 through the through hole of the positioning plate 13. The shaft 11 is composed of at least four shafts. In FIG. 1, the shafts other than the two shafts 11 shown in the figure are hidden in the position in the direction perpendicular to the paper surface (the direction penetrating through the paper surface), and therefore are not shown (other drawings (FIG. 5 (a), FIG. 26) is also omitted). Hereinafter, for convenience of explanation, it is assumed that the four shafts 11 pass through the four through holes of the positioning plate 13 on the surface of the cooling plate 2 and are provided on the four vertices of a rectangular shape in plan view.

  The pressure plate holding plate 10 has a rectangular shape in plan view, and is attached to the four shafts 11 so that the four shafts 11 can move up and down by penetrating through the four shafts 11 through the four corners. Note that the vertical movement of the pressure plate holding plate 10 is realized by the vertical movement of the pressure shaft 4, and the pressure shaft 4 is provided so as to be pressurized at a constant pressure by a hydraulic jack or the like.

  The pressure plate holding plate 10 is represented by PEEK (polyetheretherketone) material, polyimide material, Teflon (registered trademark) material, and alumina in order to electrically insulate the cooling plate 2 from the pressure plate 3. All or part of an insulator such as ceramic.

  As described above, the pressure plate holding plate 10 is adjusted so that it can be easily moved up and down, and the pressure plate 3 is pressed against the semiconductor device 1 on the cooling plate 2 at a constant pressure via the pressure shaft 4. Can do.

  On the back surface of the pressure plate holding plate 10, the surface of the pressure plate 3 having a conductivity and cooling function and serving as a pressure unit is fixed, and the back surface of the pressure plate 3 becomes a pressure surface that pressurizes the semiconductor device 1 from the surface. .

  The surface roughness Ra of the pressing surface is desirably 2 μm or less so that the surface roughness Ra is 5 μm or less. In this way, by setting the surface roughness of the pressing surface to be low, it is possible to effectively suppress scratches (scratches having a level exceeding the natural oxide film destruction level described later) on the surface electrode 72 of the semiconductor device 1. Can do.

  As described above, the pressurizing shaft 4, the pressurizing plate holding plate 10, and the shaft 11 drive the pressurizing shaft 4 to change the pressurizing plate holding plate 10 attached to the four shafts 11 to the surface (surface) of the semiconductor device 1. It functions as a pressurizing mechanism that executes a pressurizing process for pressurizing the pressurizing plate 3 in a downward direction (including the electrodes) (first direction). That is, when the pressurization process is performed by the pressurization mechanism, the pressurization surface (the lower surface in FIG. 1) that is the back surface of the pressurization plate 3 presses the semiconductor device 1 from the surface through the laminated metal foil 20.

  In addition, you may employ | adopt the structure which turns upside down both the said pressurization mechanism and the semiconductor device 1, and pressurizes with the pressurization mechanism from the lower surface (surface) of the semiconductor device 1. FIG.

  Since both the pressure plate holding plate 10 and the positioning plate 13 are attached to the four shafts 11 at the through-holes, the pressure plate holding plate 10 and the positioning plate 13 are indirectly relative to each other via the four shafts 11. The target positional relationship is fixed.

  Note that the relative position between the positioning plate 13 and the cooling plate 2 may be determined by a method other than the method using the shaft 11. For example, the relative positional relationship between the pressure plate holding plate 10 and the positioning plate 13 and the cooling plate 2 is made constant by using a separately fixed robot arm without providing the shaft 11 and the pressure shaft 4. The pressing process may be executed by pressing downward. In this case, the robot arm and the pressure plate holding plate 10 constitute a pressure mechanism.

  The pressure plate 3 serving as a pressure unit is connected to the electrode terminal P <b> 3 of the energization unit 8. The electrode terminal P3 is a terminal connected to an electrode having a polarity opposite to that of the power supply electrode of the energization unit 8 to which the electrode terminal P2 is connected. Accordingly, the energization unit 8 functions as a current supply unit that allows a direct current to flow between the cooling plate 2 and the pressure plate 3.

  FIG. 2 is a perspective view showing the structure of the pressure plate 3. As shown in the figure, the pressure plate 3 has a rectangular parallelepiped structure in a plan view.

  The pressure plate 3 is electrically connected to the surface electrode of the semiconductor device 1 through the laminated metal foil 20 for energization of the semiconductor device 1. The material of the pressure plate 3 is preferably a metal such as aluminum, copper, SUS (stainless steel) or carbon. The pressure plate 3 desirably has a thickness of 1 mm or more in order to prevent deformation due to heat and load. When the material of the pressure plate 3 is copper, the pressure surface is desirably coated with a noble metal in order to suppress oxidation due to heat generation during energization.

  The laminated metal foil 20 is installed between the surface of the semiconductor device 1 and the pressure surface of the pressure plate 3. The laminated metal foil 20 is composed of one or more partial metal foils of copper or aluminum foil each having a thickness of 10 to 500 μm. Specifically, among the plurality of partial metal foils, the thickness of the device contact metal foil which is the lowermost partial metal foil in contact with the surface of the semiconductor device 1 is 50 μm or less, and other partial metals excluding the device contact metal foil The thickness of each foil (at least one partial metal foil) is preferably set to 100 μm or more. The reason why the thickness of one partial metal foil constituting the laminated metal foil 20 is 10 μm or more is that handling (handling) is difficult if it is less than 10 μm, and the reason why the thickness is 500 μm or less is that it is hard if it exceeds 500 μm. This is because a buffer effect cannot be expected.

  Thus, handling is facilitated by setting the thickness of each of the plurality of partial metal foils (at least one partial metal foil) forming the laminated metal foil 20 to 10 μm or more, and by setting the thickness to 500 μm or more. The buffer effect can be ensured.

  The reason why the laminated metal foil 20 is composed of a plurality of metal foils is that by allowing a side slip between the stacked partial metal foils, the level of the surface electrode of the semiconductor device 1 due to deformation of the plurality of partial metal foils during energization is increased. This is to reduce the phenomenon of scratches. In addition, the apparatus can be simplified by making the laminated metal foil 20 into a single structure of a piece of partial metal foil. “Laminated metal foil” is a name that assumes a laminated structure of a plurality of partial metal foils, but for convenience of explanation, it will be described as a metal foil including a single piece of partial metal foil.

  Note that the large-level scratch is a scratch having a level exceeding a scratch of a natural oxide film destruction level described later that does not adversely affect the semiconductor device 1, and has some influence on the semiconductor device 1 (first to third described later). Means a level of scratches that may cause adverse effects.

  Also, copper or aluminum foil is desirable as the material of the partial metal foil constituting the laminated metal foil 20, which is a metal having high electrical conductivity and the same or similar softness as that of general aluminum as the material of the surface electrode 32. Because.

  As described above, the energization evaluation apparatus 101 according to the first embodiment places the semiconductor device 1 on the surface side through the laminated metal foil 20 in which the pressing surface of the pressing plate 3 is composed of a plurality of partial metal foils during the pressing process. It is pressed from. At this time, by sandwiching a plurality of partial metal foils, a side slip between the partial metal foils becomes possible, and an effect of reducing the level of scratches generated on the surface of the surface electrode of the semiconductor device 1 during the pressure treatment can be achieved. .

  In addition, the pressing surface of the pressing plate 3 facing the surface of the semiconductor device 1 is electrically connected to the surface electrode of the semiconductor device 1 by contacting the surface electrode of the semiconductor device 1 through the laminated metal foil 20. The energization unit 8 allows a relatively large direct current to flow between the front surface electrode and the back surface electrode of the semiconductor device 1 via the cooling plate 2 and the pressure plate 3.

  Specifically, the laminated metal foil 20 is elastically deformed by pressurizing the laminated metal foil 20 with a pressure plate 3 having a relatively large pressure surface whose planar shape can sufficiently include the laminated metal foil 20 and the semiconductor device 1. Due to self-heating after partial contact and energization, the deformation of the laminated metal foil 20 proceeds, and stable energization can be performed between the front electrode and the back electrode in the semiconductor device 1.

  Further, by pressing the semiconductor device 1 with a pressure plate 3 having a pressure surface corresponding to the surface of the semiconductor device 1 instead of the probe needle, the semiconductor device is connected between the surface of the semiconductor device 1 and the pressure surface of the pressure plate 3. 1 is less likely to occur between the back surface of the cooling plate 2 and the surface of the cooling plate 2, the cooling efficiency from the cooling plate 2 and the pressure plate 3 can be increased.

  As described above, the energization evaluation apparatus 101 is evaluated because it performs stable energization between the front electrode and the back electrode of the semiconductor device 1 and can evaluate the electrical characteristics without adversely affecting the semiconductor device 1. The lifetime of the semiconductor device 1 and the yield can be improved.

In addition, although the range of the pressurization by the pressurizing shaft 4 is not particularly limited, when the semiconductor device 1 is a SiC device, in order to bring the cooling plate 2 and the pressurizing plate 3 into contact with the back surface and the front surface of the semiconductor device 1 without gaps, It is desirable to apply a load of 30 kg weight or more per 1 cm ^2, and it is desirable to suppress the load to 60 kg weight or less per 1 cm ² of the area so as not to break the semiconductor device 1.

  Furthermore, the plurality of metal foils in the laminated metal foil 20 are made of aluminum or copper, which is a relatively soft metal having a high electrical conductivity, so that the surface electrode of the semiconductor device 1 at the time of performing the pressure treatment is used. The resulting large scratches can be further reduced.

  In addition, by setting the thickness of the partial metal foil other than the device contact metal foil in the laminated metal foil 20 to be relatively thick at 100 μm or more, the surface electrode of the semiconductor device, the pressure plate 3, The gap between them can be filled, and the adhesion between the front surface of the semiconductor device 1, the pressure plate 3, the back surface of the semiconductor device 1, and the cooling plate 2 is further improved, the specific resistance is lowered, and the cooling efficiency is improved. Can do.

  Further, by bringing a relatively thin device contact metal foil having a thickness of 50 μm or less present in the lowermost layer of the laminated metal foil 20 into contact with the surface electrode of the semiconductor device 1, another partial metal foil (at least one metal foil) ) Can be effectively suppressed, and the level of scratches on the surface of the surface electrode of the semiconductor device 1 can be further reduced.

(Semiconductor device)
3A and 3B are explanatory views showing the structure of the semiconductor device 1 shown in FIG. 1, wherein FIG. 3A is a top view and FIG. 3B is a cross-sectional view.

  As shown in the figure, the semiconductor device 1 includes a semiconductor substrate 70, a polyimide layer 71, a front surface electrode 72 and a back surface electrode 73. An operation circuit portion (not shown) is formed on the semiconductor substrate 70, a surface electrode 72 (one electrode) is formed on the surface (one main surface) of the semiconductor substrate 70, and a back electrode 73 is formed on the back surface. .

  Then, a polyimide layer 71 as a protective film is formed on the on-electrode polyimide forming region R12 which is an outer peripheral region of the surface electrode 72, and the polyimide layer 71 is a semiconductor which is an outer peripheral region of the semiconductor substrate 70 where the surface electrode 72 is not formed. It is formed to extend on the device outer peripheral region S2.

  Therefore, the surface region of the surface electrode 72 occupies most of the central area where the polyimide layer 71 is not formed and the on-electrode polyimide forming region R12 (electrode protective film forming region). It is classified as a surface electrode exposed region S1 (electrode exposed region). That is, the outer peripheral region formed around the central surface electrode exposed region S1 in the surface region of the surface electrode 72 is the on-electrode polyimide forming region R12. In addition, polyimide convex part area | region S12 has shown the area | region where the polyimide layer 71 protrudes from the surface of the surface electrode 72, and is formed.

(Laminated metal foil (first aspect))
FIG. 4 is an explanatory view showing the structure (first embodiment) of the laminated metal foil 20 shown in FIG. 1, wherein FIG. 4 (a) is a perspective view, FIG. 4 (b) is a top view, and FIG. Is a cross-sectional view.

  The laminated metal foil 20A shown in FIG. 4 corresponds to the laminated metal foil 20 shown in FIG. As shown in FIGS. 2A and 2B, a gate electrode 74 is selectively formed on a part of the semiconductor substrate 70 of the semiconductor device 1, and the surface electrode 72 is a semiconductor substrate 70 excluding the gate electrode 74. Formed on the main surface area of the surface. As shown in FIG. 4B, the gate electrode 74 is formed at the upper center in the figure independently of the surface electrode 72.

  The laminated metal foil 20A is characterized in that the planar shape is similar to that of the surface electrode 72 and fits in the surface electrode exposed region S1 in plan view. The shape of the laminated metal foil 20A shown in the figure is at least a part (one or more) of partial metals among one and a plurality of partial metal foils (at least one partial metal film) constituting the laminated metal foil 20A. It suffices for the foil to have the planar shape shown in the figure. The same applies to the laminated metal foils 20B, 201 to 210, 221 to 223, and 231 to 233 described below.

  The polyimide layer 71 is formed on the semiconductor substrate 70 in the on-electrode polyimide forming region R12, the semiconductor device outer peripheral region S2, and the peripheral region of the gate electrode 74.

  The energization evaluation apparatus 101 according to the first embodiment has the structure shown in FIGS. 1 to 4, and the laminated metal foil 20 </ b> A has a shape that fits in the surface electrode exposed region S <b> 1 in a plan view, so At the time of execution, a load can be concentrated on the surface electrode exposed region S1 of the surface electrode 72 through the laminated metal foil 20A. Furthermore, in the energization evaluation apparatus 101 of the first embodiment, the edge region (outer peripheral edge portion) of the laminated metal foil 20A existing on the surface electrode exposed region S1 bites into the surface of the surface electrode 72, so that the semiconductor device 1 The natural oxide film can be destroyed by reliably scratching the surface of the surface electrode 72 (natural oxide film destruction level) so as to penetrate the natural oxide film formed on the surface of the surface electrode 72 (natural oxide film destruction effect). ).

  In addition, during the pressurizing process, the applied pressure under the laminated metal foil 20A is increased by an amount corresponding to the thickness of the laminated metal foil 20A, so that a load is intensively applied to the surface electrode exposed region S1 under the laminated metal foil 20A. Become. The scratch at the natural oxide film destruction level means a relatively small level of damage that destroys the natural oxide film without affecting the semiconductor device 1.

  Hereinafter, this point will be described in detail. There are mainly three scratches that affect the semiconductor device 1, one of which leads to a direct failure. The scratches reaching the interlayer insulating film such as MOSFET formed in the semiconductor device 1 are evaluated for electrical characteristics. As a result, gate leakage occurs (first adverse effect). The other is that the polyimide layer 71 which is a protective film is scratched, and the breakdown voltage as designed cannot be obtained (second adverse effect).

  The other is an indirect failure. When a module is assembled, a wire bond is provided on the surface electrode 72 after the end of the test by the energization process. However, the bond strength of the wire bonding is reduced due to a scratch on the surface of the surface electrode 72. This is a scratch that leads to damage of the semiconductor device 1 (third adverse effect).

  The scratch at the natural oxide film destruction level means a scratch that breaks the natural oxide film at most without giving the semiconductor device 1 the effects such as the first to third adverse effects described above.

  Therefore, the energization evaluation apparatus 101 according to the first embodiment has the surface of the surface electrode 72 without being affected by the natural oxide film formed with a non-uniform film thickness in the initial stage due to the natural oxide film destruction effect. In such a situation where the resistance value becomes uniform, good electrical contact between the pressure plate 3 and the surface electrode 72 via the laminated metal foil 20A can be maintained (uniform resistance value effect). As a result, the energization evaluation apparatus 101 can avoid a large current locally flowing in the surface electrode 72 and suppress welding of the surface electrode 72.

  As a result, it is possible to improve the test accuracy for the semiconductor device 1 by the energization evaluation apparatus 101 without damaging the semiconductor device 1 (effect of improving test accuracy).

  Furthermore, since the laminated metal foil 20A has a shape that fits in the surface electrode exposed region S1 in plan view, the semiconductor device 1 is loaded so as to avoid contact between the laminated metal foil 20A and the polyimide layer 71 that is a protective film. The effect of being able to perform the pressure treatment without damaging the polyimide layer 71 of the semiconductor device 1 because the surface of the surface electrode 72 can be surely attached to the surface of the surface electrode 72 by performing the pressure treatment. Play.

  When paying attention to the above effect, it is desirable that all of the multiple (at least one) partial metal foils constituting the laminated metal foil 20A have a shape that fits in the surface electrode exposed region S1 in plan view.

  The laminated metal foil 20 is installed between the surface electrode 72 of the semiconductor device 1 and the pressure plate 3. The reason for using the laminated metal foil 20 is based on the following first and second objects. In addition to obtaining the above-described effect, the first object is that the pressure surface of the pressure plate 3 and the surface electrode 72 of the semiconductor device 1 are not always flat as well. Further, by filling the laminated metal foil 20 as a buffer material, the contact resistance between the surface electrode 72 and the pressure plate 3 in the initial stage during the energization process is lowered, and a large current can be energized. The second object is to reduce damage to the stage and pressure plate 3 for the energization evaluation apparatus 101 when a semiconductor element constituting the semiconductor device 1 is broken, and to remove fragments and dust of the semiconductor element from the laminated metal foil. Adhering to 20 facilitates removal of debris, dust and the like. In addition, the laminated metal foil 20 itself is thermally expanded during the energization process, and the contact between the surface electrode 72 and the pressure plate 3 is further improved.

(Modification 1 (Electrification evaluation device))
FIG. 5 is an explanatory diagram showing a configuration of an energization evaluation apparatus 102 that is a modification of the first embodiment. FIG. 2A shows the overall configuration, and FIG. 2B shows the structure of the pressure pin. As shown in the figure, the modified example is characterized in that a cooling plate 2B is provided instead of the cooling plate 2 and a pressurizing unit 3B is provided instead of the pressurizing plate 3. For convenience of explanation, the energization unit 8 is not shown in FIG. 5 and FIG. 26 described later.

  As shown in FIG. 2A, in the cooling plate 2B in the energization evaluation apparatus 102, the region corresponding to the rear surface (the other main surface) of the semiconductor device 1 in plan view protrudes above the other region (semiconductor device 1 side). The cooling plate terrace structure 25 is provided. The positioning plate 13 is provided on the surface of the cooling plate 2B where the cooling plate terrace structure 25 is not formed.

  The pressure unit 3B includes a pressure base 83, a plurality of pressure pins 84, and a contact plate 85. Except for the structure other than the cooling plate 2B and the pressurizing unit 3B and the presence or absence of the lower buffer plate 21, it is the same as the energization evaluation apparatus 101 shown in FIG.

  The pressure base 83 is attached to the back surface of the pressure plate holding plate 10 and has an attachment surface 83s below (on the semiconductor device 1 side).

  The plurality of pressure pins 84 are formed to extend downward (toward the semiconductor device 1) from the attachment surface 83s of the pressure base 83, and each has a tip end portion 84b.

  As shown in FIG. 4B, each pressure pin 84 is composed of a shaft portion 84a and a tip portion 84b, and has a structure in which a tip portion 84b is provided at the lower end portion of the shaft portion 84a.

  The pressurizing pin 84 is preferably formed of stainless steel in order to withstand the pressurization of the pressurizing shaft 4. The surface is preferably coated with a noble metal such as gold.

  The plurality of pressure pins 84 each having the structure shown in FIG. 5 (b) are fixed to the pressure base 83 so that the end of the shaft portion 84a is installed on the mounting surface 83s and the front end portion 84b faces downward. Is done.

  Returning to FIG. 5A, the pressurizing part 3 </ b> B is provided below the tip parts 84 b of the plurality of pressurizing pins 84 (on the semiconductor device 1 side) and faces the tip parts 84 b of the plurality of pressurizing pins 84. It further has a contact plate 85 having a front surface and a back surface serving as a pressure surface.

  By pressing the surface of the contact plate 85 with the tip portions 84 b of the plurality of pressure pins 84 during the pressure treatment, the back surface of the contact plate 85 can be used as a pressure surface for the surface electrode of the semiconductor device 1. Note that the pressing surface of the contact plate 85 is provided in a region corresponding to the surface electrode exposure region S1 in the surface electrode 72 of the semiconductor device 1 in plan view.

  Although not shown in FIG. 5, the plurality of pressure pins 84 may be cooled by forced air cooling using a fan (not shown).

  In addition to the same effects as the energization evaluation apparatus 101, the energization evaluation apparatus 102 of the modified example having such a configuration has the following effects.

  The energization evaluation apparatus 102 is provided with the cooling plate 2B having the cooling plate terrace structure 25, thereby achieving a uniform in-plane temperature distribution of the semiconductor device 1. As a result, the energization evaluation for the semiconductor device 1 can be accurately performed at a desired set temperature. It can be carried out.

  The energization evaluation apparatus 102 is provided with a plurality of pressurization pins 84 between the pressurization base 83 and the contact plate 85, and therefore is in contact with the semiconductor device 1 via the metal foil 20 when energization is performed by the energization unit 8. When heat diffusion from the contact plate 85 occurs, the contact plate 85 can be held at a higher temperature because the thermal resistance of the contact plate 85 with the plurality of pressure pins 84 is high.

(Modification (laminated metal foil))
(Second aspect)
FIG. 6 is a top view showing a second mode of the laminated metal foil 20 used in the first embodiment. As shown in the figure, it is a laminated metal foil 20B of a second aspect configured in a ribbon shape extending in the vertical direction in the drawing. The laminated metal foil 20B is used as the laminated metal foil 20 of the energization evaluation apparatus 101 (102) shown in FIG. 1 (FIG. 5) in the second mode.

  As shown in FIG. 6, when using a ribbon-like laminated metal foil 20B suitable for mass production (or a part of at least one partial metal foil constituting the laminated metal foil 20B), the width direction of the laminated metal foil 20B is used. The length W20B of the side (at least one side of the straight line) is set to a length that fits within the surface electrode exposed region S1 of the surface electrode 72. Therefore, the left and right sides of the laminated metal foil 20B extending in the vertical direction in the drawing (sides adjacent to at least one side of the straight line) can be reliably disposed on the surface electrode exposed region S1, and therefore the left and right sides are When the load is applied more intensively to the edge region to be formed, the natural oxide film damage level can be scratched on the surface of the surface electrode 72 of the semiconductor device 1.

  As described above, the second mode of the first embodiment is such that the edge region of the laminated metal foil 20B existing on the surface electrode exposed region S1 of the surface electrode 72 (the left and right sides of the laminated metal foil 20B existing on the surface electrode 72). Due to the presence of the edge region, the uniform resistance value effect and the test accuracy improvement effect accompanying the natural oxide film destruction effect are exhibited.

(Third aspect)
FIG. 7 is a top view showing a third aspect of the laminated metal foil 20 used in the first embodiment. As shown in the figure, the laminated metal foil 20B and the two end metal foils 22 configured in a ribbon shape extending in the vertical direction in the figure are the third mode. In the second embodiment, the laminated metal foil 20B and the end metal foil 22 are used as the laminated metal foil 20 of the energization evaluation apparatus 101 (102) shown in FIG. 1 (FIG. 5).

  As shown in FIG. 7, when using a ribbon-like laminated metal foil 20B and two end metal foils 22 suitable for mass production, the width of the laminated metal foil 20B is the same as in the second embodiment shown in FIG. By setting the length W20B of the direction side (the least one side of the straight line) to be within the surface electrode exposed region S1 of the surface electrode 72, the scratches at the natural oxide film destruction level are obtained as in the second mode. Can be applied to the surface of the surface electrode 72 of the semiconductor device 1 to obtain the uniform resistance value effect and the test accuracy improvement effect.

  Furthermore, by providing two end metal foils 22 on the polyimide layer 71 in the semiconductor device outer peripheral region S2 at the left and right ends in the drawing, the semiconductor is interposed via the laminated metal foil 20B and the end metal foil 22 during the pressure treatment. A load is uniformly applied to the device 1, whereby heat can be evenly dissipated through the pressure plate 3, and the Ni precipitation phenomenon from the semiconductor device 1 due to insufficient heat dissipation can be suppressed.

  Further, by setting the film thickness and material of the two end metal foils 22 to a film thickness and material different from those of the laminated metal foil 20B, scratches on the surface of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 Reduction can be expected. In particular, the material of the end metal foil 22 may be softer than the laminated metal foil 20B provided in the central portion as long as it can withstand high temperatures, and may be polyimide, fluorine resin, silicon resin, or the like. .

(4th to 13th aspects)
FIG. 8 is a top view showing fourth to ninth aspects of the laminated metal foil. In FIG. 8, the structure of the semiconductor device 1 is the same as the structure shown in FIG.

  As shown in FIG. 5A, a metal foil 201A having a planar shape similar to the surface electrode exposed region S1 is disposed so as to be within the surface electrode exposed region S1 of the surface electrode 72, and the semiconductor device outer peripheral region S2 A metal foil 201B is formed on the outer peripheral region of the semiconductor device 1 of the semiconductor device 1 including the polyimide layer 71 formed thereon, and the metal foil 201A and the metal foil 201B are formed as shown in FIG. The fourth embodiment is used as the laminated metal foil 20. In the fourth aspect, all the edge regions of the metal foil 201A are present on the surface electrode exposed region S1.

  As shown in FIG. 4B, a rectangular planar metal foil 202A in which a part of the three sides and the upper side fits in the surface electrode exposed region S1 is disposed on the surface electrode 72, and the fourth mode and Similarly, in the fifth embodiment, the metal foil 202B is formed on the outer peripheral region of the semiconductor device 1, and the metal foil 202 composed of the metal foil 202A and the metal foil 202B is used as the laminated metal foil 20 of FIG. In the fifth aspect, three sides and a part of the upper side, which are the edge regions of the metal foil 202A, are present on the surface electrode exposed region S1.

  As shown in FIG. 6C, a metal foil 203 having a cross shape in plan view is provided, and the base portion 203r of the center point of the cross is arranged so as to be within the surface electrode exposed region S1 of the surface electrode 72. It is an aspect. In the sixth aspect, the edge regions of the four base portions 203r are present on the surface electrode exposed region S1. In addition, each tip part of the cross of the metal foil 203 is formed to extend outside the surface electrode exposed region S1 in plan view.

  As shown in FIG. 4D, the metal foil 204A has a planar shape similar to the surface electrode exposed region S1 and fits in the surface electrode exposed region S1 of the surface electrode 72, and the third and fourth aspects. Similarly, the metal foil 204B formed of the metal foil 204B disposed on the outer peripheral region of the semiconductor device 1 and the metal foil 204A that connects the metal foil 204A and the metal foil 204B at four locations is represented by the laminated metal foil 20 in FIG. The seventh embodiment is used as. In the seventh aspect, almost all the edge region of the metal foil 204A exists on the surface electrode exposed region S1.

  As shown in FIG. 4E, the metal foil 205A has a rectangular planar shape in which a part of the three sides and the upper side are accommodated in the surface electrode exposed region S1, and is disposed on the surface electrode 72, Similarly to the embodiment of FIG. 1, the metal foil 205B composed of the metal foil 205B disposed on the outer peripheral region of the semiconductor device 1 and the metal foil 205C that connects the metal foil 205A and the metal foil 205B at four positions is formed as shown in FIG. The eighth embodiment is used as the metal foil 20. In the eighth aspect, three sides and a part of the upper side, which are the edge regions of the metal foil 205A, are present on the surface electrode exposed region S1.

  As shown in FIG. 5 (f), a square metal foil 206 in plan view provided with four openings 206K corresponds to the surface electrode exposure region S1 in each of the four square openings 206K in plan view. In the ninth aspect, the metal foil 206 is used as the laminated metal foil 20 shown in FIG. In the ninth aspect, the corners on the center side of the semiconductor device 1 of each of the four openings 206K and the peripheral edge region thereof exist on the surface electrode exposed region S1.

  FIG. 9 is a top view showing tenth to thirteenth aspects of the laminated metal foil. In FIG. 9, the structure of the semiconductor device 1 is the same as the structure shown in FIG.

  As shown in FIG. 6A, a rectangular planar metal foil 207 is disposed on the surface electrode 72 so that a part of two sides (the upper side and the right side in the figure) are within the surface electrode exposed region S1. In the tenth embodiment, the metal foil 207 is used as the laminated metal foil 20 of FIG. In the tenth aspect, a part (edge region) of two sides (upper side and right side) of the metal foil 207 is present on the surface electrode exposed region S1.

  As shown in FIG. 6B, a metal foil 208 having a convex shape is provided in the upper part of the drawing in plan view, and the base portion 208r of the protrusion and a part of the lower side are on the surface electrode exposed region S1 of the surface electrode 72. In the eleventh aspect, the metal foil 208 is used as the laminated metal foil 20 shown in FIG. In the eleventh aspect, the two convex root portions 208r of the metal foil 208, the periphery thereof, and a part of the lower side are present on the surface electrode exposed region S1.

  As shown in FIG. 6C, a rectangular metal foil 209 in plan view is provided and arranged in an oblique direction in plan view so that a part of the two long side portions fits on the surface electrode exposed region S1 of the surface electrode 72. In the twelfth aspect, this metal foil 209 is used as the laminated metal foil 20 of FIG. In the twelfth aspect, some of the two long side portions of the metal foil 209 are present on the surface electrode exposed region S1.

  As shown in FIG. 1D, a metal foil 210 having an elliptical shape in plan view is provided, and the metal foil 210 is disposed so as to be within the surface electrode exposed region S1 of the surface electrode 72. The thirteenth aspect is used as the laminated metal foil 20. In the thirteenth aspect, all the edge regions of the metal foil 210 are present on the surface electrode exposed region S1.

  In the metal foils 201 to 210 according to the fourth to thirteenth aspects, at least a part of the edge region is present on the surface electrode exposed region S1 in at least a part of the partial metal foil (for example, the metal foil 201A). Therefore, the damage of the natural oxide film destruction level is given to the surface of the surface electrode 72 of the semiconductor device 1, and the uniform resistance value effect and the test accuracy improvement effect accompanying the natural oxide film destruction effect are exhibited. .

  Further, by forming at least a partial metal film other than the partial metal foil (for example, the metal foil 201B) on the semiconductor device outer peripheral region S2 of the semiconductor device 1, the pressure plate 3 can be removed during the pressure treatment. By dispersing this load, it is possible to suppress the phenomenon that the surface electrode 72 and the polyimide layer 71 of the semiconductor device 1 are damaged at a level exceeding the natural oxide film destruction level.

  As described above, the shape of the (laminated) metal foils 201 to 210 shown in FIGS. 8 and 9 does not have to be exhibited by all of the plurality of partial metal foils constituting the metal foils 201 to 210. In addition, if at least a part (one or more) of the partial metal foils of the plurality of partial metal foils (at least one partial metal film) exhibits the illustrated planar shape, the above effect can be exhibited.

(14th to 16th aspects)
FIG. 10 is a top view showing the fourteenth to sixteenth aspects of the metal foil. The (multilayer) metal foils 221 to 223 (metal foil with openings) of the fourteenth to sixteenth aspects correspond to the laminated metal foil 20 shown in FIG.

  In the metal foil 221 having a square shape in plan view provided with five openings 321, one of the five openings 321 having a circular shape in plan view is at the center and the other four are as shown in FIG. It is provided at a position where each vertex of the square is formed with the central opening 321 as the center. That is, the five openings 321 are arranged to form the fifth eye of the dice.

  In the fourteenth aspect, the metal foil 221 is arranged such that at least a part of the five openings 321 is positioned on the surface electrode exposed region S1 of the surface electrode 72. In the fourteenth aspect, at least a part of the opening 321 (edge part) of the five openings 321 in the metal foil 221 is present on the surface electrode exposed region S <b> 1 as an edge region of the metal foil 221.

  As shown in FIG. 5B, in the metal foil 222 having a square shape in plan view provided with five openings 322, the five rectangular openings 322 in plan view have the same shape as the five openings 321. , Arranged to form the fifth eye of the dice.

  In the fifteenth aspect, the metal foil 222 is arranged such that at least a part of the five openings 322 is located on the surface electrode exposed region S1 of the surface electrode 72. In the fifteenth aspect, at least a part of the five openings 322 in the metal foil 222 is formed on the surface electrode exposed region S <b> 1 as an edge region of the metal foil 222.

  As shown in FIG. 4C, in the metal foil 223 having a square shape in plan view provided with four openings 323, the four rectangular openings 323 in the plan view are equally long along the vertical direction in the figure. Arranged at intervals.

  In the sixteenth aspect, the metal foil 223 is arranged so that at least a part of the four openings 323 are positioned on the surface electrode exposed region S1 of the surface electrode 72. In the sixteenth aspect, at least a part of the four openings 323 in the metal foil 223 is formed on the surface electrode exposed region S <b> 1 as an edge region of the metal foil 223.

  The metal foils 221 to 223 (metal foils with openings) in the fourteenth to sixteenth aspects are arranged so that at least a part of the edge region forming the openings 321 to 323 is present on the surface electrode exposed region S1. Therefore, a load is concentrated on the end regions forming the openings 321 to 323, so that the natural oxide film damage level can be given to the surface of the surface electrode 72 of the semiconductor device 1.

(17th to 19th aspects)
FIG. 11 is an explanatory view showing the seventeenth to nineteenth aspects of the multilayer metal foil. The (multilayer) metal foils 231 to 233 (metal foil with embossing) of the seventeenth to nineteenth aspects correspond to the laminated metal foil 20 shown in FIG.

  As shown in FIG. 5A, in a metal foil 231 in a seventeenth aspect having a square shape in plan view, in which five embossments 331 are provided on the back surface, five linear embossments 331 each extending in the vertical direction in the drawing. Are evenly arranged in the horizontal direction.

  In the seventeenth aspect, the metal foil 231 is disposed so that at least a part of the five embosses 331 is positioned on the surface electrode exposed region S1 of the surface electrode 72. In the seventeenth aspect, at least a part of the five embosses 331 in the metal foil 231 exists on the surface electrode exposed region S1.

  As shown in FIG. 4B, in the metal foil 232 having a square shape in a plan view in which four embosses 332 are provided on the back surface, two linear embosses 332 extending in the vertical direction in the drawing and extending in the horizontal direction in the drawing. Two straight lines 322 are arranged so as to cross each other in the vicinity of the center.

  In the eighteenth aspect, the metal foil 232 is disposed so that at least a part of the four embosses 332 is positioned on the surface electrode exposed region S1 of the surface electrode 72. In the eighteenth aspect, at least a part of the four embosses 332 in the metal foil 232 exists on the surface electrode exposed region S1.

  As shown in FIG. 6C, in the metal foil 233 having a square shape in plan view in which twelve planar shapes are provided with a horizontally long oval shape on the back surface, the twelve embossed 333s are illustrated in units of three. Four embossed 333s arranged in the middle and vertical direction are arranged so as to be arranged in the horizontal direction.

  In the nineteenth aspect, the metal foil 233 is disposed so that at least a part of the twelve embosses 333 is located on the surface electrode exposed region S1 of the surface electrode 72. In the nineteenth aspect, at least a part of the twelve embosses 333 in the metal foil 233 is present on the surface electrode exposed region S1.

  The metal foils 231 to 223 (metal foil with emboss) in the seventeenth to nineteenth aspects are arranged so that at least a part of the embosses 331 to 333 exists on the surface electrode exposed region S1.

  Therefore, in the seventeenth to nineteenth aspects, by having the embossed portions (embossed 331 to 333), local plastic deformation of the embossed portions during the pressure treatment occurs, and the hardness of the deformed portion increases. By applying a concentrated load below the deformed portion, the natural oxide film damage level can be applied to the surface of the surface electrode 72 of the semiconductor device 1.

  When the semiconductor device 1 is actually used, the edge region (14th to 16th aspects) and the embossing in the openings 321 to 333 are performed in order to perform wire bonding such as aluminum on the surface electrode 72 after the test by the energization treatment. The formation positions (17th to 19th aspects) of the processed parts (embosses 331 to 333) are desirably patterns that avoid the positions of wire bonds.

  As described above, the shapes of the metal foils 221 to 223 and 231 to 233 shown in FIGS. 10 and 11 are one and a plurality of portions constituting the (laminated) metal foils 221 to 223 and 231 to 233. If at least a part (one or more) of partial metal foils of the metal foil (at least one partial metal film) has the illustrated planar shape, the above effect can be exhibited.

  Further, in the case of the seventeenth to nineteenth aspects, even when all the edge regions of the metal foils 231 to 233 are not disposed on the surface electrode exposed region S1, at least a part of the embosses 331 to 333 is exposed to the surface electrode. If it is arranged on the region S1, the above-described effects can be exhibited. That is, even if the entire shape of the metal foils 231 to 233 is formed in an arbitrary shape, the above effect is exhibited by satisfying the condition that at least a part of the embosses 331 to 333 is disposed on the surface electrode exposed region S1. be able to.

<Embodiment 2>
The overall configuration of the energization evaluation apparatus of the second embodiment is the same as that of the energization evaluation apparatus 101 shown in FIG. 1 or the energization evaluation apparatus 102 shown in FIG. 5, and the pressure plate 3 or the contact plate 85 of the pressure unit 3B is The second embodiment replaces the pressure plates 51 to 63 of the first to fourteenth aspects described below.

(First aspect)
FIG. 12 is an explanatory diagram showing a first mode of the pressure plate in the energization evaluation apparatus of the second embodiment. In FIG. 12, the structure of the semiconductor device 1 is the same as that of the first embodiment shown in FIG. (A) is a perspective view of the pressure plate 51 as viewed from the back side, (b) is a top view of the pressure plate 51, and (c) is a cross-sectional view taken along the line AA of FIG. (B). It is sectional drawing shown.

  As shown in the figure, in the pressing plate 51, a region corresponding to a plan view of the electrode inner region included in the front surface electrode 72 and the gate electrode 74 of the semiconductor device 1 on the back surface serving as the pressing surface is larger than that in the other region. It has a pressure plate terrace structure 41A that protrudes to one side (first direction). The surface (projection surface, lower surface) of the pressure plate terrace structure 41A becomes an electrode pressure surface that actually pressurizes the surface electrode 72 and the gate electrode 74 during the pressure treatment, and the electrode pressure surface that is the surface of the pressure plate terrace structure 41A is: The portion corresponding to the surface electrode 72 is accommodated in the surface electrode exposed region S1 in plan view, and the portion corresponding to the gate electrode 74 is accommodated in the surface exposed region of the gate electrode 74 in plan view.

  Therefore, the concave structure 41C is provided by the step between the back surface of the pressure plate 51 where the pressure plate terrace structure 41A is not formed and the pressure plate terrace structure 41A. In other words, the pressure plate 51 has an anti-pressurization direction (in a direction opposite to the pressurization direction) from the surface (lower surface) of the pressure plate terrace structure 41A serving as an electrode pressurization surface so that the polyimide layer 71 is not pressurized during the pressure treatment. It has a concave structure 41C that is recessed in the second direction.

  The step difference between the pressure plate terrace structure 41A and the concave structure 41C is preferably 10 μm or more.

  The pressure plate 51 according to the first aspect of the second embodiment has the concave plate structure 41C together with the pressure plate terrace structure 41A on the back surface, so that no load is applied to the polyimide layer 71 as a protective film during the pressure treatment. There is an effect of reliably avoiding the phenomenon of damaging the polyimide layer 71 when the device 1 is tested.

  In addition, since the surface (lower surface) of the pressure plate terrace structure 41A serving as the electrode pressure surface for the surface electrode 72 is arranged so as to be accommodated in the surface electrode exposed region S1 in plan view, the load is concentrated on the surface electrode 72. In addition, the edge region of the pressure plate terrace structure 41A bites into the surface of the surface electrode 72, whereby the surface of the surface electrode 72 can be damaged by the natural oxide film destruction level.

  This effect also applies to the relationship between the electrode pressing surface for the gate electrode 74 and the gate electrode 74. Hereinafter, for convenience of explanation, the electrode pressing surface for the surface electrode 72 occupying most of the area of the electrode pressing surface will be described as a representative.

  Accordingly, the natural oxide film formed on the surface of the surface electrode 72 is broken through (natural oxide film destruction effect), and the surface electrode 72 accompanying the destruction of the natural oxide film formed with a non-uniform film thickness in the initial stage during the energization process. In such a situation that the resistance value becomes uniform in the plane, good electrical contact between the pressure plate 51 and the surface electrode 72 can be maintained (uniform resistance value effect). As a result, it is possible to improve the test accuracy with respect to the semiconductor device by the energization evaluation apparatus (test accuracy improvement effect).

(Second aspect)
FIG. 13 is an explanatory view showing a second mode of the pressure plate in the energization evaluation apparatus of the second embodiment. In FIG. 13, the structure of the semiconductor device 1 is the same as that of the first embodiment shown in FIG. (A) is a perspective view of the pressure plate 52 as viewed from the back side, (b) is a top view of the pressure plate 52, and (c) is a cross-sectional view taken along the line BB of FIG. (B). It is sectional drawing shown.

  As shown in the figure, the pressurizing plate 52 has a region corresponding to a plan view of an electrode internal region (electrode exposed region) included in the surface electrode 72 and the gate electrode 74 of the semiconductor device 1 on the back surface serving as the pressurizing surface. A central terrace structure 42A protruding from the region toward the semiconductor device 1 side. The surface (lower surface) of the central terrace structure 42A becomes an electrode pressing surface for the surface electrode 72 and the gate electrode 74 during the pressing process. Therefore, the electrode pressing surface of the central terrace structure 42A for the surface electrode 72 is within the surface electrode exposed region S1 in plan view.

  Further, on the back surface of the pressure plate 52, the outer peripheral region has an outer peripheral terrace structure 42B protruding to the semiconductor device 1 side, like the central terrace structure 42A. This outer peripheral terrace structure 42B overlaps with a part of the polyimide layer 71 (part of the semiconductor device 1) formed on the semiconductor device outer peripheral region S2 without overlapping with the surface electrode exposed region S1 in plan view. .

  Therefore, the concave structure 42C is provided on the back surface of the pressure plate 52 where the central terrace structure 42A and the outer peripheral terrace structure 42B are not formed by a step between the central terrace structure 42A and the outer peripheral terrace structure 42B. That is, the pressing plate 52 is recessed from the surface (lower surface) of the central terrace structure 42A and the outer peripheral terrace structure 42B in the anti-pressing direction so that the polyimide layer 71 is not pressed during the pressing process. have.

  The step difference between the central terrace structure 42A and the outer peripheral terrace structure 42B and the concave structure 42C is preferably 10 μm or more. The concave structure 42C overlaps with the on-electrode polyimide forming region R12 (on-electrode protective film forming region) in plan view so as to avoid contact with the polyimide layer 71 protruding from the surface of the surface electrode 72. In order to ensure reliable avoidance of contact with the polyimide layer 71, it is desirable to overlap with the polyimide convex region S12 in plan view. The same necessity applies to the planar shapes of the recessed structures 43C to 49C and 30C to 34C in the pressure plates 53 to 63 according to third to fourteenth aspects described later.

  Since the pressure plate 52 of the second aspect of the second embodiment has the concave portion structure 42C together with the central terrace structure 42A and the outer peripheral terrace structure 42B on the back surface, no load is applied to the polyimide layer 71 during the pressure treatment, As a result, there is an effect of reliably avoiding the phenomenon of damaging the polyimide layer 71 during the test of the semiconductor device 1.

  Since the surface (lower surface) of the central terrace structure 42A serving as the electrode pressing surface for the surface electrode 72 is disposed so as to be accommodated in the surface electrode exposed region S1 in plan view, the natural terrace is formed in the same manner as in the first aspect. The uniform resistance value effect and the test accuracy improvement effect accompanying the oxide film destruction effect are exhibited.

  Furthermore, in the second aspect, a part of the semiconductor device outer peripheral region S2 where the surface electrode 72 is not formed is pressed by the surface (lower surface) of the outer peripheral terrace structure 42B that becomes the electrode peripheral pressurizing surface during the pressurizing process. Therefore, it is possible to form a cooling path from the semiconductor device outer peripheral region S2 via the pressure plate 3 and to suppress warping of the semiconductor device 1 as a result. As a result, a cooling function via the pressure plate 52 ( It is possible to improve the heat dissipation action.

(Third aspect)
FIG. 14 is an explanatory view showing a third mode of the pressure plate in the energization evaluation apparatus of the second embodiment. In FIG. 14, the structure of the semiconductor device 1 is the same as that of the first embodiment shown in FIG. The figure is a perspective view of the pressure plate 53 viewed from the back side.

  As shown in the figure, the pressure plate 53 has a central terrace structure 43A having substantially the same structure as the central terrace structure 42A of the second aspect on the back surface serving as the pressure surface. The surface (lower surface) of the central terrace structure 43A becomes an electrode pressing surface during the pressing process.

  Further, on the back surface of the pressure plate 53, the outer peripheral region has partial outer peripheral terrace structures 43B1 and 43B2 protruding to the semiconductor device 1 side in the same manner as the outer peripheral terrace structure 42B. The partial outer peripheral terrace structures 43B1 and 43B2 overlap with a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Therefore, the concave structure 43C is provided on the back surface of the pressure plate 53 where the central terrace structure 43A (and the partial outer peripheral terrace structures 43B1 and 43B2) is not formed by a step with the central terrace structure 43A. That is, the pressure plate 53 has a concave structure 43C that is recessed in the anti-pressurization direction from the surface (lower surface) of the central terrace structure 43A so that the polyimide layer 71 is not pressurized during the pressure treatment.

  Furthermore, two notch portions 43E are provided in each of the partial outer peripheral terrace structures 43B1 and 43B2 for securing an arrangement path for the metal foil 20B to be arranged along the horizontal direction in the drawing. Therefore, the ribbon-shaped multilayer metal foil 20B can be arranged with the direction from one side to the other of the pair of cutout portions 43E as the longitudinal direction. At this time, by making the width of the cutout portion 43E slightly larger than the width of the ribbon-like metal foil 20B, it is possible to avoid pressurization to the metal foil 20B by the partial outer peripheral terrace structures 43B1 and 43B2 during the pressurizing process. it can.

  Regarding the multilayer metal foil 20B, the third mode assumes a configuration in which one of the plurality of partial metal foils is formed in a ribbon shape like the multilayer metal foil 20B shown in FIG.

  Further, the step difference between the central terrace structure 43A and the partial outer peripheral terrace structures 43B1 and 43B2 and the concave structure 43C is desirably 10 μm or more.

  The pressure plate 53 according to the third aspect of the second embodiment has the concave portion structure 43C together with the central terrace structure 43A and the outer peripheral terrace structure 43B on the back surface, and therefore has the same effect as the second aspect shown in FIG. Both have the effect of making the ribbon-shaped metal foil 20B usable.

  In addition, the multilayer metal foil 20B (at least a part of the partial metal film) has at least a part of the edge region disposed on the surface electrode exposed region S1, so that the natural oxide film destruction level is damaged. An effect that can be applied to the surface of the surface electrode 72 of the semiconductor device 1 is further exhibited.

  The above effect is similarly achieved when the (laminated) metal foils 20A, 201-210, 221-223, 231-233 described in the first embodiment are used instead of the laminated metal foil 20B.

  In addition, by providing the concave structure 43C on the region where the polyimide layer 71 and the laminated metal foil 20B overlap, it is possible to avoid the polyimide layer 71 of the semiconductor device 1 from being damaged by the laminated metal foil 20B.

(Fourth aspect)
FIG. 15 is a cross-sectional view schematically showing the back surface structure of the pressure plate 50 in the fourth mode of the second embodiment.

  FIG. 5A shows a structure represented by a second mode consisting of a central terrace structure 40A, an outer peripheral terrace structure 40B, and a concave structure 40C. As described above, this structure is desirably 2 μm or less so that the surface roughness Ra is 5 μm or less.

  As shown in FIGS. 4B to 4C, in the fourth embodiment, the surface of the central terrace structure 40A is provided with uneven portions 26A to 26C, which are uneven processed cross sections. The center terrace structure 40A corresponds to the pressure plate terrace structure 41A of the first aspect and the center terrace structures 42A and 43A of the second and third aspects. Similar to the first to third aspects, the corresponding relationship also applies to the outer peripheral terrace structure 40B and the recess structure 40C.

  The concave / convex processing content may be a curved shape such as the concave / convex portion 26A shown in FIG. 4B, or the triangular shape of the concave / convex portion 26B shown in FIG. 4C, or the square of the concave / convex portion 26C shown in FIG. It may be in shape. Moreover, the structure which provides the uneven | corrugated | grooved parts 26A-26C in a part or all of the surface of 40 A of center part terrace structures can be considered. However, when there is a region where wire bonding or the like is performed on the surface electrode 72 of the semiconductor device 1, it is desirable that the portion corresponding to the region is not subjected to uneven processing.

  In the fourth aspect of the second embodiment, the surface electrode 72 has scratches at the level of natural oxide film destruction caused by the uneven portions 26A to 26C (uneven processed cross section) provided on at least a part of the surface of the central terrace structure 40A. There is an effect that can be applied to the surface.

(5th aspect)
FIG. 16 is an explanatory view showing a fifth mode of the pressure plate in the energization evaluation apparatus of the second embodiment. FIG. 4A is a perspective view of the inner pressure plate 54A viewed from the back side, FIG. 4B is a perspective view of the outer pressure plate 54B viewed from the back side, and FIG. It is the perspective view which looked at the pressure plate from the back side.

  As shown in the figure, the combination pressure plate 54 is constituted by a combination of an inner pressure plate 54A and an outer pressure plate 54B which are separated from each other.

  As shown in FIG. 5A, the inner pressure plate 54A is in plan view on the inner surface of the electrode included in the surface electrode 72 and the gate electrode 74 of the semiconductor device 1 on the back surface serving as the pressure surface, as in the second embodiment. The corresponding region has a central terrace structure 44A that protrudes toward the semiconductor device 1 from other regions.

  As shown in FIG. 4B, the outer pressure plate 54B has an outer peripheral terrace structure 44B that protrudes toward the semiconductor device 1 on the rear surface in the same manner as the outer peripheral region of the central terrace structure 44A. The outer peripheral terrace structure 44B overlaps a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Further, the outer pressure plate 54B has an accommodation opening 44K that can accommodate the inner pressure plate 54A therein.

  Therefore, as shown in FIG. 6C, the inner pressure plate 54A is accommodated in the accommodating opening 44K with the central terrace structure 44A side down, and the surface (upper surface) of the inner pressure plate 54A and the outer pressure plate 54B are accommodated. By forming a combined pressure plate 54 having a structure that matches the surface (upper surface), the formation height (in the drawing) of the surface (lower surface) of the central terrace structure 44A and the surface (lower surface) of the outer peripheral terrace structure 44B is obtained. The lower surface formation position) can be matched.

  As a result, in the back surface of the combined pressure plate 54, the region where the central terrace structure 44A on the back surface on the inner pressure plate 54A side and the outer peripheral terrace structure 44B on the back surface on the outer pressure plate 54B side are not formed. A recess structure 44C is provided by a step between 44A and the outer peripheral terrace structure 44B. That is, the combination pressure plate 54 has a concave structure 44C that is recessed in the anti-pressurization direction from the surface of the central terrace structure 44A and the outer peripheral terrace structure 44B so that the polyimide layer 71 is not pressurized during the pressure treatment. doing.

  The step difference between the central terrace structure 44A and the outer peripheral terrace structure 44B and the concave structure 44C is preferably 10 μm or more.

  Since the combination pressure plate 54 according to the fifth aspect of the second embodiment has the concave portion structure 44C together with the central terrace structure 44A and the outer peripheral terrace structure 44B on the back surface, no load is applied to the polyimide layer 71 during the pressure treatment. Therefore, there is an effect of reliably avoiding the phenomenon of damaging the polyimide layer 71 during the test of the semiconductor device 1.

  Since the surface (lower surface) of the central terrace structure 44A serving as the electrode pressing surface for the surface electrode 72 is disposed so as to be accommodated in the surface electrode exposed region S1 in a plan view, the natural terrace is the same as in the first aspect. The uniform resistance value effect and the test accuracy improvement effect accompanying the oxide film destruction effect are exhibited.

  Further, in the fifth aspect, since the outer surface terrace structure 44B whose surface (lower surface) is the electrode peripheral pressure surface is provided, as in the second aspect, the cooling function (heat radiation) via the combination pressure plate 54 is provided. (Action) can be improved.

  In addition, in the fifth aspect, a combination of an inner pressure plate 54A (first partial pressure portion) and an outer pressure plate 54B (second partial pressure portion) that can separate and independently combine the pressure plates 54 from each other. It is realized by. Accordingly, the inner pressure plate 54A and the outer pressure plate 54B can be manufactured independently, so that one or both of the inner pressure plate 54A and the outer pressure plate 54B can be replaced. A combination pressure plate 54 composed of a combination of the outer peripheral terrace structures 44B can be obtained relatively easily.

(Sixth aspect)
FIG. 17 is an explanatory view showing a sixth mode of the pressure plate in the energization evaluation apparatus of the second embodiment. 4A is a top view of the combination pressure plate 55, and FIG. 2B is a cross-sectional view taken along the line C-C in FIG.

  As shown in the figure, the combination pressure plate 55 is constituted by a combination of an inner pressure plate 55A and an outer pressure plate 55B which are separated from each other.

  The inner pressure plate 55A has a central surface in which a region corresponding to the electrode inner region included in the surface electrode 72 and the gate electrode 74 of the semiconductor device 1 on the back surface serving as a pressure surface protrudes toward the semiconductor device 1 from other regions. It has a partial terrace structure 45A.

  The outer pressurizing plate 55B has an outer peripheral terrace structure 45B that protrudes toward the semiconductor device 1 on the rear surface in the same manner as the outer peripheral region of the central terrace structure 45A. The outer peripheral terrace structure 45B overlaps with a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Further, the outer pressurizing plate 55B has an accommodation opening (not shown) capable of accommodating the inner pressurizing plate 55A therein, like the outer pressurizing plate 54B of the fifth aspect.

  Accordingly, as shown in FIG. 17, the inner side pressure plate 55A is accommodated in the accommodation opening of the outer pressure plate 55B with the central terrace structure 45A side down, and the surfaces (upper surfaces) of the inner pressure plate 55A and the outer pressure plate 55B. Can be made to coincide with each other so that the formation heights of the surface (lower surface) of the central terrace structure 45A and the surface (lower surface) of the outer peripheral terrace structure 45B can be matched.

  As a result, as shown in FIG. 5B, the central terrace structure 45A on the back surface on the inner pressure plate 55A side and the outer peripheral terrace structure 45B on the back surface on the outer pressure plate 55B side are formed on the back surface of the combined pressure plate 55. In the region that is not formed, a concave structure 45C is provided by a step between the central terrace structure 45A and the outer peripheral terrace structure 45B. That is, the combination pressure plate 55 has a concave structure 45C that is recessed in the anti-pressurization direction from the surface of the central terrace structure 45A and the outer peripheral terrace structure 45B so that the polyimide layer 71 is not pressurized during the pressure treatment. doing.

  The step difference between the central terrace structure 45A and the outer peripheral terrace structure 45B and the concave structure 45C is preferably 10 μm or more.

  Thus, according to the sixth aspect, the combined pressure plate 55 can realize a structure substantially equivalent to the combined pressure plate 54 of the fifth aspect in the structure before and after the combination, and the same effect as the fifth aspect Play.

(Seventh aspect)
FIG. 18 is an explanatory view showing a seventh mode of the pressure plate in the energization evaluation apparatus of the second embodiment. FIG. 4A is a top view of the combination pressure plate 56, and FIG. 4B is a cross-sectional view taken along the line DD of FIG.

  As shown in the figure, the combination pressure plate 56 is constituted by a combination of an inner pressure plate 56A and an outer pressure plate 56B which are separated from each other.

  The inner pressure plate 56A has a central surface in which the region corresponding to the electrode inner region included in the front surface electrode 72 and the gate electrode 74 of the semiconductor device 1 in plan view protrudes toward the semiconductor device 1 from other regions on the rear surface serving as the pressure surface. A partial terrace structure 46A is provided. Further, as shown in FIG. 5A, the inner pressure plate 56A has an upper layer extending region 46D formed in a cross shape in a plan view with the upper layer portion extending outward in the plan view.

  The outer pressurizing plate 56B has an outer peripheral terrace structure 46B that protrudes toward the semiconductor device 1 on the rear surface in the same manner as the outer peripheral region of the central terrace structure 46A. The outer peripheral terrace structure 46B overlaps with a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Further, the outer pressure plate 56B has a passage opening (not shown) for allowing the central terrace structure 46A to pass therethrough, and is provided with a lower layer remaining region 46R positioned below the upper layer extending region 46D. When obtaining the combined structure of the pressure plates 56, the four upper layer extending regions 46D of the inner pressure plate 56A can be supported by the four lower layer remaining regions 46R formed in a cross shape in plan view.

  Accordingly, as shown in FIG. 18, the inner side pressure plate 56A is passed through the passage opening of the outer side pressure plate 56B with the central terrace structure 46A side down, and the upper layer extending region 46D is disposed on the lower layer remaining region 46R. By doing so, the formation heights of the surface of the central terrace structure 46A and the surface of the outer peripheral terrace structure 46B can be made to coincide with each other with high accuracy.

  As a result, as shown in FIG. 4B, on the back surface of the combined pressure plate 56, a central terrace structure 46A on the back surface on the inner pressure plate 56A side and an outer peripheral terrace structure 46B on the back surface on the outer pressure plate 56B side are formed. In the area that has not been formed, the concave structure 46C is provided by a step between the central terrace structure 46A and the outer peripheral terrace structure 46B. That is, the combination pressure plate 56 is a concave structure that is recessed in the anti-pressurization direction from the surface (lower surface) of the central terrace structure 46A and the outer peripheral terrace structure 46B so that the polyimide layer 71 is not pressurized during the pressure treatment. 46C.

  The step difference between the central terrace structure 46A and the outer peripheral terrace structure 46B and the concave structure 46C is preferably 10 μm or more.

  Thus, according to the seventh aspect, the combined pressure plate 56 can obtain a structure substantially equivalent to the combined pressure plate 54 of the fifth aspect in the structure after the combination, and the same effect as the fifth aspect can be obtained. Play.

  In addition, in the seventh aspect, the four upper layer extending regions 46D can be set as pressure target regions by the pressurizing mechanism (the pressurizing unit 3B of the energization evaluation apparatus 102 shown in FIG. 5). There is further an effect that the inner pressure plate 56A and the outer pressure plate 56B can be evenly pressurized during processing.

(Eighth aspect)
FIG. 19 is an explanatory view showing an eighth mode of the pressure plate in the energization evaluation apparatus of the second embodiment. 4A is a top view of the combination pressure plate 57, and FIG. 2B is a cross-sectional view showing the EE cross section of FIG.

  As shown in the figure, the combination pressure plate 57 is constituted by a combination of an inner pressure plate 57A and an outer pressure plate 57B which are separated from each other.

  The inner pressure plate 57A has a central surface in which the area corresponding to the electrode internal area included in the surface electrode 72 and the gate electrode 74 of the semiconductor device 1 on the back surface serving as the pressure surface protrudes toward the semiconductor device 1 from the other areas. A partial terrace structure 47A is provided. Further, as shown in FIG. 6A, the inner pressure plate 57A has an upper layer extending region 47D formed by extending the upper layer portion in a deformed cross shape slightly shifted in the vertical direction and the horizontal direction in plan view. Have.

  The outer pressure plate 57B has an outer peripheral terrace structure 47B that protrudes toward the semiconductor device 1 on the rear surface in the same manner as the outer peripheral region of the central terrace structure 47A. The outer peripheral terrace structure 47B overlaps with a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Further, as in the seventh aspect, the outer pressure plate 57B has a passage opening for allowing the central terrace structure 47A to pass therethrough, and by providing a lower layer remaining region 47R located below the upper layer extending region 47D, When obtaining the combined structure of the combined pressure plates 57, the four upper layer extending regions 47D can be supported by the four lower layer remaining regions 47R formed in a deformed cross shape in plan view.

  Therefore, as shown in FIG. 19, the inner side pressure plate 57A is passed through the passage opening of the outer side pressure plate 57B with the central terrace structure 47A side down, and the upper layer extension region 47D is disposed on the lower layer remaining region 47R. By doing so, the formation heights of the surface (lower surface) of the central terrace structure 47A and the surface (lower surface) of the outer peripheral terrace structure 47B can be made to coincide with each other with high accuracy.

  As a result, as shown in FIG. 6B, the combination pressure plate 57 is formed from the surface (lower surface) of the central terrace structure 47A and the outer peripheral terrace structure 47B so that the polyimide layer 71 is not pressurized during the pressure treatment. In this case, the concave structure 47C is recessed in the anti-pressurizing direction.

  The step difference between the central terrace structure 47A, the outer peripheral terrace structure 47B, and the concave structure 47C is preferably 10 μm or more.

  Thus, according to the eighth aspect, the combined pressure plate 57 can obtain a structure substantially equivalent to the combined pressure plate 54 of the fifth aspect in the structure after the combination, and the same effect as the fifth aspect can be obtained. Play.

  In addition, in the eighth aspect, similar to the seventh aspect, the four upper layer extending areas 47D can be set as areas to be pressurized by the pressure mechanism, so that the inner pressure plate 57A and the outer pressure plate 57A can be added during the pressure treatment. There is further an effect that the pressure plate 57B can be evenly pressurized.

(Ninth aspect)
FIG. 20 is an explanatory view showing a ninth mode of the pressure plate in the energization evaluation apparatus of the second embodiment. 4A is a top view of the combination pressure plate 58, and FIG. 2B is a cross-sectional view showing the FF cross section of FIG.

  As shown in the figure, the combination pressure plate 58 is constituted by a combination of inner pressure plates 58A1 and 58A2 and an outer pressure plate 58B which are separated from each other.

  The inner pressure plate 58A is subdivided and includes an inner pressure plate 58A1 and an inner pressure plate 58A2.

  The inner pressure plate 58A2 is disposed outside the inner pressure plate 58A1 by accommodating the inner pressure plate 58A1 in the accommodation opening at the center. On the back surface, which is the pressure surface of the inner pressure plate 58A2, a region corresponding to the electrode inner region included in the surface electrode 72 and the gate electrode 74 of the semiconductor device 1 in plan view protrudes toward the semiconductor device 1 from other regions. It has a terrace structure 48A2. Further, the back surface of the inner pressure plate 58A1 becomes the central terrace structure 48A1 as it is.

  Therefore, the inner pressure plate 58A, which is a combined structure of the inner pressure plate 58A1 and the inner pressure plate 58A2, has a structure equivalent to the inner pressure plate 55A of the sixth aspect.

  The outer pressure plate 58B has an outer peripheral terrace structure 48B that protrudes toward the semiconductor device 1 on the rear surface, and has an outer peripheral area similar to the central terrace structures 48A1 and 48A2. The outer peripheral terrace structure 48B overlaps with a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Further, the outer pressurizing plate 58B has an accommodating opening capable of accommodating the inner pressurizing plate 58A therein, like the outer pressurizing plate 54B of the fifth aspect.

  Accordingly, as shown in FIG. 20, the inner side pressure plates 58A1 and 58A2 are accommodated in the accommodation opening of the outer pressure plate 58B with the central terrace structures 48A1 and 48A2 facing downward, and the inner pressure plates 58A1, 58A2 and the outer pressure plates are accommodated. By combining them so that the surfaces (upper surfaces) of 58B coincide with each other, the formation heights of the surfaces (lower surfaces) of the central terrace structures 48A1 and 48A2 and the surfaces (lower surfaces) of the outer peripheral terrace structures 48B can be matched.

  As a result, as shown in FIG. 5B, the combination pressure plate 58 is applied to the surface of the central terrace structure 48A2 and the outer peripheral terrace structure 48B so that the polyimide layer 71 is not pressurized during the pressure treatment. It has a recessed structure 48C recessed in the pressure direction.

  The step difference between the central terrace structures 48A1 and 48A2 and the outer peripheral terrace structure 48B and the concave structure 48C is preferably 10 μm or more.

  Thus, according to the ninth aspect, the combined pressure plate 58 can realize a structure substantially equivalent to the combined pressure plate 54 of the fifth aspect in the structure after the combination, and the same effect as the fifth aspect Play.

(Tenth aspect)
FIG. 21 is an explanatory view showing a tenth aspect of the pressure plate in the energization evaluation apparatus of the second embodiment. FIG. 5A is a top view of the combination pressure plate 59, and FIG. 5B is a cross-sectional view showing a GG cross section of FIG.

  As shown in the figure, the combination pressure plate 59 is constituted by a combination of an inner pressure plate 59A and an outer pressure plate 59B which are separated from each other.

  The inner pressure plate 59A has a central terrace structure 49A in which a region corresponding to a plan view of the electrode inner region included in the surface electrode 72 of the semiconductor device 1 on the back surface serving as the pressure surface protrudes from the other region to the semiconductor device 1 side. have. Further, the inner pressure plate 59A has a gate conductive region 59G in a region corresponding to a plan view at the center of the electrode inner region included in the gate electrode 74, and the gate conductive region 59G is made of the inner pressure plate 59A by an insulating material 59X. Insulation with other conductive regions (regions electrically connected to the surface electrode 72) is ensured.

  The outer pressurizing plate 59B has an outer peripheral terrace structure 49B that protrudes toward the semiconductor device 1 on the rear surface in the same manner as the outer peripheral region of the central terrace structure 49A. The outer peripheral terrace structure 49B overlaps with a part of the polyimide layer 71 formed on the semiconductor device outer peripheral region S2 in plan view.

  Further, the outer pressurizing plate 59B has an accommodation opening capable of accommodating the inner pressurizing plate 59A in the same manner as the outer pressurizing plate 54B of the fifth aspect.

  Therefore, as shown in FIG. 21, the inner side pressure plate 59A is accommodated in the accommodating opening of the outer pressure plate 59B with the central terrace structure 49A side down, and the surfaces (upper surfaces) of the inner pressure plate 59A and the outer pressure plate 59B. Can be made to coincide with each other in the formation height of the surface (lower surface) of the central terrace structure 49A and the surface (lower surface) of the outer peripheral terrace structure 49B.

  As a result, as shown in FIG. 5B, the combination pressure plate 59 is formed from the surface (lower surface) of the central terrace structure 49A and the outer terrace structure 49B so that the polyimide layer 71 is not pressurized during the pressure treatment. The concave structure 49C is recessed in the anti-pressurizing direction.

  The step difference between the central terrace structure 49A, the outer peripheral terrace structure 49B, and the concave structure 49C is preferably 10 μm or more.

  Thus, according to the tenth aspect, the combined pressure plate 59 can realize a structure substantially equivalent to the combined pressure plate 54 of the fifth aspect in the structure before and after the combination, and the same effect as the fifth aspect Play.

  In addition, the tenth aspect has an effect that a gate voltage can be applied to the gate electrode 74 through the gate conductive region 59G independently of the surface electrode 72 during the energization process.

(Eleventh aspect)
FIG. 22 is an explanatory view showing an eleventh aspect of the pressure plate in the energization evaluation apparatus of the second embodiment. FIG. 4A is a perspective view of the inner pressure plate 60A viewed from the back side, and FIG. 4B is a perspective view of the outer pressure plate 60B viewed from the back side.

  As shown in the figure, the combination pressure plate 60 is constituted by a combination of an inner pressure plate 60A and an outer pressure plate 60B which are separated from each other.

  As shown in FIG. 5A, the inner pressure plate 60A has a central terrace structure 30A having substantially the same structure as the central terrace structure 42A of the second aspect on the back surface serving as the pressure surface. The surface (lower surface) of the central terrace structure 30A becomes an electrode pressing surface during the pressing process.

  On the back surface of the outer pressure plate 60B, partial outer peripheral terrace structures 30B1 and 30B2 substantially equivalent to the partial outer peripheral terrace structures 43B1 and 43B2 of the third mode are provided.

  Further, the outer pressure plate 60B has an accommodation opening 30K that can accommodate the inner pressure plate 60A therein. Accordingly, the inner pressure plate 60A is accommodated in the accommodating opening 30K with the central terrace structure 30A side down, and the inner pressure plate 60A and the outer pressure plate 60B are combined so that the surfaces (upper surfaces) of the inner pressure plate 60A coincide with each other. The formation height of the surface (lower surface) of the partial terrace structure 30A and the surface (lower surface) of the outer peripheral terrace structure 30B can be matched.

  As a result, concave structures 30C1 and 30C2 are provided on the rear surface of the combined pressure plate 60 where the central terrace structure 30A (and the partial outer peripheral terrace structures 30B1 and 30B2) are not formed due to a step difference from the central terrace structure 30A. That is, the combination pressure plate 60 has the recessed structures 30C1 and 30C2 that are recessed in the anti-pressurizing direction from the surface of the central terrace structure 30A so that the polyimide layer 71 is not pressed during the pressing process.

  Furthermore, two notch portions 30E for securing the arrangement path of the laminated metal foil 20B (or at least one partial metal foil) along the horizontal direction in the drawing are provided in each of the partial outer peripheral terrace structures 30B1 and 30B2. Provided. Therefore, the ribbon-shaped laminated metal foil 20B can be arranged with the direction from one side to the other of the pair of cutout portions 30E as the longitudinal direction. At this time, by making the width of the cutout portion 30E slightly wider than the width of the ribbon-like laminated metal foil 20B, it is possible to avoid pressurization of the laminated metal foil 20B by the partial outer peripheral terrace structures 30B1 and 30B2 during the pressure treatment. Can do.

  The step difference between the central terrace structure 30A, the partial outer peripheral terrace structures 30B1 and 30B2, and the concave structure 30C is preferably 10 μm or more.

  Since the combination pressure plate 60 of the eleventh aspect of the second embodiment has the concave portion structure 30C together with the central terrace structure 30A and the outer peripheral terrace structure 30B on the back surface, the same effect as the second aspect shown in FIG. In addition to the effect, the ribbon-shaped laminated metal foil 20B can be used.

  In addition, the eleventh aspect is based on a combination of an inner pressure plate 60A (first partial pressure plate) and an outer pressure plate 60B (second partial pressure plate) that can separate and independently combine the pressure plates 60 from each other. Since this is realized, the combination pressure plate 60 composed of various combinations of the central terrace structure 30A and the outer peripheral terrace structure 30B can be obtained relatively easily as in the fifth to tenth aspects.

(Twelfth aspect)
FIG. 23 is an explanatory view showing a twelfth aspect of the pressure plate in the energization evaluation apparatus of the second embodiment. This figure is a perspective view of the combination pressure plate 61 viewed from the back side.

  As shown in the figure, the combination pressure plate 61 is the same as that of the fifth embodiment shown in FIG. 16 except that the cushioning material 81 is formed on the surface (lower surface) of the outer peripheral terrace structure 31B of the outer pressure plate 61B. A structure equivalent to the pressure plate 54 is exhibited.

  Accordingly, in relation to the fifth aspect, the inner pressure plate 61A is the inner pressure plate 54A, the outer pressure plate 61B is the outer pressure plate 54B, the central terrace structure 31A is the central terrace structure 44A, and the outer peripheral terrace structure. 31B corresponds to the outer peripheral terrace structure 44B, and the concave structure 31C corresponds to the concave structure 44C.

  The material of the buffer material 81 may be a soft material that can withstand high temperatures, such as polyimide, fluorine resin, silicon resin, PEEK material, Teflon material, and the like.

  The twelfth aspect of such a structure has the same effect as the fifth aspect, and the shock absorber 81 reduces the impact between the outer peripheral terrace structure 44B and the polyimide layer 71 of the semiconductor device during the pressure treatment. By doing so, the semiconductor device 1 can be protected.

(13th aspect)
FIG. 24 is an explanatory view showing a thirteenth aspect of the pressure plate in the energization evaluation apparatus of the second embodiment. This figure is a perspective view of the combination pressure plate 62 viewed from the back side.

  As shown in the figure, the combined pressure plate 62 is the eleventh embodiment shown in FIG. 22 except that the cushioning material 82 is formed on the surface (lower surface) of the partial outer peripheral terrace structure 32B1 and 32B2 of the outer pressure plate 62B. The combination pressure plate 60 is equivalent in structure.

  Therefore, in relation to the fifth aspect, the inner pressure plate 62A is the inner pressure plate 60A, the outer pressure plate 62B is the outer pressure plate 60B, the central terrace structure 32A is the central terrace structure 30A, and the partial outer peripheral terrace. The structures 32B1 and 32B2 correspond to the partial outer peripheral terrace structures 30B1 and 30B2, and the recessed structure 32C corresponds to the recessed structure 30C.

  The material of the buffer material 82 may be a soft material that can withstand high temperatures, such as polyimide, fluorine resin, silicon resin, PEEK material, Teflon material, and the like.

  The thirteenth aspect of such a structure has the same effects as the fifth and eleventh aspects, and the buffer layer 82 allows partial outer peripheral terrace structures 30B1 and 30B2 during pressure treatment to be applied to the polyimide layer of the semiconductor device. The semiconductor device 1 can be protected by alleviating the impact between 71.

(14th aspect)
FIG. 25 is an explanatory view showing a fourteenth aspect of the pressure plate in the energization evaluation apparatus of the second embodiment. This figure is a perspective view of the combination pressure plate 63 viewed from the back side.

  As shown in the figure, the combination pressure plate 63 has a structure equivalent to the combination pressure plate 54 of the fifth mode shown in FIG. 16 except that the upper metal foil 27 is further formed on the surface of the inner pressure plate 63A. Presents.

  Therefore, in relation to the fifth aspect, the inner pressure plate 63A is the inner pressure plate 54A, the outer pressure plate 63B is the outer pressure plate 54B, the central terrace structure 33A is the central terrace structure 44A, and the outer peripheral terrace structure. 33B corresponds to the outer peripheral terrace structure 44B, and the concave structure 33C corresponds to the concave structure 44C.

  The combined pressure plate 63 of the fourteenth aspect further forms the upper metal foil 27 on the surface of the inner pressure plate 63A, so that the highest portion of the inner pressure plate 63A (the surface of the upper metal foil 27) The film thickness can be made higher than the highest part of the outer pressure plate 63B (the surface of the outer pressure plate 63B). As a result, when a uniform pressing force is applied to the inner pressure plate 63A and the outer pressure plate 63B by a pressure mechanism (for example, the plurality of pressure pins 84 of the pressure unit 3B shown in FIG. 5) during the pressure treatment. However, the pressing force (load) by the central terrace structure 33A can be made larger than the pressing force by the outer peripheral terrace structure 33B.

  The fourteenth aspect of such a structure has the same effect as the fifth aspect, and the upper metal foil 27 makes the pressure applied by the central terrace structure 33A larger than the pressure applied by the outer peripheral terrace structure 33B. Thus, the applied pressure can be more concentrated on the surface electrode 72 and the gate electrode 74 of the semiconductor device 1.

  At this time, the energization evaluation apparatus can be realized using the inner pressure plate 63A and the outer pressure plate 63B having a structure equivalent to that of the fifth mode by the pressure mechanism using the upper metal foil 27 as the pressure adjusting member. Therefore, an increase in apparatus cost can be minimized.

  As described above, the fourteenth aspect is such that the center terrace structure 33A, which is the electrode pressing surface, has the surface by the pressure changing function of the pressing mechanism realized by providing the upper metal foil 27 on the surface of the inner pressing plate 63A. The semiconductor device 1 can be protected by reducing the pressure applied between the outer peripheral terrace structure 33B, which is the electrode peripheral pressure surface, and the semiconductor device 1 while reducing the contact resistance between the electrodes 72.

(15th aspect)
FIG. 26 is an explanatory diagram showing the configuration of the energization evaluation apparatus 103 according to the fifteenth aspect of the second embodiment. In the same figure, the point by which the pressurization part 3B was replaced by the pressurization part 3C differs from the electricity supply evaluation apparatus 102 shown in FIG.

  The contact plate 85 is a combination contact plate composed of an inner contact plate 85A and an outer contact plate 85B, and is any one of the combination pressure plates 54 to 63 of the fifth to fourteenth aspects shown in FIGS. It corresponds to. The inner contact plate 85A corresponds to any one of the inner pressure plates 54A to 63A, and the outer contact plate 85B corresponds to any one of the outer pressure plates 54B to 63B.

  As shown in the drawing, the shaft portion 84a of the pressure pin 84 is partially embedded in the pressure base 83 from the mounting surface 83s. The pressure base 83 has a shim (SIM) 28 formed in the uppermost layer in a region corresponding to the surface electrode 72 and the gate electrode 74 of the semiconductor device 1 in a plan view, that is, a region corresponding to the inner contact plate 85A.

  The shim 28 as the adjustment fastening part is preferably made of a rigid material such as stainless steel and has a thickness of about 1 μm to 100 μm.

  The lengths of the shaft portions 84a and the tip portions 84b of the plurality of pressure pins 84 are the same. Among the plurality of pressure pins 84, the outer contact plate 85 </ b> B, that is, a pin provided in a region corresponding to the semiconductor device outer peripheral region S <b> 2 is arranged such that the tip (base portion) of the shaft portion 84 a coincides with the surface of the pressure base 83. Embedded in. On the other hand, among the plurality of pressurizing pins 84, the tip of the shaft portion 84a of the inner contact plate 85A, that is, the pin provided at the position corresponding to the surface electrode exposed region S1 (and the electrode exposed region in the gate electrode 74) is shim 28. Embedded to reach.

  As a result, the tip 84b of the pressure pin 84 corresponding to the inner contact plate 85A has a height difference so that it is positioned lower by the thickness of the shim 28 than the pressure pin 84 corresponding to the outer contact plate 85B. Can be made.

  Since the other configuration is the same as that of the energization evaluation apparatus 102 shown in FIG. 5, the same reference numerals are given as appropriate and description thereof is omitted.

  The fifteenth aspect having such a structure has the same effects as those of the fifth to thirteenth aspects, and the shim 28 is provided in the pressure base 83 and the plurality of pressure pins 84 are provided with different heights. Due to the pressure mechanism, the pressure applied by the inner contact plate 85A (center terrace structure) is made larger than the pressure applied by the outer contact plate 85B (outer terrace structure) and applied to the surface electrode 72 and the gate electrode 74 of the semiconductor device 1. The pressure can be concentrated more.

  At this time, since it is not necessary to process the contact plate 85 at all, an increase in apparatus cost can be suppressed to a necessary minimum.

  Thus, in the fifteenth aspect, the electrode pressurization surface (the lower surface of the inner contact plate 85A), the surface electrode is provided by the pressurization changing function of the pressurization mechanism realized by incorporating the shim 28 in the pressurization base 83. The semiconductor device 1 can be protected by reducing the pressure applied between the electrode peripheral pressure surface (the lower surface of the outer contact plate 85B) and the semiconductor device 1 while reducing the contact resistance between the two.

<Others>
In the first embodiment, the metal foil constituting the laminated metal foil 20 (20A, 20B, 201-210, 221-223, 231-233) may be intentionally provided with an uneven structure. The presence of this uneven structure reduces the initial contact resistance of the energization process by reducing the resistance inside the laminated metal foil 20, and the surface of the surface electrode 72 has a large level by appropriately collapsing the uneven structure during the pressure treatment. The effect of reducing the phenomenon of scratches can be exhibited.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2, 2B Cooling plate, 3, 3B, 3C, 50-53 Pressure plate, 13 Positioning plate, 21 Lower buffer plate, 20, 20A, 20B, 201-210, 221-223, 231-233 (Lamination) ) Metal foil, 22 End metal foil, 27 Upper metal foil, 28 Shim, 54-63 Combination pressure plate, 54A-57A, 58A1, 58A2, 59A-63A Inner pressure plate, 54B-63B Outer pressure plate, 70 Semiconductor substrate , 71 Polyimide layer, 72 Front electrode, 73 Back electrode, 74 Gate electrode, 81, 82 Buffer material, 83 Pressure substrate, 84 Pressure pin, 85 Contact plate, 101-103 Current evaluation device, 331-333 Emboss.

Claims (13)

A semiconductor test apparatus for testing the semiconductor device by passing a current between one electrode and the other electrode in a semiconductor device having one electrode and the other electrode on one main surface and the other main surface,
Placing the semiconductor device while being electrically connected to the other electrode of the semiconductor device, and a cooling plate having conductivity and a cooling function;
Wherein Ru is provided on one electrode of the semiconductor device, the laminated metal foil made by stacking a plurality of partial metal foil,
A pressure part disposed above one main surface of the semiconductor device, having a pressure surface facing the one main surface, and having conductivity;
In operation, a pressurizing mechanism that executes a pressurizing process that pressurizes the pressurizing unit in a first direction toward one main surface of the semiconductor device;
It characterized the Turkey and a current supply unit for executing energization process applying a direct current between the pressing and the cooling plate,
Semiconductor test equipment. The semiconductor test apparatus according to claim 1 ,
The thickness of each of the plurality of partial metal foils is set in a range of 10 μm or more and 500 μm or less,
Semiconductor test equipment. A semiconductor test apparatus according to claim 1 or claim 2 , wherein
The material of each of the plurality of partial metal foils is aluminum, gold, copper, or an alloy mainly composed of at least one of aluminum, gold and copper,
Semiconductor test equipment. The semiconductor test apparatus according to any one of claims 1 to 3 ,
Wherein the plurality of partial metal foil, including embossed with a metal foil having embossments on the backside,
Semiconductor test equipment. The semiconductor test apparatus according to any one of claims 1 to 3,
Before asked pressure section is characterized by having the previous SL pressing surface and said first direction a recess structure recessed in a second direction opposite directions,
Semiconductor test equipment. The semiconductor test apparatus according to claim 5 ,
The pressurizing part has an electrode pressurizing surface, and the electrode pressurizing surface selectively has an uneven processing cross section,
Semiconductor test equipment. A semiconductor test apparatus for testing the semiconductor device by passing a current between one electrode and the other electrode in a semiconductor device having one electrode and the other electrode on one main surface and the other main surface,
Placing the semiconductor device while being electrically connected to the other electrode of the semiconductor device, and a cooling plate having conductivity and a cooling function;
A pressure part disposed above one main surface of the semiconductor device, having a pressure surface facing the one main surface, and having conductivity;
In operation, a pressurizing mechanism that executes a pressurizing process that pressurizes the pressurizing unit in a first direction toward one main surface of the semiconductor device;
A current supply unit that executes an energization process for passing a direct current between the cooling plate and the pressurizing unit;
The pressurizing part is
A first portion pressing with electric GokuKa pressure surface,
And a second portion pressing with a peripheral pressing surface electrodes,
It said first and second portions pressing are combined in a manner to form a recess structure,
Semiconductor test equipment. A semiconductor test apparatus for testing the semiconductor device by passing a current between one electrode and the other electrode in a semiconductor device having one electrode and the other electrode on one main surface and the other main surface,
Placing the semiconductor device while being electrically connected to the other electrode of the semiconductor device, and a cooling plate having conductivity and a cooling function;
A pressure part disposed above one main surface of the semiconductor device, having a pressure surface facing the one main surface, and having conductivity;
In operation, a pressurizing mechanism that executes a pressurizing process that pressurizes the pressurizing unit in a first direction toward one main surface of the semiconductor device;
A current supply unit that executes an energization process for passing a direct current between the cooling plate and the pressurizing unit;
The pressurizing part is
A first partial pressure unit having an electrode pressure surface;
A second partial pressure unit having an electrode peripheral pressure surface,
It further comprises a buffer material formed on the electrode peripheral pressure surface.
Semiconductor test equipment. The semiconductor test apparatus according to claim 7 ,
The pressure mechanism is
During the pressurizing process, the first and second partial pressurizing units are independently pressurized in the first direction, so that the pressure applied by the electrode pressurization surface is greater than the pressure applied by the electrode peripheral pressurization surface. Has a larger pressure change function,
Semiconductor test equipment. One electrode is provided on one main surface, the other electrode is provided on the other main surface, a protective film is formed on the outer peripheral region of the one electrode, and the protective film is formed in the surface region of the one electrode Placing the other electrode of the semiconductor device in which the region that is not defined as an electrode exposure region is placed on a cooling plate having conductivity and a cooling function, and electrically connecting the other electrode and the cooling plate;
Arranging the metal foil on the one electrode, and providing the at least part of the edge region of the metal foil on the electrode exposed region; and
The cooling plate is cooled, a pressurizing surface of a pressurizing unit having conductivity is disposed above the one main surface, and the pressurizing unit is applied in a first direction toward the one main surface by a pressurizing mechanism. A step of testing the semiconductor device by performing an energization process of passing a direct current between the one electrode and the other electrode while pressing,
Semiconductor test method . A semiconductor test method according to claim 10, wherein
The metal foil has a shape that fits in the electrode exposure region in plan view,
Semiconductor test method . A semiconductor test method according to claim 10 or 11, wherein
The metal foil is a laminated metal foil formed by laminating a plurality of partial metal foils.
Semiconductor test method . The semiconductor test method according to any one of claims 10 to 12,
The pressurizing portion has an electrode pressurizing surface, and the electrode pressurizing surface has a shape that fits in the electrode exposure region in plan view.
Semiconductor test method .

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