JP6257554B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor element having a channel region formed of a part of a semiconductor substrate and an electrode.

  Semiconductor devices include power semiconductor chips such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors). As a gate structure in these semiconductor chips, there are mainly a planar gate structure and a trench gate structure.

  Conventionally, for example, polycrystalline silicon has been used as a gate material in the trench gate structure. In recent years, a method using a refractory metal has been proposed to reduce the specific resistance of a trench gate. For example, according to Japanese Patent Laid-Open No. 2001-44435, a polycrystalline silicon layer as a buffer layer and a refractory metal are formed in a trench in a trench gate structure.

  In addition, a resistance element called a gate resistance may be connected to the gate. Conventionally, the gate resistor has been externally attached to the semiconductor chip, but recently, it has been proposed to incorporate the gate resistor in the semiconductor chip.

  For example, according to Japanese Patent Laid-Open No. 2002-83964, a gate resistor (built-in gate resistor) built in a semiconductor chip is proposed. According to this publication, the switching operation when semiconductor elements are connected in parallel is stabilized by a built-in gate resistance made of polycrystalline silicon or the like.

  Further, for example, according to Japanese Patent Laid-Open No. 2003-197914, a semiconductor device having a structure in which a built-in gate resistor made of polycrystalline silicon or the like is provided under a gate pad that is an exposed portion of a gate external connection electrode via an interlayer insulating film. Has been proposed. According to this publication, with this configuration, a semiconductor device having a large area of built-in gate resistance and suppressing a transient pulse current density can be obtained without reducing the area of the active region of the semiconductor substrate. .

JP 2001-44435 A JP 2002-83964 A JP 2003-197914 A

  The semiconductor device to which the gate resistor is externally attached has a problem that the number of parts increases. Further, the connection portion between the gate resistor and the semiconductor chip is susceptible to potential change due to external noise, and this potential change directly affects the gate in the semiconductor chip without going through the gate resistor. For this reason, there has been a problem that malfunction and oscillation of the semiconductor device are likely to occur.

  In addition, when a large current flows through the gate resistance, for example, when a current is supplied to hundreds to tens of thousands of gates of the IGBT, the cross-sectional area of the current path in the gate resistance is increased to ensure reliability. There is a need to. In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2002-83964, the width dimension or thickness dimension of the built-in gate resistor needs to be increased. However, when the thickness dimension is increased, there are a problem that a time required for forming a film serving as a built-in gate resistance becomes long and a process after the film formation becomes difficult. Further, when the width dimension is increased, there is a problem that the area of the built-in gate resistor increases and the area of the semiconductor chip increases.

  The built-in gate resistor disclosed in Japanese Patent Application Laid-Open No. 2003-197914 is effective in reducing the area of the semiconductor chip because the gate pad and the built-in gate resistor overlap with each other. However, the reduction effect is less than the gate pad area. There is a problem that there is.

  Therefore, an object of the present invention is to provide a semiconductor device having a resistance element with a small plane area that can flow a large current with high reliability.

  Another object of the present invention is to provide a semiconductor device having a resistance element whose resistance value can be controlled.

  Still another object of the present invention is to provide a semiconductor device having a plurality of gate electrodes and suppressing a delay difference in transmission of a potential signal to each gate electrode.

  Still another object of the present invention is to provide a smaller semiconductor device having a shunt resistor.

  Still another object of the present invention is to provide a semiconductor device having a wiring with a small parasitic resistance.

  The semiconductor device of the present invention includes a semiconductor substrate, an insulating film, a semiconductor element, and a resistance element. The semiconductor substrate has a first groove. The insulating film covers the inner surface of the first groove. The semiconductor element has a channel region formed of a part of a semiconductor substrate and an electrode. The resistance element is electrically connected to the electrode so as to have a resistance to the current flowing through the electrode, and is provided in the first groove portion via the insulating film.

The semiconductor device may have the following characteristics.
A semiconductor device according to one aspect includes a semiconductor substrate, an insulating film, a semiconductor element, and a resistance element. The insulating film covers at least a part of the semiconductor substrate. The semiconductor element has a channel region formed of a part of a semiconductor substrate and an electrode. The resistance element is electrically connected to the electrode so as to be a resistance to a current flowing through the electrode, and is provided on the semiconductor substrate via an insulating film. The resistance element includes a semiconductor region, and a depletion layer is generated in the semiconductor region due to a potential difference between the semiconductor substrate and the resistance element.

  A semiconductor device according to another aspect includes a semiconductor substrate, a semiconductor element, an insulating film, and at least one resistance element. The semiconductor element has a channel region formed of a part of a semiconductor substrate and a gate electrode for controlling the channel region. The insulating film is provided on the semiconductor substrate. The resistance element is provided on the insulating film, is electrically connected to the gate electrode so as to have resistance to a current flowing through the gate electrode, and has a pn junction.

  A semiconductor device according to another aspect includes a semiconductor substrate, a semiconductor element, an insulating film, and a resistance element. The semiconductor substrate has a first groove.

  The semiconductor element has a channel region formed of a part of a semiconductor substrate and an electrode. The insulating film is provided on the semiconductor substrate. The resistance element includes a junction field effect transistor that is provided on the insulating film and is electrically connected to the electrode such that a resistance between the source and the drain is a resistance to a current flowing through the electrode.

  A semiconductor device according to another aspect includes a semiconductor substrate, a semiconductor element, an insulating film, and a resistance element. The semiconductor element has a channel region formed of a part of a semiconductor substrate and an electrode. The insulating film is provided on the semiconductor substrate. The resistance element includes a MIS field effect transistor that is provided on the insulating film and is electrically connected to the electrode so that the resistance between the source and the drain is a resistance against the current flowing through the electrode.

  A semiconductor device according to another aspect includes a semiconductor substrate, a semiconductor element, an insulating film, and a resistance element. The semiconductor element has a channel region formed of a part of a semiconductor substrate and an electrode. The insulating film is provided on the semiconductor substrate. The resistance element is provided on the insulating film, and is electrically connected to the electrode so as to be a resistance to a current flowing through the electrode, and includes at least one region having a diode and an ohmic resistance in parallel.

  A semiconductor device according to still another aspect includes a semiconductor substrate, a semiconductor element, a gate pad, a gate wiring, and a plurality of resistance elements. The semiconductor element has a channel region formed of a part of a semiconductor substrate and a plurality of gate electrodes for controlling the channel region. The gate pad is electrically connected to the plurality of gate electrodes. The gate wiring electrically connects at least one of the plurality of gate electrodes and the gate pad. The resistance element is provided in the middle of the gate wiring. The resistance value of the resistance element connected to the gate electrode relatively close to the gate pad is larger than the resistance value of the resistance element connected to the gate electrode relatively far from the gate pad.

  A semiconductor device according to still another aspect includes a semiconductor substrate, an insulated gate bipolar transistor, an insulating film, and first and second resistance elements. The insulated gate bipolar transistor has a channel region formed of a part of a semiconductor substrate, first and second emitter electrodes, and a gate electrode. The insulating film is provided on the semiconductor substrate. The first resistance element is provided on the insulating film and electrically connects the first and second emitter electrodes to each other. The second resistance element is provided on the insulating film, and electrically connects the first emitter electrode and the gate electrode with an electrical resistance corresponding to the potential of the second emitter electrode.

  A semiconductor device according to still another aspect includes a semiconductor substrate, an insulated gate bipolar transistor, an insulating film, and first and second resistance elements. The insulated gate bipolar transistor has a channel region formed of a part of a semiconductor substrate, first and second emitter electrodes, and a gate electrode. The insulating film is provided on the semiconductor substrate. The first resistance element is provided on the insulating film and electrically connects the first and second emitter electrodes to each other. The second resistance element is provided on the insulating film, has an electrical resistance corresponding to the potential of the second emitter electrode, and is electrically connected to the gate electrode so as to be a resistance to a current flowing through the gate electrode. Yes.

  A semiconductor device according to still another aspect includes a semiconductor substrate, a semiconductor element, an insulating film, and first and second wirings. The semiconductor substrate has a groove. The semiconductor element has a channel region formed of a part of a semiconductor substrate and an electrode. The insulating film covers the inner surface of the groove. The first wiring is electrically connected to the electrode and is provided in the groove through an insulating film. The second wiring is provided on the groove, and is electrically connected in parallel with the first wiring.

  In the semiconductor device of the present invention, the resistance element is provided in the first groove. Thereby, the plane area of the resistance element that can flow a large current with high reliability can be reduced.

  In the semiconductor device according to one aspect of the present invention, the resistance element includes a semiconductor region. By using the semiconductor characteristics of the semiconductor region, the resistance value of the resistance element can be controlled.

  In the semiconductor device according to another aspect of the present invention, the resistance value of the resistance element connected to the gate electrode relatively close to the gate pad is compared with the resistance value of the resistance element connected to the gate electrode relatively far from the gate pad. Is big. As a result, a delay difference in transmission of the potential signal to each gate electrode is suppressed.

  In the semiconductor device according to still another aspect of the present invention, the first resistance element that electrically connects the first and second emitter electrodes to each other is provided on the insulating film. Thereby, the semiconductor device having a shunt resistor can be reduced in size.

  In the semiconductor device according to still another aspect of the present invention, the first wiring provided in the groove and the second wiring provided on the groove are connected in parallel. Thereby, the parasitic resistance of the wiring can be reduced.

1 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. 1 is a top view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic partial top view of the III section of FIG. FIG. 4 is a diagram in which the gate pad, the gate main wiring, and the emitter pad (emitter electrode) in FIG. 3 are omitted. FIG. 5 is a diagram in which the interlayer insulating film in FIG. 4 is omitted. FIG. 6 is a diagram in which the polycrystalline silicon layers on the gate pad side and the main wiring side in FIG. 5 are omitted. FIG. 7 is a diagram in which a part of the gate oxide film and a part of the insulating film in FIG. 6 are omitted. It is a figure which shows the schematic equivalent circuit of the state with which the semiconductor device in Embodiment 1 of this invention was mounted in the printed circuit board. It is explanatory drawing which shows roughly the mode of the connection of the gate pad of the semiconductor device in Embodiment 1 of this invention, and the pad of a printed circuit board. It is a top view which shows roughly the structure of the resistive element in the modification of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary top view which shows roughly the structure of the resistance element in the modification of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary top view which shows roughly the structure of the resistance element in the modification of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary top view which shows roughly the structure of the resistance element in the modification of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary top view which shows roughly the structure of the resistance element in the modification of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary top view which shows roughly the structure of the resistance element in the modification of the semiconductor device of Embodiment 1 of this invention. It is a top view which shows roughly the structure of the semiconductor device in a 1st comparative example. It is explanatory drawing which shows roughly the mode of a connection with the gate pad of the semiconductor device in a 1st comparative example, and the pad of a printed circuit board. It is a rough equivalent circuit of the state where the semiconductor device in the 1st comparative example was mounted in the printed circuit board. It is a schematic partial top view of the semiconductor device in the 2nd comparative example. FIG. 20 is a schematic cross-sectional view taken along line XX-XX in FIG. 19. It is a fragmentary top view which shows roughly the structure of the semiconductor device in Embodiment 2 of this invention. FIG. 22 is a schematic cross-sectional view along the line XXII-XXII in FIG. 21. FIG. 22 is a schematic sectional view taken along line XXIII-XXIII in FIG. 21. FIG. 22 is a schematic sectional view taken along line XXIV-XXIV in FIG. 21. It is a fragmentary top view which shows schematically the structure of the resistive element with which the metal part was embedded in the 1st modification of the semiconductor device of Embodiment 2 of this invention. It is a fragmentary top view which shows schematically the structure of the resistance element with which the metal part was embedded in the 2nd modification of the semiconductor device of Embodiment 2 of this invention. FIG. 22 is a schematic cross-sectional view showing a first step of the method for manufacturing a semiconductor device in the second embodiment of the present invention, which is a cross-sectional view corresponding to the XXXIIa-XXXIIa line in FIG. 21 and a cross-sectional view corresponding to the XXXIIb-XXXIIb line; (B). FIG. 22 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device in the second embodiment of the present invention, which is a cross-sectional view corresponding to the XXXIIa-XXXIIa line in FIG. 21 and a cross-sectional view corresponding to the XXXIIb-XXXIIb line; (B). FIG. 22 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device in the second embodiment of the present invention, which is a cross-sectional view corresponding to the XXXIIa-XXXIIa line in FIG. 21 and a cross-sectional view corresponding to the XXXIIb-XXXIIb line; (B). FIG. 22 is a schematic cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device in the second embodiment of the present invention, which is a cross-sectional view corresponding to the XXXIIa-XXXIIa line in FIG. 21 and a cross-sectional view corresponding to the XXXIIb-XXXIIb line; (B). FIG. 22 is a schematic cross-sectional view showing a fifth step of the method of manufacturing a semiconductor device in the second embodiment of the present invention, which is a cross-sectional view corresponding to the XXXIIa-XXXIIa line in FIG. 21 and a cross-sectional view corresponding to the XXXIIb-XXXIIb line; (B). FIG. 22 is a schematic cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device in the second embodiment of the present invention, which is a cross-sectional view corresponding to XXXIIa-XXXIIa line in FIG. 21 and a cross-sectional view corresponding to XXXIIb-XXXIIb line; (B). FIG. 20 is a schematic partial cross-sectional view showing a first step of a method for manufacturing a semiconductor device in a third comparative example, and is a partial cross-section in the vicinity of a planar built-in gate resistor among cross-sectional positions corresponding to line XX-XX in FIG. 19. FIG. 22 is a partial cross-sectional view (b) at a cross-sectional position corresponding to the line XXXIIb-XXXIIb in FIGS. FIG. 20 is a schematic partial cross-sectional view showing a second step of the method of manufacturing a semiconductor device in the third comparative example, and is a partial cross-section in the vicinity of the planar built-in gate resistance among the cross-sectional positions corresponding to the line XX-XX in FIG. 19. FIG. 22 is a partial cross-sectional view (b) at a cross-sectional position corresponding to the line XXXIIb-XXXIIb in FIGS. FIG. 20 is a schematic partial cross-sectional view showing a third step of the method of manufacturing a semiconductor device in the third comparative example, and is a partial cross-section in the vicinity of the planar built-in gate resistance in the cross-sectional position corresponding to the line XX-XX in FIG. 19. FIG. 22 is a partial cross-sectional view (b) at a cross-sectional position corresponding to the line XXXIIb-XXXIIb in FIGS. FIG. 20 is a schematic partial cross-sectional view showing a fourth step of the method of manufacturing a semiconductor device in the third comparative example, and is a partial cross-section in the vicinity of the planar built-in gate resistance in the cross-sectional position corresponding to the line XX-XX in FIG. 19. FIG. 22 is a partial cross-sectional view (b) at a cross-sectional position corresponding to the line XXXIIb-XXXIIb in FIGS. FIG. 20 is a schematic partial cross-sectional view showing a fifth step of the method of manufacturing a semiconductor device in the third comparative example, and is a partial cross-section in the vicinity of the planar built-in gate resistance among the cross-sectional positions corresponding to the line XX-XX in FIG. 19. FIG. 22 is a partial cross-sectional view (b) at a cross-sectional position corresponding to the line XXXIIb-XXXIIb in FIGS. FIG. 20 is a schematic partial cross-sectional view showing a sixth step of the method for manufacturing a semiconductor device in the third comparative example, and is a partial cross-section in the vicinity of the planar built-in gate resistance in the cross-sectional position corresponding to the line XX-XX in FIG. 19. FIG. 22 is a partial cross-sectional view (b) at a cross-sectional position corresponding to the line XXXIIb-XXXIIb in FIGS. It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element vicinity of the semiconductor device in the 1st modification of Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element vicinity of the semiconductor device in the 2nd modification of Embodiment 3 of this invention. It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in the 3rd modification of Embodiment 3 of this invention. It is explanatory drawing for demonstrating operation | movement of the resistive element of the semiconductor device in Embodiment 3 of this invention. It is explanatory drawing for demonstrating operation | movement of the resistive element of the semiconductor device in Embodiment 3 of this invention. It is explanatory drawing for demonstrating operation | movement of the resistive element of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in Embodiment 4 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element in the 1st modification of the semiconductor device of Embodiment 4 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element in the 2nd modification of the semiconductor device of Embodiment 4 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element in the 3rd modification of the semiconductor device of Embodiment 4 of this invention. It is a top view which shows roughly the structure of the resistive element of the semiconductor device in Embodiment 6 of this invention. It is a top view which shows roughly the structure of the resistive element of the semiconductor device in the modification of Embodiment 6 of this invention. It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in Embodiment 7 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element vicinity of the semiconductor device in Embodiment 8 of this invention. It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in Embodiment 9 of this invention. It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in Embodiment 10 of this invention. Partial sectional view (a) schematically showing the configuration in the vicinity of the resistance element of the semiconductor device according to the eleventh embodiment of the present invention and the schematic configuration in the vicinity of the resistance element of the semiconductor device in the modification of the eleventh embodiment of the present invention. It is a fragmentary sectional view (b) shown in FIG. FIG. 18A is a diagram showing an equivalent circuit of a resistance element of a semiconductor device in an eleventh embodiment of the present invention, and FIG. 20B is a diagram showing an equivalent circuit of a resistance element of a semiconductor device in a modification of the eleventh embodiment of the present invention. . An explanatory diagram (a) of voltage-current characteristics in the case of R ₂ << R ₁ << R ₀ of the resistance element of the semiconductor device in the eleventh embodiment of the present invention and the modification thereof, and the eleventh embodiment of the present invention and its voltage for _{R 1> R} 2 >> _{R 0} of the resistance element of the semiconductor device in a modified example - is an explanatory view of a current characteristic (b). It is a fragmentary sectional view which shows roughly the structure of the resistive element vicinity of the semiconductor device in Embodiment 12 of this invention. It is a fragmentary sectional view which shows schematically the structure of the resistive element vicinity of the semiconductor device in Embodiment 13 of this invention. The top view (a) which shows roughly the structure of the resistive element of the semiconductor device in the modification of Embodiment 12 of this invention, and the structure of the resistive element of the semiconductor device in the modification of Embodiment 13 of this invention is schematic. It is a top view (b) shown in FIG. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 14 of this invention. FIG. 63 is a schematic partial plan view of the LXIII portion of FIG. 62. FIG. 38 is a partial plan view schematically showing a plane layout in the vicinity of a resistance element of a semiconductor device in Embodiment 15 of the present invention. FIG. 38 is a partial plan view schematically showing a plane layout in the vicinity of a resistance element of a semiconductor device in a modification of Embodiment 15 of the present invention. It is a schematic sectional drawing for demonstrating the structure of the sense electrode of the semiconductor device in Embodiment 15 of this invention. It is a fragmentary sectional perspective view which shows roughly the structure of the gate main wiring vicinity of the semiconductor device in Embodiment 16 of this invention. It is a fragmentary sectional view which shows schematically the structure of the gate main wiring vicinity of the semiconductor device in the 1st modification of Embodiment 16 of this invention. It is a fragmentary sectional view which shows schematically the structure of the gate main wiring vicinity of the semiconductor device in the 2nd modification of Embodiment 16 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
First, an outline of the configuration of the semiconductor device of this embodiment will be described.

  1A to 1C are partial sectional views schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a top view schematically showing a configuration of the semiconductor device according to the first embodiment of the present invention. Referring to FIGS. 1A to 1C, the IGBT chip according to the present embodiment is a power semiconductor device, and includes an IGBT element EL which is a trench gate type semiconductor element and a trench type built-in which is a resistance element. A gate resistor 4t.

  Referring to FIGS. 1A and 1B, trench-type built-in gate resistor 4t is formed in first trench T1 provided in semiconductor substrate 101 via insulating film 14b. Thereby, the trench-type built-in gate resistor 4t has a configuration in which the cross-sectional area of the current path is increased by deepening the first groove T1.

  Referring to FIGS. 1A and 1C, the IGBT element EL has a part of the semiconductor substrate 101 as a channel region. The IGBT element EL has a number of gate electrodes 13 for controlling the channel region. The number of gate electrodes 13 is, for example, several hundred to several tens of thousands.

  Referring to FIGS. 1A to 1C and FIG. 2, gate electrodes 13 of each cell of IGBT element EL are electrically connected to each other by a gate main wiring 5. The gate main wiring 5 is electrically connected to the gate pad 1 around the gate pad 1 via a trench-type built-in gate resistor 4t.

  Thereby, the IGBT chip has a configuration in which an input to the gate pad 1 is transmitted to each gate electrode 13 of the IGBT element EL via the trench-type built-in gate resistor 4t. That is, the trench-type built-in gate resistor 4t is electrically connected to the gate electrode 13 so as to provide a resistance (gate resistance) to the current flowing through the gate electrode 13. This gate resistance mainly has a function of delaying the potential transmitted to the gate electrode 13 and adjusting the rise of current / voltage during switching of the IGBT element EL.

  The gate main wiring 5 has a polycrystalline silicon layer 12b made of n-type polycrystalline silicon which is a gate material doped with impurities at a high concentration, for example. The gate main wiring 5 has a main wiring metal layer 10b so that the resistance as a wiring is reduced. In the main wiring side contact hole 9b, the polycrystalline silicon layer 12b and the main wiring metal layer 10b are in contact with each other and are electrically connected to each other.

  Next, details of the configuration of the semiconductor device of the present embodiment will be described. FIG. 3 is a schematic partial top view of part III in FIG. FIG. 4 is a diagram in which the gate pad, the gate main wiring, and the emitter pad (emitter electrode) in FIG. 3 are omitted. FIG. 5 is a diagram in which the interlayer insulating film of FIG. 4 is omitted. FIG. 6 is a diagram in which the polycrystalline silicon layers on the gate pad side and main wiring side in FIG. 5 are omitted. FIG. 7 is a diagram in which a part of the gate oxide film and a part of the insulating film in FIG. 6 are omitted. Each of the Ia-Ia line, Ib-Ib line, and Ic-Ic line in FIGS. 3 to 7 indicates the cross-sectional position of each of FIGS. 1 (a) to 1 (c).

  Referring to FIG. 1A again, the IGBT chip has a semiconductor substrate 101 as a base material. The IGBT chip has an IGBT element EL including a part of the semiconductor substrate 101. The IGBT chip includes an insulating film 14b, a trench-type built-in gate resistor 4t, a field oxide film 7, polycrystalline silicon layers 12a and 12b, an interlayer insulating film 11, a gate pad metal layer 10a, and a main wiring metal layer. 10b.

  The field oxide film 7 is a film that insulates the semiconductor substrate 101 and the polycrystalline silicon layers 12a and 12b, and is formed by, for example, a LOCOS (Local Oxidation of Silicon) method. Gate pad metal layer 10a and main wiring metal layer 10b are made of a low-resistance conductor material such as an aluminum alloy.

  Referring mainly to FIGS. 1A, 1B and 7, the semiconductor substrate 101 has a first trench T1 whose inner surface is covered with an insulating film 14b. That is, the bottom surface and the side surface of the first groove T1 are covered with the insulating film 14b. By this insulating film 14b, the trench type built-in gate resistor 4t provided in the first trench T1 and the semiconductor substrate 101 are electrically insulated.

  The dimensions of the first groove T1 are, for example, a depth dimension (vertical dimension in FIG. 1A) of about 10 μm and a width dimension (lateral dimension in FIG. 1B) of 1.2 μm. As shown in FIG. 5, the plurality of first groove portions T1 are formed so as to run in parallel at a pitch of 2.5 μm. The insulating film 14b has a film thickness dimension smaller than the dimension of the first trench T1. The film thickness of the insulating film 14b is, for example, several tens to 200 nm.

  Since there is no complicated structure between the adjacent trench-type built-in gate resistors 4t, the pitch of the trench (first groove portion T1) for the trench-type built-in gate resistor 4t is the trench for the gate electrode 13 (first trench). It is possible to make it smaller than the pitch of the two groove portions T2). That is, the pitch of the first groove portions T1 can be a narrow pitch of about 2.5 μm, for example.

The trench-type built-in gate resistor 4t is made of a material used as an electric resistor, for example, n-type polycrystalline silicon doped at a high concentration of 1 × 10 ¹⁹ / cm ³ or more. The trench-type built-in gate resistor 4t has, for example, the same width dimension as the width dimension W1 (FIG. 6) of the gate electrode 13, and has a function of giving resistance to the current flowing along the length direction (lateral direction in FIG. 6). Have. The depth dimension of the trench-type built-in gate resistor 4t (the vertical dimension in FIGS. 1A and 1B) is, for example, 5 to 20 μm.

  The resistance value of the trench type built-in gate resistor 4t is a value depending on the dimension of the trench in which the trench type built-in gate resistor 4t is buried and the doping concentration of the buried n-type polycrystalline silicon. This resistance value is, for example, several hundred Ω to several kΩ for a length of 1 mm of the trench-type built-in gate resistor 4t.

  One trench-type built-in gate resistor 4t has a reliability that allows a current of several tens to several hundreds of mA to flow. One trench type built-in gate resistor 4t has, for example, a resistance value of 1 kΩ per 1 mm length, and has a reliability capable of flowing a current of 200 mA at maximum. In order to obtain an 8Ω resistor through which a maximum current of 5 A flows, 25 trench-type built-in gate resistors 4t having a length of 200 μm may be connected in parallel.

  Referring to FIGS. 1A and 1B, trench-type built-in gate resistor 4t formed to be embedded in first trench T1 is formed by interlayer insulating film 11 on the opening side of first trench T1. It is covered. In the interlayer insulating film 11, a gate pad side contact hole 9a and a main wiring side contact hole 9b are formed.

  In the gate pad side contact hole 9a, the gate pad metal layer 10a is connected to the trench type built-in gate resistor 4t through the polycrystalline silicon layer 12a. In the main wiring side contact hole 9b, the main wiring metal layer 10b is connected to the trench type built-in gate resistor 4t through the polycrystalline silicon layer 12b.

  Referring to FIGS. 1A and 3, the upper surface side of gate pad metal layer 10 a functions as gate pad 1. That is, the upper surface side of the gate pad metal layer 10a is configured so that wiring from the outside can be connected by wire bonding or the like. Main wiring metal layer 10b constitutes gate main wiring 5 together with polycrystalline silicon layer 12b.

  Referring to FIG. 1A, in the region where the IGBT element EL is formed, the IGBT chip includes a semiconductor substrate 101, a gate insulating film 14a, a gate electrode 13, a polycrystalline silicon layer 12b, and an interlayer insulating film 11. And an emitter pad 18.

  Referring to FIG. 2, IGBT element EL has a structure composed of, for example, several hundred to tens of thousands of cells in the region where emitter pad 18 is formed. The IGBT element EL has a gate electrode 13 in each cell.

  1A, 1C, and 7, a semiconductor substrate 101 includes an n-type emitter region 15, a high-concentration p-type region 16, a p-type channel region 17, and a low-concentration n-type drift region. 8, an n-type buffer region 20, and a p-type collector region 19.

  The semiconductor substrate 101 has a second trench T2 whose inner surface is covered with the gate insulating film 14a. That is, the bottom surface and the side surface of the second trench T2 are covered with the gate insulating film 14a. The gate insulating film 14a electrically insulates the gate electrode 13 provided in the second trench T2 from the semiconductor substrate 101.

The dimensions of T2 are, for example, a depth dimension (vertical dimension in FIG. 1A) of about 10 μm and a width dimension (lateral dimension in FIG. 1C) of 1.2 μm, as shown in FIG. The plurality of second groove portions T2 are formed so as to run in parallel at a pitch of 5.0 μm. The gate insulating film 14a has a film thickness dimension smaller than the dimension of the second trench T2. The film thickness of the gate insulating film 14a is, for example, several tens to 200 nm. Gate electrode 13 is formed of n-type polycrystalline silicon doped at a high concentration of, for example, 1 × 10 ¹⁹ / cm ³ or more.

  Referring to FIGS. 1A, 1C, and 5, polycrystalline silicon layer 12b is in contact with gate electrode 13. Thereby, the gate electrode 13 is connected to the gate main wiring 5.

  Referring to FIGS. 1A and 1C, the gate electrode 13 formed so as to be embedded in the second trench T2 is covered with the interlayer insulating film 11 on the opening side of the second trench T2. Yes.

  Referring to FIGS. 3 and 4, emitter contact hole 9 d is formed in interlayer insulating film 11. An emitter pad (emitter electrode) 18 is connected to the n-type emitter region 15, the high-concentration p-type region 16, and the p-type channel region 17 through the emitter contact hole 9d.

  In the above configuration, preferably, as shown in FIG. 1A, the gate pad side contact hole 9a is formed so as to have an overlapping region with the surface on the opening side of the first trench T1 of the trench type built-in gate resistor 4t. ing. That is, the interlayer insulating film 11 has the gate pad side contact hole 9aD on the opening side of the first trench T1 of the trench type built-in gate resistor 4t as a part of the gate pad side contact hole 9a.

  The main wiring side contact hole 9b is formed so as to have an overlapping region with the opening side surface of the first trench T1 of the trench type built-in gate resistor 4t. That is, the interlayer insulating film 11 has a main wiring side contact hole 9bD on the opening side of the first trench T1 of the trench type built-in gate resistor 4t as a part of the main wiring side contact hole 9b.

  Further, as shown in FIGS. 1A and 2, the gate pad 1 and the gate main wiring 5 are separated by an interlayer insulating film 11, and the current path between the gate pad 1 and the gate electrode 13 is substantially the same. Thus, only the current path via the trench-type built-in gate resistor 4t is present. Here, the substantial current path is a current path that does not include a current path caused by parasitic capacitance or parasitic inductance or a path of a minute current flowing through the insulator.

  As shown in FIGS. 1A to 1C and FIG. 7, the semiconductor substrate 101 is in contact with the insulating film 14b and has a conductivity type opposite to that of the low-concentration n-type drift region 8 of the IGBT element EL. A mold region 21 is included. More preferably, the impurity concentration for making the p-type region 21 opposite to the conductivity type opposite to that of the low-concentration n-type drift region 8 is such that the p-type channel region 17 of the IGBT element EL is opposite to that of the low-concentration n-type drift region 8. The impurity concentration for making the mold is higher.

  The potential of the p-type region 21 is controlled so that no inversion layer is formed in the p-type region 21. In order to perform this control, for example, p type region 21 is electrically connected to n type emitter region 15 of IGBT element EL.

  Next, a method for using the IGBT chip of this embodiment will be described. FIG. 8 is a diagram showing a schematic equivalent circuit in a state where the semiconductor device according to the first embodiment of the present invention is mounted on a printed board. FIG. 9 is an explanatory diagram schematically showing a state of connection between the gate pad of the semiconductor device and the pad of the printed circuit board according to the first embodiment of the present invention.

  Referring to FIGS. 8 and 9, IGBT chip circuit 100 is used by being incorporated in a printed circuit board circuit 200, for example. The printed circuit board has an external emitter pad 3e, an external gate pad 3g, and an external collector pad 3c. External emitter pad 3e, external gate pad 3g, and external collector pad 3c are made of a low-resistance conductor material such as an aluminum alloy.

The gate pad 1 of the IGBT chip and the external gate pad 3g of the printed circuit board are connected by a wire 2a made of aluminum or gold. Further, the n-type emitter region 15 (FIG. 1C) and the p-type collector region 19 (FIG. 1A) of the IGBT chip are electrically connected to the external emitter pad 3e and the external collector pad 3c, respectively. ing. An external potential V _g is applied to the external gate pad 3g.

  Note that each of the capacitor symbol and the coil symbol in FIG. 8 represents a parasitic capacitance and a parasitic inductance in the IGBT chip. Moreover, the arrows in the figure represent paths through which the outputs from the collector and emitter of the IGBT element EL return to the gate electrode via the parasitic capacitance and the parasitic inductance.

  Note that the semiconductor device of this embodiment can be manufactured by a method in which a part of the method of manufacturing the semiconductor device in Embodiment 2 described later is simplified.

  Next, a modification of the configuration of the trench type built-in gate resistor 4t in the present embodiment will be described.

  FIG. 10 is a plan view schematically showing a configuration of a resistance element in a modification of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 10, trench-type built-in gate resistor 4t has a width dimension WE1 wider than the width dimension W1 equal to the minimum width in the part facing interlayer insulating film 11 in the part facing gate pad side contact hole 9a. Contains the part you have. Trench-type built-in gate resistor 4t includes a portion having a width dimension WE1 that is wider than width dimension W1, which is the minimum width in the portion facing interlayer insulating film 11, in the portion facing main wiring side contact hole 9b. .

  The shape of the trench-type built-in gate resistor 4t in this modification is not limited to the shape shown in FIG. 10, and can be the shapes shown in FIGS. 11 to 15 show the vicinity of the portion facing the gate pad side contact hole 9a of the trench-type built-in gate resistor 4t, but the portion facing the main wiring side contact hole 9b has the same configuration. be able to.

Next, a first comparative example will be described.
First, the configuration of the semiconductor device in this comparative example will be described. FIG. 16 is a top view schematically showing the configuration of the semiconductor device in the first comparative example. Referring to FIG. 16, the IGBT chip as the semiconductor device of this comparative example has a gate pad 1 </ b> C and a gate main wiring 5 formed integrally with each other. Since the gate pad 1C and the gate main wiring 5 are integrated, there is no resistance element as a gate resistance between them.

  Next, a method of using the IGBT chip in this comparative example will be described. FIG. 17 is an explanatory view schematically showing a state of connection between the gate pad of the semiconductor device and the pad of the printed circuit board in the first comparative example. FIG. 18 is a schematic equivalent circuit of the semiconductor device in the first comparative example mounted on a printed circuit board.

Referring to FIG. 17, external gate resistor 4e is prepared as a separate component from the IGBT chip and connected to external gate pad 3g. In order to control the potential of the gate electrode, the potential V _g is applied from the outside via the external gate resistor 4e.

  Referring to FIG. 18, each of a capacitor symbol and a coil symbol represents a parasitic capacitance and a parasitic inductance in circuit 100C of the IGBT chip. Moreover, the arrows in the figure represent paths through which the outputs from the collector and emitter of the IGBT element EL return to the gate electrode via the parasitic capacitance and the parasitic inductance.

  The external gate resistor 4e is not provided between the gate electrode of the IGBT element EL and the external gate pad 3g. That is, the external gate resistor 4e does not exist on the path where the output from the collector and emitter of the IGBT element EL returns to the gate electrode.

  For this reason, when the potential of the external gate pad 3g varies due to external noise, the potential variation is directly transmitted to the gate electrode of the IGBT element EL via the parasitic inductance. As a result, the gate electrode is susceptible to noise.

  Further, when the above fluctuation takes the IGBT element EL as an amplifier and returns to the gate electrode of the IGBT element EL through the path indicated by the arrow in the figure, the Q value represented by the following formula increases.

For this reason, oscillation is likely to occur in the gate-emitter voltage V _ge , the collector-emitter voltage V _ce , the collector current I _{c, and the} like. In the above equation, L represents a parasitic inductance, C represents a parasitic capacitance, and R represents a gate resistance.

  Next, a second comparative example will be described. FIG. 19 is a schematic partial plan view of a semiconductor device according to a second comparative example. 20 is a schematic cross-sectional view taken along line XX-XX in FIG. The position shown in FIG. 19 corresponds to the position shown in FIG. 5, and the gate pad, the main gate wiring, the emitter pad, and the interlayer insulating film are omitted as in FIG.

  Referring to FIGS. 19 and 20, the IGBT chip as the semiconductor device of this comparative example has a planar built-in gate resistor 4 p as a gate resistor between gate pad 1 and gate main wiring 5. The planar built-in gate resistor 4 p is a planar resistive element that is provided on the field oxide film 7 and has a plane parallel to the substrate surface of the semiconductor substrate 101. The planar built-in gate resistor 4p is formed, for example, by patterning a polycrystalline silicon film having a film thickness of about several hundred nm.

  For example, when a current is supplied to the gate electrodes 13 of hundreds to tens of thousands of IGBT elements EL, the planar built-in gate resistor 4p needs to have reliability to withstand a large current. Therefore, the cross-sectional area with respect to the current path is increased so that the current density does not become excessively high. In order to increase the cross-sectional area, it is necessary to increase the film thickness dimension (vertical dimension in FIG. 20) of the planar built-in gate resistor 4p or increase the width dimension (vertical dimension in FIG. 19). is there.

  In order to increase the film thickness dimension, the process time required for film formation becomes longer. For example, it takes several hours to deposit polycrystalline silicon having a thickness of several hundreds of nanometers, which is the thickness of a commonly used planar built-in gate resistor 4p. When this film thickness is increased to several μm, the deposition time becomes several tens of hours, and the manufacturing cost increases. Further, since the polycrystalline silicon film becomes thicker, it becomes difficult to ensure the depth of focus at the time of photoengraving in patterning, and to remove the residue at the step portion at the time of etching.

  When the width dimension of the planar built-in gate resistor 4p is increased, the area occupied by the planar built-in gate resistor 4p on the substrate surface of the semiconductor substrate 101 is increased, which does not meet the demand for downsizing of the semiconductor device.

  Referring to FIG. 20, field oxide film 7 provided below planar built-in gate resistor 4p has a thickness of about 1 μm or more. Since field oxide film 7 is an oxide film, its thermal conductivity is low. That is, a thin film having low thermal conductivity is formed under the planar built-in gate resistor 4p. For this reason, the heat radiation of the planar built-in gate resistor 4p is hindered, the temperature of the planar built-in gate resistor 4p rises, and the resistance value is likely to change due to temperature dependency.

  According to the present embodiment, the gate electrode 13 of the IGBT element EL is electrically connected to the trench type built-in gate resistor 4t. As a result, the trench-type built-in gate resistor 4t can function as the gate resistor of the gate electrode 13.

  Further, as shown in FIGS. 1A and 1B, the trench-type built-in gate resistor 4t is provided in the first trench T1. Therefore, by increasing the depth dimension of the first trench T1, the dimension in the depth direction of the trench-type built-in gate resistor 4t can also be increased. Therefore, the current density of the trench built-in gate resistor 4t is reduced while the plane area (area in FIG. 6) of the trench built-in gate resistor 4t on the substrate surface of the semiconductor substrate 101 is kept small, and the trench built-in gate resistor 4t Can improve the reliability.

  Further, as shown in FIG. 8, the gate pad 1 is connected to the gate electrode 13 via a trench-type built-in gate resistor 4t. Therefore, a potential change due to noise applied to the gate pad 1 or the external gate pad 3g connected to the gate pad 1 is suppressed by the trench-type built-in gate resistor 4t when transmitted to the gate electrode 13.

  Preferably, the current path between the gate pad 1 and the gate electrode 13 is substantially only the current path passing through the trench-type built-in gate resistor 4t. For this reason, there is no current path for bypassing the trench-type built-in gate resistor 4t, and it is possible to prevent a substantial gate resistance from being lowered or a failure from occurring in the IGBT chip due to the bypassed current path. it can.

  Further, as shown in FIG. 1A, the interlayer insulating film 11 has a gate pad side contact hole 9aD on the opening side of the first trench T1 of the trench type built-in gate resistor 4t. Therefore, a wide electrical path is secured between the gate pad 1 and the trench-type built-in gate resistor 4t, and reliability deterioration due to current concentration can be prevented.

  Further, as shown in FIG. 1A, the interlayer insulating film 11 is formed on the main wiring side contact hole 9bD on the opening side of the first trench T1 on the opening side of the first trench T1 of the trench-type built-in gate resistor 4t. have. Therefore, a wide electrical path between the gate main wiring 5 and the trench-type built-in gate resistor 4t is ensured, and reliability deterioration due to current concentration can be prevented.

  Further, as shown in FIGS. 1A and 1C, since the gate electrode 13 is provided in the second groove T2, the structure of the gate electrode 13 can be a trench gate structure. Since the second trench T2 can be formed simultaneously with the first trench T1, the process cost for forming the trench gate can be suppressed.

  As shown in FIGS. 1A and 1B, the semiconductor substrate 101 is in contact with the insulating film 14b and has a p-type region 21 having a conductivity type opposite to that of the low-concentration n-type drift region 8 of the IGBT element EL. Is included. Thereby, it is possible to prevent the breakdown voltage degradation between the collector and the emitter of the IGBT element EL.

  More preferably, the impurity concentration for making p-type region 21 opposite to the conductivity type opposite to that of low-concentration n-type drift region 8 is such that p-type channel region 17 of IGBT element EL is opposite to that of low-concentration n-type drift region 8. The impurity concentration is set higher than that for the conductivity type. Thereby, the p-type channel region 17 can be inverted to the n-type without inverting the p-type region 21 to the n-type. Compared to the case where there is a relatively thick field oxide film 7 of about 1 μm to 2 μm between the gate resistance and the p-type region 21 as in the second comparative example, it is several tens as in the present embodiment. In the case where only the thin insulating film 14b of about 200 μm is present, the conductivity type inversion of the p-type region 21 occurs relatively easily. Therefore, a great effect can be obtained by setting the impurity concentration described above.

  The potential of the p-type region 21 is controlled so that no inversion layer is formed in the p-type region 21. In order to perform this control, for example, p type region 21 is electrically connected to n type emitter region 15 of IGBT element EL. Thereby, it is possible to prevent the breakdown voltage degradation between the collector and the emitter of the IGBT element EL.

[Embodiment 2]
First, the configuration of the IGBT chip as the semiconductor device of the present embodiment will be described.

  FIG. 21 is a partial plan view schematically showing the configuration of the semiconductor device in the second embodiment of the present invention. 22 to 24 are schematic cross-sectional views taken along lines XXII-XXII, XXIII-XXIII, and XXIV-XXIV in FIG. 21, respectively.

  The position shown in FIG. 21 corresponds to the position shown in FIG. In FIG. 21, as in FIG. 6, the gate pad, the gate main wiring, the emitter pad, the interlayer insulating film, and the polycrystalline silicon layers on the gate pad side and the main wiring side are omitted.

  Referring to FIGS. 21 to 24, the IGBT chip of the present embodiment has a metal part 22. The metal part 22 includes metal parts 22b1 and 22b2 embedded in the first groove part T1, and a metal part 22a embedded in the second groove part T2. The material of the metal part 22 has a specific resistance lower than that of a semiconductor material such as high-concentration n-type polycrystalline silicon. As a material of the metal part 22, for example, a refractory metal such as tungsten, titanium, platinum, or copper can be used.

  Referring to FIG. 24, gate electrode 13 has a polycrystalline silicon layer 12g and a metal portion 22a embedded in this polycrystalline silicon layer 12g.

  Referring to FIGS. 22 and 23, trench type built-in gate resistor 4t has a buried metal portion 22b1 in a portion facing gate pad side contact hole 9aD. The trench-type built-in gate resistor 4t has a buried metal portion 22b2 in a portion facing the main wiring side contact hole 9bD.

  The portions other than the buried metal portions 22b1 and 22b2 of the trench-type built-in gate resistor 4t are formed from the polycrystalline silicon layer 12r. The embedded metal portions 22b1 and 22b2 are electrically connected to each other via the polycrystalline silicon layer 12r.

  Referring mainly to FIG. 21, interlayer insulating film 11 (FIGS. 23 and 24) is formed on trench type built-in gate resistor 4t between gate pad side contact hole 9a and main wiring side contact hole 9b indicated by a broken line in the figure. ) Is provided. The minimum width of the trench-type built-in gate resistor 4t in the portion where the trench-type built-in gate resistor 4t faces the interlayer insulating film 11 is the width dimension W2. FIG. 21 exemplifies a case where the width of the trench type built-in gate resistance 4t in the portion where the trench type built-in gate resistance 4t faces the interlayer insulating film 11 is constant at the width dimension W2.

  The trench-type built-in gate resistor 4t includes a portion having a width dimension WE1 wider than the width dimension W2 in the portion facing the gate pad side contact hole 9a. The portion having the wide width dimension WE1 has a length dimension WE2 larger than the width dimension W2.

  Referring to FIG. 22, the portion having the width dimension W2 is located below interlayer insulating film 11, and is formed of polycrystalline silicon layer 12r. The portion having the width dimension WE1 includes a metal portion 22b1 having a specific resistance lower than that of the polycrystalline silicon layer 12r.

  The trench type built-in gate resistor 4t includes a portion having a width dimension WE1 wider than the width dimension W2 in the portion facing the main wiring side contact hole 9b. The portion having the wide width dimension WE1 has a length dimension WE2 larger than the width dimension W2.

  Referring to FIG. 23, the portion having the width dimension WE1 includes a metal portion 22b2 having a specific resistance lower than that of the polycrystalline silicon layer 12r.

  Referring to FIG. 21, gate electrode 13 has a width dimension W1 as a maximum width (a dimension in the vertical direction in the figure). The width dimension W1 is larger than the width dimension W2. FIG. 21 illustrates the case where the width of the gate electrode 13 is constant at the width dimension W1.

  Referring to FIG. 24, the portion where the gate electrode 13 has the width dimension W1 includes a metal portion 22a having a specific resistance lower than that of the polycrystalline silicon layer 12g.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  Next, a modification of the configuration of the trench type built-in gate resistor 4t in the present embodiment will be described.

  FIG. 25 and FIG. 26 are partial plan views schematically showing the configuration of the resistance element in which the metal portion is embedded in each of the first and second modifications of the semiconductor device according to the second embodiment of the present invention. It is. The broken line in the figure indicates the approximate positional relationship of the resistance element with respect to the field oxide film, the gate pad side contact hole, and the interlayer insulating film.

  Referring to FIG. 25, in the first modification, trench-type built-in gate resistor 4t has a portion having a width dimension WE1 larger than width dimension W2 at a portion facing gate pad side contact hole 9a. Yes. Further, the portion of the width dimension WE1 has a portion of a length dimension WE2 larger than the width dimension W2. The portion of the trench type built-in gate resistor 4t having the width dimension WE1 has a buried metal portion 22b1.

  Referring to FIG. 26, in the second modification, trench type built-in gate resistor 4t has a plurality of portions having a width dimension WE1 wider than width dimension W2 at the portion facing gate pad side contact hole 9a. ing. Each of the width dimension WE1 portions has a length dimension WE2 larger than the width dimension W2. Each of the width dimension WE1 portions of the trench-type built-in gate resistor 4t has a buried metal portion 22b1.

  In the first and second modified examples, the configuration in which a part of the metal portion 22 is embedded in the portion facing the gate pad side contact hole 9a has been described. However, the portion facing the main wiring side contact hole 9b is described. Can be configured similarly.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 27 to 32 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. Each of FIGS. 27 (a) to 32 (a) and FIGS. 27 (b) to 32 (b) shows a cross section corresponding to each of the XXXIIa-XXXIIa line and the XXXIIb-XXXIIb line of FIG. Yes.

  27A and 27B, an interlayer insulating film 11a made of a silicon oxide film or the like is deposited on the semiconductor substrate 101. The interlayer insulating film 11a is a film that becomes a part of the interlayer insulating film 11.

  Next, the interlayer insulating film 11a is patterned by photolithography. Etching of the semiconductor substrate 101 is performed using the patterned interlayer insulating film 11a as a mask. Thereby, the first groove T1 and the second groove T2 are formed. An insulating film 14b and a gate insulating film 14a are formed on the inner surfaces of the first trench T1 and the second trench T2 by oxidation or deposition, respectively.

  As a result, the first trench T1 covered with the insulating film 14b having the width dimension W2 is formed. A second trench T2 having a width dimension W1 and covered with the gate insulating film 14a is formed.

  Referring mainly to FIGS. 28A and 28B, a polycrystalline silicon layer 12 doped with a high concentration of impurities is deposited on a semiconductor substrate 101. By this deposition, as shown in FIG. 28A, the width dimension W2 (FIG. 27A) of the first groove T1 is completely filled. Further, only a part of the portion where the width dimension of the first groove T1 is WE1 (the portion facing the gate pad side contact hole 9aD in FIG. 22) is filled. In addition, as shown in FIG. 28B, only a part of the second groove T2 is filled.

  29A and 29B, a metal portion 22 made of a refractory metal or the like is deposited on the polycrystalline silicon layer 12 on the semiconductor substrate 101. As a result, the partially remaining groove is completely filled in the portion where the width dimension of the first groove portion T1 is WE1 (portion facing the gate pad side contact hole 9aD in FIG. 22). In addition, as shown in FIG. 29B, the second groove T2 is completely filled.

Next, the metal portion 22 and the polycrystalline silicon layer 12 are sequentially etched back.
Referring to FIGS. 30A and 30B, the interlayer insulating film 11a is exposed by the etch back.

Referring to FIGS. 31A and 31B, an interlayer insulating film 11 b is formed on the semiconductor substrate 101. As a formation method, for example, a method of depositing a BPSG (Boro-Phospho Silicate Glass) film and applying a heat treatment to planarize the surface of the insulating film is used. The interlayer insulating film 11b is a film that becomes a part of the interlayer insulating film 11.

  Referring mainly to FIGS. 32A and 32B, by selectively removing interlayer insulating films 11a and 11b, emitter contact hole 9d, gate pad side contact hole 9a (FIG. 21) and main A wiring side contact hole 9b (FIG. 21) is formed.

  Next, a metal film made of an electrode material such as aluminum or a compound thereof is deposited, and the deposited metal film is patterned. Thereby, emitter pad 18, gate pad metal layer 10a (FIG. 22) and main wiring metal layer 10b (FIGS. 23 and 24) are formed.

As described above, the IGBT chip as the semiconductor device of the present embodiment is formed.
The process of forming the n-type emitter region 15, the high-concentration p-type region 16, the p-type channel region 17 and the like on the semiconductor substrate 101 is performed before and after the formation of the first trench T1 and the second trench T2. Can be formed.

  Next, a method for manufacturing a semiconductor device in the third comparative example will be described. In addition, this comparative example is the structure by which the metal part 22 was attached | subjected with respect to the structure of the 2nd comparative example.

  33 to 38 are schematic cross-sectional views showing the method of manufacturing the semiconductor device in the third comparative example in the order of steps. 33A to FIG. 38A are schematic partial cross sections showing the vicinity of the planar built-in gate resistor 4p in the cross sectional position corresponding to the line XX-XX in FIG. 19 in the second comparative example. FIG. Moreover, FIG.33 (b)-FIG.38 (b) show the cross-sectional position corresponding to the XXXIIb-XXXIIb line | wire of FIG. 21 in Embodiment 2. FIG.

  Referring mainly to FIGS. 33 (a) and (b), steps similar to the steps up to FIGS. 29 (a) and (b) of the present embodiment are performed, but are different from the present embodiment. As a result, the first groove portion T1 is not formed. As a result, as shown in FIG. 33A, a planar built-in gate resistor 4p is formed along the flat substrate surface of the semiconductor substrate 101 instead of the trench built-in gate resistor 4t of the present embodiment.

  Referring to FIGS. 34A and 34B, a photoresist 31a is applied on semiconductor substrate 101. Next, as shown in FIG. 34A, the photoresist 31a is patterned by a photoengraving method. Thereby, a part of the metal portion 22 is exposed on the planar built-in gate resistor 4p.

  Referring to FIGS. 35A and 35B, the portion of metal portion 22 that is not covered with photoresist 31a is etched. Thereby, as shown to Fig.35 (a), the metal part 22 is isolate | separated into a some area | region. Thereafter, the photoresist 31a is removed.

  Referring mainly to FIGS. 36A and 36B, a photoresist 31b is applied on the semiconductor substrate 101. Next, the photoresist 31b is patterned by a photoengraving method so that the photoresist 31b covers the region where the planar built-in gate resistor 4p is formed and the vicinity of the gate electrode 13 is exposed. In the region not covered with the photoresist 31b, the metal part 22 and the polycrystalline silicon layer 12 (FIG. 35B) are sequentially etched back so that the interlayer insulating film 11a is exposed. Thereafter, the photoresist 31b is removed.

  Referring to FIGS. 37A and 37B, an interlayer insulating film 11 b is formed on the semiconductor substrate 101. As a formation method, for example, a method of depositing a BPSG (Boro-Phospho Silicate Glass) film and applying a heat treatment to planarize the surface of the insulating film is used.

  Referring to FIGS. 38A and 38B, interlayer insulating films 11a and 11b are selectively etched. As a result, contact holes such as the emitter contact hole 9d are formed. Next, the emitter pad 18, the gate pad metal layer 10a, and the main wiring metal layer 10b are formed.

  Thus, the semiconductor device of this comparative example is formed. In the manufacturing method of the semiconductor device of this comparative example, the metal portion 22 is partially etched using the mask made of the photoresist 31a from FIGS. 34 (a) and (b) to FIGS. 35 (a) and (b). The manufacturing process is complicated.

  Further, when the etching for removing the metal portion 22 is performed, the thickness of the planar built-in gate resistor 4p varies due to variations in overetching. As a result, the resistance value as the gate resistance of the planar built-in gate resistance 4p varies.

  According to the present embodiment, the portion having the width dimension WE1 (FIG. 21) of the trench built-in gate resistor 4t is such that the trench built-in gate resistor 4t faces the gate pad side contact hole 9aD as shown in FIG. The portion includes metal portion 22b1 in addition to polycrystalline silicon layer 12r. The metal portion 22b1 is a portion having a specific resistance lower than that of the polycrystalline silicon layer 12r. Therefore, local concentration of current between the gate pad 1 and the trench-type built-in gate resistor 4t is alleviated, and the reliability of the IGBT chip is increased.

  Further, as shown in FIG. 23, the portion having the width dimension WE1 (FIG. 21) of the trench-type built-in gate resistor 4t is the polycrystalline silicon layer 12r in the portion where the trench-type built-in gate resistor 4t faces the main wiring side contact hole 9bD. In addition, a metal portion 22b2 is included. The metal portion 22b2 has a specific resistance lower than that of the polycrystalline silicon layer 12r. Therefore, local concentration of current between the gate main wiring 5 and the trench-type built-in gate resistor 4t is alleviated, and the reliability of the IGBT chip is increased.

  Further, as shown in FIG. 21, the width dimension W1 of the gate electrode 13 is larger than the width dimension W2 of the trench-type built-in gate resistor 4t. That is, as shown in FIGS. 27A and 27B, the groove having the width W1 for forming the gate electrode 13 is wider than the groove having the width W2 for forming the trench-type built-in gate resistor 4t. Is big. Therefore, the entire groove having the width dimension W2 can be filled with the polycrystalline silicon layer 12, and at the same time, the width dimension W1 can not be completely filled. Therefore, as shown in FIG. 30, the metal portion 22a can be embedded in the unfilled portion.

  As described above, the entire trench having the width dimension W2 is filled with the polycrystalline silicon layer 12 having a relatively high specific resistance, whereby a trench-type built-in gate resistor 4t having a sufficiently high resistance value is obtained.

  At the same time, since the gate electrode 13 includes the metal portion 22a having a specific resistance lower than that of the polycrystalline silicon layer 12, the electric resistance of the gate electrode 13 can be suppressed. Therefore, variation in the propagation delay of the gate potential in the gate electrode 13 is suppressed. Therefore, the time in which the ON region and the OFF region are mixed in the switching operation of the IGBT element EL is suppressed. Therefore, the time during which the current flowing between the collector and the emitter of the IGBT element EL is concentrated in a part of the ON region can be shortened. Therefore, local heat generation in a part of the ON region is suppressed, so that the reliability of the IGBT chip can be improved.

[Embodiment 3]
First, the configuration of the IGBT chip as the semiconductor device of the present embodiment will be described. FIG. 39 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in the third embodiment of the present invention.

  Referring to FIG. 39, trench type built-in gate resistance 4t which is a resistance element of the semiconductor device of the present embodiment has n-type low-concentration polycrystalline silicon layer 23a which is a semiconductor region as a main part. The trench-type built-in gate resistor 4t has an n-type high-concentration polycrystalline silicon layer 24a provided in a portion in contact with the gate pad side contact hole 9a and the main wiring side contact hole 9b.

  The difference between the present embodiment and the semiconductor device shown in the first and second embodiments is that the main part of the material embedded in the trench-type built-in gate resistor 4t has a concentration higher than that in the first and second embodiments. By adjusting the potential difference between the trench-type built-in gate resistor 4t and the p-type region 21 in contact therewith, the n-type low-concentration polycrystalline silicon layer 23a is in the accumulation state, depletion state, and inversion state. Of these, at least two states can be taken.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of the resistance element in the semiconductor device of this embodiment will be described. 43 to 45 are explanatory diagrams for explaining the operation of the resistance element of the semiconductor device according to the third embodiment of the present invention. In the figure, V _23H and V _23L respectively indicate potentials at both ends of the current path of the n-type low concentration polycrystalline silicon layer 23a. V ₂₁ is a potential on the insulating film 14 b side of the semiconductor substrate 101, and indicates the potential of the p-type region 21 when the semiconductor substrate 101 has the p-type region 21.

Referring to FIG. 43, when V ₂₁ is applied so as to satisfy V ₂₁ > V _23L >> V _23H , n-type low-concentration polycrystalline silicon layer 23a is in an accumulation state. That is, an electron storage layer 32a is formed on the surface of the n-type low-concentration polycrystalline silicon layer 23a on the insulating film 14b side. In this case, electrons as carriers are distributed over the entire n-type low-concentration polycrystalline silicon layer 23a, so that the entire n-type low-concentration polycrystalline silicon layer 23a can serve as a current path in the trench-type built-in gate resistor 4t.

Referring to FIG. 44, V ₂₁ is _{0> (V 2 1-V} 23L)> when applied to satisfy (V _th at V _23L), n-type lightly doped polycrystalline silicon layer 23a is depleted It becomes. That is, the depletion layer 32d is formed on the surface of the n-type low concentration polycrystalline silicon layer 23a on the insulating film 14b side. In this case, the depletion layer 32d portion does not serve as a current path in the trench built-in gate resistor 4t, so that the resistance value of the trench built-in gate resistor 4t increases. In the above equation, V _th is a potential that reaches a threshold value as to whether or not the n-type low-concentration polycrystalline silicon layer 23a can flow current.

Referring to FIG. 45, when V ₂₁ is applied so that 0> (V _th at V _23H )> (V ₂₁ −V _23H ), n-type low-concentration polycrystalline silicon layer 23a is in an inverted state. Become. That is, the depletion layer 32d and the inversion layer 32i are formed on the surface of the n-type low concentration polycrystalline silicon layer 23a on the insulating film 14b side. In this case, the portion of the depletion layer 32d does not become a current path in the trench type built-in gate resistor 4t. The inversion layer 32i is separated from the current path of the trench-type built-in gate resistor 4t by the depletion layer 32d. Therefore, the resistance value of the trench type built-in gate resistance 4t further increases.

  Each of FIGS. 40 to 42 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in each of first to third modifications of the third embodiment of the present invention.

  Referring to FIG. 40, trench-type built-in gate resistor 4t, which is a resistance element of the semiconductor device of the first modification of the present embodiment, is different from the present embodiment in that gate pad side contact hole 9a and A p-type high-concentration polycrystalline silicon layer 24b is further provided at a portion in contact with the main wiring side contact hole 9b.

  Referring to FIG. 41, trench-type built-in gate resistor 4t which is a resistance element of the semiconductor device of the second modification of the present embodiment has, as a main part, p-type low-concentration polycrystalline silicon layer 23b which is a semiconductor region. have. The trench-type built-in gate resistor 4t has a p-type high-concentration polycrystalline silicon layer 24b provided in a portion in contact with the gate pad side contact hole 9a and the main wiring side contact hole 9b.

  Referring to FIG. 42, the trench-type built-in gate resistor 4t, which is the resistance element of the semiconductor device of the third modification of the present embodiment, is different from the second modification of the present embodiment in that the gate It further has an n-type high-concentration polycrystalline silicon layer 24a provided in a portion in contact with the pad side contact hole 9a and the main wiring side contact hole 9b.

  When the gate resistance in the depletion state is very high for the purpose of obtaining a desired gate delay, the trench type built-in gate resistance 4t (FIG. 1A) in the first embodiment and the trench type built-in gate resistance in the second embodiment are used. It may be used in combination with 4t (FIGS. 22 and 23).

  Further, when the gate electrode 13 and the trench-type built-in gate resistor 4t are formed in separate steps, it is possible to dope polycrystalline silicon at different concentrations in each step. Thus, if the resistance is lowered by increasing the doping concentration of the gate electrode 13 and the gate main wiring 5, the delay and loss of the IGBT chip can be suppressed.

  According to the present embodiment, a depletion layer is generated in the n-type low-concentration polycrystalline silicon layer 23a of the trench-type built-in gate resistance 4t due to a potential difference between the p-type region 21 and the trench-type built-in gate resistance 4t, thereby forming a trench type. The resistance value of the built-in gate resistor 4t can be adjusted.

  In addition, since the n-type high-concentration polycrystalline silicon layer 24a is formed at the contact portion of the trench-type built-in gate resistor 4t, the gate resistance increases with time when the IGBT element EL is turned off. Thereby, the surge of the IGBT element EL can be reduced.

Further, according to each of the first and third modifications of the present embodiment, the n-type high-concentration polycrystalline silicon layer 24a and the p-type high-concentration polycrystalline silicon layer are provided in the electrical contact portion of the trench-type built-in gate resistor 4t. 24b is formed. As a result, the gate resistance in the accumulation state is reduced, and the delay time is stabilized particularly when a potential of V _g <0 V is applied.

[Embodiment 4]
First, the structure of the resistance element included in the semiconductor device of this embodiment will be described. FIG. 46 is a partial cross sectional view schematically showing a configuration in the vicinity of the resistance element of the semiconductor device in the fourth embodiment of the present invention.

  Referring to FIG. 46, the IGBT chip of the present embodiment has a diode-type built-in gate resistor 4d as a resistance element. The diode-type built-in gate resistor 4d includes a p-type high-concentration polycrystalline silicon layer 24b, an n-type low-concentration polycrystalline silicon layer 23a, and an n-type high-concentration polycrystalline silicon layer 24a. The n-type low-concentration polycrystalline silicon layer 23a is electrically connected to each of the gate pad 1 and the gate main wiring 5 through the p-type high-concentration polycrystalline silicon layer 24b and the n-type high-concentration polycrystalline silicon layer 24a. It is connected.

  With the above configuration, the diode-type built-in gate resistor 4d of the present embodiment has a diode having a pn junction surface at the interface between the p-type high-concentration polycrystalline silicon layer 24b and the n-type low-concentration polycrystalline silicon layer 23a (diode in the figure). Symbol).

  Note that the selection range of the impurity concentration of the n-type low-concentration polycrystalline silicon layer 23a in this embodiment is wider than that in the third embodiment. In other words, as described above, the impurity concentration of n-type low-concentration polycrystalline silicon layer 23a in the third embodiment is adjusted so that it can take at least two states among an inverted state, an accumulation state, and a depletion state. This form is not subject to such restrictions.

  Since the configuration other than the above is substantially the same as the configuration of the third embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  Next, the operation of the resistance element in the semiconductor device of this embodiment will be described. In the initial and final stages of the switching operation of the IGBT element EL (not shown in FIG. 46), the potential difference between both ends of the diode-type built-in gate resistor 4d which is the gate resistance of the gate electrode 13 (not shown in FIG. 46) is small. The diode has a high resistance when the potential difference between the anode and the cathode is small, and conversely, it has a low resistance when the potential difference between both ends is large. For this reason, the diode-type built-in gate resistor 4d has a higher resistance value in the initial stage and the final stage than in the middle stage of the switching operation.

  Next, a modification of the semiconductor device of this embodiment will be described. 47 to 49 are partial cross sectional views schematically showing a configuration of a resistance element in each of first to third modifications of the semiconductor device according to the fourth embodiment of the present invention.

  Referring to FIG. 47, in the first modification of the present embodiment, diode-type built-in gate resistor 4d has an interface between p-type low-concentration polycrystalline silicon layer 23b and n-type high-concentration polycrystalline silicon layer 24a. Includes a diode having a pn junction surface (diode symbol in the figure).

  Referring to FIG. 48, in the second modification of the present embodiment, unlike the present embodiment, diode-type built-in gate resistor 4d is not embedded in the trench of semiconductor substrate 101, and is formed on field oxide film 7. Is formed.

  Referring to FIG. 49, in the third modification of the present embodiment, the conductivity types of the diodes in the second modification are switched.

  According to the present embodiment, the diode-type built-in gate resistor 4d has a higher resistance value at the initial stage and the final stage than in the middle stage of the switching operation of the IGBT element EL. Therefore, the occurrence of surge is suppressed. Thereby, an IGBT chip with a small loss can be obtained.

  In addition, when a rapidly changing noise signal with a small pulse width is applied to the gate pad 1, the response of the potential of the gate electrode 13 to the noise signal can be blunted, and malfunction of the IGBT element EL can be suppressed.

  When the concentration of n-type low-concentration polycrystalline silicon layer 23a in FIG. 46 is the same as that in the third embodiment, the same effect as in the third embodiment is also expected.

  The diode-type built-in gate resistor 4d of the present embodiment has a resistance value due to the potential difference between the resistor element which is the ohmic gate resistor shown in the first embodiment and the p-type region 21 shown in the third embodiment. It may be combined with a variable resistance element or a conventional resistance element. This combination can be performed by, for example, parallel connection.

  In this case, it is possible to bring the switching waveform closer to a desired one by finely controlling the gate resistance value by the gate potential or the potential difference between both ends of the gate.

[Embodiment 5]
The semiconductor element in the semiconductor device of the present embodiment has a diode as in the fourth embodiment (FIG. 46). However, the diode included in the resistance element of the present embodiment is a Zener diode in which the n-type low-concentration polycrystalline silicon layer 23a has a high impurity concentration and a low reverse breakdown voltage. That is, the resistance element of the present embodiment is a Zener diode type gate resistance. This Zener diode is set so as to have a constant breakdown voltage by utilizing the reverse characteristics.

  Since the configuration other than the above is substantially the same as the configuration of the fourth embodiment described above, the description thereof is omitted.

  According to the present embodiment, the gate electrode 13 is not charged / discharged when noise having a breakdown voltage or lower is applied to the gate. Thereby, malfunction of the IGBT chip can be suppressed.

[Embodiment 6]
First, the structure of the resistance element included in the semiconductor device of this embodiment will be described. 50 and 51 are each a plan view schematically showing a configuration of a resistance element of the semiconductor device in each of the sixth embodiment of the present invention and the modifications thereof. The broken line in the drawing shows the approximate positional relationship of the resistance elements with respect to the gate pad side contact hole 9a, the main wiring side contact hole 9b, and the interlayer insulating film 11.

  Referring to FIG. 50, the semiconductor device of the present embodiment has a plurality of diodes as resistance elements between gate pad side contact hole 9a and main wiring side contact hole 9b. That is, the gate pad 1 (not shown in FIG. 50) and the gate main wiring 5 (not shown in FIG. 50) have a plurality of resistance elements electrically connected in parallel to each other.

  The plurality of diodes include at least one forward diode-type built-in gate resistor 4f and at least one reverse diode-type built-in gate resistor 4r. Here, the forward direction and the reverse direction are the polarities of the diode based on the direction from the gate pad 1 to the gate main wiring 5.

  Preferably, the number of trench-type built-in gate resistors 4t is different from the number of diode-type built-in gate resistors 4r in the reverse direction.

  Since the configuration other than the above is substantially the same as the configuration of the above-described fourth or fifth embodiment, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  According to the present embodiment, the same effect as in the fourth or fifth embodiment can be obtained when switching of the IGBT element EL is turned on and off.

  In addition, the number of the diode-type built-in gate resistors 4f in the forward direction is different from the number of the diode-type built-in gate resistors 4r in the reverse direction, so that the plurality of resistance elements include the gate pad 1, the gate main wiring 5, and the like. It functions as a resistance element having a different resistance value depending on the current direction. Therefore, it is possible to form resistance elements having different electric resistances when the IGBT element EL is on and off.

  As shown in the modification of FIG. 51, the resistance element of the present embodiment is the same as the resistance element that is the ohmic gate resistance shown in the first embodiment, or the p-type region 21 shown in the third embodiment. A resistance element whose resistance value changes due to the potential difference between the two or a built-in gate resistance 4i which is a conventional resistance element may be included.

[Embodiment 7]
First, the structure of the resistance element included in the semiconductor device of this embodiment will be described. FIG. 52 is a partial cross sectional view schematically showing a configuration in the vicinity of the resistance element of the semiconductor device in the seventh embodiment of the present invention.

  Referring to FIG. 52, the IGBT chip of the present embodiment has a JFET type built-in gate resistor 4j which is a resistance element including a junction field effect transistor (JFET). The JFET type built-in gate resistor 4j includes a p-type low-concentration polycrystalline silicon layer 23b serving as a channel region, a pair of p-type high-concentration polycrystalline silicon layers 24b and 24b serving as source / drain regions, and an n-type serving as a gate. And a high-concentration polycrystalline silicon layer 25.

  An electrode 26 electrically connected to the n-type high concentration polycrystalline silicon layer 25 is formed on the n-type high concentration polycrystalline silicon layer 25. The electrode 26 has a function of controlling the potential of the n-type high concentration polycrystalline silicon layer 25.

  Next, the operation of the resistance element of this embodiment will be described. The potential of the n-type high concentration polycrystalline silicon layer 25 is controlled by the electrode 26. As a result, the depth dimension (the dimension in the vertical direction in the figure) in which the depletion layer 27 spreads is controlled, so that the resistance value of the JFET type built-in gate resistor 4j is controlled.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  According to the present embodiment, the resistance value of the resistance element can be changed by applying a potential signal to the electrode 26 from the outside of the resistance element.

  In the above description, the JFET type built-in gate resistor 4j including the p-channel type JFET has been described as the resistance element. However, a JFET type built-in gate resistor including the n-channel type JFET may be used.

  In the above description, the JFET-type built-in gate resistor 4j embedded in the first trench T1 is described as the resistance element. However, the resistance element may be a planar type.

  In order to obtain the same effect as in the sixth embodiment, for example, the number of electrodes 26 connected to n-type high-concentration polycrystalline silicon layer 25 may be changed between on and off.

[Embodiment 8]
FIG. 53 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in an eighth embodiment of the present invention. Referring to FIG. 53, the IGBT chip of the present embodiment has a junction control diode type built-in gate resistor 4k as a resistance element.

  Junction control diode type built-in gate resistor 4k has a pn junction surface at the interface between p-type low-concentration polycrystalline silicon layer 23b and n-type high-concentration polycrystalline silicon layer 24a. As a result, the junction control diode type built-in gate resistor 4k includes a diode.

  Since the configuration other than this is substantially the same as that of the above-described seventh embodiment (FIG. 52), the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  According to the present embodiment, the resistance value of the resistance element can be changed by applying a potential signal to the electrode 26 from the outside of the resistance element. In addition, the same effects as in the fourth and fifth embodiments can be obtained.

  As the resistance element, a resistance element in which the conductivity type of the above-described junction control diode type built-in gate resistance 4k is reversed can also be used.

  FIG. 53 shows the junction control diode type built-in gate resistor 4k embedded in the first trench T1, but the resistance element may be a planar type.

  In order to obtain the same effect as in the sixth embodiment, for example, the number of electrodes 26 connected to n-type high-concentration polycrystalline silicon layer 25 may be changed between on and off.

[Embodiment 9]
FIG. 54 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in Embodiment 9 of the present invention. Referring to FIG. 54, the IGBT chip as the semiconductor device of the present embodiment has a MOS (Metal Oxide Semiconductor) type gate resistor 4m which is a resistance element including a MIS (Metal Insulator Semiconductor) type field effect transistor. Yes. The IGBT chip has an electrode 26 for controlling the gate potential of the MOS type gate resistor 4m itself.

  The MOS type gate resistance 4m includes a p-type low-concentration polycrystalline silicon layer 23b, a pair of n-type high-concentration polycrystalline silicon layers 24a and 24a, a built-in gate resistance control gate electrode 28, and a built-in gate resistance control gate insulating film. 29.

  The p-type low-concentration polycrystalline silicon layer 23b forms a channel region of the MOS-type gate resistance 4m. One set of n-type high-concentration polycrystalline silicon layers 24a, 24a functions as a source / drain region for the channel region. The built-in gate resistance control gate electrode 28 has a function of controlling the carrier concentration in the channel region in accordance with the potential of the built-in gate resistance control gate electrode 28. The built-in gate resistance control gate insulating film 29 insulates the built-in gate resistance control gate electrode 28 from the p-type low-concentration polycrystalline silicon layer 23b. The electrode 26 has a function of controlling the potential of the built-in gate resistance control gate electrode 28.

  Since the configuration other than this is substantially the same as that of the third modified example (FIG. 49) of the fourth embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted. .

  According to the present embodiment, the resistance value of the resistance element can be changed by applying a potential signal to the electrode 26 from the outside of the resistance element. In addition, the same effects as in the fourth and fifth embodiments can be obtained.

  Although the description of the present embodiment has been made using the n-channel MOS gate resistor 4m, the MOS-type gate resistor 4m may be a p-channel type.

  Further, although FIG. 54 shows a planar MOS gate resistor 4m, the resistor element may be a trench type embedded in the first groove T1.

  The MOS transistor included in the MOS gate resistor 4m may be either an enhancement type or a depletion type.

  In order to obtain the same effect as in the sixth embodiment, for example, the number of electrodes 26 connected to the built-in gate resistance control gate electrode 28 may be changed between on and off.

[Embodiment 10]
FIG. 55 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in Embodiment 10 of the present invention. Referring to FIG. 55, the IGBT chip as the semiconductor device of the present embodiment has a gate control diode type gate resistor 4g as a resistance element. The IGBT chip has an electrode 26 for controlling the gate potential of the gate control diode type gate resistor 4g itself.

  The gate control diode type gate resistor 4g includes a p-type low concentration polycrystalline silicon layer 23b, a p-type high concentration polycrystalline silicon layer 24b, an n-type high concentration polycrystalline silicon layer 24a, a built-in gate resistance control gate electrode 28, And a built-in gate resistance control gate insulating film 29.

  Since the configuration other than this is substantially the same as that of the above-described ninth embodiment (FIG. 54), the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

  According to the present embodiment, the resistance value of the resistance element can be changed by applying a potential signal to the electrode 26 from the outside of the resistance element. In addition, the same effects as in the fourth and fifth embodiments can be obtained. In addition, the same effects as in the fourth and fifth embodiments can be obtained.

  Although the description of the present embodiment has been made using the n-channel gate control diode type gate resistor 4g, the gate control diode type gate resistor 4g may be a p-channel type.

  FIG. 55 shows the planar gate control diode type gate resistor 4g, but the resistance element may be a trench type embedded in the first groove T1.

  In order to obtain the same effect as in the sixth embodiment, for example, the number of electrodes 26 connected to the built-in gate resistance control gate electrode 28 may be changed between on and off.

[Embodiment 11]
First, the structure of the resistance element included in the semiconductor device of this embodiment will be described. 56 (a) and 56 (b) are partial cross sectional views schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in each of the eleventh embodiment of the present invention and its modification.

  Referring to FIG. 56 (a), the semiconductor device in the present embodiment includes an n-type low-concentration polycrystalline silicon layer 23a, a pair of n-type high-concentration polycrystalline silicon layers 24a and 24a, as resistance elements. a p-type high-concentration polycrystalline silicon layer 24b. This resistance element is formed on the insulating film IL. The insulating film IL is the field oxide film 7 or the insulating film 14b. Further, the semiconductor device has a set of metal layers 10 on the resistance element.

  A set of n-type high-concentration polycrystalline silicon layers 24a, 24a is electrically connected to each other via an n-type low-concentration polycrystalline silicon layer 23a. Since the n-type high-concentration polycrystalline silicon layer 24a and the n-type low-concentration polycrystalline silicon layer 23a have the same conductivity type, the pair of n-type low-concentration polycrystalline silicon layers 23a and 23a has an ohmic resistance. It functions as a built-in gate resistor 4i.

  The p-type high concentration polycrystalline silicon layer 24b is provided between the pair of n-type high concentration polycrystalline silicon layers 24a and 24a. Between one n-type high-concentration polycrystalline silicon layer 24a and the p-type high-concentration polycrystalline silicon layer 24b in the set of n-type high-concentration polycrystalline silicon layers 24a, the n-type low concentration is present. They are electrically connected via the polycrystalline silicon layer 23a.

  Since the p-type high-concentration polycrystalline silicon layer 24b and the n-type low-concentration polycrystalline silicon layer 23a have different conductivity types, a pn junction is formed at the interface between them. That is, between the p-type high concentration polycrystalline silicon layer 24b and the n-type high concentration polycrystalline silicon layer 24a, the forward direction from the p-type high concentration polycrystalline silicon layer 24b toward the n-type high concentration polycrystalline silicon layer 24a A diode-type built-in gate resistor 4d including the diode is formed.

  With the above configuration, the resistance element of the present embodiment includes a region having a monolithic diode and an ohmic resistor in parallel.

  One (left side in the figure) of the pair of metal layers 10, 10 is formed on one (left side in the figure) n-type high-concentration polycrystalline silicon layer 24a so as to be in contact with each other. Yes.

  The other (right side in the figure) metal layer 10 of the pair of metal layers 10 and 10 is p-type high density polycrystalline silicon from the other (right side in the figure) n-type high density polycrystalline silicon layer 24a. It is formed over the layer 24b. The other metal layer 10 is formed in contact with each of the other n-type high concentration polycrystalline silicon layer 24a and p-type high concentration polycrystalline silicon layer 24b. The other metal layer 10 and the n-type low-concentration polycrystalline silicon layer 23a are electrically insulated by the interlayer insulating film 11.

  With the configuration of the other metal layer 10 described above, an ohmic structure in which a part of the other metal layer 10 is connected in parallel between the other n-type high-concentration polycrystalline silicon layer 24a and the p-type high-concentration polycrystalline silicon layer 24b. A function as a simple resistor 30.

  In addition, since it is substantially the same as Embodiment 1-10 mentioned above about the structure other than this, the same code | symbol is attached | subjected about the same or corresponding element, and the description is abbreviate | omitted.

Next, an outline of the operation of the resistance element included in the semiconductor device of this embodiment will be described.
When the p-type high-concentration polycrystalline silicon layer 24b side has a low potential, the resistance element functions as a normal built-in gate resistor 4i using the n-type low-concentration polycrystalline silicon layer 23a as a resistance.

  When the p-type high-concentration polycrystalline silicon layer 24b side has a high potential, the relationship between the resistance value of the resistor 30 connected in parallel and the impurity concentration of the n-type low-concentration polycrystalline silicon layer 23a is appropriately adjusted. A parallel operation of the diode and the resistor is realized.

  Referring to FIG. 56B, in the modification of the present embodiment, p-type high-concentration polycrystalline silicon layer 24b is one of a pair of n-type high-concentration polycrystalline silicon layers 24a, 24a (FIG. Along with the n-type high-concentration polycrystalline silicon layer 24a on the left side (middle left), the n-type high-concentration polycrystalline silicon layer 24a on the other side (right side in the figure) is provided. Between one set of n-type high-concentration polycrystalline silicon layers 24a and 24a (left side in the figure) n-type high-concentration polycrystalline silicon layer 24a and p-type high-concentration polycrystalline silicon layer 24b is n-type low. They are electrically connected via the concentration polycrystalline silicon layer 23a.

Next, details of the operation of the resistance element included in the semiconductor device of this embodiment will be described.
FIGS. 57 (a) and 57 (b) are diagrams showing an equivalent circuit of the resistance element of the semiconductor device in each of the eleventh embodiment and the modifications thereof.

Referring to FIGS. 56 (a) and 57 (a), in this embodiment, potential V ₀ is the potential of one metal layer 10 (left side in the figure). The potential V ₁ is a potential at a portion in contact with the other (right side in the figure) n-type high-concentration polycrystalline silicon layer 24a of the other (right side in the figure). The potential V _x is a potential at a portion in contact with the p-type high concentration polycrystalline silicon layer 24b of the other metal layer 10 (right side in the drawing).

The resistance R ₀ is a resistance of a portion between one (left side in the figure) of the n-type high concentration polycrystalline silicon layer 24a and the p-type high concentration polycrystalline silicon layer 24b in the built-in gate resistance 4i. The resistor R1 is the resistance of the portion between the other (right side in the figure) n-type high-concentration polycrystalline silicon layer 24a and p-type high-concentration polycrystalline silicon layer 24b in the built-in gate resistor 4i. Resistor R ₂ is resistor 30.

Each of the currents i ₀ , i ₁ and i ₂ is a current flowing through each of the resistors R ₀ , R ₁ and R ₂ .

Referring to FIG. 56 (b) and FIG. 57 (b), in a variation of this embodiment, p-type heavily doped polycrystalline silicon layer in the metal layer 10 of the potential V ₁ was other (right side in the drawing) This is the potential at the portion in contact with 24b. The potential V _x is a potential at a portion in contact with the other (right side in the figure) n-type high concentration polycrystalline silicon layer 24a.

The resistor R ₀ is the resistance of a portion between the pair of n-type high-concentration polycrystalline silicon layers 24a and 24a in the built-in gate resistor 4i. The resistor R ₁ is the resistor 30. The resistor R ₂ is the resistance of the portion between the other (right side in the figure) n-type high-concentration polycrystalline silicon layer 24a and p-type high-concentration polycrystalline silicon layer 24b in the built-in gate resistor 4i.

FIG. 58A is an explanatory diagram of voltage-current characteristics when R ₂ << R ₁ << R ₀ of the resistance elements of the semiconductor device according to the eleventh embodiment of the present invention and the modification thereof. FIG. 58B is an explanatory diagram of voltage-current characteristics when R ₁ >> R ₂ >> R ₀ of the resistance element of the semiconductor device according to the eleventh embodiment of the present invention and the modification thereof.

58 (a) and 58 (b), the vertical axis in the graph indicates each of currents i ₀ , i ₁ , i ₂ . The horizontal axis represents the V ₁ -V _x for currents i _1, i ₂ indicated by a broken line, shows the V ₁ -V ₀ for current i _0. Φ is a function of the voltage-current characteristic of the diode.

In order for the diode to be forward-biased by the voltage drop (V ₁ −V _x ) generated in the resistor R ₁ , which is a part of the resistance component, a predetermined current _if and a voltage V _f are required for the diode current to start flowing. At that time, the voltage V ₁ -V ₀ is applied to the entire resistance element so that V ₁ -V _x = V _f . If the current through the diode is not less than the current i _f, the current depends on the ratio of the resistance R ₂ of the resistor R ₁ and a diode side is a part has a resistance component flows. However, when current flows through the diode, the resistance R ₀ and the resistance R ₂ in FIG.

When R ₂ << R ₁ << R ₀ , a large current _If is required. _{Therefore, i 0 = (V 1 -V} 0) to large at the _{(V 1 -V 0) / (} R 1 + R 0) current flows, then the diode is turned on the resistance R ₂ is lower. That is, a snapback SB showing a negative resistance occurs.

In the case of R ₁ >> R ₂ >> R ₀ , the snap-back SB does not occur because the diode is turned on even if _If is small. Further, when (V ₁ −V ₀ ) <0, no current flows through the diode, and therefore a current of i ₀ = (V ₁ −V ₀ ) / (R ₁ + R ₀ ) flows.

  According to the present embodiment, the resistive element has a diode and an ohmic resistor in parallel in a monolithic manner. Therefore, the same effect as that of the semiconductor device shown in the modification of the sixth embodiment (FIG. 51) can be achieved with a small area.

  Further, as shown in FIG. 58 (a), the resistance characteristic by the snapback SB can also be realized. Therefore, when both ends of the resistance element have a constant potential difference, charging / discharging of the IGBT element EL to the gate electrode 13 can be accelerated by snapback. Note that the modified example is more likely to cause snapback SB than the present embodiment unless the resistance 30 is increased.

  In order to change the resistance value of at least a part of the n-type low-concentration polycrystalline silicon layer 23a, the distance between the other n-type high-concentration polycrystalline silicon layer 24a and the p-type high-concentration polycrystalline silicon layer 24b It is also effective to change the concentration of the n-type low-concentration polycrystalline silicon layer 23a at least partially.

  In addition, the resistive element may be a trench type or a planar type as long as the high concentration layer located in the middle does not block the current path.

  Further, the configuration in which the conductivity type in the configuration of the present embodiment is inverted is a configuration substantially equivalent to the present invention.

[Embodiment 12]
First, the structure of the resistance element included in the semiconductor device of this embodiment will be described. FIG. 59 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in Embodiment 12 of the present invention.

  Referring to FIG. 59, the semiconductor device according to the present embodiment includes an n-type low-concentration polycrystalline silicon layer 23a, a set of n-type high-concentration polycrystalline silicon layers 24a and 24a, and a set of resistance elements. p-type high-concentration polycrystalline silicon layers 24b and 24b. This resistance element is formed on the insulating film IL. The insulating film IL is the field oxide film 7 or the insulating film 14b. Further, the semiconductor device has a set of metal layers 10 on the resistance element.

  Each of the set of n-type high-concentration polycrystalline silicon layers 24a and 24a and the set of p-type high-concentration polycrystalline silicon layers 24b and 24b is formed on the n-type low-concentration polycrystalline silicon layer 23a.

  One (left side in the figure) p-type high-concentration polycrystalline silicon layer 24b and the other (right side in the figure) n-type high-concentration polycrystalline silicon layer 24a are the length of the n-type low-concentration polycrystalline silicon layer 23a. It is electrically connected through a portion having a length L1. One (left side in the figure) n-type high-concentration polycrystalline silicon layer 24a and the other (right side in the figure) p-type high-concentration polycrystalline silicon layer 24b are the length of the n-type low-concentration polycrystalline silicon layer 23a. It is electrically connected via a portion having a length L2.

  The pair of n-type high-concentration polycrystalline silicon layers 24a and 24a are electrically connected through the length L3 portion of the n-type low-concentration polycrystalline silicon layer 23a. Since the n-type high-concentration polycrystalline silicon layer 24a and the n-type low-concentration polycrystalline silicon layer 23a have the same conductivity type, the pair of n-type low-concentration polycrystalline silicon layers 23a and 23a has an ohmic resistance. It functions as a built-in gate resistor 4i.

  One (left side in the figure) n-type high-concentration polycrystalline silicon layer 24a and one p-type high-concentration polycrystalline silicon layer 24b are electrically connected by a metal layer 10 with a resistor 30. . The other (right side in the figure) n-type high-concentration polycrystalline silicon layer 24a and the other p-type high-concentration polycrystalline silicon layer 24b are electrically connected by the other metal layer 10 with a resistor 30. Yes.

  The interface between one (left side in the figure) p-type high-concentration polycrystalline silicon layer 24b and n-type low-concentration polycrystalline silicon layer 23a and the other (right side in the figure) p-type high-concentration polycrystalline silicon layer 24b and n A pn junction is formed at each of the interfaces with the type low-concentration polycrystalline silicon layer 23a. That is, a pair of pn junction diodes are formed.

  From one (left side in the figure) of the metal layer 10, one p-type high concentration polycrystalline silicon layer 24b, n-type low concentration polycrystalline silicon layer 23a, and the other (right side in the figure) p-type high concentration polycrystalline silicon. With respect to the current direction toward the other metal layer 10 via the layer 24b, one of the pair of diodes has a forward polarity, and the other diode has a reverse polarity. Yes.

  With the above configuration, the resistance element of the present embodiment includes a pair of regions each having a diode and an ohmic resistor in parallel, and the polarities of the diodes included in each of the pair of regions are different from each other.

  Since the configuration other than this is almost the same as that of the above-described eleventh embodiment, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of the resistance element included in the semiconductor device of this embodiment will be described.
When one side (left side in the figure) of the metal layer 10 side (E1 side in the figure) has a higher potential than the other side (right side in the figure) side (E2 side in the figure), n The diode in the region of the length L1 of the type low-concentration polycrystalline silicon layer 23a is activated by applying a forward voltage. On the other hand, the diode in the region of the length dimension L2 of the n-type low-concentration polycrystalline silicon layer 23a is inactivated by applying a reverse voltage.

  Conversely, when the E1 side is set to a lower potential than the E2 side, the diode in the region of the length dimension L1 of the n-type low-concentration polycrystalline silicon layer 23a is applied with a reverse voltage and becomes inactive. On the other hand, the diode in the region of the length dimension L2 of the n-type low-concentration polycrystalline silicon layer 23a is activated by applying a forward voltage.

  Note that the resistance of the length L3 of the n-type low-concentration polycrystalline silicon layer 23a is activated regardless of the potential relationship between the E1 side and the E2 side.

  According to the present embodiment, the resistance value of the resistance element can be independently adjusted for each voltage direction between the E1 side and the E2 side by changing the length dimensions L1 and L2. Therefore, the gate resistance when the switching of the IGBT element EL is turned on and off can be adjusted independently.

  Similarly to the structure of the eleventh embodiment shown in FIG. 56 (a), the negative resistance characteristic due to snapback can be realized when the potential difference between both ends of the resistance element reaches a certain value. For this purpose, the value of the resistance 30 of the metal layers 10 connected in parallel is increased, the resistance of at least a part of the n-type low-concentration polycrystalline silicon layer 23a is decreased, or the metal layers 10 are connected to each other. The distance between the n-type high concentration polycrystalline silicon layer 24a and the p-type high concentration polycrystalline silicon layer 24b may be reduced.

  Similarly to the relationship between the structure of FIG. 56 (a) and the structure of FIG. 56 (b) in the eleventh embodiment, n-type high-concentration polycrystalline silicon layer 24a and p-type high-concentration polycrystalline silicon in FIG. The arrangement with the layer 24b may be changed.

  In addition, the resistive element may be a trench type or a planar type as long as the high concentration layer located in the middle does not block the current path.

  Further, the configuration in which the conductivity type in the configuration of the present embodiment is inverted is a configuration substantially equivalent to the present invention.

[Embodiment 13]
First, the structure of the resistance element included in the semiconductor device of this embodiment will be described. FIG. 60 is a partial cross sectional view schematically showing a configuration in the vicinity of a resistance element of a semiconductor device in Embodiment 13 of the present invention.

  Referring to FIG. 60, the semiconductor device in the present embodiment includes a p-type low-concentration polycrystalline silicon layer 23b, a set of n-type high-concentration polycrystalline silicon layers 24a and 24a, and a set of resistance elements. P-type high-concentration polycrystalline silicon layers 24b and 24b, a built-in gate resistance control gate insulating film 29, and a built-in gate resistance control gate electrode 28 are provided. In addition, the semiconductor device has an electrode 26 and a pair of metal layers 10 and 10 on the resistance element.

  The pair of p-type high-concentration polycrystalline silicon layers 24b and 24b are provided on the p-type low-concentration polycrystalline silicon layer 23b and are electrically connected to each other via the p-type low-concentration polycrystalline silicon layer 23b. Yes. Since the conductivity type of the p-type high-concentration polycrystalline silicon layer 24b and the p-type low-concentration polycrystalline silicon layer 23b is the same, there is a normal built-in gate resistance between the pair of p-type high-concentration polycrystalline silicon layers 24b and 24b. 4i functions.

  A set of n-type high-concentration polycrystalline silicon layers 24a and 24a is provided on the p-type low-concentration polycrystalline silicon layer 23b. A built-in gate resistance control gate insulating film 29 and a built-in gate resistance control gate electrode 28 are formed on the p-type low concentration polycrystalline silicon layer 23b positioned between the pair of n-type high concentration polycrystalline silicon layers 24a and 24a. Are provided in this order. With this configuration, the resistance element of the present embodiment has a MIS type structure, and includes the same structure as the MOS type gate resistance 4m (FIG. 54) of the ninth embodiment.

  A semiconductor layer such as the p-type low-concentration polycrystalline silicon layer 23b in the MIS type structure is provided on the insulating film IL. That is, the resistance element has an SOI type structure.

  The IGBT chip has an electrode 26 for controlling the gate potential of the MOS type gate resistor 4m itself.

  One end (left side in the figure) of the portion corresponding to the built-in gate resistor 4i in the present embodiment and one end of the portion corresponding to the MOS type gate resistor 4m are electrically connected by one metal layer 10. . The other end (right side in the figure) of the portion corresponding to the built-in gate resistor 4i and the other end of the portion corresponding to the MOS type gate resistor 4m are electrically connected by the other metal layer 10. That is, the resistance element has a configuration in which a MOS gate resistor 4m and a built-in gate resistor 4i are connected in parallel.

  Since the configuration other than this is almost the same as that of the above-described eleventh embodiment, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of the resistance element included in the semiconductor device of this embodiment will be described.
When a signal is input to the electrode 26, the potential of the built-in gate resistance control gate electrode 28 changes, and the channel on the built-in gate resistance control gate insulating film 29 side of the p-type low-concentration polycrystalline silicon layer 23b is controlled. Thereby, the resistance value of the portion corresponding to the MOS type gate resistor 4m is controlled from the outside.

  By inputting a signal to the electrode 26 so as to eliminate the channel, the resistance value of the resistance element is maximized and becomes the resistance value of the built-in gate resistance 4i.

  On the contrary, when a signal is input to the electrode 26 so that a channel by the inversion layer is formed, a current path passing through a portion corresponding to the MOS type gate resistor 4m is added to the resistance element, and the resistance value decreases.

  According to the present embodiment, the resistance element has the built-in gate resistance 4i equivalent portion and the MOS gate resistance 4m equivalent portion connected in parallel. Thereby, the resistance value of the resistance element can be easily changed from the outside. Unlike the ninth embodiment (FIG. 54), the maximum resistance value can be set to the resistance value corresponding to the built-in gate resistance 4i. In addition, since the portion corresponding to the built-in gate resistor 4i and the portion corresponding to the MOS type gate resistor 4m are formed so as to overlap each other in the thickness direction of the semiconductor substrate 101, the resistance element can be formed with a small area on the semiconductor substrate 101.

  The description of the present embodiment has been made on a parallel structure of an n-channel MOS gate resistor 4m and a normal built-in gate resistor 4i made of a p-type semiconductor layer. The combination of the conductivity types of the built-in gate resistor 4i is arbitrary.

  The MOS gate resistor 4m may be either an enhancement type or a depletion type.

The resistance element may be either a planar type or a trench type.
In Embodiments 11 to 13, the case where the combination of the structures described in Embodiments 1 and 3 to 10 is formed monolithically has been described. However, this combination is limited to the structure described in the above description. It is not something.

  For example, the diode-type built-in gate resistor 4d can be replaced with the Zener diode-type gate resistor described in the fifth embodiment. Further, the MOS type gate resistor 4m can be replaced with a JFET type gate resistor 4j. The built-in gate resistor 4i may be adjusted in impurity concentration as described in the third embodiment.

  Further, the n-type high-concentration polycrystalline silicon layer 24a and the p-type high-concentration polycrystalline silicon layer 24b may be two-dimensionally arranged in a plane in the depth direction of the illustrated sectional views. For example, the resistance elements of the twelfth embodiment (FIG. 59) and the thirteenth embodiment (FIG. 60) can be arranged as shown in FIGS. 61 (a) and (b).

  Further, although an example has been described in which one of the n-type low-concentration polycrystalline silicon layer 23a and the p-type low-concentration polycrystalline silicon layer 23b is formed in one resistance element, the present invention is not limited to this. is not. For example, a common contact for electrical connection between each of the n-type high-concentration polycrystalline silicon layer 24a and the p-type high-concentration polycrystalline silicon layer 24b and the metal layer 10 is used, so that the n-type low-concentration polycrystalline silicon is used. A silicon layer having both the layer 23a and the p-type low-concentration polycrystalline silicon layer 23b can also be used.

[Embodiment 14]
In the first to thirteenth embodiments, the description has mainly been given of the resistance element itself which is a gate resistance connected to the IGBT element EL. In an actual IGBT chip, the gate main wiring 5 and the gate electrode 13 itself also have electrical resistance. Therefore, the gate main wiring 5 and the gate electrode 13 act as a parasitic gate resistance.

  In the IGBT element EL having a plurality of gate electrodes 13, the gate electrode 13 far from the gate pad 1 is more affected by the parasitic gate resistance because the wiring path from the gate pad 1 becomes longer. Conversely, the gate electrode 13 near the gate pad 1 is hardly affected by the parasitic gate resistance.

  For this reason, due to the length of the wiring path from the gate pad 1, there is a time difference in the on / off operation of the IGBT element EL between the cells in which the gate electrodes 13 are formed. As a result, current concentrates in some cells, or as described above, the Q value for the partial amplifier where the current is concentrated increases and oscillation occurs.

  FIG. 62 is a top view schematically showing a configuration of the semiconductor device in the fourteenth embodiment of the present invention. FIG. 63 is a schematic partial plan view of the LXIII portion of FIG.

  Referring to FIGS. 62 and 63, the IGBT chip as the semiconductor device of the present embodiment has a plurality of gate electrodes 13a to 13d. The length of the wiring path that electrically connects the gate pad 1 and each of the gate electrodes 13a to 13d is generally longer in the order of the gate electrode 13a, the gate electrode 13b, the gate electrode 13c, and the gate electrode 13d.

  The IGBT chip includes a built-in gate resistor 4ia that is a resistance element and a built-in gate resistor 4ib that is a resistance element having a resistance value smaller than that of the built-in gate resistor 4ia. The gate pad 1 and a part of the gate main wiring 5 (upper part in FIG. 63) are integrally formed and are electrically connected to each other.

  The gate electrode 13a and the gate pad 1 are electrically connected to each other through a built-in gate resistor 4ia.

  The side of the gate electrode 13b close to the gate pad 1 and the gate pad 1 are electrically connected to each other via a built-in gate resistor 4ia. Further, the side of the gate electrode 13b far from the gate pad 1 and the gate pad 1 are electrically connected to each other via a built-in gate resistor 4ib.

  The side of the gate electrode 13c close to the gate pad 1 and the gate pad 1 are electrically connected to each other via a built-in gate resistor 4ib. Further, the side of the gate electrode 13c far from the gate pad 1 and the gate pad 1 are electrically connected to each other without going through a built-in gate resistor.

  Each of the gate electrode 13d near and far from the gate pad 1 and the gate pad 1 are electrically connected to each other without using a built-in gate resistor.

  In addition, since it is substantially the same as the structure of Embodiment 1-13 mentioned above about the structure except the above, the same code | symbol is attached | subjected about the same or corresponding element, and the description is abbreviate | omitted.

  According to the present embodiment, the gate electrode 13a is connected to the gate electrode 13a relatively close to the gate pad 1 as compared with the resistance value of the built-in gate resistor 4ib connected to the gate electrodes 13b and 13c relatively far from the gate pad 1. The resistance value of the built-in gate resistor 4ia is increased. The gate electrode 13d that is generally farthest from the gate pad 1 is connected to the gate pad 1 without any of the built-in gate resistors 4ia and 4ib.

  As a result, the above-described variation in the parasitic gate resistance can be offset to some extent, and variation in the degree of delay of the electric signal depending on the wiring path from the gate pad 1 can be suppressed. Therefore, a delay difference in transmission of a potential signal to each gate electrode due to the wiring between the gate pad 1 and each gate electrode is suppressed. Therefore, an IGBT chip that is less likely to cause current concentration in the local ON region in the IGBT element EL and is resistant to oscillation is realized.

[Embodiment 15]
In the first to fourteenth embodiments, the resistor element that is electrically connected to the gate electrode 13 and functions as a gate resistor has been described. However, the electrode to which the resistance element of the present invention is electrically connected is not limited to the gate electrode 13, and may be connected to another electrode or installed between the wiring layers.

  64 and 65 are partial plan views schematically showing a planar layout in the vicinity of the resistance element of the semiconductor device in each of the fifteenth embodiment and the modification thereof. Note that the arrows in the figure schematically indicate the direction of current flow. FIG. 66 is a schematic cross sectional view for illustrating the structure of the sense electrode of the semiconductor device in the fifteenth embodiment of the present invention.

  Referring mainly to FIG. 64, the IGBT chip as the semiconductor device of the present embodiment includes an emitter pad 18 which is a normal emitter electrode (first emitter electrode) and a sense pad (second emitter electrode). And an electrode 26. The IGBT chip has a shunt resistor (first resistor element) 4s and a MOS gate resistor (second resistor element) 4m as resistor elements. The IGBT chip has a wire 2a to the gate pad 1, a wire 2b to the emitter pad 18, and a contact 9 for electrical connection.

  Referring to FIG. 66, the sense pad (electrode 26) is a pad in which the emitter current is shunted to 1/100, for example. In the figure, S represents a sense terminal, E represents an emitter terminal, and C represents a collector terminal.

  Referring to FIG. 64 again, shunt resistor 4s electrically connects emitter pad 18 and sense pad (electrode 26) to each other. Thereby, the shunt resistor 4s has a function of generating a potential difference according to the current flowing through the shunt resistor 4s between the emitter pad 18 and the sense pad (electrode 26). As a specific configuration of the shunt resistor 4s, the configuration of the resistance element described in the first to thirteenth embodiments can be used.

  The MOS type gate resistor 4m electrically connects the gate pad 1 and the emitter pad 18 to each other. The built-in gate resistance control gate electrode 28 of the MOS gate resistance 4m is electrically connected to the sense pad (electrode 26). Thus, the MOS type gate resistor 4m has a function of electrically connecting the gate pad 1 and the emitter pad 18 with an electrical resistance corresponding to the potential of the sense pad (electrode 26). The built-in gate resistance control gate electrode 28 and the electrode 26 may be provided integrally.

  In addition, since it is substantially the same as the structure of Embodiment 1-14 mentioned above about the structure except the above, the same code | symbol is attached | subjected about the same or corresponding element, and the description is abbreviate | omitted.

Next, the operation of the resistance element included in the IGBT chip of this embodiment will be described.
When a high current flows through the shunt resistor 4s, the potential difference generated across the shunt resistor 4s increases. As a result, when the MOS type gate resistor 4m is, for example, an enhancement type n-channel MOSFET, the gate pad 1 and the emitter pad 18 are short-circuited. When the MOS type gate resistor 4m is, for example, a depletion type p-channel MOSFET, the gate pad 1 and the emitter pad 18 are connected with a high electric resistance.

  Referring to FIG. 65, in the modification of the present embodiment, MOS type gate resistor 4m electrically connects gate pad 1 and main wiring metal layer 10b to each other.

  According to the present embodiment, unlike the case where a shunt resistor is provided outside the IGBT chip, it is not necessary to connect a wire to the sense pad (electrode 26). Thereby, the area of the sense pad (electrode 26) can be reduced, and the IGBT chip can be reduced in size. Moreover, overcurrent detection at high speed is possible.

  64 (a) and 64 (b) show an example in which a signal generated at the sense pad (electrode 26) is directly transmitted to the built-in gate resistance control gate electrode 28 of the MOS type gate resistance 4m. Is not limited to this. For example, a logic circuit is formed in a semiconductor layer electrically isolated from a semiconductor substrate 101 obtained by irradiating an amorphous silicon layer deposited on an insulating film with an energy beam such as a laser. The result output may be given to the built-in gate resistance control gate electrode 28.

  If the Zener diode type built-in resistor shown in the fifth embodiment is used as the shunt resistor 4s, the output voltage generated at the sense pad can be made almost constant.

[Embodiment 16]
In the first to fifteenth embodiments, examples in which various resistance elements are provided between a plurality of isolated conductor layers have been described. The grooved structure as the current path shown in the first to third embodiments is also effective for reducing the parasitic resistance value of the gate main wiring, for example.

  FIG. 67 is a partial cross-sectional perspective view schematically showing a configuration in the vicinity of the gate main wiring of the semiconductor device in the sixteenth embodiment of the present invention. Referring to FIG. 67, the gate main wiring of the present embodiment has a main wiring metal layer 10b, a metal portion 22, and a polycrystalline silicon layer 12. The semiconductor substrate 101 also has a groove T3 whose inner surface is covered with an insulating film 14.

  At least a part of the wiring (first wiring) made of the polycrystalline silicon layer 12 and the metal portion 22 is provided in the trench T3 with the insulating film 14 interposed therebetween. The main wiring metal layer 10b (second wiring) is provided on the trench T3. The main wiring metal layer 10b and the metal portion 22 are electrically connected in parallel to each other by being connected at the contact hole 9c in the gate main wiring. That is, the first and second wirings are electrically connected in parallel with each other.

  In addition, since it is substantially the same as the structure of Embodiment 1-15 mentioned above about the structure except the above, the same code | symbol is attached | subjected about the same or corresponding element, and the description is abbreviate | omitted.

  68 and 69 are partial cross sectional views schematically showing a configuration in the vicinity of the gate main wiring of the semiconductor device in each of the first and second modifications of the sixteenth embodiment of the present invention.

  Referring to FIG. 68, in the first modification, only metal portion 22 is embedded in groove portion T3 whose inner surface is covered with insulating film.

  Referring to FIG. 69, in the second modification, polycrystalline silicon layer 12 is omitted, and main wiring metal layer 10b and metal portion 22 are connected at the portion of contact hole 9c.

  According to the present embodiment, since a part of the gate main wiring is formed by being embedded in the trench T3, the planar wiring in which the dimensions of the gate main wiring 5 in the width direction (lateral direction in the figure) are the same. Compared to the above, the parasitic resistance can be reduced. Thereby, a delay difference in transmission of the potential signal to each gate electrode 13 due to the wiring between the gate pad 1 and each gate electrode 13 is suppressed. Therefore, an IGBT chip that is less likely to cause current concentration in the local ON region in the IGBT element EL and is resistant to oscillation is realized.

  In each of the above embodiments, the semiconductor device having the IGBT element EL as the semiconductor element has been described. However, the present invention can also be applied to a semiconductor device having another semiconductor element such as a power MOSFET element.

  Further, instead of the metal layer 10, a semiconductor layer having a sufficiently low resistance compared to the built-in gate resistance can be used.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor device including a semiconductor element having a channel region formed of a part of a semiconductor substrate and an electrode.

  EL IGBT element, IL insulating film, T1 first groove, T2 second groove, T3 groove, 1,1C gate pad, 2a, 2b wire, 3c external collector pad, 3e external emitter pad, 3g external gate pad, 4d Diode type built-in gate resistance, 4e External gate resistance, 4f Forward diode type built-in gate resistance, 4g Gate control diode type gate resistance, 4i, 4ia, 4ib Built-in gate resistance, 4j JFET type built-in gate resistance, 4k Junction control diode Type built-in gate resistance, 4m MOS type gate resistance, 4p planar type built-in gate resistance, 4r reverse diode type built-in gate resistance, 4s shunt resistance, 4t trench type built-in gate resistance, 5 gate main wiring, 7 field oxide film, 8 Low concentration n-type drift region, 9 contacts, 9a, 9aD gate pad side contact hole, 9b, 9bD main wiring side contact hole, 9c gate main wiring contact hole, 9d emitter contact hole, 10 metal layer, 10a gate pad metal layer, 10b main wiring metal layer, 11 , 11a, 11b Interlayer insulation film, 12, 12a, 12b, 12g, 12r polycrystalline silicon layer, 13, 13a, 13b, 13c, 13d gate electrode, 14 insulation film, 14a gate insulation film, 14b insulation film, 15 n-type Emitter region, 16 high-concentration p-type region, 17 p-type channel region, 18 emitter pad, 19 p-type collector region, 20 n-type buffer region, 21 p-type region, 22 metal part, 22a, 22b1, 22b2 buried metal Part, 23a n-type low concentration polycrystalline silicon layer, 23b p-type Concentration polycrystalline silicon layer, 24a n-type high-concentration polycrystalline silicon layer, 24b p-type high-concentration polycrystalline silicon layer, 25n-type high-concentration polycrystalline silicon layer, 26 electrode, 27 depletion layer, 28 built-in gate resistance control gate electrode 29, built-in gate resistance control gate insulating film, 30 resistance, 31a, 31b photoresist, 32a storage layer, 32d depletion layer, 32i inversion layer, 100, 100C IGBT chip circuit, 101 semiconductor substrate, 200 printed circuit board.

Claims (4)

A semiconductor substrate;
A semiconductor element having a channel region formed of a part of the semiconductor substrate and an electrode;
An insulating film provided on the semiconductor substrate;
A resistive element including at least one region provided on the insulating film, electrically connected to the electrode so as to be a resistance to a current flowing through the electrode, and having a diode and an ohmic resistor in parallel;
In the at least one region of the resistance element,
A first conductivity type first concentration layer formed in contact with the insulating film and having a first concentration as a first conductivity type;
A first conductivity type second concentration layer formed in a depth direction from the surface of the first conductivity type first concentration layer and having a second concentration higher than the first concentration as the concentration of the first conductivity type;
The first conductivity type first concentration layer is formed in a depth direction from the surface, is separated from the first conductivity type second concentration layer, and the first conductivity type concentration is higher than the first concentration. A first conductivity type third concentration layer having three concentrations;
The first conductivity type first concentration layer is formed in a depth direction from the surface, and has a fourth concentration higher than the first concentration as a second conductivity type concentration, and the first conductivity type second concentration layer and A second conductivity type fourth concentration layer spaced apart from the first conductivity type third concentration layer is formed;
Between the first conductivity type second concentration layer and the second conductivity type fourth concentration layer is the diode,
Between the first conductive type second concentration layer and the first conductive type third concentration layer, Ri said Do the ohmic resistor,
A metal layer formed on the at least one region and electrically connecting the first conductivity type third concentration layer and the second conductivity type fourth concentration layer;
The semiconductor device, wherein the metal layer has another ohmic resistance . The semiconductor device according to claim 1, wherein the second conductivity type fourth concentration layer is disposed between the first conductivity type second concentration layer and the first conductivity type third concentration layer. The semiconductor device according to claim 1, wherein the first conductivity type third concentration layer is disposed between the first conductivity type second concentration layer and the second conductivity type fourth concentration layer. 4. The diode according to claim 1, wherein the at least one region is a pair of regions electrically connected in series with each other, and the polarities of the diodes of the pair of regions are different from each other . The semiconductor device according to any one of the above.

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