JP6253707B2 - Control device - Google Patents

Description

  The present invention relates to a control device that drives a load such as an ignition device or a fuel injection valve.

  In order to improve internal signal transmission efficiency in a control device for driving a load, a method of transmitting a control signal from a processor to a drive circuit including a switching element using serial communication has been proposed. In serial communication, many control signals are transmitted by one set of serial communication lines, and therefore, superposition of minute noises that need not be considered in the transmission method using parallel communication becomes a problem. Therefore, in order to improve the reliability of communication, as described in Japanese Patent Laid-Open No. 6-204989 (Patent Document 1), a technique for transmitting and receiving data of the same content twice in succession has been proposed.

Japanese Patent Laid-Open No. 6-204989

  However, in a control device that drives a load, if data having the same content is continuously transmitted and received twice, the load on the processor is increased and a delay occurs in the drive control of the load to be driven. If a delay occurs in the drive control of the load, for example, a problem such as a decrease in engine response may occur.

  Accordingly, an object of the present invention is to provide a control device that suppresses an increase in processor load and a delay in drive control while taking measures against noise.

In order to solve the above-described problems, a control device of the present invention includes a plurality of switching elements for driving a plurality of single-type drive target devices provided for each cylinder of a multi-cylinder engine, and from a processor at predetermined intervals. A drive circuit configured to change a first operating state and a second operating state of the plurality of switching elements based on a plurality of control signals respectively corresponding to the plurality of switching elements received together; A communication circuit that transmits the plurality of control signals by serial communication in the circuit, and when the plurality of signals indicating the first operating state are included in the plurality of control signals collectively received from the processor, A plurality of control signals are determined to be abnormal , or the drive target device is driven using past signals of the plurality of control signals .

  While taking measures against noise, it is possible to suppress an increase in processor load and delay in load drive control.

It is a block diagram of 1st Embodiment of an engine control unit. It is a circuit diagram which shows an example of a data processing circuit. Details of the control signal are shown, (A) is an explanatory diagram of a command frame, and (B) is an explanatory diagram of a data frame. It is a timing chart explaining operation of a data processing circuit. It is a timing chart explaining operation of a data processing circuit. It is a timing chart explaining operation of a data processing circuit. It is a timing chart explaining the control state of load. It is a timing chart explaining the control state of load when a command frame is transmitted between data frames. It is a timing chart explaining the communication cycle of serial communication. It is a block diagram of 2nd Embodiment of an engine control unit. It is explanatory drawing of the table which controls an ignition device.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.
Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

[First Embodiment]
FIG. 1 shows an engine control unit (hereinafter referred to as “ECU”) 100 that drives a fuel injection valve and an ignition device of a four-cylinder gasoline engine as an example of a control device that drives a load. Note that the ECU 100 is not limited to a four-cylinder gasoline engine, and can drive loads such as a gasoline engine having another number of cylinders and a diesel engine having an arbitrary cylinder (the same applies hereinafter).

  The ECU 100 includes a CPU 110 (processor) that generates timing for driving the fuel injection valve 200 and the ignition device 300 as an example of a load, and a drive circuit 120 that drives the fuel injection valve 200 and the ignition device 300. ing.

  The CPU 110 calculates the timing for driving the fuel injection valve 200 and the ignition device 300 according to the driving state of the vehicle, for example, according to a control program stored in a non-volatile memory such as a flash memory, and sends the timing to the drive circuit 120 at that timing. Output a control signal. Therefore, the CPU 110 includes a communication circuit 112 that transmits and receives various signals to and from the drive circuit 120 by serial communication.

The drive circuit 120 includes a communication circuit 122 that transmits and receives various signals to and from the CPU 110 by serial communication, an injector driver 124 that outputs a drive signal to the fuel injection valve 200, and an igniter predriver that outputs a drive signal to the ignition device 300. 126, and a control circuit 128 that controls the injector driver 124 and the igniter pre-driver 126. The injector driver 124 and the igniter pre-driver 126 include a switching element that drives a load. Further, the drive circuit 120 is provided with a diagnostic circuit 130 for diagnosing whether or not the fuel injection valve 200 and the ignition device 300 are abnormal, and the diagnostic signal is input to the control circuit 128.

The communication circuit 112 of the CPU 110 and the communication circuit 122 of the drive circuit 120 are connected to a clock signal Clock, an enable signal Enable, a data input signal Data SI, and a data output signal Data.
They are connected by four signal lines that transmit SO. Here, the clock signal Clock, the enable signal Enable, and the data input signal Data SI are examples of control signals. Examples of the data output signal Data SO include a diagnostic signal from the diagnostic circuit 130.

  The communication circuit 122 of the drive circuit 120 includes a data processing circuit 132 that processes the control signal transmitted from the CPU 110 and outputs the drive signal to the injector driver 124 and the igniter predriver 126 via the control circuit 128. It is. Note that the data processing circuit 132 is not limited to the communication circuit 122 but may be incorporated in the control circuit 128 or may exist as a single circuit.

The fuel injection valve 200 is an electromagnetic injection valve in which a coil operates in response to a drive signal from the injector driver 124 and a needle valve that is biased in the valve closing direction lifts to inject fuel. The ignition device 300 includes an IGBT (Insulated Gate Bipolar Transistor), a coil, and an igniter (ignition plug). The IGBT operates in response to a drive signal from the igniter predriver 126, and sparks are generated in the igniter by the action of the coil. Is generated.

Reference numerals VB and 310 are fuses for protecting the power supply voltage line and the ignition device 300, respectively.
As shown in FIG. 2, the data processing circuit 132 is configured by appropriately arranging and connecting an AND circuit, a NOT circuit, an SR flip-flop, a D flip-flop, a delay circuit, a clock counter, and the like. 132A, a frame signal generator 132B, a shift register 132C, a data register 132D, a data register 132E, and a drive signal output unit 132F.

The data determination unit 132A counts the clock signal Clock while the enable signal Enable received from the CPU 110 is active, and determines whether the data input signal Data SI received during that time is valid. In addition to determining whether or not the data input signal Data SI is valid, the data determination unit 132A generates a data latch signal Latch that defines the timing for capturing the data input signal Data SI. The frame signal generation unit 132B generates a data frame signal Frame that defines the timing for generating a data frame from the data input signal Data SI based on the clock signal Clock and the enable signal Enable. Shift register 132
When C receives the data frame signal Frame from the frame signal generation unit 132B,
The data input signal Data SI is sequentially fetched to generate a data frame of a predetermined bit. When the data register 132D receives the data latch signal Latch from the data determination unit 132A, the data register 132D reads and holds the data frame from the shift register 132C. When the data register 132E receives the data latch signal Latch from the data determination unit 132A, the data register 132E reads and holds the data frame from the data register 132D. Therefore, the data register 132E holds a data frame that is temporally older than the data frame held in the data register 132D. The drive signal output unit 132F compares the data frames held in the data registers 132D and 132E, respectively, and outputs a drive signal to the control circuit 128 when they are the same.

  For each bit of the data frame, a double collating unit that determines whether two temporally continuous data registers are the same is formed by the data registers 132D and 123E and the drive signal output 132F.

Here, control signals transmitted and received between the CPU 110 and the drive circuit 120 will be described.
As shown in FIG. 3, there are two types of control signals, command frames and data frames. Examples of the command frame include a control command transmitted from the CPU 110 to the drive circuit 120, a diagnosis result of the diagnosis circuit 130 transmitted from the drive circuit 120 to the CPU 110, and the like. Examples of the data frame include data for controlling the injector driver 124 and the igniter pre-driver 126 transmitted from the CPU 110 to the drive circuit 120. As shown in FIG. 3A, the command frame is a 1-bit command selection bit “1” indicating a command frame, 5-bit command bits C0 to C4, and 11-bit data bits D0 to D10. And having. As shown in FIG. 3B, the data frame has a 1-bit data selection bit “0” indicating a data frame and 16-bit data bits D0 to D15. Therefore, the command frame and the data frame have a format that can be distinguished by the polarity of the first bit immediately after the enable signal Enable becomes active (Active Level). The data bits D0 to D15 of the data frame are assigned to each driver that drives a load that is a driving target, and form a control signal for each driver.

FIG. 4 is a timing chart for explaining the operation of the data processing circuit 132.
The clock signal Clock input to the data processing circuit 132 is inverted by the NOT circuit to become an inverted clock signal Clock ^* . The enable signal Enable input to the data processing circuit 132 is inverted by the NOT circuit to become an inverted enable signal Enable ^* . The D flip-flop of the frame signal generation unit 132B latches the inverted enable signal Enable ^* at the rising edge of the inverted clock signal Clock ^* , and generates the data selection bit latch signal Select that latches the polarity of the data selection bit. When the data selection bit latch signal Select is input, the other D flip-flop of the frame signal generation unit 132B outputs the data enable signal Data Enable if the data input signal Data SI is Low (0). The AND circuit of the frame signal generation unit 132B outputs a data frame signal Frame that is a logical product of the data input signal Data SI and the data enable signal Data Enable to the shift register 132C. While the data frame signal Frame is being output, the shift register 132C receives the frame signal by the function of the D flip-flop according to the inverted clock signal Clock ^* obtained by inverting the logical product of the inverted enable signal Enable ^* and the clock signal Clock. The data frame signal Frame from the generation unit 132B is held and expanded.

On the other hand, the clock signal Clock input while the enable signal Enable is active (Low) is counted by the clock counter of the data determination unit 132A. The clock counter outputs a data number OK signal OK when the counted clock signal Clock is normal, that is, when the clock signal Clock is counted 16 times in the data frame shown in FIG. Then, another AND circuit of the data determination unit 132A outputs a logical product signal And of the enable signal Enable and the data number OK signal OK. Further, a delayed data number OK signal OK ′ obtained by delaying the logical product signal And and the data number OK signal OK by the delay circuit is input to the D flip-flop, and the D flip-flop has a normal data frame and the enable signal Enable is HIGH. A data latch signal Latch indicating that is output. Therefore, the data latch signal Latch is output every time one data frame is normally received.

Next, an operation when a plurality of data frames are received will be described.
In FIG. 5, the data signal Data of a predetermined bit of the data frame held in the shift register 132C is latched by the D flip-flop of the data register 132D by the data latch signal Latch that is output every time the data frame is normally received. Is done. The data signal Data latched by the D flip-flop of the data register 132D is latched by the D flip-flop of the data register 132E by the data latch signal Latch. Therefore, the data registers 132D and 132E hold data frames received at successive times, respectively.

The data signal Data held in the data registers 132D and 132E is logically ANDed by the AND circuit from the Q terminal of the D flip-flop as the data signals Data1 and Data2 to the S terminal of the SR flip-flop of the drive signal output unit 132F. Entered. The data signal Data held in the data registers 132D and 132E is transferred from the inverted Q terminal of the D flip-flop to the R terminal of the SR flip-flop of the drive signal output unit 132F as inverted data signals Data1 ^* and Data2 ^{* by an} AND circuit. It is input while being ANDed. For this reason, the SR flip-flop performs HI twice consecutively at the rising edge of the data latch signal Latch.
When GH continues, a driver drive set signal Set is output, and when LOW continues twice, a driver drive reset signal Reset is output.

Thus, the data latch signal Latc that is output every time a data frame is normally received
By latching and comparing the predetermined bit of the data frame in two stages by h, when the predetermined bit becomes HIGH twice in succession, the drive signal Drive becomes HIGH and the load is driven. When the predetermined bit becomes LOW twice in succession, the drive signal Drive becomes LOW, and the drive of the load is stopped.

  On the other hand, as shown in FIG. 6, after the data signal Data rises once at timing T001 and becomes HIGH, it becomes LOW again at timing T002, and when it becomes HIGH again at timing T003, the driver drive set signal Set is output at timing T004. Is done. Similarly, when the data signal Data falls, the data signal Data once becomes LOW at the timing T010, and then becomes HIGH again at the timing T011, and then becomes LOW again at the timing T012, so that the driver drive reset signal Reset becomes the timing T013. Is output.

Thus, the data latch signal Latc that is output every time a data frame is normally received
By latching and comparing the predetermined bit of the data frame in two stages by h, if the predetermined bit does not become HIGH twice in succession, the drive signal Drive does not become HIGH and the previous state is maintained. Similarly, when the predetermined bit does not become LOW twice in succession, the drive signal Drive does not become LOW, and the previous state is maintained.

In short, as shown in FIG. 7, when HIGH continues twice for a predetermined bit of the data frame, the drive signal Drive is switched from LOW (OFF) to HIGH (ON),
The drive signal output from the ECU 100 to the fuel injection valve 200 or the ignition device 300 changes as shown in the figure. On the other hand, when LOW continues twice for a predetermined bit of the data frame, the drive signal Drive is switched from HIGH to LOW, and the fuel injection valve 200 is switched from the ECU 100.
Or the drive signal output to the ignition device 300 changes as shown in the figure.

For this reason, for example, even if noise is superimposed on the control signal transmitted from the CPU 110 to the drive circuit 120 due to a surge, an external radio wave, etc., unless the predetermined bit of the data frame becomes HIGH or LOW twice in succession, Since the drive signal output from the ECU 100 to the load does not change, an increase in the load on the CPU 110 and a delay in drive control can be suppressed while taking measures against noise. Here, since the control signal transmitted from the CPU 110 to the drive circuit 120 defines a control state synchronized with the clock signal Clock, a technique for transmitting and receiving the same data frame twice consecutively as in the prior art. Compared with, the delay in drive control is negligible.

  In the first embodiment, the data frame is latched in two stages, but when the data frame is latched in three stages or more and a predetermined bit of the data frame is continuously HIGH or LOW for a predetermined number of times, the ECU 110 The drive signal output to the load may be changed (the same applies hereinafter).

In addition, the ECU 100 described above has the following effects.
That is, in serial communication, since two types of frames including a command frame and a data frame are used, a command frame may be transmitted between the data frame and the data frame as shown in FIG. However, in the data processing circuit 132 shown in FIG. 2, a predetermined process is executed only when the frame is a data frame. Therefore, the command frame transmitted between the data frames is a predetermined one of the data frames. It does not affect the counting of the number of times HIGH or LOW continues for a bit. For this reason, it is possible to control the driving of the load with only predetermined bits of the data frame.

FIG. 9 shows an example of a timing chart for controlling the driving of the fuel injection valve 200 and the ignition device 300.
In the drive control of the fuel injection valve 200 and the ignition device 300, the rotation angle (crank angle) of the crankshaft of the engine is detected with a resolution in increments of 1 degree, for example, by a rotation angle sensor. As shown in the drawing, the injection signal of the fuel injection valve 200 and the ignition signal of the ignition device 300 change according to the change in the crank angle. That is, the ignition signal and the injection signal change at a predetermined angle in synchronization with the determined resolution while the engine rotates twice. In this case, the period per resolution is represented by a period T.

In the first embodiment, the drive signal output from the ECU 100 to the load is changed when a predetermined bit of the data frame is continuously HIGH or LOW twice. Therefore, as shown in FIG. 9, when the drive control of the ignition device 300 is performed at a resolution of 1 degree, the data frame is transmitted at a cycle of T / 2 or less so as not to cause a delay.

  In short, when the drive signal is changed when a predetermined bit of the data frame becomes HIGH or LOW continuously N times, the transmission period of the data frame is the control resolution of the fuel injection valve 200 and the ignition device 300, that is, the engine. It is set to 1 / N or less of the period T required for the crank angle to change once by the maximum rotational speed.

[Second Embodiment]
In addition to the configuration of the ECU 100 according to the first embodiment, the ECU 100 according to the second embodiment includes a combination determination circuit 134 and a table 136 between the data processing circuit 132 and the control circuit 128 as shown in FIG. It is the composition made to do.

The combination determination circuit 134 determines whether or not a problem will occur even when simultaneous ignition of a plurality of cylinders is instructed by, for example, noise superposition, for the engine ignition control by the ignition device 300. In addition, as shown in FIG. 11, the table 134 sets whether or not the engine is affected by simultaneous ignition of a plurality of cylinders.

  When ECU 100 performs ignition control on a three-cylinder engine, it is assumed that data bits of the data frame are rewritten due to noise superposition or the like, and two cylinders are simultaneously ignited. At this time, as shown in FIG. 11, when the # 1 cylinder is ignited, if the # 2 cylinder is also ignited at the same time, backfire or the like may occur and the engine may be affected. Ignition has no effect on the engine. When igniting the # 2 cylinder, igniting the # 1 cylinder at the same time does not affect the engine. However, if the # 3 cylinder is ignited at the same time, backfire or the like may occur and the engine may be affected. There is. Furthermore, when the # 3 cylinder is ignited, if the # 1 cylinder is ignited at the same time, backfire may occur and the engine may be affected. There is no. In addition, in the ignition control of the 4-cylinder, 6-cylinder, and 8-cylinder engines, the influence on the engine as shown in FIG. 11 is assumed.

  As described above, when noise or the like is superimposed on the control signal transmitted from the CPU 110 to the drive circuit 120, the data bits of the data frame are rewritten, and the two cylinders are simultaneously ignited, resulting in backfire or pre-ignition. May affect the engine. However, in the second embodiment, a combination of simultaneous ignitions that may affect the engine is stored in the table 136, and the combination determination circuit 134 verifies the data frame output from the data processing circuit 132. This avoids the effect of simultaneous ignition on the engine. At this time, when the combination determination circuit 134 determines that the simultaneous ignition has an influence on the engine, the combination determination circuit 134 outputs a drive signal to the ignition device 300 based on the latest data frame determined to have no influence on the engine. In this way, it is possible to avoid the influence on the engine in advance, and the ECU 100 can be made highly reliable.

  Here, the combination determination circuit 134 determines that at least one of the CPU 110 and the communication circuits 112 and 122 is out of order when the data frames for driving the plurality of ignition devices 300 are continuously received a predetermined number of times, and the determination is made. The ignition device 300 can be inactivated after a predetermined time has elapsed. In this way, execution of ignition control that affects the engine can be avoided and the engine can be protected in a state where the ECU 100 has a failure. In this case, the predetermined time may be a time required for limp home control so that the vehicle can be transported to the service factory.

  When performing normal engine ignition control without the possibility of simultaneous ignition of two cylinders, if the data bits of the data frame include ignition control data for two or more cylinders, the data frame is abnormal. The drive signal to the ignition device 300 is output by the latest data frame in which the data bit is normal. In this way, the data frame abnormality can be determined in advance with a simpler circuit configuration, and the ECU 100 can be made highly reliable.

  Further, the control device for driving the load is not limited to the engine control unit, but includes, for example, a transmission control unit and a brake control unit.

100 ECU
110 CPU (processor)
DESCRIPTION OF SYMBOLS 120 Drive circuit 122 Communication circuit 124 Injector driver 126 Igniter pre-driver 128 Control circuit 132 Data processing circuit 134 Combination determination circuit 136 Table 200 Fuel injection valve 300 Ignition device

Claims (4)

It includes a plurality of switching elements for respectively driving a plurality of single-type drive target devices provided for each cylinder of the multi-cylinder engine, and each corresponds to the plurality of switching elements that are collectively received from the processor at predetermined time intervals. A drive circuit that changes a first operating state and a second operating state of the plurality of switching elements based on a plurality of control signals;
A communication circuit for transmitting the plurality of control signals from the processor to the drive circuit by serial communication;
A vehicle-mounted control apparatus that determines that the plurality of control signals are abnormal when a plurality of signals indicating the first operating state are included in the plurality of control signals collectively received from the processor. It includes a plurality of switching elements for respectively driving a plurality of single-type drive target devices provided for each cylinder of the multi-cylinder engine, and each corresponds to the plurality of switching elements that are collectively received from the processor at predetermined time intervals. A drive circuit that changes a first operating state and a second operating state of the plurality of switching elements based on a plurality of control signals;
A communication circuit for transmitting the plurality of control signals from the processor to the drive circuit by serial communication;
A vehicle-mounted control device that drives the device to be driven using past signals of the plurality of control signals when a plurality of signals indicating the first operation state are included in the plurality of control signals received collectively from the processor . In the vehicle-mounted control apparatus as described in any one of Claim 1 or 2,
The device to be driven is an ignition device for the multi-cylinder engine,
An in-vehicle control device that controls an ignition timing of the multi-cylinder engine by changing an operating state of the switching element. The in-vehicle control device according to claim 3,
When the drive circuit receives a control signal including data for driving a plurality of the ignition devices, the drive circuit refers to a table in which the influence on the engine due to the simultaneous ignition of each cylinder is set, and the influence on the engine The ignition device is driven by the past control signal including data for driving one ignition device when it is determined whether there is an influence on the engine. In-vehicle control device.

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