JP6246057B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6246057B2 JP6246057B2 JP2014089000A JP2014089000A JP6246057B2 JP 6246057 B2 JP6246057 B2 JP 6246057B2 JP 2014089000 A JP2014089000 A JP 2014089000A JP 2014089000 A JP2014089000 A JP 2014089000A JP 6246057 B2 JP6246057 B2 JP 6246057B2
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- Prior art keywords
- semiconductive layer
- insulating substrate
- main surface
- circuit board
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
まず本実施の形態の半導体装置の構成としてパワーモジュールの構成について図1および図2を用いて説明する。
Claims (8)
- 絶縁性を有する絶縁基板と、
前記絶縁基板の一方の主表面上に接続された導体基板と、
前記導体基板の前記絶縁基板と対向する主表面と反対側の主表面上に載置された半導体チップと、
前記絶縁基板、前記導体基板および前記半導体チップを封止する封止材と、
前記絶縁基板の一方の主表面上の一部と、前記導体基板の前記反対側の主表面の端部と、前記導体基板の端面とを覆う半導電層とを備える、半導体装置。 - 前記絶縁基板と前記導体基板とはロウ材を介在することにより接続され、
前記ロウ材の端面は前記半導電層に覆われる、請求項1に記載の半導体装置。 - 前記半導電層は、導電性フィラーが絶縁性高分子に充填された複合体からなる請求項1または請求項2に記載の半導体装置。
- 前記導電性フィラーはカーボンブラックであり、前記絶縁性高分子はエポキシ樹脂である、請求項3に記載の半導体装置。
- 前記半導電層は、π電子共役系導電性高分子からなる請求項1または請求項2に記載の半導体装置。
- 前記π電子共役系導電性高分子はポリアニリンまたはポリアセチレンである、請求項5に記載の半導体装置。
- 前記半導電層の導電率は10-10〜101S/cmである、請求項1〜請求項6のいずれか1項に記載の半導体装置。
- 前記絶縁基板はセラミックス材料または有機絶縁シートからなる、請求項1〜請求項7のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014089000A JP6246057B2 (ja) | 2014-04-23 | 2014-04-23 | 半導体装置 |
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JP2014089000A JP6246057B2 (ja) | 2014-04-23 | 2014-04-23 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015207731A JP2015207731A (ja) | 2015-11-19 |
JP6246057B2 true JP6246057B2 (ja) | 2017-12-13 |
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JP2014089000A Active JP6246057B2 (ja) | 2014-04-23 | 2014-04-23 | 半導体装置 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110447098B (zh) * | 2017-03-29 | 2022-11-25 | 三菱电机株式会社 | 功率半导体模块 |
JP6395173B1 (ja) * | 2017-03-29 | 2018-09-26 | 三菱電機株式会社 | パワー半導体モジュール |
JP7002993B2 (ja) * | 2018-05-10 | 2022-01-20 | 株式会社 日立パワーデバイス | パワー半導体モジュール |
CN114823371B (zh) * | 2022-06-28 | 2022-09-02 | 南通泓金贝电子科技有限公司 | 一种电源芯片的点胶封装装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000340719A (ja) * | 1999-05-26 | 2000-12-08 | Hitachi Ltd | パワー半導体装置 |
EP2337070A1 (en) * | 2009-12-17 | 2011-06-22 | ABB Technology AG | Electronic device with non-linear resistive field grading and method for its manufacturing |
JP5368492B2 (ja) * | 2011-02-07 | 2013-12-18 | 三菱電機株式会社 | パワー半導体装置 |
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