JP6231459B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP6231459B2
JP6231459B2 JP2014220459A JP2014220459A JP6231459B2 JP 6231459 B2 JP6231459 B2 JP 6231459B2 JP 2014220459 A JP2014220459 A JP 2014220459A JP 2014220459 A JP2014220459 A JP 2014220459A JP 6231459 B2 JP6231459 B2 JP 6231459B2
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semiconductor device
manufacturing
semiconductor chip
mold
film member
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JP2016092021A (en
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淳史 黒羽
淳史 黒羽
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Aoi Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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  • Moulds For Moulding Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Light Receiving Elements (AREA)

Description

本発明は、半導体デバイスの製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

基板上の半導体チップを樹脂封止する技術が知られている（特許文献１参照）。従来技術では、被成形品の上側を樹脂封止する際に、通常は被成形品の上面側のみにリリースフィルムを用いるところ、被成形品の上面側と下面側とにそれぞれリリースフィルムを用いることによって、被成形品の基板の厚さのばらつきを吸収する点が開示される。   A technique for resin-sealing a semiconductor chip on a substrate is known (see Patent Document 1). In the prior art, when resin-sealing the upper side of the molded product, a release film is usually used only on the upper surface side of the molded product, and a release film is used on each of the upper surface side and the lower surface side of the molded product. Is disclosed to absorb variations in the thickness of the substrate of the molded article.

特開２０００−２７７５５１号公報JP 2000-277551 A

従来技術では、金型成形した樹脂から半導体チップの一部を露出させる場合への適用が困難であった。   In the prior art, it has been difficult to apply to the case where a part of the semiconductor chip is exposed from the resin molded into the mold.

本発明は、金型成形した樹脂から半導体チップの一部を露出させる半導体デバイスの製造方法に適用される。そして、上型および下型を有する金型が閉じた状態で、上型から延設されたマスキング部により、前記マスキング部の押圧面と前記半導体チップの上面の予定露出位置との間に設けられた第１の弾性フィルム部材を押圧して変形させるとともに、前記下型により支持されるプレートにより、前記プレートの上面と前記半導体チップの下面との間に設けられた第２の弾性フィルム部材を押圧して変形させ、前記第１の弾性フィルム部材の前記変形による厚さの変化が、前記第２の弾性フィルム部材の前記変形による厚さの変化よりも大きい。 The present invention is applied to a method for manufacturing a semiconductor device in which a part of a semiconductor chip is exposed from a resin molded with a mold. Then, with the mold having the upper mold and the lower mold closed, the masking section extending from the upper mold is provided between the pressing surface of the masking section and the expected exposure position of the upper surface of the semiconductor chip. were together to deform to press the first elastic film member, the plate being supported by said lower die, pressing the second elastic film member provided between the upper surface and the lower surface of the semiconductor chip of the plate The thickness change due to the deformation of the first elastic film member is larger than the thickness change due to the deformation of the second elastic film member .

本発明によれば、半導体チップの上面および下面のダメージを軽減できる。   According to the present invention, damage to the upper and lower surfaces of the semiconductor chip can be reduced.

図１(a)は半導体デバイスの上面図、図１(b)は半導体デバイスの断面図である。FIG. 1A is a top view of the semiconductor device, and FIG. 1B is a cross-sectional view of the semiconductor device. 製造方法を説明する図である。It is a figure explaining a manufacturing method. 製造方法を説明する図である。It is a figure explaining a manufacturing method. 製造方法を説明する図である。It is a figure explaining a manufacturing method. 製造方法を説明する図である。It is a figure explaining a manufacturing method. 製造方法を説明する図である。It is a figure explaining a manufacturing method. 複数個の半導体デバイスを一括製造する場合を説明する図である。It is a figure explaining the case where a several semiconductor device is manufactured collectively.

以下、図面を参照して本発明を実施するための形態について説明する。
図１は、本発明の一実施の形態による半導体デバイス１を例示する図である。図１(a)は半導体デバイス１の上面図、図１(b)は図１(a)における半導体デバイス１のＥ−Ｅ’断面図である。半導体デバイス１は、平置きした半導体チップ１０を樹脂１３で封入してパッケージ化したものである。本実施形態では、ＰＬＰ(Plating Lead Package)と呼ばれるパッケージ化を行う。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a semiconductor device 1 according to an embodiment of the invention. 1A is a top view of the semiconductor device 1, and FIG. 1B is a cross-sectional view taken along the line EE ′ of the semiconductor device 1 in FIG. The semiconductor device 1 is obtained by enclosing a flatly placed semiconductor chip 10 with a resin 13 and packaging it. In the present embodiment, packaging called PLP (Plating Lead Package) is performed.

図１(a)および図１(b)において、半導体デバイス１の上面は樹脂１３で覆われている。半導体デバイス１の上面の一部に開口部２０が設けられており、開口部２０から半導体チップ１０の上面の一部が露出する。半導体チップ１０の上面のうち開口部２０から露出する領域には、例えば、発光素子の発光部や、受光素子の受光部が構成される。これにより、半導体チップ１０の発光部からの光が開口部２０を介して半導体デバイス１の外部へ射出され、半導体デバイス１の外部からの光が開口部２０を介して半導体チップ１０の受光部へ入射される。   1A and 1B, the upper surface of the semiconductor device 1 is covered with a resin 13. An opening 20 is provided in a part of the upper surface of the semiconductor device 1, and a part of the upper surface of the semiconductor chip 10 is exposed from the opening 20. In the region exposed from the opening 20 in the upper surface of the semiconductor chip 10, for example, a light emitting part of the light emitting element and a light receiving part of the light receiving element are configured. Thereby, light from the light emitting part of the semiconductor chip 10 is emitted to the outside of the semiconductor device 1 through the opening 20, and light from the outside of the semiconductor device 1 is sent to the light receiving part of the semiconductor chip 10 through the opening 20. Incident.

半導体デバイス１の下面も樹脂１３で覆われる。ただし、半導体デバイス１の下面の一部に、半導体チップ１０の下面と、端子群１１ａおよび端子群１１ｂの下面とが露出する。端子群１１ａおよび端子群１１ｂは、例えばニッケル材によって構成される。
端子群１１ａおよび端子群１１ｂを、銅材によって構成してもよい。 The lower surface of the semiconductor device 1 is also covered with the resin 13. However, the lower surface of the semiconductor chip 10 and the lower surfaces of the terminal group 11 a and the terminal group 11 b are exposed at a part of the lower surface of the semiconductor device 1. The terminal group 11a and the terminal group 11b are made of nickel material, for example.
The terminal group 11a and the terminal group 11b may be made of a copper material.

露出した半導体チップ１０の下面は、ＤＡＦ（Die Attach Film）１４で覆われている。後述するように、ＤＡＦ１４は絶縁材料で構成されるため、半導体チップ１０の下面は絶縁性を備える。このため、完成した半導体デバイス１を使用する際に、例えば、半導体デバイス１を実装する基板の実装面において、半導体デバイス１の実装位置に配線パターンを通しても、この配線パターンと半導体チップ１０の下面とが短絡することがない。   The exposed lower surface of the semiconductor chip 10 is covered with a DAF (Die Attach Film) 14. As will be described later, since the DAF 14 is made of an insulating material, the lower surface of the semiconductor chip 10 has an insulating property. For this reason, when the completed semiconductor device 1 is used, for example, even if the wiring pattern is passed through the mounting position of the semiconductor device 1 on the mounting surface of the substrate on which the semiconductor device 1 is mounted, Will not short circuit.

図１(b)において、半導体デバイス１の下面を構成する樹脂１３、ＤＡＦ１４（半導体チップ１０の下面）、端子群１１ａおよび端子群１１ｂは、略面一（つらいち）である。   In FIG. 1B, the resin 13, DAF 14 (lower surface of the semiconductor chip 10), terminal group 11a, and terminal group 11b that constitute the lower surface of the semiconductor device 1 are substantially flush.

平置きされた半導体チップ１０上の不図示の端子は、ボンディングワイヤ１２ａおよびボンディングワイヤ１２ｂによって、端子群１１ａおよび端子群１１ｂとそれぞれ接続される。半導体チップ１０の端子が多い場合は、ボンディングワイヤの数を増やして端子群１１ａや端子群１１ｂと接続される。   Terminals (not shown) on the horizontally placed semiconductor chip 10 are connected to the terminal group 11a and the terminal group 11b, respectively, by bonding wires 12a and bonding wires 12b. When the number of terminals of the semiconductor chip 10 is large, the number of bonding wires is increased to connect to the terminal group 11a and the terminal group 11b.

半導体チップ１０、ボンディングワイヤ１２ａ、ボンディングワイヤ１２ｂ、端子群１１ａおよび端子群１１ｂは、樹脂１３によって封止される。上述したように、半導体デバイス１の上面側に設けられた樹脂１３の開口部２０から、半導体チップ１０の上面の一部が露出する。樹脂１３は、例えば、遮光性のフィラーを含有し、赤外光の透過率が概ね１０％以下の黒色系の樹脂である。   The semiconductor chip 10, the bonding wire 12a, the bonding wire 12b, the terminal group 11a, and the terminal group 11b are sealed with a resin 13. As described above, a part of the upper surface of the semiconductor chip 10 is exposed from the opening 20 of the resin 13 provided on the upper surface side of the semiconductor device 1. The resin 13 is, for example, a black resin containing a light-shielding filler and having an infrared light transmittance of approximately 10% or less.

上述した半導体デバイス１の製造方法について、図２−図６を参照して説明する。図２において、例えば、厚さ１５０μｍのステンレス板３０の上面の所定位置に、ＤＡＦ１４を用いて半導体チップ１０をダイマウントする。ＤＡＦ１４は、例えば、厚さ２５μｍの熱硬化性樹脂によって構成されている。具体的には、エポキシ、シリコン、およびシリカなどの混合物によってＤＡＦ１４が構成されており、ＤＡＦ１４の弾性率は、例えば１５ＧＰａである。
半導体チップ１０の厚さは、例えば４００μｍである。 A method for manufacturing the semiconductor device 1 will be described with reference to FIGS. In FIG. 2, for example, the semiconductor chip 10 is die-mounted using a DAF 14 at a predetermined position on the upper surface of a stainless plate 30 having a thickness of 150 μm. The DAF 14 is made of, for example, a thermosetting resin having a thickness of 25 μm. Specifically, the DAF 14 is composed of a mixture of epoxy, silicon, and silica, and the elastic modulus of the DAF 14 is, for example, 15 GPa.
The thickness of the semiconductor chip 10 is, for example, 400 μm.

ステンレス板３０の上面の所定位置には、端子群１１ａおよび端子群１１ｂがメッキにより形成されている。   A terminal group 11a and a terminal group 11b are formed at predetermined positions on the upper surface of the stainless steel plate 30 by plating.

図３において、半導体チップ１０の不図示の端子と、端子群１１ａ、端子群１１ｂとの間を、上述したボンディングワイヤ１２ａ、およびボンディングワイヤ１２ｂでそれぞれ接続する。図３に例示した構成を、被成形品１Ｂと呼ぶことにする。   In FIG. 3, terminals (not shown) of the semiconductor chip 10 are connected to the terminal group 11a and the terminal group 11b by the bonding wire 12a and the bonding wire 12b, respectively. The configuration illustrated in FIG. 3 will be referred to as a molded product 1B.

図４において、トランスファーモールド法による樹脂封止用の金型は、上型５１および下型５２によって構成される。下型５２の上に、図３の被成形品１Ｂを載置する。さらに、被成形品１Ｂの上から、離型フィルム４０を介して上型５１をセットする。   In FIG. 4, a mold for resin sealing by transfer molding is constituted by an upper mold 51 and a lower mold 52. The molded product 1B of FIG. 3 is placed on the lower mold 52. Further, the upper mold 51 is set via the release film 40 from the molded product 1B.

図５は、金型（下型５２および上型５１）を閉じた状態を説明する図である。上型５１には、樹脂１３の開口部２０を設けるために、略円柱状の凸部５１ｃが設けられている。凸部５１ｃの先端面は、円形の開口部２０を得るために円形状に構成される。凸部５１ｃの先端面は、離型フィルム４０を介して半導体チップ１０の上面の開口予定位置に当接する。また、上型５１の左当接面５１ａは、離型フィルム４０を介して下型５２の左当接面５２ａに当接する。さらに、上型５１の右当接面５１ｂは、離型フィルム４０を介して下型５２の右当接面５２ｂに当接する。   FIG. 5 is a diagram illustrating a state in which the molds (the lower mold 52 and the upper mold 51) are closed. The upper mold 51 is provided with a substantially cylindrical convex portion 51 c in order to provide the opening 20 of the resin 13. The front end surface of the convex portion 51 c is formed in a circular shape in order to obtain the circular opening 20. The front end surface of the convex portion 51 c comes into contact with the planned opening position of the upper surface of the semiconductor chip 10 through the release film 40. Further, the left contact surface 51 a of the upper mold 51 is in contact with the left contact surface 52 a of the lower mold 52 through the release film 40. Further, the right contact surface 51 b of the upper mold 51 contacts the right contact surface 52 b of the lower mold 52 through the release film 40.

離型フィルム４０は、上記金型（上型５１および下型５２）による樹脂成形面を覆う広さの面積を有し、例えば、厚さ７５μｍのＥＴＦＥ（エチレン-テトラフロロエチレン）によって構成されている。離型フィルム４０の弾性率は、例えば１５〜２０ＭＰａである。   The release film 40 has an area that covers the resin molding surface of the above molds (upper mold 51 and lower mold 52), and is made of, for example, ETFE (ethylene-tetrafluoroethylene) having a thickness of 75 μm. Yes. The elastic modulus of the release film 40 is, for example, 15 to 20 MPa.

離型フィルム４０は、上型５１による樹脂成形面の凹凸に倣って変形する柔軟性と、樹脂成形時における金型（下型５２および上型５１）の加熱温度に耐える耐熱性と、樹脂１３および金型（下型５２および上型５１）との剥離が容易な容易剥離性と、を備える。   The release film 40 is flexible so as to be deformed following the unevenness of the resin molding surface by the upper mold 51, heat resistant to withstand the heating temperature of the mold (the lower mold 52 and the upper mold 51) during resin molding, and the resin 13. And easy releasability that is easy to separate from the mold (lower mold 52 and upper mold 51).

一般に、離型フィルム４０は、金型（下型５２および上型５１）の樹脂成形面と、樹脂１３との剥離目的で用いられる。本実施形態では、剥離目的に加えて、離型フィルム４０による弾性効果と、半導体チップ１０の下面側に設けられているＤＡＦ１４による弾性効果とによって以下のように相乗効果を生み出す。   In general, the release film 40 is used for the purpose of peeling the resin 13 from the resin molding surface of the mold (the lower mold 52 and the upper mold 51). In the present embodiment, in addition to the purpose of peeling, a synergistic effect is produced as follows by the elastic effect of the release film 40 and the elastic effect of the DAF 14 provided on the lower surface side of the semiconductor chip 10.

先ず、半導体チップ１０の上面の開口予定位置に直に接する離型フィルム４０が弾性を有しており、この離型フィルム４０を介して半導体チップ１０の上面に対して圧力を加える。一方、半導体チップ１０の下面に直に接するＤＡＦ１４が弾性を有しており、このＤＡＦ１４を介して半導体チップ１０の下面に対して圧力を加える。   First, the release film 40 in direct contact with the planned opening position on the upper surface of the semiconductor chip 10 has elasticity, and pressure is applied to the upper surface of the semiconductor chip 10 through the release film 40. On the other hand, the DAF 14 that is in direct contact with the lower surface of the semiconductor chip 10 has elasticity, and pressure is applied to the lower surface of the semiconductor chip 10 through the DAF 14.

ＤＡＦ１４の厚さ２５μｍと、離型フィルム４０の厚さ７５μｍとで合わせて合計１００μｍであるところ、下型５２および上型５１を閉じた図５の状態では、ＤＡＦ１４および離型フィルム４０が共につぶれて変形するように金型（下型５２および上型５１）が構成されている。ＤＡＦ１４および離型フィルム４０の変形量（押しつぶれ量）は、約５０μｍ（３０μｍ〜７０μｍ程度）である。変形量は、押しつぶれた状態の厚さと、押しつぶれる前の厚さとの差である。   When the total thickness of the DAF 14 having a thickness of 25 μm and the release film 40 having a thickness of 75 μm is 100 μm in total, the DAF 14 and the release film 40 are both crushed in the state of FIG. The molds (lower mold 52 and upper mold 51) are configured so as to be deformed. The deformation amount (crushing amount) of the DAF 14 and the release film 40 is about 50 μm (about 30 μm to 70 μm). The amount of deformation is the difference between the thickness in the crushed state and the thickness before being crushed.

すなわち、金型（下型５２および上型５１）が閉じられたとき、上型５１の凸部５１ｃの先端面が圧力を加える位置（半導体チップ１０の上面の開口予定位置）において、離型フィルム４０およびＤＡＦ１４を合わせた厚さは、金型（下型５２および上型５１）が閉じられる前の１００μｍから半分程度の厚さまで変形する。離型フィルム４０およびＤＡＦ１４がそれぞれ変形することで、半導体チップ１０の厚さのばらつきを半導体チップ１０のすぐ上とすぐ下においてそれぞれ吸収する。   That is, when the molds (the lower mold 52 and the upper mold 51) are closed, the release film at a position where the tip surface of the convex portion 51c of the upper mold 51 applies pressure (scheduled opening position on the upper surface of the semiconductor chip 10). The total thickness of 40 and DAF 14 is deformed from 100 μm before the mold (lower mold 52 and upper mold 51) is closed to about half the thickness. By deforming the release film 40 and the DAF 14, the thickness variation of the semiconductor chip 10 is absorbed immediately above and immediately below the semiconductor chip 10.

ここで、ＤＡＦ１４の弾性率は離型フィルム４０の弾性率よりも大きい。また、離型フィルム４０を介して半導体チップ１０の上面から押圧される面積（凸部５１ｃの円形状の先端面の面積）の方が、ＤＡＦ１４を介して半導体チップ１０の下面から押圧される面積（半導体チップ１０の下面面積）よりも狭い。このため、離型フィルム４０の方がＤＡＦ１４よりも変形量が大きいと推定される。   Here, the elastic modulus of DAF 14 is larger than the elastic modulus of release film 40. Further, the area pressed from the upper surface of the semiconductor chip 10 through the release film 40 (the area of the circular tip surface of the convex portion 51 c) is the area pressed from the lower surface of the semiconductor chip 10 through the DAF 14. It is narrower than (the lower surface area of the semiconductor chip 10). For this reason, it is estimated that the release film 40 has a larger deformation amount than the DAF 14.

さらに、離型フィルム４０の厚さをＤＡＦ１４の厚さより厚くしたので、離型フィルム４０の厚さをＤＡＦ１４の厚さと同等、または離型フィルム４０の厚さをＤＡＦ１４の厚さより薄くする場合に比べて、離型フィルム４０の変形代を大きく確保できる。   Furthermore, since the thickness of the release film 40 is thicker than the thickness of the DAF 14, the thickness of the release film 40 is equal to the thickness of the DAF 14, or compared with the case where the thickness of the release film 40 is thinner than the thickness of the DAF 14. Thus, a large deformation allowance of the release film 40 can be secured.

以上のことから、半導体チップ１０の上面の開口予定位置において、上型５１の凸部５１ｃの先端面（円形状）で押圧された離型フィルム４０が、半導体チップ１０の上面に適切に密着する。これにより、半導体チップ１０の上面の開口予定位置に局所的に過大な押圧力を作用させることなく、開口予定位置において凸部５１ｃが壁となって樹脂１３の進入を防止する。   From the above, the release film 40 pressed by the tip end surface (circular shape) of the convex portion 51 c of the upper mold 51 properly adheres to the upper surface of the semiconductor chip 10 at the planned opening position of the upper surface of the semiconductor chip 10. . As a result, the protruding portion 51c serves as a wall at the planned opening position to prevent the resin 13 from entering without applying an excessively large pressing force locally to the planned opening position on the upper surface of the semiconductor chip 10.

金型（下型５２および上型５１）を閉じた図５において、金型の内部空間の高さＷは、例えば、ステンレス板３０の上面から７００μｍである。   In FIG. 5 in which the molds (the lower mold 52 and the upper mold 51) are closed, the height W of the inner space of the mold is, for example, 700 μm from the upper surface of the stainless steel plate 30.

加熱された金型（上型５１および下型５２）の内部空間へ、不図示の供給路を介して樹脂１３を流し込んで供給する。被成形品１Ｂ、すなわち、半導体チップ１０、ボンディングワイヤ１２ａ、１２ｂ、端子群１１ａ、１１ｂをそれぞれ覆うように、樹脂１３で封止する。   The resin 13 is supplied by pouring into the internal space of the heated mold (upper mold 51 and lower mold 52) via a supply path (not shown). The molded product 1B, that is, the semiconductor chip 10, the bonding wires 12a and 12b, and the terminal groups 11a and 11b are sealed with a resin 13 so as to cover them.

上述したように、上型５１の凸部５１ｃの先端面（円形状）で押圧された離型フィルム４０を、半導体チップ１０の上面の開口予定位置に密着させたことにより、空間内に充填された樹脂１３が半導体チップ１０の上面の開口予定位置へ進入しないので、開口部２０（図１）にバリが生起されることがない。   As described above, the release film 40 pressed by the tip surface (circular shape) of the convex portion 51 c of the upper mold 51 is brought into close contact with the planned opening position of the upper surface of the semiconductor chip 10, thereby filling the space. Since the resin 13 does not enter the planned opening position on the upper surface of the semiconductor chip 10, no burr is generated in the opening 20 (FIG. 1).

図６において、樹脂１３の固化後に金型（上型５１および下型５２）を開いて半導体デバイス１を取り出し、ステンレス板３０を引きはがす。端子群１１ａおよび端子群１１ｂは、ステンレス板３０をはがした際に樹脂１３側（すなわち半導体デバイス１側）に残る。また、半導体チップ１０の下面のＤＡＦ１４は、ステンレス板３０をはがした際に半導体チップ１０の下面に残る。   In FIG. 6, after the resin 13 is solidified, the mold (upper mold 51 and lower mold 52) is opened, the semiconductor device 1 is taken out, and the stainless steel plate 30 is peeled off. The terminal group 11a and the terminal group 11b remain on the resin 13 side (that is, the semiconductor device 1 side) when the stainless steel plate 30 is peeled off. Further, the DAF 14 on the lower surface of the semiconductor chip 10 remains on the lower surface of the semiconductor chip 10 when the stainless steel plate 30 is peeled off.

これにより、半導体デバイス１の下面に、略面一に形成された樹脂１３、ＤＡＦ１４（半導体チップ１０の下面）、端子群１１ａおよび端子群１１ｂが露出する。線Ｆで示す位置で両端の不要な樹脂を切り落とすことにより、図１に例示した半導体デバイス１が完成する。   As a result, the resin 13, DAF 14 (lower surface of the semiconductor chip 10), terminal group 11 a, and terminal group 11 b formed substantially flush are exposed on the lower surface of the semiconductor device 1. By cutting off unnecessary resin at both ends at the position indicated by the line F, the semiconductor device 1 illustrated in FIG. 1 is completed.

上述した実施の形態によれば、次の作用効果が得られる。
（１）上型５１および下型５２を有する金型が閉じた状態で、上型５１から延設された凸部５１ｃと、凸部５１ｃが当接する半導体チップ１０の上面の開口予定位置との間に設けられた離型フィルム４０を押圧して変形させるとともに、下型５２により支持されるステンレス板３０と、半導体チップ１０の下面との間に設けられたＤＡＦ１４を押圧して変形させるようにした。例えば、離型フィルム４０およびＤＡＦ１４を合わせた厚さを、金型５１、５２が閉じられる前の厚さ１００μｍから半分程度の厚さ５０μｍまで変形させる。離型フィルム４０およびＤＡＦ１４がそれぞれ変形することで、半導体チップ１０の厚さのばらつきを半導体チップ１０のすぐ上とすぐ下においてそれぞれ吸収する。この結果、半導体チップ１０の上面と下面とでそれぞれダメージを軽減できる。 According to the embodiment described above, the following operational effects can be obtained.
(1) With the mold having the upper mold 51 and the lower mold 52 closed, the protrusion 51c extending from the upper mold 51 and the planned opening position of the upper surface of the semiconductor chip 10 with which the protrusion 51c contacts The release film 40 provided therebetween is pressed and deformed, and the DAF 14 provided between the stainless steel plate 30 supported by the lower mold 52 and the lower surface of the semiconductor chip 10 is pressed and deformed. did. For example, the combined thickness of the release film 40 and the DAF 14 is deformed from a thickness of 100 μm before the molds 51 and 52 are closed to a thickness of about 50 μm. By deforming the release film 40 and the DAF 14, the thickness variation of the semiconductor chip 10 is absorbed immediately above and immediately below the semiconductor chip 10. As a result, damage can be reduced on the upper surface and the lower surface of the semiconductor chip 10.

（２）離型フィルム４０およびＤＡＦ１４がそれぞれ変形した状態で、金型５１、５２の内部へ樹脂１３を供給する。離型フィルム４０およびＤＡＦ１４がそれぞれ変形すると、凸部５１ｃの先端面で押圧された離型フィルム４０が半導体チップ１０の上面の開口予定位置に適切に密着する。このため、開口予定位置において凸部５１ｃが壁となって、内部に充填された樹脂１３が半導体チップ１０の上面の開口予定位置へ進入しないことから、開口部２０（図１）にバリが生起されることが防止される。 (2) The resin 13 is supplied into the molds 51 and 52 with the release film 40 and the DAF 14 being deformed. When the release film 40 and the DAF 14 are respectively deformed, the release film 40 pressed by the front end surface of the convex portion 51 c is properly adhered to the planned opening position on the upper surface of the semiconductor chip 10. For this reason, the convex portion 51c becomes a wall at the planned opening position, and the resin 13 filled therein does not enter the planned opening position on the upper surface of the semiconductor chip 10, so that burrs are generated at the opening 20 (FIG. 1). Is prevented.

（３）離型フィルム４０の変形前の厚さ７５μｍが、ＤＡＦ１４の変形前の厚さ２５μｍより厚くされている。これにより、離型フィルム４０の変形代をＤＡＦ１４の変形代より大きく確保し、とくに、凸部５１ｃが当接する半導体チップ１０の上面においてダメージを軽減できる。 (3) The thickness 75 μm before the deformation of the release film 40 is thicker than the thickness 25 μm before the deformation of the DAF 14. Thereby, the deformation allowance of the release film 40 is ensured larger than the deformation allowance of the DAF 14, and damage can be reduced particularly on the upper surface of the semiconductor chip 10 with which the convex portions 51c abut.

（４）本実施形態では、離型フィルム４０の弾性率よりもＤＡＦ１４の弾性率を大きくしたので、上記（３）と合わせて、とくに、凸部５１ｃが当接する半導体チップ１０の上面においてダメージを軽減できる。 (4) In this embodiment, since the elastic modulus of the DAF 14 is larger than the elastic modulus of the release film 40, in combination with the above (3), damage is particularly caused on the upper surface of the semiconductor chip 10 with which the convex portion 51c contacts. Can be reduced.

（５）離型フィルム４０の弾性を利用するとともに、ＤＡＦ１４の弾性を利用するので、新たなフィルム部材を用いることなく、半導体チップ１０の厚さのばらつきを半導体チップ１０のすぐ上とすぐ下においてそれぞれ吸収できる。 (5) Since the elasticity of the release film 40 and the elasticity of the DAF 14 are utilized, the thickness variation of the semiconductor chip 10 can be changed immediately above and immediately below the semiconductor chip 10 without using a new film member. Each can be absorbed.

（６）ステンレス板３０を、金型成形後に除去するので、ステンレス板３０をはがした後の厚さが薄い半導体デバイス１を製造できる。 (6) Since the stainless steel plate 30 is removed after molding, the semiconductor device 1 having a small thickness after the stainless steel plate 30 is peeled off can be manufactured.

（７）ＤＡＦ１４を、ステンレス板３０の除去後も半導体チップ１０の下面に残すので、半導体チップ１０の下面を絶縁できる。 (7) Since the DAF 14 remains on the lower surface of the semiconductor chip 10 even after the stainless steel plate 30 is removed, the lower surface of the semiconductor chip 10 can be insulated.

次のような変形も本発明の範囲内であり、変形例の一つ、もしくは複数を上述の実施形態と組み合わせることも可能である。
（変形例１）
上述した説明では、ステンレス板３０の上に半導体チップ１０や端子群１１ａ、１１ｂをマウントする例を説明した。ステンレス板３０の代わりに、銅板を用いてもよい。 The following modifications are also within the scope of the present invention, and one or a plurality of modifications can be combined with the above-described embodiment.
(Modification 1)
In the above description, the example in which the semiconductor chip 10 and the terminal groups 11a and 11b are mounted on the stainless steel plate 30 has been described. A copper plate may be used instead of the stainless plate 30.

（変形例２）
以上の説明では図１(a)、図１(b)に例示した単一の半導体デバイス１を製造する製造手順を説明したが、一般には、複数個の半導体デバイス１を一括して製造することが好ましい。図７は、複数個の半導体デバイス１を一括製造する場合の金型（上型５１Ｇおよび下型５２Ｇ）を閉じた状態を説明する図である。上型５１Ｇには、複数個の半導体チップ１０上にそれぞれ開口部２０（図１）を設けるために、略円柱状の凸部５１ｃが複数個設けられている。離型フィルム４０は、上記金型（上型５１Ｇおよび下型５２Ｇ）による樹脂成形面を覆う広さの面積を有する。 (Modification 2)
In the above description, the manufacturing procedure for manufacturing the single semiconductor device 1 illustrated in FIGS. 1A and 1B has been described. In general, a plurality of semiconductor devices 1 are manufactured in a lump. Is preferred. FIG. 7 is a diagram for explaining a state in which the molds (upper mold 51G and lower mold 52G) are closed when a plurality of semiconductor devices 1 are manufactured at once. The upper die 51G is provided with a plurality of substantially cylindrical convex portions 51c in order to provide the openings 20 (FIG. 1) on the plurality of semiconductor chips 10, respectively. The release film 40 has an area large enough to cover the resin molding surface of the above molds (upper mold 51G and lower mold 52G).

単一の半導体デバイス１を製造する場合と同様に、ステンレス板３０Ｇの上面の所定位置に、ＤＡＦ１４を用いて複数個の半導体チップ１０がそれぞれダイマウントされている。ステンレス板３０Ｇの上面の所定位置には、端子群１１Ｇがメッキにより形成されている。端子群１１Ｇは、樹脂封止後において線Ｆの位置でカットされる。   As in the case of manufacturing a single semiconductor device 1, a plurality of semiconductor chips 10 are die-mounted using DAFs 14 at predetermined positions on the upper surface of the stainless steel plate 30G. A terminal group 11G is formed by plating at a predetermined position on the upper surface of the stainless steel plate 30G. The terminal group 11G is cut at the position of the line F after resin sealing.

半導体チップ１０の不図示の端子と、対応する端子群１１Ｇとの間が、それぞれボンディングワイヤによって接続されている。金型（上型５１Ｇおよび下型５２Ｇ）が閉じられたとき、上型５１Ｇの凸部５１ｃの先端面が圧力を加える位置（半導体チップ１０の上面の開口予定位置）において、離型フィルム４０およびＤＡＦ１４がそれぞれ変形し、半導体チップ１０の厚さのばらつきを半導体チップ１０のすぐ上とすぐ下においてそれぞれ吸収する点は、単一の半導体デバイス１を製造する場合と同様である。   A terminal (not shown) of the semiconductor chip 10 and the corresponding terminal group 11G are connected by bonding wires. When the molds (the upper mold 51G and the lower mold 52G) are closed, the release film 40 and the position where the tip surface of the convex portion 51c of the upper mold 51G applies pressure (scheduled opening position on the upper surface of the semiconductor chip 10) The point that the DAF 14 is deformed and the thickness variation of the semiconductor chip 10 is absorbed immediately above and immediately below the semiconductor chip 10 is the same as in the case of manufacturing the single semiconductor device 1.

加熱された金型（上型５１Ｇおよび下型５２Ｇ）の内部空間へ樹脂が流し込まれて樹脂封止される。樹脂の固化後に金型（上型５１Ｇおよび下型５２Ｇ）を開いて半導体デバイスを取り出し、ステンレス板３０Ｇを引きはがす。端子群１１Ｇは、ステンレス板３０Ｇをはがした際に樹脂側（すなわち半導体デバイス側）に残る。また、半導体チップ１０の下面のＤＡＦ１４は、ステンレス板３０Ｇをはがした際に半導体チップ１０の下面に残る。   Resin is poured into the internal space of the heated molds (upper mold 51G and lower mold 52G) and sealed with resin. After the resin is solidified, the mold (upper mold 51G and lower mold 52G) is opened to take out the semiconductor device, and the stainless steel plate 30G is peeled off. The terminal group 11G remains on the resin side (that is, the semiconductor device side) when the stainless steel plate 30G is peeled off. Further, the DAF 14 on the lower surface of the semiconductor chip 10 remains on the lower surface of the semiconductor chip 10 when the stainless steel plate 30G is peeled off.

線Ｆで示す位置で両端の不要な樹脂を切り落とすとともに、デバイスを個片化することにより、図１に例示した半導体デバイス１が複数個完成する。以上例示した説明によれば、図１(a)、図１(b)に例示した単一の半導体デバイス１をまとめて製造することができる。   At the position indicated by the line F, unnecessary resin at both ends is cut off and the devices are separated into individual pieces, thereby completing a plurality of semiconductor devices 1 illustrated in FIG. According to the description exemplified above, the single semiconductor device 1 exemplified in FIGS. 1A and 1B can be manufactured together.

（変形例３）
上述した説明では、半導体デバイス１のパッケージとしてＰＬＰを例に説明したが、ＤＦＮＰ(Dual Flat No-lead Package)等のパッケージ化においても同様に行うことができる。 (Modification 3)
In the above description, the PLP is described as an example of the package of the semiconductor device 1. However, the same can be applied to packaging such as a DFNP (Dual Flat No-lead Package).

上記では、種々の実施の形態および変形例を説明したが、本発明はこれらの内容に限定されるものではない。本発明の技術的思想の範囲内で考えられるその他の態様も本発明の範囲内に含まれる。   Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

１…半導体デバイス
１０…半導体チップ
１１ａ，１１ｂ、１１Ｇ…端子群
１３…樹脂
１４…ＤＡＦ
２０…開口部
３０、３０Ｇ…ステンレス板
４０…離型フィルム
５１、５１Ｇ…上型
５１ｃ…凸部
５２、５２Ｇ…下型 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Semiconductor chip 11a, 11b, 11G ... Terminal group 13 ... Resin 14 ... DAF
20 ... opening 30, 30G ... stainless steel plate 40 ... release film 51, 51G ... upper die 51c ... convex 52, 52G ... lower die

Claims (9)

金型成形した樹脂から半導体チップの一部を露出させる半導体デバイスの製造方法において、
上型および下型を有する金型が閉じた状態で、
前記上型から延設されたマスキング部により、前記マスキング部の押圧面と前記半導体チップの上面の予定露出位置との間に設けられた第１の弾性フィルム部材を押圧して変形させるとともに、
前記下型により支持されるプレートにより、前記プレートの上面と前記半導体チップの下面との間に設けられた第２の弾性フィルム部材を押圧して変形させ、
前記第１の弾性フィルム部材の前記変形による厚さの変化が、前記第２の弾性フィルム部材の前記変形による厚さの変化よりも大きい、
半導体デバイスの製造方法。 In a method for manufacturing a semiconductor device in which a part of a semiconductor chip is exposed from a mold-molded resin,
With the mold having the upper mold and the lower mold closed,
With the masking part extending from the upper mold, the first elastic film member provided between the pressing surface of the masking part and the planned exposed position of the upper surface of the semiconductor chip is pressed and deformed,
The plate supported by the lower mold presses and deforms the second elastic film member provided between the upper surface of the plate and the lower surface of the semiconductor chip ,
The thickness change due to the deformation of the first elastic film member is larger than the thickness change due to the deformation of the second elastic film member ,
A method for manufacturing a semiconductor device. 請求項１に記載の半導体デバイスの製造方法において、In the manufacturing method of the semiconductor device according to claim 1,
前記マスキング部の前記押圧面は、前記半導体チップの上面の予定露出位置に前記第１の弾性フィルム部材を介して当接する、The pressing surface of the masking portion is in contact with a predetermined exposed position on the upper surface of the semiconductor chip via the first elastic film member.
半導体デバイスの製造方法。  A method for manufacturing a semiconductor device. 請求項１または２に記載の半導体デバイスの製造方法において、In the manufacturing method of the semiconductor device according to claim 1 or 2,
前記マスキング部により押圧される前記半導体チップの面積は、前記プレートにより押圧される前記半導体チップの面積よりも狭い、The area of the semiconductor chip pressed by the masking portion is smaller than the area of the semiconductor chip pressed by the plate,
半導体デバイスの製造方法。A method for manufacturing a semiconductor device. 請求項１から３のいずれか一項に記載の半導体デバイスの製造方法において、
前記第１の弾性フィルム部材および前記第２の弾性フィルム部材がそれぞれ変形した状態で、前記金型の内部へ前記樹脂が供給される、
半導体デバイスの製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 1 to 3 ,
With the first elastic film member and the second elastic film member deformed, the resin is supplied into the mold.
A method for manufacturing a semiconductor device. 請求項１から４のいずれか一項に記載の半導体デバイスの製造方法において、
前記第１の弾性フィルム部材の前記変形前の厚さが、前記第２の弾性フィルム部材の前記変形前の厚さよりも厚い、
半導体デバイスの製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 1 to 4 ,
A thickness of the first elastic film member before the deformation is thicker than a thickness of the second elastic film member before the deformation;
A method for manufacturing a semiconductor device. 請求項１から５のいずれか一項に記載の半導体デバイスの製造方法において、
前記第１の弾性フィルム部材の弾性率よりも前記第２の弾性フィルム部材の弾性率が大きい、
半導体デバイスの製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 1 to 5 ,
The elastic modulus of the second elastic film member is larger than the elastic modulus of the first elastic film member ,
A method for manufacturing a semiconductor device. 請求項１から６のいずれか一項に記載の半導体デバイスの製造方法において、
前記第１の弾性フィルム部材は、離型フィルムであり、
前記第２の弾性フィルム部材は、ＤＡＦである、
半導体デバイスの製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 1 to 6 ,
The first elastic film member is a release film,
The second elastic film member is DAF.
A method for manufacturing a semiconductor device. 請求項１から７のいずれか一項に記載の半導体デバイスの製造方法において、
前記プレートを、前記金型成形後に除去する、
半導体デバイスの製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 1 to 7 ,
Removing the plate after molding the mold;
A method for manufacturing a semiconductor device. 請求項８に記載の半導体デバイスの製造方法において、
前記第２の弾性フィルム部材を、前記プレートの除去後も前記半導体チップの下面に残す、
半導体デバイスの製造方法。
In the manufacturing method of the semiconductor device according to claim 8 ,
Leaving the second elastic film member on the lower surface of the semiconductor chip even after removal of the plate;
A method for manufacturing a semiconductor device.
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