JP6228866B2 - Electronic circuit - Google Patents

Description

  The present invention relates to an electronic circuit having three terminals, a power supply terminal, a signal terminal, and a ground terminal.

  In an end product, there is an electronic circuit provided with only three terminals, that is, a power terminal, a signal terminal, and a ground terminal as external terminals. In such an electronic circuit, the communication terminal or the switching terminal can be used in addition to the three terminals in the process before becoming the final product in the entire manufacturing process, and the electronic circuit and the external adjustment device can be used using these terminals. Input or output signals for testing or adjustment. However, since such communication terminals or switching terminals cannot be used in the final product, the final product cannot be tested and adjusted using these terminals.

  By the way, in order to adjust the final product of the electronic circuit as described above, a voltage pulse that is significantly larger than the normal use range is supplied to the power supply terminal, and the signal terminal is driven by a powerful buffer circuit. In some cases, the circuit is switched to an adjustment mode, and an adjustment signal is input via a signal terminal to perform an adjustment operation.

  However, as described above, in order to supply a voltage pulse significantly larger than the normal use range to the power supply terminal of the electronic circuit, it is required in the normal use range of the electronic circuit as a device in the electronic circuit connected to the power supply terminal. Therefore, there is a problem that the size and cost of the electronic circuit are increased.

  The present invention has been made in view of such circumstances, and an object of the present invention is to significantly increase the power supply terminal from the normal use range in an electronic circuit having only three terminals of a power supply terminal, a signal terminal, and a ground terminal as external terminals. An electronic circuit capable of external communication without applying a voltage pulse is provided.

In order to solve the problem and achieve the above-described object, the electronic circuit of the present invention includes a power supply terminal, a signal terminal, and a ground terminal, and selectively operates in a normal operation mode and a non-normal operation mode. In the electronic circuit , the first signal superimposed on a power supply voltage supplied from the outside to the power supply terminal, and oscillating in a first voltage range not including a voltage used in the normal operation mode. First signal detection means for detecting a first signal and a second signal supplied from the outside to the signal terminal are connected to rise or rise of the first signal detected by the first signal detection means. The normal operation mode and the non-normal operation are performed on the condition that the signal acquisition means that is acquired in synchronization with the downlink and the second signal acquired by the signal acquisition means matches a predetermined signal pattern. And determining the mode switching determining means and for switching the operation mode between a mode, based on a determination result of the mode switching determining unit, and a control unit for switching the operation mode.

According to the electronic circuit of the present invention, when switching the operation mode, the first signal that vibrates in the first voltage range not including the voltage used in the normal operation mode is supplied from the outside to the power supply terminal. Is done. Further, a second signal indicating a predetermined signal pattern input to the signal terminal is input.
In the electronic circuit of the present invention, the first signal detecting means detects the first signal oscillating in the first voltage range not including the voltage used in the normal operation mode.
Then, the signal acquisition unit acquires the second signal in synchronization with the rise or fall of the first signal detected by the first signal detection unit.
Then, the mode switching determination unit determines to switch the operation mode on condition that the second signal acquired by the signal acquisition unit matches a predetermined signal pattern.
And a control means switches an operation mode between the said normal operation mode and the said non-normal operation mode based on the determination result of the said mode switching determination means.
Thus, by using the first signal that vibrates in the first voltage range not including the voltage used in the normal operation mode for switching the operation mode, the operation mode is erroneously switched in the normal operation mode. Can be avoided.
Also, on the condition that the first signal is detected by the first signal detection circuit, the control means determines whether or not the second signal matches a predetermined signal pattern. The reliability of operation mode switching can be improved.
Further, according to the electronic circuit of the present invention, the operation based on the first signal superimposed on the power supply voltage supplied from outside to the power source terminal, and a second signal supplied from outside to the signal terminal Since the mode is switched, the reliability of mode switching can be improved as compared with the case where the operation mode is switched based only on the power supply voltage.

  Preferably, the first signal detection means of the electronic circuit of the present invention sets a predetermined threshold value in the first voltage range that is not used in any of the normal operation mode and the non-normal operation mode. A clock signal is generated by comparing the first signal that vibrates between the threshold and the threshold value, and the signal acquisition means uses the clock signal generated by the first signal detection means as a reference for the second signal. Get the signal.

Preferably, the control means of the electronic circuit of the present invention performs at least one of signal transmission and signal reception via the signal terminal in the non-normal operation mode.
Thereby, in the non-normal operation mode, not only an external signal input but also a processing result can be output from the signal terminal to the outside.

Preferably, the first voltage range of the electronic circuit of the present invention is a voltage range lower than a power supply voltage used in the normal operation mode.
As a result, it is not necessary to apply a voltage pulse significantly larger than the normal use range to the power supply terminal, so that it is not necessary to use a component exceeding the rating required for the user mode. As a result, post-production testing and adjustment can be realized with a small-scale and low-cost configuration.

Preferably, the electronic circuit of the present invention is superimposed on the power supply voltage in the non-normal operation mode, the maximum voltage is higher than the voltage used in the normal operation mode, and the minimum voltage is higher than the first voltage range. The apparatus further comprises second signal detection means for detecting a third signal oscillating in a high second voltage range, wherein the signal acquisition means is detected by the second signal detection means in the non-normal operation mode. The second signal is acquired in synchronization with the rising or falling edge of the third signal, and the control means is configured to acquire the non-normal operation mode based on the second signal acquired by the signal acquiring means. Perform the process.
According to this configuration, in the non-normal operation mode, not only an external signal input but also a processing result can be output from the signal terminal to the outside.
The third signal described above oscillates in a second voltage range in which the second maximum voltage is higher than the voltage used in the normal operation mode and the minimum voltage is higher than the first voltage range. Therefore, an unintended normal operation mode operation and an unintended mode switching operation can be avoided with high reliability.

Preferably, the control circuit of the electronic circuit of the present invention outputs a signal corresponding to the processing in the non-normal operation mode via the signal terminal in synchronization with a rise or fall of the third signal. .
According to this configuration, in the non-normal operation mode, not only an external signal input but also a processing result can be output from the signal terminal to the outside.

Preferably, the electronic circuit of the present invention further includes a main circuit that generates a signal to be output through the signal terminal in the normal operation mode, and the main circuit is in a non-operation state in the non-normal operation mode. Become.
According to this configuration, it is possible to reduce power consumption and save power. In addition, in this way, by monitoring the power consumption of the electronic circuit of the present invention, it can be externally determined whether the electronic circuit is operating in the normal operation mode or the non-normal operation mode from the outside of the electronic circuit. Easy to judge.

  According to the present invention, in an electronic circuit having only three terminals of a power supply terminal, a signal terminal, and a ground terminal as external terminals, an electronic device capable of external communication without applying a voltage pulse significantly larger than the normal use range to the power supply terminal. A circuit can be provided.

FIG. 1 is a diagram for explaining an external connection mode in a user mode of a three-terminal electronic circuit according to an embodiment of the present invention. FIG. 2 is a diagram for explaining an external connection mode in the adjustment mode of the three-terminal electronic circuit according to the embodiment of the present invention. FIG. 3 is a waveform diagram of signals of the three-terminal electronic circuit at timings before and after switching from the user mode to the adjustment mode, FIG. 3A is a waveform diagram of the power supply voltage VDD supplied to the power supply terminal TVDD, and FIG. FIG. 3C is a waveform diagram of a mode switching determination signal S24 generated by the mode switching determination circuit. 4A and 4B are waveform diagrams of signals of the three-terminal electronic circuit at timings before and after switching from the adjustment mode to the user mode, FIG. 4A is a waveform diagram of the power supply voltage VDD supplied to the power supply terminal TVDD, and FIG. 4B is a signal terminal. 4C is a waveform diagram of a mode switching determination signal S24 generated by the mode switching determination circuit. FIG. 4C is a waveform diagram of a signal input via the TSG. FIG. 5 is a waveform diagram of signals of the three-terminal electronic circuit 1 when switching in the order of the user mode, the adjustment mode, and the user mode, and FIG. 5A is a waveform diagram of the power supply voltage VDD supplied to the power supply terminal TVDD, FIG. FIG. 4 is a waveform diagram of a signal input via a signal terminal TSG. FIG. 6 is a configuration diagram of the three-terminal electronic circuit shown in FIGS. 1 and 2. FIG. 7 is a diagram for explaining an example of the first clock signal generation circuit and the second clock signal generation circuit shown in FIG. FIG. 8 is a flowchart showing an example of the operation of the three-terminal electronic circuit according to the embodiment of the present invention.

Hereinafter, a three-terminal electronic circuit according to an embodiment of the present invention will be described.
FIG. 1 is a diagram for explaining an external connection mode in a user mode of a three-terminal electronic circuit 1 according to an embodiment of the present invention. FIG. 2 is a diagram for explaining an external connection mode in the adjustment mode of the three-terminal electronic circuit 1 according to the embodiment of the present invention.
In the present embodiment, the user mode is a mode in which the three-terminal electronic circuit 1 performs an original operation as a final product and outputs an output signal corresponding to the operation from the signal terminal TSG to the outside. On the other hand, the adjustment mode is a mode for testing or adjusting the function of the three-terminal electronic circuit 1 before or after the shipment of the three-terminal electronic circuit 1. Examples of the function of the three-terminal electronic circuit 1 to be tested or adjusted include a sensor function.
The user mode is an example of the normal operation mode of the present invention, and the adjustment mode is an example of the non-normal operation mode of the present invention.

As shown in FIGS. 1 and 2, the three-terminal electronic circuit 1 includes a three-terminal electronic circuit including three terminals: a power supply terminal TVDD to which a VDD voltage is supplied, a signal terminal TSG for signals, and a ground terminal TGND. Circuit.
The power supply terminal TVDD is an example of the power supply terminal of the present invention, the signal terminal TSG is an example of the signal terminal of the present invention, and the ground terminal TGND is an example of the ground terminal of the present invention.

  As shown in FIG. 1, in the user mode, the power supply terminal TVDD, the signal terminal TSG, and the ground terminal TGND of the three-terminal electronic circuit 1 are connected to corresponding terminals of the user external device 3, for example. In the user mode, the three-terminal electronic circuit 1 outputs an analog signal corresponding to the operation from the signal terminal TSG to the user external device 3.

As shown in FIG. 2, in the adjustment mode, the power supply terminal TVDD, the signal terminal TSG, and the ground terminal TGND of the three-terminal electronic circuit 1 are connected to the corresponding terminals of the adjustment device 5 such as a manufacturer, for example. In the adjustment mode, the three-terminal electronic circuit 1 transmits and receives an adjustment signal to and from the adjustment device 5 through the signal terminal TSG.
The ground terminal TGND of the three-terminal electronic circuit 1 may be connected to a device or connection point other than the user external device 3 and the adjustment device 5.
The three-terminal electronic circuit 1 automatically switches the operation mode between the user mode and the adjustment mode based on the VDD voltage supplied to the power supply terminal TVDD and the signal input to the signal terminal TSG.

Hereinafter, signals supplied from the user external device 3 and the adjustment device 5 to the three-terminal electronic circuit 1 in the user mode and the adjustment mode described above will be described.
FIG. 3 is a waveform diagram of a signal of the three-terminal electronic circuit 1 before and after switching from the user mode to the adjustment mode, FIG. 3A is a waveform diagram of the power supply voltage VDD supplied to the power supply terminal TVDD, and FIG. 3C is a waveform diagram of a mode switching determination signal S24 generated by the mode switching determination circuit 24. FIG. 3C is a waveform diagram of a signal input via the terminal TSG.
4A and 4B are waveform diagrams of signals of the three-terminal electronic circuit 1 before and after switching from the adjustment mode to the user mode, FIG. 4A is a waveform diagram of the power supply voltage VDD supplied to the power supply terminal TVDD, and FIG. 4C is a waveform diagram of a mode switching determination signal S24 generated by the mode switching determination circuit 24. FIG. 4C is a waveform diagram of a signal input via the terminal TSG.
FIG. 5 is a waveform diagram of signals of the three-terminal electronic circuit 1 when switching in the order of the user mode, the adjustment mode, and the user mode, and FIG. 5A is a waveform diagram of the power supply voltage VDD supplied to the power supply terminal TVDD, FIG. FIG. 4 is a waveform diagram of a signal input via a signal terminal TSG.

As shown in FIGS. 3A, 4A, and 5A, in the user mode in which the user external device 3 is connected to the three-terminal electronic circuit 1, the power supply voltage VDD supplied to the power supply terminal TVDD is the voltage VDD_U.
When the adjustment device 5 is connected to the three-terminal electronic circuit 1, the power supply voltage VDD supplied from the adjustment device 5 to the power supply terminal TVDD of the three-terminal electronic circuit 1 has a mode switching signal MCS indicated in the mode switching period MCV. Are superimposed. The mode switching signal MCS is an example of the first signal of the present invention.
The mode switching signal MCS oscillates in a voltage range between a minimum voltage VDD_L1 and a maximum voltage VDD_H1 lower than the voltage VDD_U used in the normal operation mode. The mode switching signal MCS is a signal in a voltage range that is not used in the user mode or the adjustment mode. That is, the mode switching signal MCS is a signal that is lower than the rated voltage of the three-terminal electronic circuit 1 and vibrates in a voltage range in which the three-terminal electronic circuit 1 can operate. A voltage range between the minimum voltage VDD_L1 and the maximum voltage VDD_H1 is an example of the first voltage range of the present invention.

  Further, as shown in FIG. 2, when the adjusting device 5 is connected to the three-terminal electronic circuit 1, the signal terminal TSG of the three-terminal electronic circuit 1 is driven by the buffer device by the adjusting device 5, and FIGS. For example, a mode switching signal pattern MCSP indicating “1001” is transmitted from the adjusting device 5 to the three-terminal electronic circuit 1 within the mode switching period MCV shown in FIG. The signal input from the adjusting device 5 to the signal terminal TSG is an example of the second signal of the present invention, and the mode switching signal pattern MCSP is an example of the signal pattern of the present invention.

  As described above, the three-terminal electronic circuit 1 operates on the basis of the mode switching signal MCS superimposed on the power supply voltage VDD supplied to the power supply terminal TVDD and the mode switching signal pattern MCSP input from the signal terminal TSG. Switch.

In addition, when the adjustment device 5 is connected to the three-terminal electronic circuit 1 as shown in FIG. 2 and is operating in the adjustment mode, the adjustment signal AJS is superimposed on the power supply voltage VDD as shown in FIGS. 3A and 5A. . The adjustment signal AJS is an example of the third signal of the present invention.
The adjustment signal AJS oscillates in a voltage range where the maximum voltage TDD_H2 is higher than the voltage VDD_U in a range in which the operation of the three-terminal electronic circuit 1 is not hindered, and the minimum voltage VDD_L2 is higher than the maximum voltage VDD_H1 of the mode switching signal MCS. A voltage range between the maximum voltage TDD_H2 and the minimum voltage VDD_L2 is an example of the second voltage range of the present invention.

Hereinafter, the configuration of the three-terminal electronic circuit 1 shown in FIGS. 1 and 2 will be described in detail.
FIG. 6 is a configuration diagram of the three-terminal electronic circuit 1 shown in FIGS. 1 and 2.
As shown in FIG. 6, the three-terminal electronic circuit 1 includes, for example, a first clock signal generation circuit 21, a second clock signal generation circuit 22, a data acquisition circuit 23, a mode switching determination circuit 24, a control circuit 25, and a main circuit 27. Have
A switch SW1 is selectively turned on or off between the control circuit 25 and the signal terminal TSG. A switch SW2 selectively turns on or off between the main circuit 27 and the signal terminal TSG.

In the user mode, the control circuit 25 turns off the switch SW1 and turns on the switch SW2, and outputs an analog signal output from the main circuit 27 to the user external device 3 shown in FIG. 1 via the signal terminal TSG. . In the user mode, the mode switching determination circuit 24 determines the operation mode switching based on the signal from the main circuit 27 and the data S23 from the data acquisition circuit 23.
In the adjustment mode, the control circuit 25 turns on the switch SW1 and turns off the switch SW2. Then, the control circuit 25 and the adjusting device 5 shown in FIG. 2 perform an adjusting operation by transmitting and receiving an adjusting signal via the signal terminal TSG.

  Each circuit in the three-terminal electronic circuit 1 is supplied with the VDD voltage supplied to the power supply terminal TVDD via a power supply line or the like. Further, the ground potential of the ground terminal TGND is used as the ground potential of each circuit in the three-terminal electronic circuit 1.

The first clock signal generation circuit 21 is effective for data acquisition in the data acquisition circuit 23 based on the mode switching signal MCS superimposed on the power supply voltage VDD input from the power supply terminal TVDD within the mode switching period MCV. A simple clock signal.
That is, in the present embodiment, utilizing the fact that the three-terminal electronic circuit 1 operates even at a voltage lower than the rated voltage, the voltage range is lower than the rated voltage of the three-terminal electronic circuit 1 and the three-terminal electronic circuit 1 can operate. An oscillating mode switching signal MCS is transmitted from the adjusting device 5 to the three-terminal electronic circuit 1 and detected by the three-terminal electronic circuit 1.
Therefore, while the three-terminal electronic circuit 1 is operating in the user mode with the voltage VDD_U being the rated voltage supplied to the power supply terminal TVDD, the clock signal effective for data acquisition in the data acquisition circuit 23 is the first clock signal. It is not generated by the generation circuit 21. Thereby, it is possible to avoid erroneous operation mode switching.

FIG. 7 is a diagram for explaining an example of the first clock signal generation circuit 21 and the second clock signal generation circuit 22.
As shown in FIG. 7, the first clock signal generation circuit 21 is realized using a comparator 100 and resistors R11 and R12.
A voltage obtained by dividing the voltage between the VDD voltage of the power supply terminal TVDD and the ground by the resistors R11 and R12 is supplied to the negative terminal of the comparator 100.
Further, a reference voltage (clock determination level voltage) V_REF1 is supplied to a + terminal of the comparator 100 from a predetermined reference voltage source. The reference voltage V_REF1 is higher than the voltage at the −terminal when the VDD voltage becomes the lowest voltage VDD_L1 of the mode switching signal MCS, and the voltage at the −terminal when the VDD voltage becomes the maximum voltage VDD_H1 of the mode switching waveform. A lower voltage is used.
The reference voltage V_REF1 can be adjusted by changing the ratio of the resistance values of the resistors R11 and R12.

The comparator 100 compares the voltage at the − terminal and the reference voltage at the + terminal, and generates a signal S21 that switches the level each time the comparison result is switched.
The signal S21 is a clock signal when the mode switching signal MCS is superimposed on the VDD voltage, and is not a clock signal in other cases.

In the adjustment mode, the second clock signal generation circuit 22 is a clock signal effective for data acquisition by the data acquisition circuit 23 based on the adjustment signal AJS superimposed on the power supply voltage VDD input from the power supply terminal TVDD. Is generated.
As shown in FIG. 7, the second clock signal generation circuit 22 has basically the same configuration as the first clock signal generation circuit 21, and is realized using a comparator 200 and resistors R21 and R22.

A voltage obtained by dividing the voltage between the VDD voltage of the power supply terminal TVDD and the ground by the resistors R21 and R22 is supplied to the negative terminal of the comparator 200.
Further, the reference voltage V_REF2 is supplied to the + terminal of the comparator 200 from a predetermined reference voltage source. The reference voltage V_REF2 is higher than the voltage at the −terminal when the VDD voltage becomes the lowest voltage VDD_L2 of the adjustment signal AJS, and the voltage at the −terminal when the VDD voltage becomes the maximum voltage VDD_H2 of the mode switching waveform. A lower voltage is used.
The reference voltage V_REF2 can be adjusted by changing the ratio of the resistance values of the resistors R21 and R22.

The comparator 200 compares the voltage at the − terminal and the reference voltage at the + terminal, generates a signal S22 for switching the level every time the comparison result is switched, and outputs the signal S22 to the data acquisition unit 23 and the control circuit 25. .
The signal S22 is a clock signal when the adjustment signal AJS is superimposed on the VDD voltage (adjustment mode), and is not a clock signal otherwise.

When the signal S21 from the first clock signal generation circuit 21 is a clock signal, the data acquisition circuit 23 acquires data from the signal input from the signal terminal TSG with reference to the falling timing of the signal S21. The data acquisition circuit 23 outputs the acquired data S23 to the mode switching determination circuit 24. The data acquisition circuit 23 may acquire data from the signal input from the signal terminal TSG with reference to the rising timing of the signal S21.
The signal input from the signal terminal TSG is performed when the adjusting device 5 is connected to the three-terminal electronic circuit 1 as shown in FIG.

The mode switching determination circuit 24 compares the data acquired by the data acquisition circuit 23 with the predetermined mode switching signal pattern MCSP, and on the condition that they match, the mode switching determination circuit 24 The mode switching determination signal S24 indicating the switching of the operation mode is output to the control circuit 25. Further, in the user mode, the mode switching determination circuit 24 further uses the signal from the main circuit 27 to set the mode switching determination indicating the switching from the user mode to the adjustment mode on condition that the comparison result matches. The signal S24 is output to the control circuit 25.
For example, as illustrated in FIGS. 3C and 4C, the mode switching determination circuit 24 generates a mode switching determination signal S24 that is at a high level in the user mode and at a low level in the adjustment mode.

  The control circuit 25 turns off the switch SW1 and turns on the switch SW2 in the user mode. In the user mode, an analog signal from the main circuit 27 is output to the external device 3 shown in FIG. 1 via the signal terminal TSG.

On the other hand, the control circuit 25 turns on the switch SW1 and turns off the switch SW2 in the adjustment mode. In the adjustment mode, the control circuit 25 performs a predetermined adjustment operation, and transmits / receives an adjustment signal to / from the adjustment device 5 shown in FIG. 2 via the signal terminal TSG.
Specifically, in the adjustment mode, a clock signal is generated by the second clock signal generation circuit 22 in accordance with the adjustment signal AJS superimposed on the power supply voltage VDD, and a signal is received by the data acquisition unit 23 based on this. Data is acquired from the signal supplied to the terminal TSG. Then, the acquired data S23 is output from the data acquisition unit 23 to the control circuit 25.
The control circuit 25 performs adjustment processing based on the input data S23.
Further, the control circuit 25 outputs the data generated according to the adjustment process from the signal terminal TSG to the adjustment device 5 based on the clock signal of the signal S22 from the second clock signal generation circuit 22.

  In addition, the control circuit 25 puts the main circuit 27 into a non-operating state in the adjustment mode. Thereby, power saving can be achieved. In addition, in this way, by monitoring the power consumption of the three-terminal electronic circuit 1, the three-terminal electronic circuit 1 operates from the outside of the three-terminal electronic circuit 1 in either the user mode or the adjustment mode. It can be easily determined from the outside whether or not.

Hereinafter, an operation example of the three-terminal electronic circuit 1 will be described.
FIG. 8 is a flowchart showing an example of the operation of the three-terminal electronic circuit 1 according to the embodiment of the present invention.

Step ST1:
For example, when the control circuit 25 determines that the power is turned on based on an operation signal corresponding to an operation of an operation unit (not shown), the control circuit 25 proceeds to step ST2.

Step ST2:
Each circuit in the three-terminal electronic circuit 1 is activated. Specifically, each circuit in the three-terminal electronic circuit 1 including the first clock signal generation circuit 21, the data acquisition circuit 23, the control circuit 25, and the main circuit 27 is based on the VDD voltage supplied from the power supply terminal TVDD. It is activated.

Step ST3:
The control circuit 25 reads a program from a memory (not shown) and executes it.

Step ST4:
The control circuit 25 controls each circuit so as to perform the user mode operation first in accordance with the program executed in step ST3.
In the user mode, the control circuit 25 turns off the switch SW1 and turns on the switch SW2, and outputs an analog signal output from the main circuit 27 to the user external device 3 shown in FIG. 1 via the signal terminal TSG. .

Step ST5:
The mode switching determination circuit 24 determines whether or not to switch the operation mode within the mode switching determination period shown in FIG. The mode switching determination period is defined at a predetermined time interval.
The mode switching determination circuit 24 compares the data acquired by the data acquisition circuit 23 with a predetermined mode switching signal pattern, and determines that the operation mode is switched when they match. In the user mode, the mode switching determination circuit 24 identifies the user mode based on the signal from the main circuit 27.

  Here, as shown in FIG. 1, when the three-terminal electronic circuit 1 is connected to the user external device 3, the VDD voltage applied to the power supply terminal TVDD is higher than the maximum voltage VDD_H1 of the mode switching signal MCS. It is held at VDD_U. Therefore, the signal S21 generated by the first clock signal generation circuit 21 is not a clock signal, and data acquisition by the data acquisition circuit 23 is not performed. In this case, even if the mode switching determination circuit 24 compares the data acquired by the data acquisition circuit 23 with the predetermined mode switching signal pattern MCSP, they do not match, so the mode switching determination signal S24 does not indicate switching of the operation mode (holds the level).

On the other hand, as shown in FIG. 2, when the three-terminal electronic circuit 1 is connected to the adjusting device 5, as shown in FIG. 3A, the mode switching signal MCS is set to the VDD voltage applied from the adjusting device 5 to the power supply terminal TVDD. Superimposed. Further, the adjustment device 5 outputs a mode switching signal pattern MCSP indicating, for example, “1001” to the signal terminal TSG as shown in FIG. 3B during the period in which the mode switching signal MCS is superimposed on the power supply voltage VDD.
Therefore, the signal S21 output from the first clock signal generation circuit 21 to the data acquisition circuit 23 is a clock signal corresponding to the mode switching signal MCS.

The data acquisition circuit 23 acquires data from the signal input from the signal terminal TSG with reference to the falling timing of the clock signal, which is the signal S21 from the first clock signal generation circuit 21. The data acquisition circuit 23 outputs the acquired data S23 to the mode switching determination circuit 24. At this time, the data S23 indicates a mode switching signal pattern MCSP.
The mode switching determination circuit 24 compares the data S23 input from the data acquisition circuit 23 with a predetermined mode switching signal pattern MCSP. Since these match, the mode switching determination circuit 24 switches from the user mode to the adjustment mode. Do. At this time, as shown in FIG. 3C, the mode switching determination circuit 24 switches the level of the mode switching determination signal S24 from the level (high) indicating the user mode to the level (low) indicating the adjustment mode.

Step ST6:
The control circuit 25 controls each circuit to operate in the adjustment mode based on the mode switching determination signal S24 from the mode switching determination circuit 24.
In the adjustment mode, the control circuit 25 turns on the switch SW1 and turns off the switch SW2. Then, the control circuit 25 and the adjustment device 5 shown in FIG. 8 perform an adjustment operation by transmitting and receiving an adjustment signal via the signal terminal TSG. In the adjustment operation, for example, the gain of the operational amplifier is adjusted.

In the adjustment mode, the adjustment signal AJS shown in FIGS. 3A and 5A is superimposed on the VDD voltage supplied from the adjustment device 5 shown in FIG. 2 to the power supply terminal TVDD of the three-terminal electronic circuit 1.
In the three-terminal electronic circuit 1, the clock signal is generated by the second clock signal generation circuit 22 in accordance with the adjustment signal AJS superimposed on the power supply voltage VDD, and the signal terminal is generated by the data acquisition unit 23 based on this. Data is acquired from the signal supplied to the TSG. Then, the acquired data S23 is output from the data acquisition unit 23 to the control circuit 25.
The control circuit 25 performs adjustment processing based on the input data S23.
Further, the control circuit 25 outputs the data generated according to the adjustment process from the signal terminal TSG to the adjustment device 5 based on the clock signal of the signal S22 from the second clock signal generation circuit 22.

Step ST7:
The mode switching determination circuit 24 determines whether or not to switch the operation mode as in step ST5.
When it is determined that the operation mode is to be switched, the mode switching determination circuit 24 changes the level of the mode switching determination signal S24 from the level indicating the adjustment mode (low) to the level indicating the user mode (see FIG. 4C). Switch to High).
Thereafter, the three-terminal electronic circuit 1 proceeds to the operation of step ST4 described above.

  As described above, according to the three-terminal electronic circuit 1, when the adjusting device 5 is connected to the three-terminal electronic circuit 1, both the maximum voltage VDD_H1 and the minimum voltage VDD_L1 are VDD voltages used in the user mode. The operation mode switching determination is performed on condition that a mode switching signal MCS lower than a certain VDD_U is supplied from the adjusting device 5 to the signal terminal TVDD of the three-terminal electronic circuit 1. Accordingly, since the operation mode switching determination is not performed in the range of the VDD voltage used in the user mode, unintended operation mode switching can be avoided.

In addition, according to the three-terminal electronic circuit 1, the mode switching signal pattern MCSP is input from the signal terminal TSG during the period when the above-described mode switching signal MCS is superimposed on the power supply voltage VDD in the operation mode switching determination. Switch the operation mode on the condition.
As described above, the three-terminal electronic circuit 1 switches the operation mode when both predetermined conditions of the VDD voltage supplied to the power supply terminal TVDD and the signal supplied to the signal terminal TSG are satisfied. For this reason, the reliability of switching of the operation mode can be improved.

  Further, according to the three-terminal electronic circuit 1, since it is not necessary to apply a voltage pulse that is significantly larger than the normal use range to the power supply terminal as in the conventional case, it is not necessary to use components exceeding the rating required for the user mode. As a result, in a three-terminal device 1 having only three terminals of the power supply terminal TVDD, the signal terminal TSG, and the ground terminal TGND as external terminals in the final product, a small-scale and low-cost configuration for testing and adjustment after commercialization Can be realized.

Further, in the three-terminal electronic circuit 1, a pulse signal can be generated from the adjustment signal AJS by superimposing the adjustment signal AJS on the power supply voltage VDD in the adjustment mode, and adjustment is performed with the control circuit 25 via the signal terminal DSG. Input / output of signals for adjustment with the device 5 becomes possible.
If the pulse signal is not superimposed on the power supply voltage VDD, it is necessary to fix the data amount of the test signal transmitted from the adjusting device 5 to the three-terminal electronic circuit. In addition, a signal indicating a result corresponding to the input test signal cannot be obtained from the three-terminal electronic circuit. The three-terminal electronic circuit 1 has an advantage over such a technique.

  Further, according to the three-terminal electronic circuit 1, in the adjustment mode, the main circuit 27 is inactivated and the output of the main circuit 27 is set to high impedance. Thereby, power consumption can be reduced and power saving can be achieved. In addition, in this way, by monitoring the power consumption of the three-terminal electronic circuit 1, it is possible to easily determine from the outside whether the terminal electronic circuit 1 is operating in the user mode or the adjustment mode. .

The present invention is not limited to the embodiment described above.
That is, those skilled in the art may make various modifications, combinations, subcombinations, and alternatives regarding the components of the above-described embodiments within the technical scope of the present invention or an equivalent scope thereof.
In the embodiment described above, the first clock signal generation circuit 21 and the second clock signal generation circuit 22 are individually provided. However, by changing the resistance value by one clock signal generation circuit, these functions can be performed one by one. You may implement | achieve with a clock signal generation circuit.
The configuration block of the three-terminal electronic circuit 1 shown in FIG. 6 is an example, and a plurality of configuration blocks may be realized by one circuit, or one configuration block may be realized by a plurality of circuits.

In the above-described embodiment, the analog main circuit 27 is illustrated as an example of the main circuit of the present invention, but a digital circuit may be used.
In the above-described embodiment, the mode switching signal MCS exemplifies a case where it oscillates in the range between the minimum voltage VDD_L1 lower than the voltage VDD_U used in the normal operation mode and the maximum voltage VDD_H1, but the minimum voltage higher than the voltage VDD_U. You may make it oscillate in the range of VDD_L1 and maximum voltage VDD_H1. In that case, the adjustment signal AJS is oscillated in a range lower than the voltage VDD_U.

  In the above-described embodiment, the adjustment mode is exemplified as the non-normal mode of the present invention. However, the non-normal mode may be a mode other than the adjustment mode (for example, a secret mode).

  Further, the functions of the mode switching determination circuit 24 and the control circuit 25 shown in FIG. 6 may be realized by a single circuit.

DESCRIPTION OF SYMBOLS 1 ... 3 terminal electronic circuit 3 ... User external apparatus 5 ... Adjustment apparatus 21 ... 1st clock signal generation circuit 22 ... 2nd clock signal generation circuit 23 ... Data acquisition part 24 ... Mode switching determination circuit 25 ... Control circuit 27 ... Main circuit TVDD: power supply terminal TSG: signal terminal TGND: ground terminal

Claims (7)

In an electronic circuit that includes a power supply terminal, a signal terminal, and a ground terminal, and selectively performs operations in a normal operation mode and a non-normal operation mode.
A first signal superimposed on a power supply voltage supplied from the outside to the power supply terminal and oscillating in a first voltage range not including a voltage used in the normal operation mode is detected. First signal detecting means for
A signal acquisition means for acquiring a second signal supplied from the outside to the signal terminal in synchronization with a rise or fall of the first signal detected by the first signal detection means;
It is determined that the operation mode is switched between the normal operation mode and the non-normal operation mode on condition that the second signal acquired by the signal acquisition means matches a predetermined signal pattern. Mode switching determination means;
And an electronic circuit having control means for switching the operation mode based on a determination result of the mode switching determination means . The first signal detection means includes the first signal that oscillates with a predetermined threshold in the first voltage range that is not used in any of the normal operation mode and the non-normal operation mode. Generate a clock signal compared to the threshold,
The signal acquisition means, said first signal detecting means electronic circuit according to claim 1, wherein obtaining the second signal as a reference the clock signal generated. The electronic circuit according to claim 1, wherein the control unit performs at least one of signal transmission and signal reception via the signal terminal in the non-normal operation mode. Wherein the first voltage range, the electronic circuit according to claim 1 wherein a lower voltage range than the power supply voltage used in the normal operation mode. In the non-normal operation mode, a third voltage that is superimposed on the power supply voltage and oscillates in a second voltage range in which the maximum voltage is higher than the voltage used in the normal operation mode and the minimum voltage is higher than the first voltage range. A second signal detecting means for detecting the signal of
The signal acquisition means acquires the second signal in synchronization with the rising or falling edge of the third signal detected by the second signal detection means in the non-normal operation mode;
The control means, based on said second signal by the signal acquisition unit has acquired, an electronic circuit according to the processing of the non-normal operation mode to any one of claims 1 to 4 intends row. The electronic circuit according to claim 5 , wherein the control unit outputs a signal corresponding to processing in the non-normal operation mode via the signal terminal in synchronization with a rise or fall of the third signal. A main circuit for generating a signal to be output through the signal terminal in the normal operation mode;
The main circuit includes an electronic circuit according to any one of claims 1 to 6 comprising non-operation state in the non-normal operation mode.