JP3105808B2 - Semiconductor device and mode setting method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a mode switching circuit and a mode switching method for a semiconductor device, and more particularly to a switching circuit and a mode switching method which do not require an external terminal for setting a test mode.

[0002]

2. Description of the Related Art Referring to FIG. 4, which shows an example of a conventional mode switching circuit of this type in which a dedicated external terminal is used to switch between a normal operation and a test mode, the circuit includes a test terminal TEST. In response to a test signal input from the terminal via the buffer 41, the input terminal I
The signal supplied to N, the output pin via a buffer 44
A plurality internal mode switching circuit 2b to be output to, during normal operation is supplied signal output of these mode switching circuit 2b, the internal and outputs a signal processing result from an output terminal OUT is returned to the mode switching circuit 2b logic And a circuit 3. The mode switching circuit 2b includes an inverter 25 for inputting a test signal, its output and a buffer.
AND 26 for receiving an output signal of the buffer 42 and a buffer 42
Logic of the output and input an output signal of the buffer 41 perilla
And AND27 for outputting the product result to the internal logic circuit 3 and a selector circuit 28 for outputting the output of these AND26 and Internal logic circuit 3 to selectively output terminal OUT.

In the test mode switching circuit described above, during a normal operation, a high level (hereinafter, referred to as "1") of a logic level is supplied to a test terminal TEST, so that an AND 26 of the mode switching circuit 2b is connected to an input terminal I.
Irrespective of the logical value of N,
The AND 27 supplies "1" to the internal logic circuit 3, and outputs an output of a predetermined signal processing result inside the internal logic circuit 3 to the selector circuit unit 28 of the mode switching circuit 2b. The selector circuit 28 is AND2
6 is "0", the output of the internal logic circuit is selected and output to the output terminal OUT for normal operation.

In a test mode operation, a test terminal TES
By supplying "0" to T, the AND 27 of the mode switching circuit 2b becomes uniquely "0" regardless of the logical value of the input terminal IN, and the AND 26 outputs "1" to the selector circuit unit 28. , The selector circuit 28 is AND2
The test operation is performed by selecting "1" of the output of No. 6 and outputting it to the output terminal OUT. That is, the internal operation mode is switched by a signal input from the outside to the dedicated terminal.

On the other hand, the number of external terminals has been increasing remarkably due to the recent increase in the scale and the number of functions of semiconductor devices, and thus the reduction of external terminals has become urgent. An example of realizing mode switching without using a dedicated external terminal to meet this need is described in Japanese Patent Application Laid-Open No. 63-10538.

Referring to FIG. 5 which shows a circuit diagram of an example in which a mode switching control terminal is shared with other terminals, the mode switching circuit comprises an input buffer to which a signal is supplied from a control terminal IN. 51, level determining circuits 52 and 55 to which the output of the input buffer 51 is supplied, and an AND 54 for receiving the output of the level determining circuit 55 and the output of the level determining circuit 52 via the inverter 53, respectively. It comprises a counter 56 for inputting and counting the output of the AND 54.

Further, referring to FIG. 6 showing a timing chart for explaining the operation of FIG. 5 and FIG. 7 showing the timing chart in consideration of waveform blunting, respectively, the mode switching circuit includes, for example, a control terminal IN. Is a signal of “1” as an input signal during normal operation, and V as a determination level of the level determination circuit unit 52 during test operation.
It is assumed that a signal of an intermediate level between the TH level and the VTL level serving as the determination level of the level determination circuit unit 55 is supplied. At this time, the level judgment circuit 52
A region V1 for recognizing a logical value "1" between the level and the power supply potential VDD, a region V2 for recognizing a logical value "1" between the VTL level and the power supply potential VDD by the level determination circuit 55,
A region V3 in which the level determination circuit 52 recognizes a logical value "0" between the VTH level and the ground potential GND;
5 is a region V4 for recognizing a logical value “0” between the VTL level and the ground potential GND (input waveform of the control terminal IN in FIGS. 6 and 7).

Here, a normal operation will be described first with reference to FIG. 6 (abnormal operation using FIG. 7 will be described later). At the time of normal operation, the VDD level is supplied to the control terminal IN as the above-mentioned “1” signal and the GND level is supplied as the “0” signal, so that the level determination circuit unit 52 is set to the VDD level higher than the determination level VTH. In response, the same VDD level as the input signal is output (the output waveform of the level determination circuit 52 in FIG. 6).

The inverter 53 at the next stage outputs the inverted level of "0" from the inverter 53 since this waveform is within the area where the waveform is recognized as logic "1" (the output waveform of the inverter 53 in FIG. 6). ). The level judgment circuit 55 is also VDD.
Since the level is higher than the determination level VTH, the same VDD level as the input signal is output (the output waveform of the level determination circuit 55 in FIG. 6).

Therefore, the output signals of the inverter 53 and the level determination circuit 55 have opposite polarities, and the output of the AND 54 receiving these signals is GN.
D level (output waveform of AND 54 in FIG. 6).

In the test mode operation, the above-mentioned intermediate level signal is supplied to the control terminal IN, so that the level judgment circuit 52 outputs the GND level in response to the intermediate level lower than the judgment level VTH (FIG. 6). Of the level determination circuit unit 52), and the inverted “1” is output from the inverter 53 (the output of the inverter 53 in FIG. 6).

The level judgment circuit 55 outputs the VDD level because the intermediate level is higher than the judgment level VTL (the output circuit of the level judgment circuit 55 in FIG. 6).

Therefore, the output signals of inverter 53 and level determination circuit 55 attain the VDD level, and the output of AND 54 receiving these signals is at VDD level.
D level (output waveform of AND 54 in FIG. 6).

That is, the internal operation mode can be switched according to the potential of the signal supplied to the control terminal from the outside.

Another conventional example in which a signal input terminal and a control terminal for mode switching are shared is disclosed in Japanese Patent Laid-Open No. 7-12.
No. 902. Referring to FIG. 8A which shows a circuit diagram of the mode switching circuit described in the publication and FIG. 8B which shows a timing chart for explaining the operation thereof, this circuit includes a power supply potential VDD2 and a power supply potential VDD1. , A load resistor 803 and an N-channel MOS transistor 801 are connected in series, and a mode setting detection signal is extracted from this series connection point.

A mode setting signal is supplied from the control terminal IN to the gate electrode of the N-channel MOS transistor 801, and this signal is also supplied to the internal logic circuit.

In a normal operation state, "0" of the input signal is at the GND level, "1" is the VDD1 potential, "0" of the mode setting signal at the time of the test is the GND potential, and "1" is VDD.
3 potentials, the drive power supply of the semiconductor device 80 is VDD2 potential, N
The potential on the source electrode side of the channel type MOS transistor 801 is set to VDD1 potential or higher.

In normal operation, even if the GND potential or the VDD1 potential, which is the level of the normal signal, is supplied to the control terminal IN, the mode setting detection signal 804 indicates the N-channel type MO.
Since the source electrode of the S transistor 801 is at or above the VDD1 potential, it is in a non-conductive state, so that a VDD2 potential obtained by adding a potential at or above VDD1 which is the threshold potential of the N-channel MOS transistor 801 to the VDD1 potential is output. .

At the time of the test mode operation, the potential VDD3 which is the mode setting signal “1” is supplied to the control terminal IN to make the N-channel MOS transistor 801 conductive, and the potential VDD1 is output as the mode setting detection signal 804. Is done.

That is, the internal operation mode is switched according to the potential of the signal supplied from the outside to the control terminal IN. In the case where the VDD2 potential is generated by a single power supply, this is realized by using a booster circuit in the semiconductor device 80.

[0021]

As described above, the conventional mode switching circuit described in Japanese Patent Application Laid-Open No. Hei 7-12902 is designed so that the package does not become as large as possible despite the increase in the size of the semiconductor device. Therefore, the number of external terminals that can be arranged has not increased so much. As a result, if a dedicated terminal for the test mode is provided, the number of external terminals used in normal operation can be reduced, and the function of the internal logic circuit must be reduced.

Therefore, when the test mode is realized, a dedicated external terminal is required, and there is a disadvantage that a desired circuit cannot be realized due to an increase in the number of terminals.

Further, a semiconductor device constituted by a CMOS circuit is characterized in that no power supply current is generated in a steady state. Utilizing this feature, a defect occurring during manufacturing is detected by an IDDQ test for measuring whether or not a power supply current flows. However, when a constant power supply current is generated in a steady state by a booster circuit, this IDDQ There is a disadvantage that the test cannot be applied and the reliability of the semiconductor device is reduced.

On the other hand, in the conventional mode switching circuit disclosed in Japanese Patent Application Laid-Open No. 63-10538, the actual input signal waveform supplied to the control terminal IN has a certain time width as shown in the timing chart of FIG. And changes from the power supply potential VDD to the ground potential GND, or from the ground potential GND to the power supply potential VDD, so that a spike waveform is generated at the output of the AND circuit 54.

That is, as described above with reference to FIG. 6, if the input signal is an ideal input signal having a short time width of potential change, the AND 54 outputs “0” in response to “1” of the control terminal IN during normal operation. However, when “1” of the control terminal IN has the time width of the timings t1 to t7, the output of the level determination circuit 52 shifts to the timing t6 when the logic value “1” becomes the recognition area V5, and further, the inverter 53 At timing t7, it recognizes the input and outputs "0".

On the other hand, the level judgment circuit 54 operates at the timing t2.
Recognizes "1" of the control terminal IN and outputs "1". As a result, the AND 55 becomes the inverter 53 at the timing t3.
"1" whose output has not changed yet and the level judgment circuit 5
The output “1” after the change of “4” is calculated, and a spike pulse of “1” is generated.

Similarly, at timings t8 to t14 when the control terminal IN transitions from "1" to "0", the AND55 recognizes "1" at the timing t11 and generates a spike pulse of "1" at timing t11 due to the time width. I do. Therefore, in the normal operation state, the VDD potential of “1” is applied to the control terminal,
When the GND potential of “0” is supplied, there is a disadvantage that the setting of the mode switching circuit is erroneously set, and a desired operation may not be realized.

In any of the above-described conventional examples, an additional capacitance is always added to the input terminal used during normal operation by the mode switching circuit. When the control terminals for switching are shared, there is also a disadvantage that the operation speed is reduced during normal operation.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned drawbacks, without providing a dedicated external terminal for switching between a normal operation and a test mode operation, and providing a normal input terminal and a dedicated control terminal. Without sharing
It is an object of the present invention to provide a mode switching circuit and a switching method having a normal input terminal that can shift to a test mode by changing a power supply potential VDD.

[0030]

A feature of the mode switching circuit of the present invention is that a test mode setting signal is generated in response to a mode setting signal supplied from the outside to switch to a test mode or a normal operation mode, and an internal logic circuit is generated. In a semiconductor device provided with a mode switching circuit for outputting to a circuit, a first power supply supplied from outside the semiconductor device, a level shift element, and the level shift element lowers the first power supply to a predetermined voltage. A second power supply which is supplied as an internal power supply to the mode switching circuit and the internal logic circuit in the semiconductor device, and the first power supply is momentarily turned off for a predetermined time to reach a ground potential. And a potential holding capacitance element that maintains the potential of the second power supply at the predetermined voltage for at least the predetermined time when the first power supply is disconnected. The potential change when the on-off from one to said mode setting signal.

[0031]

The mode switching circuit includes a first inverter having an input terminal connected to the first power supply, a second inverter cascaded to the first inverter, and a second inverter connected to the first inverter. And a mode setting circuit section comprising a multi-bit binary counter which outputs each bit output to the internal logic circuit as the test mode setting signal.

[0033] In addition, the binary counter, n (n
Consists of 2 or more integer) bits, the bit output
Normal operation mode when all bits of
The other bit output is set to a maximum of 2 ⁿ
-1 test applied to each test mode setting
It can be output to the internal logic circuit as a mode setting signal .

The mode switching method of the semiconductor device according to the present invention is characterized in that a test mode setting signal is generated in response to a mode setting signal supplied from the outside to switch to a test mode or a normal operation mode and output to an internal logic circuit. A first power supply supplied from outside the semiconductor device, a level shift element, and the first power supply is set to a predetermined voltage by the level shift element. The mode switching circuit in the semiconductor device which is stepped down and the internal
A second power supply supplied as an internal power supply to the logic circuit , and when the first power supply is instantaneously turned off to a ground potential for a predetermined time, the potential of the second power supply is changed at least for the predetermined time. A potential holding capacitance element for maintaining a predetermined voltage,
A first inverter having an input connected to the first power supply
Each multi-bit binary counter which outputs a bit output to the internal logic circuit as said test mode setting signal with counts the output of the second inverter a second inverter Toko cascaded to the first inverter of Toko said mode switching circuit composed of a consisting mode setting circuit unit from, have for wo, said first power supply and turning on and off from the outside, the first time before <br/> SL binary counter this off operation all bits in the low logic level, the internal logic circuit in the output value of the low level is shifted to the normal operation mode, each output value of the binary counter that changes according to the on-off operation of the second and subsequent The purpose is to sequentially shift the internal logic circuits to at most 2 ⁿ -1 types of test modes.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment showing a mode switching circuit of the present invention and its peripheral circuits. Referring to FIG. 1, this semiconductor device has a first power supply potential (hereinafter referred to as VDD1).
Enter the change of the mode switching circuit 2a for generating a test mode setting signal, the mode switching circuit 2
and an internal logic circuit 3 to which a test mode setting signal output from a is supplied. The potential of the cathode electrode of the diode element 1 that connects the anode electrode to the potential of VDD1 is referred to as a second power supply potential (hereinafter referred to as VDD2). ) And this VD
The mode switching circuit 2a, the internal logic circuit 3, and the capacitor 21 are connected between D2 and GND. This capacitive element 21 is turned on by setting VDD1 to a potential of, for example, 3.3 V.
After that, when VDD1 is set to the ground potential and turned off, it has a role of maintaining, for example, a 2.8V VDD2 potential for a time determined by the capacitance value.

The mode switching circuit 2a includes VDD2 and G
Between ND, an inverter circuit 22 composed of a P-channel MOS transistor P1 and an N-channel MOS transistor N1, an inverter circuit 23 composed of a P-channel MOS transistor P2 and an N-channel MOS transistor N2, and a mode setting circuit section 24 Are connected in parallel, and the input terminal of the inverter circuit 22 is VDD1
The output terminal is connected to the input terminal of the inverter circuit 23, and the output terminal of the inverter circuit 23 is connected to the mode setting circuit unit 2.
The output terminals of the mode setting circuit unit 24 are connected to the internal logic circuit 3 input terminals.

That is, while the mode switching circuit 2a and the internal logic circuit 3 are supplied with current from VDD2, the input terminal of the inverter 22 on the input side of the mode setting circuit 2a has a potential VDD1 higher than VDD2. It is connected to the.

The capacitance element 21 is formed, for example, by using an unused electrode pad in a semiconductor device when it is designed by a gate array, and is formed by an empty area of a pad area when it is designed by a cell-based IC. Formed of a material such as aluminum or polysilicon.

The outline of the operation of the mode setting circuit section 24 having the above-described circuit configuration is as follows. That is, during normal operation, VDD1 is always maintained at a predetermined power supply potential, here 3.3 V, so that the internal logic circuit 3 and the mode switching circuit 2a receive VDD2.
8 V is supplied and normal operation is performed. In this circuit, VD
When D1 is instantaneously lowered to "0", the diode element 1
The potential VDD2 on the cathode side of the capacitor element decreases in accordance with the capacitance value of the capacitive element 21. When the potential VDD2 returns to "1", the potential VDD2 responds to the speed of a predetermined time constant determined by the on-resistance value of the diode element 1 and the capacitance value of the capacitive element 21. The potential rises.

Therefore, in the test mode, VDD
1 is instantaneously reduced to “0” and this VDD
The potential of VDD1 is returned to the original "1" faster than the speed of decrease of the drive voltage VDD2 determined by the capacitor 21 following the change of "1", and the potential change of VDD1 is detected by the mode setting circuit unit 24. The mode setting signal of the mode setting circuit section 24 is activated, and the internal logic circuit 3 is switched to the test mode to perform a predetermined test.

Here, a case where a known binary counter is used as the mode setting circuit section 24 will be described.
Referring to FIG. 2A, which shows a circuit diagram of the binary counter, the input terminal of the binary counter of the mode setting circuit unit 24 is connected to the output terminal of the inverter 23 of FIG. 1, and the output terminals OUT1 and OUT2 are internally connected. This is a 2-bit counter connected to the logic circuit 3 and composed of general T-type flip-flops 247 and 278 as an example. OUT1 is the output of the flip-flop 247, OUT2 is the flip-flop 2
Forty-eight outputs, the signal of OUT1 is used for the first test mode of the internal logic circuit 3, and the signal of OUT2 is used for the second test mode. Each of these test modes is selected in the internal logic circuit, and the corresponding circuit is tested.

Referring to FIG. 2B showing a timing chart for explaining the operation, the mode setting circuit section 24 based on the binary counter has timings OUT1 and OUT2 whose timings t3 and t4 are the first test mode setting periods, timing t5 and t6 period becomes the second test mode setting period, timing t7 and t8 period indicates to be a third test mode setting period,
A total of three test modes can be set. 5th M
If the mode setting signal is returned to "1" at the timing of the trailing edge of the ODE signal, and the state is maintained thereafter, the normal operation state can be restored. Therefore, if the configuration of the counter is n (n is an integer of 2 or more) bits, 2 ⁿ −
One type of test mode can be set.

Next, the operation will be described with reference to FIG. 2 and FIG. 3 showing a timing chart for explaining the operation of the mode setting circuit section using this binary counter.

As described above, when VDD1 is supplied with 3.3 V, the threshold voltage of the diode element 1 is 0.5 V, and the capacitance value of the capacitor 21 is 30 pF, VDD2 is supplied with 2.8 V. . In this state, the mode setting signal MODE supplied to the clock C terminal of the binary counter 24 changes the power supply potential VDD1 from 3.3 V to 0 instantaneously.
The normal operation mode and the test mode are set by changing V → 3.3V.

First, the first V at timing t1 to t2
The flip-flops 247 and 248 are respectively initialized by the mode setting signal MODE “0” supplied in response to the change of DD1 of 3.3V → 0V → 3.3V, and the normal operation mode is set.

In response to the first mode setting signal MODE, flip-flop 247 transits to "0",
Timing t3 for inputting the next mode setting signal MODE
Hold that state until. During this period t1 to t3, the flip-flops 247 and 248 are both “0” and VD
Since D1 is returned to 3.3 V at timing t2, the mode setting signal MODE also returns to "1", the semiconductor device as a whole is in the normal power supply potential state, and the period from t2 to t3 is in the normal operation mode.

Next, at timing t3, the mode setting signal MODE supplied in response to the second change of VDD1 3.3V → 0V → 3.3V becomes “0” again. With this “0”, the first test mode of the internal logic circuit 3 is set. At this time, the polarity of the output OUT1 of the flip-flop 247 is inverted to “1”, and the state is maintained until the next mode setting signal MODE is input. The output OUT2 of the flip-flop 248 still maintains “0”.

Since VDD1 has returned to 3.3 V at timing t4, the mode setting signal MODE also returns to "1",
The semiconductor device as a whole is normally at the power supply potential state,
t4 t5 the predetermined circuit of the internal logic circuit is in the first test mode.

Next, at timing t5, the mode setting signal MODE supplied in response to the third change VDD1 of 3.3V → 0V → 3.3V becomes “0” again. With this “0”, the second test mode of the internal logic circuit 3 is set. At this time, the output OUT1 of the flip-flop 247 inverts the polarity again to “0” and maintains that state until the next mode setting signal MODE is input. The output OUT2 of the flip-flop 248 returns to “1” at this timing t5, and the flip-flop 247
"1" is maintained until the output is inverted.

Also in this case, since VDD1 is returned to 3.3 V at the timing t6, the mode setting signal MODE also returns to "1", the semiconductor device as a whole is in the normal power supply potential state, and after the period t6, the next timing change occurs . t7 or
Predetermined circuit of the internal logic circuit 3 becomes the second test mode.

By executing the above operation until the count value of the 2-bit binary counter makes one round, a test mode setting signal can be generated and the internal logic circuit can be brought into the test state.

As described above, VDD1 is increased from 3.3 V to 0 V by 2 ⁿ times the number of bits of the binary counter.
And following the change of VDD1, the capacitance element 2
1, the potential of VDD1 is returned to the original 3.3V faster than the reduction speed of the driving voltage VDD2 determined by the drive voltage VDD2.
By detecting the potential change of 1 by the binary counter of the mode setting circuit section 24, the test mode can be set for 2 ⁿ -1 times.

[0053]

As described above, the mode switching circuit of the present invention generates a test mode setting signal in response to a mode setting signal supplied to switch to the test mode or the normal operation mode, and generates the test mode setting signal to the internal logic circuit. A mode switching circuit built in the semiconductor device for outputting, wherein the inside of the semiconductor device is driven by a second power supply obtained by reducing a first power supply supplied from the outside to a predetermined voltage by a semiconductor element; When the power is turned off, the second power supply potential is maintained by the potential holding capacitance element for a predetermined time, and
When a predetermined potential of the first power supply is lowered to the ground potential by an external operation using a mode switching circuit that uses a potential change of the first power supply as a mode setting signal, the potential is maintained following the potential reduction. By performing a predetermined number of ON / OFF operations for returning the first power supply to a predetermined potential before the potential of the capacitive element transitions to the ground potential,
Since the internal logic circuit is shifted to the test mode or the normal operation mode, the first effect is that a dedicated control terminal for setting the test mode is not required, and at least one external terminal can be reduced as compared with the related art.

The second effect is that since there is no need to incorporate a booster circuit for generating a mode setting signal in the semiconductor device, a constant power supply current is not generated, and as a result, ID
A DQ test can be applied, and a failure detection rate of 95% or more can always be secured by applying the IDDQ test, as compared with a failure detection rate that has conventionally depended on a test pattern, thereby improving the reliability of a semiconductor device.

Further, as a third effect, since the mode switching terminal is not shared with the other signal terminals, there is no need to connect a mode switching circuit to the other signal terminals, and no additional capacitance is added. The operation speed can be increased as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a mode switching circuit of the present invention and its peripheral circuits.

FIG. 2A is a circuit diagram of a binary counter illustrating an example of a mode setting circuit unit in FIG. 1; 6B is a timing chart for explaining the operation.

FIG. 3 is a timing chart for explaining the operation of the circuit in FIG. 1;

FIG. 4 is a circuit diagram showing an example of a conventional mode setting circuit unit.

FIG. 5 is a circuit diagram showing another example of a conventional mode setting circuit unit.

FIG. 6 is a timing chart for explaining the operation of the circuit in FIG. 6;

FIG. 7 is a timing chart in consideration of waveform blunting in FIG. 6;

FIG. 8A is a circuit diagram showing still another example of the conventional mode setting circuit unit. 6B is a timing chart for explaining the operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Diode element 2a, 2b Mode switching circuit 3 Internal logic circuit 21 Capacitance element 22, 23, 25, 53 Inverter 24 Mode setting circuit part 26, 27, 54 AND 28 Selector circuit 41, 42, 51, 802 Input buffer 44 Output buffer 52, 55 Level determination circuit 56 Counter 80 Semiconductor device 247, 248 D-type flip-flop 803 Load resistance 804 Mode setting detection signal P1, P2 P-channel MOS transistor N1, N2, 801 N-channel MOS transistor

Claims (4)

(57) [Claims] 1. A semiconductor device comprising a mode switching circuit for generating a test mode setting signal in response to a mode setting signal supplied from the outside to switch to a test mode or a normal operation mode and outputting the generated signal to an internal logic circuit. A first power supply supplied from the outside of the semiconductor device, a level shift element, the first power supply stepped down to a predetermined voltage by the level shift element, the mode switching circuit in the semiconductor device and the internal A second power supply supplied to the logic circuit as an internal power supply, and the second power supply for at least the predetermined time when the first power supply is momentarily turned off to a ground potential for a predetermined time. And a potential holding capacitance element for maintaining the potential of the first power supply at the predetermined voltage, wherein the potential change when the first power supply is turned on / off from outside is determined by the mode setting signal. Wherein a is. 2. The mode switching circuit includes: a first inverter having an input terminal connected to the first power supply; a second inverter cascaded to the first inverter;
2. A mode setting circuit section comprising a multi-bit binary counter for counting the output of the second inverter and outputting each bit output as the test mode setting signal to the internal logic circuit. Semiconductor device. 3. The binary counter has an n (n is an integer of 2 or more) bit configuration. When all bits of the bit output are at a low level of a logic level, the binary counter is set to a normal operation mode setting, and the other bit outputs are set to the normal operation mode. as the test mode setting signal to be applied respectively to the maximum in 2 ⁿ -1 kinds of test mode setting, claim 2 to be output to the internal logic circuit
13. The semiconductor device according to claim 1. 4. A mode of a semiconductor device comprising a mode switching circuit for generating a test mode setting signal in response to a mode setting signal supplied from the outside to switch to a test mode or a normal operation mode and outputting the generated signal to an internal logic circuit. In the setting method, a first power supply externally supplied to the semiconductor device, a level shift element, and the mode switching in the semiconductor device by lowering the first power supply to a predetermined voltage by the level shift element Circuit and said
A second power supply supplied as an internal power supply to an internal logic circuit , and a potential of the second power supply for at least the predetermined time when the first power is momentarily turned off to a ground potential for a predetermined time. a potential holding capacitor element to maintain said predetermined voltage, a second inverter of the first second inverter Toko input to the power supply is cascaded to the first inverter of the first inverter Toko to be connected said mode switching circuit composed of a plurality of bits of the binary counter reaches the mode setting circuit from outputting the respective bit outputs to the internal logic circuit as said test mode setting signal with counts the output of, have for wo, said first power supply and turning on and off from the outside, and the low level of the total bit <br/> logic level of the binary counter at the first time of the on-off operation, It said internal logic circuit in the low level of the output value of is shifted to the normal operation mode,
A mode in which the internal logic circuit sequentially shifts to at most 2 ⁿ -1 kinds of the test modes for each output value of the binary counter that changes in accordance with the on / off operation from the second time on. Setting method.