JP4738508B2 - Reception circuit, communication device, and communication system - Google Patents

Description

  The present invention relates to a receiving circuit of a communication system for performing communication between facilities such as buildings. In particular, it is possible to save power while providing functions (means) necessary for demodulating a signal.

  From the viewpoint of global warming, depletion of energy resources, cost reduction, etc., it is very important to reduce power consumption. Even in a communication system for performing communication between facilities, it is necessary to save power by turning off the power supply when communication is not being performed. In particular, in equipment systems, devices such as sensors using batteries as a driving source are also related to battery life, so power saving is an important issue.

  Here, in the wireless communication system, unless it is basically synchronized, it is not known when the transmitting terminal transmits a signal. Therefore, the receiving terminal may be in a state where it can always receive, or the receiving terminal is intermittently activated, and the transmitting terminal transmits a signal while the receiving terminal is activated to perform communication. is there. However, when the receiving terminal is operated intermittently, the timing of transmitting a signal from the transmitting terminal depends on the state of the receiving terminal.

  Further, in a wireless communication system, a signal is attenuated depending on a distance, or a signal size is changed due to interference caused by a reflected wave or the like. Therefore, in the receiving terminal, since the magnitude of the received signal varies, the output signal becomes unstable, and it becomes difficult to detect the signal.

  Further, the receiving terminal needs a synchronization clock for detecting the level of the received signal at regular intervals. For this reason, in order to generate this clock, the receiving terminal normally requires an element for transmitting the clock and an element for synchronizing the oscillated clock with the received signal.

  As techniques for improving communication reliability in a wireless communication system, AGC (Auto Gain Control) and PLL (Phase Lock Loop) are known. If AGC is used, the output can be stably obtained regardless of the strength of the received signal. Moreover, if a PLL is used, an output with high frequency accuracy can be obtained, or clock synchronization can be performed with high accuracy.

  In the above wireless communication system, the power consumption has been increased by providing a circuit or the like for executing these functions. For this reason, for example, with respect to a clock signal, the data and synchronization information are included in the signal, the clock timing is obtained from the synchronization information in the signal, and synchronization with the signal is performed using a delay element, so that the PLL is The power consumption is reduced without using an element with high functionality and high power consumption (see, for example, Patent Document 1).

JP 2004-320086 A (Claim 1, FIG. 1)

  However, for example, in the system disclosed in Patent Document 1, it is necessary to always operate the receiving terminal in order to perform communication at any time. In addition, since it has an element that oscillates a sampling clock, power consumption has increased.

  Furthermore, it is configured without using AGC which stabilizes the output. By not using AGC, power consumption is reduced. However, the size of the received signal varies due to the distance between terminals and the interference of waves, and the output signal becomes unstable. It will decline. For example, in ASK (Amplitude Shift Keying), when AGC is not used, there is a problem that the pulse width indicating data changes due to fluctuation in the magnitude of the received signal, and data cannot be demodulated correctly. .

  Therefore, a receiving circuit that can ensure communication reliability and can always receive a signal while reducing power consumption without using a circuit such as AGC with high power consumption, and the receiving circuit thereof It aims at obtaining the communication apparatus etc. which have.

In order to solve such a problem, the receiving circuit of the present invention includes a signal receiving circuit that performs processing for extracting a data signal composed of a data pulse train from a received signal, and a signal level based on a falling edge of a pulse of the data pulse train. The level of the demodulation pulse is detected at the timing of the delay clock using the demodulation pulse generated for detection and the delay clock generated by delaying the demodulation pulse, and the data included in the data signal based on the level And a power supply control circuit that starts supplying power to the demodulation circuit based on the rising edge of the pulse of the data pulse train when the data signal is received.

  According to the present invention, since the receiving circuit supplies power to the demodulation circuit when receiving a signal, power saving can be achieved. At this time, since the delay clock is generated when power is supplied to the demodulation circuit, it is not necessary to use a clock generator, and power consumption can be reduced.

It is a figure showing the structure of the communication apparatus 10 in Embodiment 1 of this invention. 3 is a diagram illustrating an example of a configuration content of a data signal and a pulse arrangement according to Embodiment 1. FIG. 3 is a diagram illustrating an outline of a radio signal related to communication in Embodiment 1. FIG. 6 is a diagram illustrating a signal processing operation in the reception circuit 100 according to the first embodiment. FIG. 3 is a diagram illustrating a time chart in the receiving circuit 100 according to Embodiment 1. FIG. It is a figure showing the structure of 10 A of communication apparatuses in Embodiment 2 of this invention. FIG. 10 is a diagram illustrating a time chart in receiving circuit 100A of the second embodiment. It is a figure which shows an example of the content of a data signal of Embodiment 3, and a pulse arrangement | sequence. FIG. 10 is a configuration diagram of a communication system in a fourth embodiment. It is a figure which shows the structure content of the starting request signal in Embodiment 2, and a real signal. It is a figure showing the signal processing operation in the child terminal. FIG. 20 is a diagram showing an exemplary sequence in the communication system according to the fourth embodiment.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration of a communication device 10 according to Embodiment 1 of the present invention. In FIG. 1, the communication device 10 includes a receiving circuit 100 that receives and demodulates a radio signal, and a data processing circuit 108 that processes data related to the signal demodulated by the receiving circuit 100.

  The reception circuit 100 further includes a signal reception circuit 101, a demodulation circuit 102, and a power supply control circuit 103. The signal receiving circuit 101 is a circuit that receives a radio signal, removes a carrier wave from the radio signal, and extracts a baseband signal. The signal receiving circuit 101 is configured using, for example, a detection circuit using a passive element. It is always operated with low power consumption so that a wireless signal can be received.

  FIG. 2 is a diagram showing an outline of an example of the configuration content of a data signal serving as a baseband signal to be transmitted and a pulse arrangement of the signal. The data signal according to the present embodiment includes a start pulse 201 for starting the demodulation circuit 102 and a data pulse train 202 representing data obtained by digitizing (binarizing) video, sound, and data.

  FIG. 3 is a diagram showing an outline of a radio signal related to communication in the first embodiment. The transmission-side apparatus performs wireless transmission by superimposing a baseband signal on a carrier wave. Then, the receiving device extracts the baseband signal from the received carrier wave and demodulates it.

  Here, in the communication according to the present embodiment, it is assumed that a method for modulating data into a data signal is performed by pulse position modulation. This is a modulation scheme in which a data value is represented by a width of an interval between two pulses within a certain divided time width (one symbol). Thereby, here, it is assumed that two values (“1” and “0”) can be distinguished by one symbol. Two pulses are arranged in one symbol, and “1” and “0” are represented by the interval between the two pulses (the position of the second pulse). For example, when “1” is represented, the interval between the first pulse and the second pulse is set longer than the interval when “0” is represented. In this embodiment, for example, a signal having a frequency of 429 MHz is used as a carrier wave and a frequency of 100 Hz is used as a baseband signal. However, the frequency is not limited to these.

  In the present embodiment, the power supply control circuit 103 has, for example, an RS flip-flop. The RS flip-flop is a 1-bit storage element that stores “1” when a signal is input to the set terminal and stores “0” when a signal is input to the reset terminal. For example, when a start pulse of a data signal is input to the power supply control circuit 103, a signal is input to the set terminal of the RS flip-flop, and “1” is stored in the RS flip-flop. While “1” is stored, the RS flip-flop outputs “1”. On the other hand, when a stop request signal is received from the data processing circuit 108, a signal is input to the reset terminal of the RS flip-flop, and “0” is stored in the RS flip-flop. While “0” is stored, the RS flip-flop outputs “0”. The power supply control circuit 103 supplies power to the demodulation circuit 102 while the output of the RS flip-flop is “1”, and stops supplying power to the demodulation circuit 102 while the output of the RS flip-flop is “0”. Thus, power supply control to the demodulation circuit 102 is performed.

  The demodulation circuit 102 includes a pulse generation circuit 104, a delay circuit 106, a signal detection circuit 105, and a storage unit 107. When the pulse generation circuit 104 detects a rising edge or a falling edge of the pulse, the pulse generation circuit 104 inverts the signal level to a “high” level (for example, a higher voltage side) or a “low” level (for example, a lower voltage side), and demodulates the signal. It is a circuit which produces | generates the pulse which concerns on. In this embodiment, the level is inverted when a rising edge is detected. The pulse generation circuit 104 can be configured by a T flip-flop, for example. Here, the T flip-flop is a 1-bit storage element that inverts the level each time a signal is input and stores the inverted level.

  The delay circuit 106 is a circuit that generates a delay clock that is a pulse obtained by delaying the pulse generated by the pulse generation circuit 104 by a predetermined time. The delay clock generated by the delay circuit 106 is used as the clock synchronization timing when detecting the signal level. The delay circuit 106 can generate a delay clock delayed by a predetermined time by using, for example, an integration circuit composed of an RC circuit. The signal detection circuit 105 synchronizes with the delay clock, and at the timing when the delay clock rises (becomes a “high” level), the level of the pulse generated by the pulse generation circuit 104 is the “high” level or the “low” level. Is detected, and the detected level is output. The storage unit 107 stores (stores) a value based on the level detected by the signal detection circuit 105 as data. For the storage unit 107, for example, a D flip-flop is used. Here, if the level related to detection is “high” level, it is stored as “1”, and if it is “low” level, it is stored as “0”.

  The data processing circuit 108 is a circuit that processes data represented by the demodulated signal stored in the storage unit 107. When the data processing is completed, a power supply stop request signal is transmitted to the power supply control circuit 103.

  FIG. 4 is a diagram illustrating a flowchart for explaining the signal processing (demodulation processing) operation in the receiving circuit 100. Hereinafter, the signal processing operation in the receiving circuit 100 of the communication device 10 will be described with reference to the flowchart shown in FIG. In the receiving circuit 100, when receiving the radio signal, the signal receiving circuit 101 removes the carrier wave and extracts the start pulse 201 and the data pulse train 202 (S001). Next, the activation pulse 201 becomes a set signal, and the power supply control circuit 103 starts supplying power to the demodulation circuit 102 (S002).

  In the demodulation circuit 102, when the data pulse train 202 is input to the pulse generation circuit 104, a pulse for demodulating the signal (demodulation pulse) is generated (S003). The delay circuit 106 delays the demodulation pulse generated by the pulse generation circuit 104 for a predetermined time to generate a delay clock, and supplies the delay clock to the signal detection circuit 105 and the storage unit 107 (S004).

  The signal detection circuit 105 detects the level of the demodulation pulse generated by the pulse generation circuit 104 in accordance with the delay clock from the delay circuit 106 (S005). The storage unit 107 stores a value based on the level detected by the signal detection circuit 105 as data in the storage unit 107 in accordance with the delay clock supplied by the delay circuit 106 (S006).

  The data processing circuit 108 performs processing (for example, data update, sensing, etc.) based on the data stored in the storage unit 107 (S007). When the data processing circuit 108 finishes the process, it transmits a stop request signal to the power supply control circuit 103. Receiving the stop request signal, the power supply control circuit 103 stops the power supply to the demodulation circuit 102 (S008). Thereby, the signal processing operation in the receiving circuit 100 is completed.

  FIG. 5 is a diagram illustrating a time chart in the receiving circuit 100 according to the first embodiment. FIG. 5 shows the waveforms of the signals generated by the circuits in the signal processing operation of FIG. 4 when the values represented by the signals are “1” and “0”. The signal receiving circuit 101 extracts two pulses arranged in one symbol by a pulse position modulation method in the data signal. As described above, when “1”, the interval between two pulses in the data signal is wider than when “0”.

  The pulse generation circuit 104 inverts to the “high” level at the rising edge of the first pulse, and inverts to the “low” level again at the rising edge of the second pulse. Thereby, a pulse for demodulation is generated. Here, when “1”, the width of the interval between two pulses in the data signal is wide. Therefore, the demodulation pulse at “1” has a wider pulse width than at “0”. The delay clock generated by the delay circuit 106 has a waveform obtained by shifting the demodulation pulse by a predetermined time.

  When the signal detection circuit 105 detects the level of the pulse for demodulation in synchronization with the delay clock, the pulse width is wide in the case of “1”, so that it is in the “high” level state. For this reason, the storage unit 107 stores a “high” level representing “1”. On the other hand, in the case of “0”, the pulse width is narrower than “1”, and the level has already been lowered and is in the “low” level state. Therefore, the storage unit 107 stores a “low” level representing “0”.

  As described above, in the receiving circuit 100 of the communication device 10 according to the first embodiment, when the data signal composed of the start pulse 201 and the data pulse train 202 as the head of the signal is input, the power supply control circuit 103 demodulates. Since power supply to the circuit 102 is started, power consumption can be reduced by performing a demodulation operation only when a signal is received. At this time, the signal receiving circuit 101 can always receive a wireless signal, so that the transmitting communication device can transmit the wireless signal at an arbitrary timing independent of the receiving communication device. In addition, since the demodulation pulse generated by the pulse generation circuit 104 is delayed and used as a delay clock, for example, a clock is generated without using a complicated synchronization circuit such as a PLL to synchronize each symbol. Can be done. For this reason, power consumption and cost can be reduced.

  In addition, since the power supply control circuit 103 stops the power supply to the demodulation circuit 102 by the stop request signal from the data processing circuit 108, the power consumption control circuit 103 performs the demodulation operation only when the signal is received, thereby reducing the power consumption. Reduction can be achieved.

  Furthermore, since the signal detection circuit 105 detects the level from the pulse for demodulation newly generated by the rising edge or falling edge of the data signal, the pulse generation circuit 104 does not depend on the strength of the data signal, A stable output waveform with a constant pulse width can be obtained. With such a configuration, it is not necessary to use a complicated output adjustment circuit such as AGC, and communication reliability can be improved while reducing power consumption. Furthermore, since a complicated circuit is not used, cost can be reduced. In addition, the configuration of the receiving circuit 100 can be simplified by using a PPM modulation method in which two pulses are arranged in one symbol.

Embodiment 2. FIG.
FIG. 6 is a diagram showing a configuration of communication apparatus 10A according to Embodiment 2 of the present invention. In FIG. 6, the same processing operations as those described in the first embodiment are performed for circuits, means, and the like that have the same reference numerals as those in FIG. 1. The receiving circuit 100A in FIG. 6 is different from the receiving circuit 100 in that the modulation circuit 102A includes an analog conversion circuit 109.

  The analog conversion circuit 109 is a circuit that converts the pulse generated by the pulse generation circuit 104 into an analog signal. For example, a circuit that can be converted into an analog signal that can output a level (for example, voltage) corresponding to a pulse width, such as an integration circuit. For this reason, the wider the pulse width generated by the pulse generation circuit 104, the higher the level of the analog signal. In this embodiment, it is assumed that the signal detection circuit 105 detects a level in an analog signal.

  In the signal modulation method in the first embodiment, an example is shown in which one symbol represents a binary value (“0”, “1”), but the information amount in one symbol can also be increased. Therefore, in the present embodiment, a case will be described in which the amount of information in one symbol is four values (“00”, “01”, “10”, “11”).

  FIG. 7 is a diagram illustrating a time chart in the receiving circuit 100A of the second embodiment. FIG. 7 shows the waveforms generated by the respective circuits in the signal processing operation when the values represented by the signals are “00”, “01”, “10”, and “11”. The signal receiving circuit 101 extracts two pulses arranged in one symbol by a pulse position modulation method in the data signal. In order to represent four values in one symbol, the width of the interval between two pulses can be changed in four ways.

  The pulse generation circuit 104 generates a demodulation pulse based on the width of the interval between two pulses. The wider the interval between two pulses, the wider the pulse width. In this embodiment, “00”, “01”, “10”, and “11” become wider in this order. The delay clock generated by the delay circuit 106 has a waveform obtained by shifting the demodulation pulse by a predetermined time.

  The analog conversion circuit 109 outputs analog signals of different levels (here, four) depending on the pulse width difference in the demodulation pulse. The signal detection circuit 105 detects the level of the analog signal and performs output divided into four types, and the storage unit 107 stores a value based on the output of the signal detection circuit 105 as data.

  As described above, according to the receiving circuit 100A of the communication device 10A of the second embodiment, the analog conversion circuit 109 has three or more levels based on the pulse width in the demodulation pulse generated by the pulse generation circuit 104. Since it can be expressed, it is possible to represent a data value larger than two values by one symbol, and it is possible to increase the amount of information and improve the communication speed.

Embodiment 3 FIG.
FIG. 8 is a schematic diagram showing an example of a pulse arrangement of a data signal in the third embodiment. In the first embodiment, the start pulse 201 and the data pulse train 202 constitute a data signal.

  In this embodiment, as shown in FIG. 8, the first pulse of the data pulse train 202A is used as a start pulse. When the first pulse of the data pulse train 202A is a start pulse and the rising edge portion is input to the set terminal of the RS flip-flop of the power supply control circuit 103, the power supply control circuit 103 supplies power to the demodulation circuit 102. .

  Here, since the power supply control circuit 103 supplies power with the rising edge of the first pulse of the data pulse train 202A, the pulse generation circuit 104 may not be able to detect the rising edge of the first pulse. Therefore, when detecting the falling edge of the pulse in the data pulse train 202A, the pulse generation circuit 104 inverts the level and generates a pulse related to demodulation. Thereby, it is not necessary to provide a separate start pulse in the data signal, and the data signal can be configured only by the data pulse train 202A, and the configuration of the signal can be simplified.

  In the first embodiment described above, the power supply control circuit 103 stops the power supply to the demodulation circuit 102 based on the stop request signal from the data processing circuit 108. However, the present invention is not limited to this. Absent. For example, a timer or the like (not shown) may be provided, and power supply to the demodulation circuit 102 may be stopped when it is determined that a predetermined time after demodulation processing has elapsed after the start of power supply. As a result, even when the power supply control circuit 103 erroneously activates the demodulation circuit 102 using noise or the like as a start pulse, even if there is no stop request signal from the data processing circuit 108, after a certain time has passed, The power supply can be stopped. In addition, since the power supply to the demodulation circuit 102 is stopped, the data signal can be received even after receiving noise.

Embodiment 4 FIG.
FIG. 9 is a diagram showing a communication system according to Embodiment 4 of the present invention. The communication system of the present embodiment is composed of one or a plurality of parent terminals 301 and one or a plurality of child terminals 302. In FIG. 9, it is composed of one parent terminal 301 and one child terminal 302.

  The parent terminal 301 includes a transmission circuit 303 and a parent terminal second communication unit 304. The transmission circuit 303 transmits an activation request signal by wireless communication. Then, the parent terminal second communication unit 304 instructs the transmission circuit 303 to transmit an activation request signal. In addition, data signals are transmitted / received to / from the second communication unit 307 by wireless communication.

  On the other hand, the child terminal 302 includes a receiving circuit 305, a terminal identification circuit 306, and a second communication unit 307. The receiving circuit 100 is the receiving circuit 100 described in the first embodiment. In the present embodiment, the destination address represented by the data pulse train of the received activation request signal is detected as data and stored in the storage unit 107. Here, the receiving circuit 100 will be described, but the receiving circuit 100A described in the second embodiment may be used.

  The terminal identification circuit 306 includes its own terminal address storage unit 502 and a comparison circuit 504. Here, it is assumed that the terminal identification circuit 306 receives the same power supply control as that of the demodulation circuit 102 of the reception circuit 305 based on the control of the power supply control circuit 103. The own terminal address storage unit 502 stores the address data of the own terminal for the address that each terminal has uniquely in the communication system. Here, for example, a DIP switch, a D flip-flop, or the like is used for the own terminal address storage unit 502. The comparison circuit 504 compares the address data of the own terminal stored in the own terminal address 502 with the data of the destination address stored in the storage unit 107 of the receiving circuit 100. As a result, if it is determined that the data match, an activation signal is transmitted to the second communication unit 307, and the second communication unit 307 is activated. If it is determined that they do not match, the activation signal is not transmitted to the second communication unit 307 and the second communication unit 307 is not activated. Further, a stop request signal is transmitted to the power supply control circuit 103 in order to stop the power supply to the demodulation circuit 102 and the terminal identification circuit 306.

  The second communication unit 307 performs wireless communication with the parent terminal second communication unit 304 while activated. The communication performed between the parent terminal second communication unit 304 and the second communication unit 307 has a higher communication speed and higher data reliability than the communication performed between the transmission circuit 303 and the reception circuit 100. Communication. Accordingly, power consumption in the second communication unit 307 increases. Here, when the second communication unit 307 is activated, the second communication unit 307 transmits a stop request signal to the power supply control circuit 103.

  For this reason, in the communication system according to the present embodiment, the second communication unit 307 of the child terminal 302 that transmits and receives data is in a low power consumption sleep state and is activated when an activation request signal addressed to the own terminal is received. To enable transmission / reception.

  FIG. 10 is a schematic diagram showing the configuration contents of the activation request signal and the actual signal in the second embodiment. The activation request signal has the configuration of the activation pulse 201 and the data pulse train 202 described in the first embodiment. Here, in the present embodiment, data represented by the data pulse train 202 is data of the destination address 402. In addition, the actual signal has a configuration including the data of the destination address 402 and the payload 403 representing the actual data between the parent terminal 301 and the child terminal 302. Here, it is assumed that the start request signal and the actual data signal use, for example, frequencies of 429 MHz and 2.4 GHz, respectively.

  FIG. 11 is a diagram illustrating a flowchart for explaining a signal processing operation in the child terminal 302. Hereinafter, the signal processing operation will be described with reference to the flowchart shown in FIG. S101 to S106 in the flowchart of FIG. 11 are the same as S001 to S006 described in the first embodiment.

  Then, the comparison circuit 504 compares the address data of the own terminal stored in the own terminal address 502 with the data of the destination address 402 stored in the storage unit 107 of the receiving circuit 100 (S107). If it is determined that the two address data match, the comparison circuit 504 transmits an activation signal to the second communication unit 307 to activate the second communication unit 307 (S108). After being activated, the second communication unit 307 transmits a stop request signal to the power supply control circuit 103 to stop the power supply to the demodulation circuit 102 and the terminal identification circuit 306. On the other hand, if it is determined that the two address data do not match, the comparison circuit 504 does not transmit a start signal but transmits a stop request signal to the power supply control circuit 103 (S109).

  FIG. 12 is a diagram illustrating an example of a sequence in the communication system according to the fourth embodiment. FIG. 12 shows transition of activation or stop (sleep) state of each circuit of the child terminal 302 based on the flowchart of FIG.

  First, a case where the child terminal 302 receives an activation request signal including data of a destination address 402 addressed to another terminal will be described. Here, the destination address of the child terminal 302 is “YYY”. The parent terminal 301 transmits an activation request signal including the data pulse train 202 of “XXX” as the destination address 402 (S201). In response to the activation request signal including the activation pulse 201, the power supply control circuit 103 starts supplying power to the demodulation circuit 102 and the terminal identification circuit 306. The data pulse train 202 of the activation request signal is input to the demodulation circuit 102 (S202). The demodulation circuit 102 performs demodulation processing based on the data pulse train 202, and the data at the destination address 402 as a result is input to the terminal identification circuit 306 (S203). Since the comparison circuit 504 of the terminal identification circuit 306 determines that the two address data do not match, it does not transmit an activation signal to the second communication unit 307. For this reason, the second communication unit 307 is not in the activated state and remains in the stopped state. Since the comparison circuit 504 transmits a stop request signal to the power supply control circuit 103, the demodulation circuit 102 and the terminal identification circuit 306 are stopped from being supplied with power.

  Next, a case where the child terminal 302 receives an activation request signal including data of the destination address 402 addressed to the own terminal will be described. The parent terminal 301 transmits an activation request signal including the data pulse train 202 of “YYY” as the destination address 402 (S204). In response to the activation request signal including the activation pulse 201, the power supply control circuit 103 starts supplying power to the demodulation circuit 102 and the terminal identification circuit 306. The data pulse train 202 of the activation request signal is input to the demodulation circuit 102 (S205).

  The demodulation circuit 102 performs demodulation processing based on the data pulse train 202, and the data at the destination address 402 as a result is input to the terminal identification circuit 306 (S206). The comparison circuit 504 of the terminal identification circuit 306 transmits an activation signal to the second communication unit 307 in order to determine that the two address data match (S207). Thereby, the 2nd communication part 307 will be in a starting state. And the 2nd communication part 307 transmits / receives a data signal between the parent terminal 2nd communication parts 304 of the parent terminal 301, and transfers to a sleep state after completion | finish of communication. Further, since the second communication unit 307 transmits a stop request signal to the power supply control circuit 103, the power supply to the demodulation circuit 102 and the terminal identification circuit 306 is stopped, and the second communication unit 307 enters a stop state.

  Here, the second communication unit 307 is in the activated state, for example, when the second communication unit 307 is a microcomputer, the clock signal operates at a high speed and the power consumption is large. . The second communication unit 307 is in a sleep state when the clock signal is stopped, operating at a low speed, or when the peripheral circuit of the microcomputer is stopped. Thus, the power consumption is remarkably small.

  As described above, in the communication system according to the fourth embodiment, since the signal receiving circuit 101 can always receive a radio signal, the parent terminal 301 transmits a radio signal at an arbitrary timing independent of the child terminal 302. can do. In addition, when the activation request signal is received, the power supply control circuit 103 starts supplying power to the demodulation circuit 102 and the terminal identification circuit 306 by the activation pulse 201 in the activation request signal, so that power consumption is reduced. be able to. Further, when it is determined by the comparison operation of the comparison circuit 504 of the terminal identification circuit 306 that the activation request signal is addressed to the own terminal, the second communication unit 307 is activated in addition to the demodulation circuit 102 and the terminal identification circuit 306, If the terminal is not addressed to the terminal, the second communication unit 307 is not activated, the necessary circuits are operated in stages, and signal processing can be performed with minimum power consumption to process the activation request signal.

Embodiment 5 FIG.
In the above-described embodiment, wireless communication has been described. However, the present invention can also be applied to a wired case. In addition, communication can be performed with respect to the carrier medium using electromagnetic waves, infrared rays, visible light, or the like.

  In addition, although the parent terminal 301 and the child terminal 302 of the fourth embodiment are provided with the antenna for transmitting / receiving the activation request signal and the antenna for transmitting / receiving the actual signal, they may be a common antenna. Further, it may be divided into transmission and reception.

  Further, although not specifically shown in the fourth embodiment, for example, data of a broadcast address may be further stored in the own terminal address storage unit 502. Then, the comparison circuit 504 compares the broadcast address data with the data of the destination address stored in the storage unit 107 of the reception circuit 100. If the comparison circuit 504 determines that the data match, an activation signal is sent to the second communication unit 307. You may make it transmit. As a result, when communicating with a plurality of child terminals 302 in the system, it is not necessary to transmit an activation request signal for each child terminal 302, and the amount of signals in the system can be reduced.

  In the fourth embodiment, the child terminal 302 includes the receiving circuit 100, the terminal identification circuit 306, and the second communication unit 307. However, the child terminal 302 is not necessarily limited to the second communication unit 307. For example, in the sensor network, the second communication unit 307 may be configured with one or a plurality of sensors. At this time, the data of the destination address 402 of the activation request signal may be associated with each sensor of the child terminal 302. As a result, even when data of a plurality of physical quantities are included in a signal and transmitted, the receiving circuit 100 and the terminal identification circuit 306 can be configured as one, eliminating unnecessary operations and processing, and reducing power consumption. be able to.

  The present invention can be applied to a communication system used for an air conditioner, a lighting system, a sensor network, and the like. For example, in the case of an air conditioner, the air conditioner can include the parent terminal 301 in Embodiment 4, and a remote controller (hereinafter referred to as a remote controller) that operates the air conditioner can include the child terminal 302. At this time, by the operation described in the fourth embodiment, the air-conditioning apparatus transmits a signal including data such as temperature updates to the remote controller. Since the signal receiving circuit 101 of the remote controller is always in a state where signals can be received, the air conditioning apparatus can transmit data at an arbitrary time. In addition, the second communication unit 307 of the remote controller is in a sleep state except when receiving a signal. Thereby, the power consumption of the remote controller can be reduced and the battery life of the remote controller can be extended.

  Conversely, the present invention can also be applied to a system in which the air conditioning apparatus includes the child terminal 302 according to the fourth embodiment, and the remote controller that operates the air conditioning apparatus includes the parent terminal 301 according to the second embodiment. In this case, the 2nd communication part 307 of an air conditioning apparatus is always a sleep state except the case where a signal is received. Therefore, it is possible to reduce standby power of the air conditioner.

  Further, the air conditioning apparatus includes the child terminal 302 and the transmission circuit 303 in the second embodiment, and the remote controller for operating the air conditioning apparatus is also applied to a communication system including the child terminal 302 and the transmission circuit 303 in the fourth embodiment. can do. In this communication system, since the second communication unit 307 of the air conditioning device and the second communication unit 307 of the remote control are in a sleep state except when a signal is received, the power consumption of the air conditioning device and the remote control can be reduced. it can. In addition, since the signal receiving circuit 101 of the air conditioning apparatus and the signal receiving circuit 101 of the remote control can always receive the activation request signal, the transmission circuit 303 of the air conditioning apparatus and the transmission circuit 303 of the remote control can be at any time. An activation request signal can be transmitted.

  The sensor network described in the fifth embodiment can be applied to a communication system in which the terminal that controls the sensor includes the parent terminal 301 in the fourth embodiment, and the sensor includes the child terminal 302 in the fourth embodiment. it can. In such a communication system, since the second communication unit 307 of the terminal is in a sleep state except when transmitting / receiving actual signals, the power consumption of the sensor can be reduced. Also, the terminal that controls the sensor can perform wireless parameter setting, sensor data request, and the like at an arbitrary timing.

  10, 10A communication device, 100, 100A reception circuit, 101 signal reception circuit, 102, 102A demodulation circuit, 103 power supply control circuit, 104 pulse generation circuit, 105 signal detection circuit, 106 delay circuit, 107 storage unit, 108 data processing circuit 109 analog conversion circuit, 201 start pulse, 202 data pulse train, 301 parent terminal, 302 child terminal, 303 transmission circuit, 304 parent terminal second communication unit, 306 terminal identification circuit, 307 second communication unit, 402 destination address, 403 Payload, 502 own terminal address storage unit, 504 comparison circuit.

Claims (9)

A signal receiving circuit that performs a process of extracting a data signal composed of a data pulse train from the received signal;
Based on the falling edge of the pulse of the data pulse train, the demodulation pulse generated for signal level detection and the delay clock generated by delaying the demodulation pulse are used for the demodulation at the timing of the delay clock. A demodulation circuit that performs pulse level detection and generates data included in the data signal based on the level ;
A receiving circuit comprising: a power supply control circuit that starts supplying power to the demodulation circuit based on a rising edge of a pulse of the data pulse train when the data signal is received.   2. The receiving circuit according to claim 1, wherein the power supply control circuit stops the power supply to the demodulation circuit after a predetermined time has elapsed since the power supply to the demodulation circuit was started.   The power supply control circuit stops power supply to the demodulation circuit based on a stop request signal transmitted from a data processing circuit that processes data generated by the receiving circuit. The receiving circuit described. The demodulation circuit includes:
A pulse generation circuit that inverts the level of the data signal composed of a data pulse train based on a pulse position modulation system and inverts the level using a first pulse and a next pulse in a symbol in the received signal to generate a demodulation pulse When,
A delay circuit that delays a pulse generated by the pulse generation circuit for a predetermined time and generates a delay clock; and
A signal detection circuit for determining a level of a pulse generated by the pulse generation circuit in synchronization with the delay clock;
The receiving circuit according to claim 1, further comprising a storage unit that stores a value based on the level of the signal detection circuit as data. The demodulation circuit further includes an analog conversion circuit that converts an analog signal having a level based on a pulse width of the demodulation pulse generated by the pulse generation circuit,
5. The receiving circuit according to claim 4 , wherein the signal detection circuit determines the level of the analog signal generated by the analog conversion circuit instead of determining the level of the pulse generated by the pulse generation circuit. . The receiving circuit according to any one of claims 1 to 5 , wherein when receiving a start request signal from another communication device as the data signal, the start request signal is demodulated to generate data;
A terminal identification circuit that transmits an activation signal when it is determined that the activation request signal is addressed to the own communication device based on the data;
A communication device comprising: a second communication unit which is activated when receiving the activation signal and performs communication with the other communication terminal based on actual data. The activation request signal has destination address data, and the receiving circuit generates destination address data,
The terminal identification circuit includes a storage unit that stores address data related to the self-communication device,
The communication device according to claim 6 , wherein the activation signal is transmitted when the data of the destination address is compared with the data of the address related to the communication device and it is determined that they match. The storage unit further stores address data related to the broadcast,
Wherein the destination address of the data by comparing the address data of the broadcast, if it is determined that a match, the communication device according to claim 6 or 7, characterized in that for transmitting the activation signal. One or more parent terminals that transmit the activation request signal; and
Communication system, comprising one or a plurality of child terminal is a communication device according to any one of claims 6 to 8.

Images