JP6218760B2 - Photoelectric conversion element and imaging apparatus - Google Patents

Description

  The present disclosure relates to a photoelectric conversion element and an imaging apparatus using the photoelectric conversion element.

An imaging device that reads information based on radiation by converting the wavelength of radiation represented by α-rays, β-rays, γ-rays, and X-rays into a sensitivity range of a photoelectric conversion element with a wavelength converter is disclosed in, for example, Japanese Patent Application Laid-Open No. 2011-014752. It is known. The photoelectric conversion element disclosed in this patent publication is
A first semiconductor layer;
A second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; and
A third semiconductor layer composed of a conductivity type between the first semiconductor layer and the second semiconductor layer, and interposed between the first semiconductor layer and the second semiconductor layer;
including. And an insulating layer formed between the first semiconductor layer and the third semiconductor layer, and a contact hole formed in the insulating layer with an area smaller than the area of the second semiconductor layer, The first semiconductor layer and the third semiconductor layer are in contact with each other through a contact hole (see FIG. 8A). Alternatively, the first semiconductor layer is formed so that the edge is inside the edge of the second semiconductor layer (see FIG. 8B).

JP2011-014752

  By the way, in the photoelectric conversion element disclosed in this patent publication, when patterning the third semiconductor layer and the second semiconductor layer, the end portions of the third semiconductor layer and the second semiconductor layer are often used. A forward tapered slope is formed, and the end of the third semiconductor layer is not covered with the second semiconductor layer (see FIGS. 8A and 8B). In such a state, the electric field formed by applying the voltage to the second semiconductor layer does not sufficiently reach the end of the third semiconductor layer, and the end of the third semiconductor layer. It takes time for the carriers generated in step 2 to reach the second semiconductor layer. As a result, the afterimage characteristics are deteriorated, and afterimages are unevenly generated when a plurality of images are captured in a short time by the imaging device.

  Accordingly, an object of the present disclosure is to provide a photoelectric conversion element having a configuration and structure that hardly causes afterimage unevenness in an image, and an imaging apparatus using the photoelectric conversion element.

The photoelectric conversion element according to the first aspect of the present disclosure for achieving the above object is:
substrate,
A first semiconductor layer having a first conductivity type formed on a substrate;
An interlayer insulating layer that covers the substrate and the first semiconductor layer and has an opening at the bottom where the first semiconductor layer is exposed;
A third semiconductor layer formed over the first semiconductor layer exposed from the interlayer insulating layer to the bottom of the opening; and
A second semiconductor layer formed on the third semiconductor layer and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered slope is formed at the ends of the second and third semiconductor layers,
A fourth semiconductor layer having the second conductivity type is formed on at least the forward tapered slope.

The photoelectric conversion element according to the second aspect of the present disclosure for achieving the above object is
substrate,
An interlayer insulating layer covering the substrate and having an opening in which the substrate is exposed at the bottom;
A first semiconductor layer formed over the substrate exposed from the interlayer insulating layer to the bottom of the opening;
A third semiconductor layer covering the first semiconductor layer; and
A second semiconductor layer formed on the third semiconductor layer and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered slope is formed at the ends of the second and third semiconductor layers,
A fourth semiconductor layer having the second conductivity type is formed on at least the forward tapered slope.

  In order to achieve the above object, the imaging apparatus according to the present disclosure includes a photoelectric conversion element according to the first aspect or the second aspect of the present disclosure in which the second direction is different from the first direction and the first direction. Are arranged in a two-dimensional matrix in this direction.

  In the photoelectric conversion element according to the first aspect and the second aspect of the present disclosure, the fourth semiconductor layer having the second conductivity type is formed on at least the forward tapered slope, so that the voltage to the second semiconductor layer As a result of surely including the end of the third semiconductor layer in the electric field formed by the application of, the carriers generated at the end of the third semiconductor layer immediately reach the second semiconductor layer. Therefore, afterimage characteristics are deteriorated, and when a plurality of images are captured in a short time by the imaging apparatus, it is possible to reliably suppress the occurrence of a problem that afterimage unevenness occurs in the images. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.

1A and 1B are schematic partial end views of the photoelectric conversion elements of Example 1 and Example 2, respectively. 2A and 2B are schematic partial end views of the photoelectric conversion elements of Example 3 and Example 4, respectively. 3A and 3B are schematic partial end views of a substrate and the like for describing the method for manufacturing the photoelectric conversion element of Example 1. FIG. FIG. 4 is a schematic partial end view of the substrate and the like for explaining the manufacturing method of the photoelectric conversion element of Example 1 following FIG. 3B. FIG. 5 is a system configuration diagram illustrating an outline of a system configuration of the imaging apparatus according to the present disclosure. FIG. 6 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel including one photoelectric conversion element. FIG. 7 is a circuit diagram illustrating an example of a passive pixel circuit configuration. 8A and 8B are schematic partial end views of a conventional photoelectric conversion element.

Hereinafter, although this indication is explained based on an example with reference to drawings, this indication is not limited to an example and various numerical values and materials in an example are illustrations. The description will be given in the following order.
1. 1. Description of the photoelectric conversion element according to the first aspect to the second aspect of the present disclosure and the imaging apparatus of the present disclosure in general. Example 1 (a photoelectric conversion element according to the first aspect of the present disclosure, a photoelectric conversion element having the first configuration, and an imaging apparatus according to the present disclosure)
3. Example 2 (a photoelectric conversion element according to the first aspect of the present disclosure, a photoelectric conversion element having the second configuration, and an imaging apparatus according to the present disclosure)
4). Example 3 (a photoelectric conversion element according to the second aspect of the present disclosure, a photoelectric conversion element having the first configuration, and an imaging apparatus according to the present disclosure)
5. Example 4 (a photoelectric conversion element according to the second aspect of the present disclosure, a photoelectric conversion element having the second configuration, and an imaging apparatus according to the present disclosure)
6). Example 5 (system configuration of imaging apparatus)
7). Other

<Explanation Regarding Photoelectric Conversion Element According to First to Second Aspects of Present Disclosure and Imaging Device of Present Disclosure, General>
The photoelectric conversion element according to the first aspect or the second aspect of the present disclosure, the photoelectric conversion element according to the first aspect or the second aspect of the present disclosure that constitutes the imaging device of the present disclosure (hereinafter, these photoelectric conversions) In some cases, the elements may be collectively referred to as “a photoelectric conversion element or the like of the present disclosure”), and the fourth semiconductor layer may be configured to cover at least a forward tapered slope. Note that such a photoelectric conversion element of the present disclosure may be referred to as a “first configuration photoelectric conversion element” for convenience. Specifically, in the photoelectric conversion element having the first structure, the fourth semiconductor layer is formed (formed) so as to cover the end portions of the second semiconductor layer and the third semiconductor layer and the second semiconductor layer. The fourth semiconductor layer may be formed from the extended portion of the second semiconductor layer, and the end portion of the third semiconductor layer may be covered with such a fourth semiconductor layer. Alternatively, in the photoelectric conversion element or the like of the present disclosure, the fourth semiconductor layer is configured to be formed on the surface layer portion of the second semiconductor layer and the surface layer portion of the third semiconductor layer that form a forward tapered slope. Can do. Note that such a photoelectric conversion element of the present disclosure may be referred to as a “second configuration photoelectric conversion element” for convenience. Specifically, in the photoelectric conversion element having the second structure, an impurity having the second conductivity type is ion-implanted into end portions of the second semiconductor layer and the third semiconductor layer, so that the second semiconductor layer A fourth semiconductor layer (ion implantation region) can be formed in the surface layer portion and the surface layer portion of the third semiconductor layer.

In the photoelectric conversion element and the like of the present disclosure including the above preferable configuration,
The first conductivity type is p-type or n-type,
The second conductivity type is n-type or p-type,
The conductivity type of the third semiconductor layer may be i-type. That is, a PIN (Positive Intrinsic Negative) photodiode can be configured by the first semiconductor layer / the third semiconductor layer / the second semiconductor layer.

  Furthermore, in the photoelectric conversion element according to the first aspect of the present disclosure including the various preferable configurations and forms described above, the first semiconductor layer is made of polycrystalline silicon, and the second semiconductor is not limited thereto. The layer and the third semiconductor layer may be made of polycrystalline silicon or amorphous silicon. By configuring the first semiconductor layer from polycrystalline silicon, a sufficiently low-resistance semiconductor layer can be obtained, and variation in signal charge obtained in the photoelectric conversion element in the imaging device can be further reduced. Further, in the photoelectric conversion element according to the second aspect of the present disclosure including the various preferable configurations and forms described above, the first semiconductor layer is made of amorphous silicon, and the second semiconductor is not limited thereto. The layer and the third semiconductor layer may be made of polycrystalline silicon or amorphous silicon.

  Further, in the imaging device of the present disclosure including the various preferable configurations and forms described above, a wavelength converter that converts an incident energy ray into a wavelength in a sensitivity region of the photoelectric conversion element on the light incident side of the photoelectric conversion element It can be set as the form provided with.

  Furthermore, in the imaging device of the present disclosure including the various preferable configurations and forms described above, the second semiconductor layer is disposed between the photoelectric conversion element and the photoelectric conversion element along the second direction. A separation groove reaching the interlayer insulating layer via the third semiconductor layer can be formed. In this case, the second semiconductor layer and the third semiconductor layer are adjacent to each other along the first direction. The photoelectric conversion elements can be formed continuously between the photoelectric conversion elements, and further, the light shielding layer is formed between the photoelectric conversion elements adjacent in the first direction. be able to. Furthermore, in the imaging device of the present disclosure including the various preferable configurations and forms described above, each photoelectric conversion element may be connected to a source follower type read transistor. That is, the signal charge obtained by the photoelectric conversion element is input to the gate electrode of the source follower type read transistor, and the source follower type read transistor outputs an electric signal corresponding to the signal charge.

  As a substrate in the photoelectric conversion element of the present disclosure including the various preferable configurations and forms described above, various glass substrates, various glass substrates having an insulating film formed on the surface, a quartz substrate, and an insulating film formed on the surface Quartz substrate, silicon semiconductor substrate, silicon semiconductor substrate with an insulating film formed on the surface, metal substrate made of various alloys and various metals such as stainless steel; polymethyl methacrylate (polymethyl methacrylate, PMMA) and polyvinyl alcohol (PVA) , Organic polymers exemplified by polyvinylphenol (PVP), polyethersulfone (PES), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) (flexibility composed of polymer materials) Plastic film and plastic Click sheet has the form of a polymeric material such as a plastic substrate) may be mentioned.

Further, as the material constituting the interlayer insulating _{layer, SiO X, SiN Y, SiO} X N Y, SOG (Spin On Glass), BPSG, PSG, BSG, AsSG, PbSG, NSG, LTO (Low Temperature Oxide, cold CVD- SiO ₂ ), SiOF, SiC, low melting glass, glass paste, titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), chromium oxide (CrO _x ), inorganic insulating materials such as zirconium oxide (ZrO ₂ ), niobium oxide (Nb ₂ O ₅ ), tin oxide (SnO ₂ ), vanadium oxide (VO _x ); polyimide resin, epoxy resin, acrylic resin, organic Organic insulating materials such as SOG and fluorine-based resin (eg, fluorocarbon, amorphous tetrafluoroethylene, poly Aryl ether, fluorinated aryl ether, fluorinated polyimide, parylene, benzocyclobutene, amorphous carbon, cycloperfluorocarbon polymer, and fluorinated fullerene). Examples of the method for forming the interlayer insulating layer include various processes such as various CVD methods, various coating methods, various PVD methods such as sputtering and vacuum deposition, screen printing methods, plating methods, electrodeposition methods, and dipping methods. it can.

Specifically, as an imaging apparatus of the present disclosure, a radiation imaging apparatus (a radiation reading apparatus or an X-ray flat panel detector, for capturing an image based on radiation represented by α rays, β rays, γ rays, and X rays) In this case, the wavelength converter mentioned above is specifically a scintillator composed of a scintillator, which is a generic term for substances that emit fluorescence (scintillation light) upon incidence of radiation. Examples thereof include a phosphor material layer made of a layer or a phosphor material. As scintillators or phosphor materials, organic materials such as anthracene and stilbene, plastic materials containing organic light-emitting substances, cesium iodide (CsI), thallium activated cesium iodide (CsI: Tl), sodium activated cesium iodide (CsI) : Na), gadolinium silicate, Ce-added gadolinium silicate, bismuth germanate, Gd ₂ O ₂ S: Tb, lutetium silicate, Ce-added lutetium silicate, thallium activated sodium iodide (NaI: Tl), Cerium fluoride, calcium fluoride, lead tungstate, calcium tungstate, cadmium tungstate, barium fluoride, lead fluoride, ZnS: Ag, europium activated lithium iodide, corundum, (Gd, M, Eu) ₂ O it can be exemplified ₃ Here, “M” is a rare earth element. Electromagnetic waves (for example, specifically, X-rays) are converted into, for example, 300 nm to 800 nm ultraviolet rays, visible light, and infrared rays. A lens for condensing the light that passes through the wavelength converter (scintillator layer, phosphor material layer) and enters the photoelectric conversion element may be provided.

A so-called flattening film may be formed on the entire surface so as to cover the second semiconductor layer and the fourth semiconductor layer, or an insulating material layer (for example, a SiO _x film, a SiN _y film, a SiO _x film / SiN, for example). _{A Y} film laminate film) may be formed, and a planarization film may be formed thereon. Moreover, you may form the transparent conductive material layer which consists of ITO etc. which were connected to the 2nd semiconductor layer and the 4th semiconductor layer. Protective film on the planarizing film (e.g., made of SiN _Y) is formed, the wavelength converter thereon (scintillator layer, the phosphor material layer) may be formed. The first semiconductor layer is connected to, for example, a gate electrode of a thin film transistor formed on the substrate. In the photoelectric conversion element, by applying a reference potential of, for example, about 3 to 10 volts to the first semiconductor layer or the second semiconductor layer and constituting the cathode, the amount of charge corresponding to the amount of incident light Can be obtained.

  The imaging device according to the present disclosure includes photoelectric conversion elements arranged in an M × N two-dimensional matrix in a first direction and a second direction different from the first direction. , (M, N) can be exemplified by (4096, 4096), (3072, 3072), and (2048, 2048). Moreover, 43 cm x 43 cm, 32 cm x 32 cm, 27 cm x 22 cm, and 21 cm x 21 cm can be exemplified as the external dimensions of the imaging device (or a pixel array section described later).

  Example 1 relates to a photoelectric conversion element according to the first aspect of the present disclosure, a photoelectric conversion element having a first configuration, and an imaging apparatus including the photoelectric conversion element. A schematic partial end view of the photoelectric conversion element of Example 1 is shown in FIG. 1A.

The photoelectric conversion element of Example 1 or Example 2 to be described later is
Substrate 11,
A first semiconductor layer 31 formed on the substrate 11 and having a first conductivity type;
Interlayer insulating layers 12, 13 covering the substrate 11 and the first semiconductor layer 31 and having an opening 15 in which the first semiconductor layer 31 is exposed at the bottom,
A third semiconductor layer 33 formed on the first semiconductor layer 31 exposed from the interlayer insulating layers 12 and 13 to the bottom of the opening 15; and
A second semiconductor layer 32 formed on the third semiconductor layer 33 and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer 33 has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered inclined surface 35 is formed at the ends of the second semiconductor layer 32 and the third semiconductor layer 33.

  In the photoelectric conversion element of Example 1 or Example 2 described later, fourth semiconductor layers 34 and 37 having the second conductivity type are formed on at least the forward tapered slope 35. In the photoelectric conversion element of Example 1, specifically, the fourth semiconductor layer 34 covers at least the forward tapered slope 35. More specifically, the fourth semiconductor layer 34 is formed (deposited) so as to cover the end portions of the second semiconductor layer 32 and the third semiconductor layer 33 and the second semiconductor layer 32.

Here, in Example 1 or Examples 2 to 4 to be described later, specifically, the first conductivity type is p-type (more specifically, p ⁺ ), and the second conductivity type is n-type. (More specifically, n ⁺ ), and the conductivity type of the third semiconductor layer 33 is i-type. That is, the first semiconductor layer 31 / the third semiconductor layer 33 / the second semiconductor layer 32 constitute a PIN photodiode. In Example 1 or Example 2 described later, the first semiconductor layer 31 is made of polycrystalline silicon (polysilicon). In Example 1 or Examples 2 to 4 described later, the second semiconductor layer 32, The third semiconductor layer 33 is made of amorphous silicon. Furthermore, in Example 1 or Example 3 described later, the fourth semiconductor layer 34 is made of amorphous silicon. Spectral sensitivity may be changed by introducing a material such as germanium or carbon into the silicon layer constituting the semiconductor layer. The first conductivity type may be n-type and the second conductivity type may be p-type. By the way, charges are accumulated in the first semiconductor layer 31 due to a weak current flowing even after a reset operation by a reset transistor 112 (see FIG. 6) described later, and are extracted from the first semiconductor layer 31 according to the charges. There is a possibility that an image based on the generated current becomes an afterimage. By making the conductivity type of the first semiconductor layer 31 functioning as an accumulation layer for collecting and accumulating signal charges p-type, the afterimage after the reset operation is made more than the n-type conductivity type of the first semiconductor layer 31. Can be further reduced.

In Example 1 or Example 2 to Example 4 described later, the photoelectric conversion element is connected to a thin film transistor (TFT) for controlling the operation of the photoelectric conversion element. Note that a read transistor 113 described later is configured by the illustrated thin film transistor. Specifically, the thin film transistor includes a gate electrode 21 formed on a substrate 11 made of a glass substrate, a gate insulating layer 22 covering the gate electrode 21 and the substrate 11, and a channel formation region formed on the gate insulating layer 22. 24 and source / drain regions 25A and 25B. The gate electrode 21 is composed of a single layer film made of any of Ti, Al, Mo, W, Cr, etc., or a stacked film in which two or more of these are stacked. In the illustrated example, the gate electrode 21 is disposed above and below the channel formation region 24. However, the gate electrode 21 may be disposed above the channel formation region 24, or the channel formation region 24 may be configured. Alternatively, the gate electrode 21 may be disposed below the gate electrode 21. The channel formation region 24 and the source / drain regions 25A and 25B are constituted by a polysilicon layer 23, and the source / drain regions 25A and 25B are made of n ⁺ -polysilicon. In order to reduce the leakage current, an LDD (Lightly Doped Drain) may be formed between the channel formation region 24 and the source / drain regions 25A and 25B. The interlayer insulating layers 12 and 13 (the lower interlayer insulating layer 12 and the upper interlayer insulating layer 13) are made of, for example, SiN _Y and SiO _X , respectively. On the lower interlayer insulating layer 12, wiring layers 14A, 14B, and 14C are formed. The gate electrode 21 constituting the thin film transistor is connected to the first semiconductor layer 31 through the wiring layer 14A. The first semiconductor layer 31 also serves as an electrode for reading out signal charges photoelectrically converted by a PIN photodiode. The source / drain regions 25A and 25B constituting the thin film transistor are connected to a circuit (described later) through wiring layers 14B and 14C.

In the photoelectric conversion element of Example 1 or Example 2 described later, a first layer made of a polysilicon layer 23 (specifically, a p ⁺ polysilicon layer) is formed on the gate insulating layer 22. A semiconductor layer 31 is formed.

  A transparent conductive material serving as an electrode is formed on the fourth semiconductor layer 34 in Example 1 or Example 3 described later, and on the second semiconductor layer 32 in Example 2 described later or Example 4 described later. A material layer 36 is formed, and the transparent conductive material layer 36 is connected to a circuit (described later). That is, on the transparent conductive material layer 36, a power supply wiring layer (not shown) for applying (supplying) a voltage to the transparent conductive material layer 36 is a material having a lower resistance than the material constituting the transparent conductive material layer 36. For example, it is formed from a single layer film made of any of Ti, Al, Mo, W, Cr or the like, or a stacked film in which two or more of these are stacked. The power supply wiring layer is formed over the entire surface of the pixel array unit 102 described later in a mesh shape so as to surround the photoelectric conversion element.

In Example 1 or Example 2 to Example 4 to be described later, the imaging device is configured so that the photoelectric conversion elements of Example 1 or Example 2 to Example 4 to be described later are in the first direction and the first direction. Are arranged in a two-dimensional matrix in different second directions. Moreover, in Example 1 or Example 2 to Example 4 described later, the light incident side of the photoelectric conversion element is provided with a wavelength converter that converts incident energy rays into the wavelength of the sensitivity region of the photoelectric conversion element. Yes. That is, in the photoelectric conversion element in the imaging apparatus (X-ray flat panel detector, FPD) of the first to fourth embodiments, the second semiconductor layer 32 and the fourth semiconductor layers 34 and 37 are made of organic materials (organic insulation). Material) or a spin-on glass material, and a protective film made of, for example, SiN _Y is formed on the flattened film. A wavelength converter (scintillator layer) is formed on the protective film. Alternatively, a phosphor material layer) is formed. However, these planarization film, protective film, and wavelength converter are not shown. For example, X-rays radiated from an X-ray generator (not shown) pass through a subject (not shown) such as a living body and then enter a wavelength converter. In the wavelength converter, incident X-rays are converted into optical signals. Then, the photoelectric conversion element converts the intensity of the optical signal into an electric signal representing the magnitude of the electric charge, and the electric signal is sent to an amplifier 121 described later via various transistors.

  Hereinafter, the outline of the manufacturing method of the photoelectric conversion element of Example 1 is demonstrated.

[Step-100]
First, a thin film transistor having a gate electrode 21, a gate insulating layer 22, a channel formation region 24, and source / drain regions 25A and 25B is formed on the substrate 11 based on a known method. In addition, the first semiconductor layer 31 is formed on the gate insulating layer 22.

[Step-110]
Thereafter, after forming (depositing) the lower interlayer insulating layer 12 on the entire surface based on a well-known method, the wiring layer 14A for connecting the first semiconductor layer 31 and the gate electrode 21 on the lower interlayer insulating layer 12, the source / Wiring layers 14B and 14C connected to the drain regions 25A and 25B are formed. Then, after forming (depositing) the upper interlayer insulating layer 13 on the entire surface, an opening 15 in which the first semiconductor layer 31 is exposed at the bottom is provided in the interlayer insulating layers 12 and 13 based on the photolithography technique and the etching technique. Thereafter, a third semiconductor layer 33 (thickness 0.6 μm) is formed on the first semiconductor layer 31 exposed from the interlayer insulating layers 12 and 13 to the bottom of the opening 15, and further on the third semiconductor layer 33. A second semiconductor layer 32 (thickness 25 nm) is formed. In this way, the state shown in FIG. 3A can be obtained.

[Step-120]
Thereafter, a resist layer 38 for patterning the third semiconductor layer 33 and the second semiconductor layer 32 is formed by a known method, and the second semiconductor layer 32 and the third semiconductor layer 33 are used using the resist layer 38 as an etching mask. After etching (see FIG. 4), the resist layer 38 is removed. A forward tapered inclined surface 35 is formed at the ends of the second semiconductor layer 32 and the third semiconductor layer 33. That is, the projected image of the edge of the second semiconductor layer 32 onto the substrate 11 is included in the projected image of the third semiconductor layer 33 onto the substrate 11.

[Step-130]
Thereafter, a fourth semiconductor layer 34 (thickness 25 nm) is formed on the entire surface, and then the fourth semiconductor layer 34 is patterned based on a well-known method. Further, a transparent conductive material layer 36 is formed on the fourth semiconductor layer 34. By forming, the photoelectric conversion element of Example 1 shown in FIG. 1A can be obtained.

Thus, a photoelectric conversion element (specifically, a PIN photodiode) that collects charges excited by incident light or incident energy is formed, and a reference potential V _xref is applied via the transparent conductive material layer 36 and the power supply wiring layer. As a result, photoelectric conversion is performed. The charges generated by the photoelectric conversion are collected by using the first semiconductor layer 31 as an accumulation layer, and read out as a current from the first semiconductor layer 31, for example, to the gate electrode 21 of a source follower type read transistor 113 described later. Applied as a voltage.

  In the photoelectric conversion elements of Example 1 or Examples 2 to 4 to be described later, since the fourth semiconductor layer having the second conductivity type is formed on at least the forward tapered slope, the second semiconductor layer The end portion of the third semiconductor layer is surely included in the electric field formed by the application of the voltage to, and the carriers generated at the end portion of the third semiconductor layer immediately reach the second semiconductor layer. As a result, afterimage characteristics are deteriorated, and it is possible to reliably suppress the occurrence of a problem that afterimage unevenness occurs in an image when a plurality of images are captured in a short time by the imaging device. Therefore, a plurality of images can be easily combined and a moving image can be obtained. In addition, for example, the amount of X-ray exposure can be reduced.

The signal amount obtained when the photoelectric conversion element is irradiated with X-rays is L ₁ , the dark current before the photoelectric conversion element is irradiated with X-rays is D ₀ , and the dark current after the photoelectric conversion element is irradiated with X-rays When D _{1 is} assumed, the afterimage characteristic is
(D ₁ -D ₀ ) / (L ₁ -D ₀ )
Can be expressed as The dark current D ₀ is a value of dark current after a sufficient time has elapsed after irradiating the photoelectric conversion element with X-rays, and is a dark current when there is no influence of X-ray irradiation. On the other hand, the dark current D ₁ is the signal value in the first image pickup frame after irradiation with X-ray to the photoelectric conversion element. In the photoelectric conversion element of Example 1, the value of the afterimage characteristic was about 2%. On the other hand, in the photoelectric conversion element having the configuration shown in FIG. 8A (the photoelectric conversion element of the comparative example), the value of the afterimage characteristic was about 4%. That is, in the photoelectric conversion element of Example 1, it was found that the afterimage characteristics were improved about twice as compared with the photoelectric conversion element of the comparative example.

  Example 2 is a modification of Example 1, but relates to a photoelectric conversion element having a second configuration. A schematic partial end view of the photoelectric conversion element of Example 2 is shown in FIG. 1B.

  In the photoelectric conversion element of Example 2, the fourth semiconductor layer 37 is formed on the surface layer portion of the second semiconductor layer 32 and the surface layer portion of the third semiconductor layer 33 constituting the forward tapered slope 35. Specifically, in the photoelectric conversion element of Example 2, impurities having the second conductivity type (specifically, for example, phosphorus or arsenic) are formed at the ends of the second semiconductor layer 32 and the third semiconductor layer 33. ) Is ion-implanted to form a fourth semiconductor layer (ion implantation region) 37 in the surface layer portion of the second semiconductor layer 32 and the surface layer portion of the third semiconductor layer 33. That is, in the state shown in FIG. 4, after ion implantation of impurities having the second conductivity type into the exposed end portions of the second semiconductor layer 32 and the third semiconductor layer 33 that are not covered with the resist layer 38, An activation process may be performed. The thickness of the second semiconductor layer 32 was 50 nm, and the thickness of the third semiconductor layer 33 was 0.6 μm.

  Except for the above points, the photoelectric conversion element and the imaging apparatus of Example 2 can be configured and structured in the same manner as the photoelectric conversion element and the imaging apparatus described in Example 1, and thus detailed description thereof is omitted.

  Example 3 relates to a photoelectric conversion element according to the second aspect of the present disclosure, a photoelectric conversion element having the first configuration, and an imaging apparatus including the photoelectric conversion element. A schematic partial end view of the photoelectric conversion element of Example 3 is shown in FIG. 2A.

The photoelectric conversion element of Example 3 or Example 4 to be described later is
Substrate 11,
Interlayer insulating layers 12, 13 covering the substrate 11 and having an opening 15 where the substrate 11 is exposed at the bottom,
A first semiconductor layer 31 formed over the substrate 11 exposed from the interlayer insulating layers 12 and 13 to the bottom of the opening 15;
A third semiconductor layer 33 covering the first semiconductor layer 31, and
A second semiconductor layer 32 formed on the third semiconductor layer 33 and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer 33 has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered inclined surface 35 is formed at the ends of the second semiconductor layer 32 and the third semiconductor layer 33.

In the photoelectric conversion element of Example 3 or Example 4 described later, fourth semiconductor layers 34 and 37 having the second conductivity type are formed on at least the forward tapered slope 35. In the third embodiment, specifically, as in the first embodiment, the fourth semiconductor layer 34 covers at least the forward tapered slope 35. More specifically, the fourth semiconductor layer 34 is formed (deposited) so as to cover the end portions of the second semiconductor layer 32 and the third semiconductor layer 33 and the second semiconductor layer 32. The first semiconductor layer 31 is specifically composed of an amorphous silicon layer, more specifically, a p ⁺ amorphous silicon layer (amorphous silicon layer).

In the photoelectric conversion element of Example 3 or Example 4 to be described later, the p ⁺ polysilicon layer 16 is formed on the gate insulating layer 22, and the gate electrode 21 constituting the thin film transistor includes the wiring layer 14A and the gate electrode 21. The p ⁺ polysilicon layer 16 is connected to the first semiconductor layer 31. That is, the first semiconductor layer 31 is formed over the substrate 11 exposed from the interlayer insulating layers 12 and 13 to the bottom of the opening 15. Specifically, the first semiconductor layer 31 is opened from above the interlayer insulating layers 12 and 13. It is formed over the p ⁺ polysilicon layer 16 exposed at the bottom of the portion 15. The p ⁺ polysilicon layer 16 corresponds to an electrode for reading out signal charges photoelectrically converted by a PIN photodiode. End portions of the first semiconductor layer 31 on the interlayer insulating layers 12 and 13 are covered with a third semiconductor layer 33.

  Hereafter, the outline of the manufacturing method of the photoelectric conversion element of Example 3 is demonstrated.

[Step-300]
First, a thin film transistor having a gate electrode 21, a gate insulating layer 22, a channel formation region 24, and source / drain regions 25A and 25B is formed on the substrate 11 based on a known method. A p ⁺ polysilicon layer 16 is formed on the gate insulating layer 22.

[Step-310]
Thereafter, after forming (depositing) the lower interlayer insulating layer 12 on the entire surface based on a known method, the wiring layer 14A for connecting the p ⁺ polysilicon layer 16 and the gate electrode 21 on the lower interlayer insulating layer 12; Wiring layers 14B and 14C connected to the source / drain regions 25A and 25B are formed. Then, after forming (depositing) an upper interlayer insulating layer 13 on the entire surface, an opening 15 with the p ⁺ polysilicon layer 16 exposed at the bottom is provided in the interlayer insulating layers 12 and 13 based on the photolithography technique and the etching technique. . Thereafter, the first semiconductor layer 31 is formed over the p ⁺ polysilicon layer 16 exposed at the bottom from the interlayer insulating layers 12 and 13, and the first semiconductor layer 31 is patterned. Next, the third semiconductor layer 33 is formed on the entire surface, and further, the second semiconductor layer 32 is formed on the third semiconductor layer 33.

[Step-320]
Thereafter, a resist layer for patterning the third semiconductor layer 33 and the second semiconductor layer 32 is formed by a well-known method, and the second semiconductor layer 32 and the third semiconductor layer 33 are etched using the resist layer as an etching mask. Then, the resist layer is removed. A forward tapered inclined surface 35 is formed at the ends of the second semiconductor layer 32 and the third semiconductor layer 33.

[Step-330]
Thereafter, the fourth semiconductor layer 34 is formed on the entire surface, and then the fourth semiconductor layer 34 is patterned based on a well-known method, and further, the transparent conductive material layer 36 is formed on the second semiconductor layer 32, The photoelectric conversion element of Example 3 shown in FIG. 2A can be obtained.

  Except for the above points, the photoelectric conversion element and the imaging apparatus of Example 3 can have the same configuration and structure as the photoelectric conversion element and the imaging apparatus described in Example 1, and thus detailed description thereof is omitted.

  Example 4 is a modification of Example 3, but relates to a photoelectric conversion element having a second configuration. A schematic partial end view of the photoelectric conversion element of Example 4 is shown in FIG. 2B.

  As in the second embodiment, in the photoelectric conversion element of the fourth embodiment, the fourth semiconductor layer 37 is formed on the surface layer portion of the second semiconductor layer 32 and the surface layer portion of the third semiconductor layer 33 constituting the forward tapered slope 35. Is formed. Specifically, in the photoelectric conversion element of Example 4, an impurity having a second conductivity type (specifically, for example, phosphorus or arsenic) at the ends of the second semiconductor layer 32 and the third semiconductor layer 33. ) Is ion-implanted to form a fourth semiconductor layer (ion implantation region) 37 in the surface layer portion of the second semiconductor layer 32 and the surface layer portion of the third semiconductor layer 33. That is, in the state shown in FIG. 4, after ion implantation of impurities having the second conductivity type into the exposed end portions of the second semiconductor layer 32 and the third semiconductor layer 33 that are not covered with the resist layer 38, An activation process may be performed.

  Except for the above points, the photoelectric conversion element and the imaging apparatus of Example 4 can have the same configuration and structure as the photoelectric conversion element and the imaging apparatus described in Example 3 and Example 2. Is omitted.

  In the fifth embodiment, a system configuration of an imaging apparatus including the photoelectric conversion element described in the first to fourth embodiments will be described. Here, a system configuration diagram illustrating an outline of a system configuration of the imaging apparatus according to the present disclosure is illustrated in FIG. 5, and a circuit diagram illustrating an example of a circuit configuration of a unit pixel including one photoelectric conversion element is illustrated in FIG. 6.

  The imaging device 100 includes a pixel array unit 102 and a peripheral circuit unit, and the pixel array unit 102 and the peripheral circuit unit are formed on the substrate 11. The peripheral circuit unit includes, for example, a row scanning unit (vertical driving unit) 103, a horizontal selection unit 104, a column scanning unit (horizontal driving unit) 105, and a system control unit 106.

  In the pixel array unit 102, unit pixels having the photoelectric conversion elements of the first to fourth embodiments that generate and accumulate photoelectric charges having a charge amount corresponding to the amount of incident light in the first direction, and Are arranged in a two-dimensional matrix in a second direction different from the first direction.

  In the pixel array unit 102, pixel drive lines 107 are further provided in the first direction (row direction) for each pixel row, and vertical signal lines 108 are provided in the second direction (column direction) for each pixel column. ). The pixel drive line 107 transmits a drive signal for driving to read a signal from the unit pixel. One end of the pixel drive line 107 is connected to an output end corresponding to each row of the row scanning unit 103.

  The row scanning unit 103 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each unit pixel of the pixel array unit 102 in units of rows, for example. A signal output from each unit pixel in the pixel row selected and scanned by the row scanning unit 103 is sent to the horizontal selection unit 104 via each vertical signal line 108. The horizontal selection unit 104 includes an amplifier, a horizontal selection switch, and the like provided for each vertical signal line 108. The column scanning unit 105 includes a shift register, an address decoder, and the like, and sequentially drives while scanning each horizontal selection switch of the horizontal selection unit 104. By the selective scanning by the column scanning unit 105, the signal of each unit pixel transmitted through each of the vertical signal lines 108 is sequentially output to the horizontal signal line 109, and to the outside of the substrate 11 through the horizontal signal line 109. Is output. The circuit portion including the horizontal selection unit 104, the column scanning unit 105, and the horizontal signal line 109 is configured by using a circuit formed on the substrate 11 and / or an external control IC in combination.

  The system control unit 106 receives a clock given from the outside of the substrate 11, data indicating an operation mode, and the like, and outputs data such as internal information of the imaging apparatus 100. The system control unit 106 further includes a timing generator that generates various timing signals. Based on the various timing signals generated by the timing generator, the row scanning unit 103, the horizontal selection unit 104, and the column scanning unit 105 are provided. Drive and control the peripheral circuit section.

  The unit pixel 110 includes the photoelectric conversion element 111, the reset transistor 112, the reading transistor 113, and the row selection transistor 114 described in the first to fourth embodiments. For the unit pixel 110, for example, two wirings, specifically, a row selection line 107A and a reset control line 107B are provided for each pixel row as the pixel driving line 107.

  The reset transistor 112, the readout transistor 113, and the row selection transistor 114 are composed of, for example, n-channel field effect transistors. However, the combination of conductivity types of the reset transistor 112, the readout transistor 113, and the row selection transistor 114 is merely an example, and is not limited to these combinations.

As described above, the photoelectric conversion element 111 is composed of a PIN photodiode, and a reference potential V of, for example, about 3 to 10 volts is applied to a semiconductor layer corresponding to the cathode (specifically, the second semiconductor layer 32). _By applying _xref, a signal charge having a charge amount corresponding to the amount of incident light is generated. The first semiconductor layer 31 corresponds to the anode of the photoelectric conversion element 111, and the first semiconductor layer 31 also functions as the storage node ND. A capacitance component 115 exists in the storage node ND, and signal charges generated in the photoelectric conversion element 111 are stored in the storage node ND.

The reset transistor 112 is connected between a terminal 116 to which a reference potential V _ref is applied and the storage node ND, and becomes conductive in response to a reset signal V _rst having an amplitude of −5 volts to 5 volts, for example. As a result, the potential of the storage node ND is reset to the reference potential _Vref .

In the read transistor 113, the gate electrode 21 is connected to the storage node ND (first semiconductor layer 31), and one source / drain region 25A is connected to the power source V _DD. Charge is received by the gate electrode 21, and a signal voltage corresponding to the signal charge is output.

The row selection transistor 114 is connected between the other source / drain region 25B of the read transistor 113 and the vertical signal line 108, and becomes _read in response to the row scanning signal V _read. A signal output from the transistor 113 is output to the vertical signal line 108. The row selecting transistor 114 may be arranged between one source / drain region 25A of the reading transistor 113 and the power supply V _DD .

  A constant current source 120 is connected to one end of the vertical signal line 108. Here, a source follower circuit is formed by the reading transistor 113 and the constant current source 120 connected to the other source / drain region 25B of the reading transistor 113 via the row selection transistor 114 and the vertical signal line 108. ing. This source follower circuit has an advantage that high-speed signal reading can be performed even when the capacitance formed in the vertical signal line 108 is large.

  The signal read by the source follower type read transistor 113 is input to the amplifier 121 that constitutes the input unit of the horizontal selection unit 104 for each pixel column via the vertical signal line 108.

  Although the present disclosure has been described based on the preferred embodiments, the present disclosure is not limited to these embodiments. The photoelectric conversion element, the configuration of the imaging device, the structure, the system configuration of the imaging device, and the circuit configuration of the unit pixel described in the embodiments are examples, and can be changed as appropriate. The method for manufacturing the photoelectric conversion device of the embodiment Also, it can be changed as appropriate. In the photoelectric conversion element of Example 1 or Example 3, the fourth semiconductor layer may be configured from the extending portion of the second semiconductor layer, and the end portion of the third semiconductor layer may be covered with such a fourth semiconductor layer. .

The pixel circuit is not limited to the active type as shown in FIG. 6, and a passive type pixel circuit configuration may be adopted as shown in FIG. That is, the unit pixel 130 includes the photoelectric conversion element 111 described in the first to fourth embodiments, and a reading transistor 133 including, for example, an n-channel field effect transistor (TFT). A signal line DTL, a bias line BSL, and a gate line GTL are connected to the unit pixel 130. As described above, the photoelectric conversion element 111 is composed of a PIN photodiode. The second semiconductor layer 32 corresponds to the anode of the photoelectric conversion element 111 and is composed of a p ⁺ amorphous silicon layer, and the first semiconductor layer 31 corresponds to the cathode of the photoelectric conversion element 111 and is an n ⁺ polysilicon layer or n ⁺ amorphous silicon. Consists of layers. The first semiconductor layer 31 is connected to one source / drain region of the reading transistor 133. The other source / drain region of the reading transistor 133 is connected to the signal line DTL, and the gate electrode of the reading transistor 133 is connected to the gate line GTL. The first semiconductor layer 31 also functions as the storage node ND. The storage node ND has a capacitance component, and the signal charge generated in the photoelectric conversion element 111 is stored in the storage node ND. Then, the reading transistor 133 is turned on in response to the reset signal from the gate line GTL, whereby the potential of the storage node ND is reset via the signal line DTL. Further, when a bias voltage is applied from the bias line BSL to the semiconductor layer corresponding to the anode (specifically, the second semiconductor layer 32), a signal charge having a charge amount corresponding to the amount of incident light is generated. . Then, the reading transistor 133 is turned on in response to a read signal from the gate line GTL, whereby a signal voltage corresponding to the signal charge is output to the signal line DTL.

  Instead of adopting a configuration in which the peripheral circuit unit including the row scanning unit 103 for driving the unit pixel is provided on the same substrate 11 as the pixel array unit 102, a configuration in which the peripheral circuit unit is provided outside the substrate 11 may be employed. Is possible. However, if, for example, a configuration in which the row scanning unit 103 is provided on the substrate 11 is employed, synchronization variation between the driving ICs that occurs when timing control is performed from a plurality of driving ICs provided outside the substrate 11 occurs. This eliminates the need for the synchronous control system between the driving ICs and the adjustment work. Further, since the operation of connecting the plurality of driving ICs and the substrate 11 is not required, the cost can be significantly reduced. Furthermore, a handy type radiation imaging apparatus can be obtained, and the possibility of failure due to vibration during movement is reduced, and the reliability can be greatly improved. In addition, the imaging apparatus can be downsized as compared with the case where a plurality of driving ICs and the substrate 11 are connected by a flexible cable or the like.

In addition, this indication can also take the following structures.
[A01] << Photoelectric conversion element: first embodiment >>
substrate,
A first semiconductor layer having a first conductivity type formed on a substrate;
An interlayer insulating layer that covers the substrate and the first semiconductor layer and has an opening at the bottom where the first semiconductor layer is exposed;
A third semiconductor layer formed over the first semiconductor layer exposed from the interlayer insulating layer to the bottom of the opening; and
A second semiconductor layer formed on the third semiconductor layer and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered slope is formed at the ends of the second and third semiconductor layers,
A photoelectric conversion element in which a fourth semiconductor layer having a second conductivity type is formed on at least a forward tapered slope.
[A02] << Photoelectric conversion element: second embodiment >>
substrate,
An interlayer insulating layer covering the substrate and having an opening in which the substrate is exposed at the bottom;
A first semiconductor layer formed over the substrate exposed from the interlayer insulating layer to the bottom of the opening;
A third semiconductor layer covering the first semiconductor layer; and
A second semiconductor layer formed on the third semiconductor layer and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered slope is formed at the ends of the second and third semiconductor layers,
A photoelectric conversion element in which a fourth semiconductor layer having a second conductivity type is formed on at least a forward tapered slope.
[A03] << Photoelectric conversion element: first configuration >>
The fourth semiconductor layer is the photoelectric conversion element according to [A01] or [A02], which covers at least a forward tapered slope.
[A04] << Photoelectric conversion element: Second configuration >>
The fourth semiconductor layer is the photoelectric conversion element according to [A01] or [A02], which is formed on a surface layer portion of the second semiconductor layer and a surface layer portion of the third semiconductor layer constituting a forward tapered slope.
[A05] The first conductivity type is p-type or n-type,
The second conductivity type is n-type or p-type,
The photoelectric conversion element according to any one of [A01] to [A04], wherein the conductivity type of the third semiconductor layer is i-type.
[A06] The first semiconductor layer is made of polycrystalline silicon,
The photoelectric conversion element according to any one of [A01] and [A05], in which the second semiconductor layer and the third semiconductor layer are made of polycrystalline silicon or amorphous silicon, and [A01] is cited from [A01]. .
[A07] The first semiconductor layer is made of amorphous silicon,
The photoelectric conversion element according to any one of [A02] and [A05], in which the second semiconductor layer and the third semiconductor layer are made of polycrystalline silicon or amorphous silicon, and [A02] is cited. .
[B01] << Imaging device >>
An imaging device in which the photoelectric conversion elements [A01] to [A07] are arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction.
[B02] The imaging device according to [B01], wherein a wavelength conversion body that converts incident energy rays into wavelengths in a sensitivity region of the photoelectric conversion element is provided on a light incident side of the photoelectric conversion element.

DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12, 13 ... Interlayer insulation layer, 14A, 14B, 14C ... Wiring layer, 15 ... Opening part, 16 ... p ⁺ polysilicon layer, 21 ... Gate electrode 22 ... gate insulating layer, 23 ... polysilicon layer, 24 ... channel formation region, 25A, 25B ... source / drain region, 31 ... first semiconductor layer, 32 ... first 2 semiconductor layers, 33 ... third semiconductor layer, 34 ... fourth semiconductor layer, 35 ... forward tapered slope, 36 ... transparent conductive material layer, 37 ... fourth semiconductor layer ( Ion implantation region), 38 ... resist layer, 100 ... imaging device, 102 ... pixel array section, 103 ... row scanning section (vertical drive section), 104 ... horizontal selection section, 105 · ..Column scanning unit (horizontal drive unit) 106... System control unit 107 -Pixel drive line, 107A ... row selection line, 107B ... reset control line, 108 ... vertical signal line, 109 ... horizontal signal line, 110 ... unit pixel, 111 ... photoelectric conversion Element 112, reset transistor 113, readout transistor 114, row selection transistor 115, capacitance component 116, terminal 120, constant current source 121,.・ Amplifier, ND ... Storage node

Claims (9)

substrate,
A first semiconductor layer having a first conductivity type formed on a substrate;
An interlayer insulating layer that covers the substrate and the first semiconductor layer and has an opening at the bottom where the first semiconductor layer is exposed;
A third semiconductor layer formed over the first semiconductor layer exposed from the interlayer insulating layer to the bottom of the opening; and
A second semiconductor layer formed on the third semiconductor layer and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered slope is formed at the ends of the second and third semiconductor layers,
A photoelectric conversion element in which a fourth semiconductor layer having a second conductivity type is formed on at least a forward tapered slope. substrate,
An interlayer insulating layer covering the substrate and having an opening in which the substrate is exposed at the bottom;
A first semiconductor layer formed over the substrate exposed from the interlayer insulating layer to the bottom of the opening;
A third semiconductor layer covering the first semiconductor layer; and
A second semiconductor layer formed on the third semiconductor layer and having a second conductivity type opposite to the first conductivity type;
With
The third semiconductor layer has a conductivity type between the first conductivity type and the second conductivity type,
A forward tapered slope is formed at the ends of the second and third semiconductor layers,
A photoelectric conversion element in which a fourth semiconductor layer having a second conductivity type is formed on at least a forward tapered slope.   The photoelectric conversion element according to claim 1, wherein the fourth semiconductor layer covers at least a forward tapered slope.   3. The photoelectric conversion element according to claim 1, wherein the fourth semiconductor layer is formed on a surface layer portion of the second semiconductor layer and a surface layer portion of the third semiconductor layer constituting a forward tapered slope. The first conductivity type is p-type or n-type,
The second conductivity type is n-type or p-type,
The photoelectric conversion element according to claim 1, wherein the conductivity type of the third semiconductor layer is i-type. The first semiconductor layer is made of polycrystalline silicon,
The photoelectric conversion element according to claim 1, wherein the second semiconductor layer and the third semiconductor layer are made of polycrystalline silicon or amorphous silicon. The first semiconductor layer is made of amorphous silicon,
The photoelectric conversion element according to claim 2, wherein the second semiconductor layer and the third semiconductor layer are made of polycrystalline silicon or amorphous silicon.   8. An imaging device comprising the photoelectric conversion elements according to claim 1 arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction.   The imaging apparatus according to claim 8, wherein a wavelength conversion body that converts incident energy rays into wavelengths in a sensitivity region of the photoelectric conversion element is provided on a light incident side of the photoelectric conversion element.

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