JP6218722B2 - Switching power supply - Google Patents

Description

  The present invention relates to a flyback switching power supply that operates by critical mode control.

  Flyback power supply devices that operate under critical mode control have been widely used. Accumulation energy is stored in the transformer while the main switching element is on, then the main switching element is turned off, and the excitation energy is output rectified. After being emitted through the element, the main switching element is immediately turned on.

  An example of this type of switching power supply is a ringing choke switching power supply 10 shown in FIG. The switching power supply device 10 is provided with a transformer 12 having an input winding 12a, an output winding 12b, and an auxiliary winding 12c, and a main switching element 14 is connected in series with the input winding 12a. The main switching element 14 is an N-channel MOS type FET (an NPN type bipolar transistor may be used), and its source is connected to the ground 16. In FIG. 18, the main switching element 14 is divided into a main FET 14a that is a part of the FET element and an auxiliary diode 14b that is a parasitic diode existing between the drain and the source. The input voltage Vi supplied from the input power supply 18 is input to both ends of a series circuit of the input winding 12a and the main switching element 14, and when the main switching element 14 is turned on / off, the input voltage Vi is applied to both ends of the input winding 12a. An intermittent voltage is generated. The dots attached to the transformer 12 represent the polarities of the respective windings, and the auxiliary winding 12c has a terminal on which the dots are not attached connected to the ground 16.

  The output winding 12b is connected to an output rectifying element 20 that is a diode that rectifies a voltage generated when the main switching element 14 is turned off, and the subsequent stage smoothes the rectified voltage output from the output rectifying element 20. An output smoothing capacitor 24 that supplies an output voltage Vo and an output current Io to the load 22 is connected.

  The switching control circuit for controlling on / off of the main FET 14a includes an activation circuit 26, a positive feedback circuit 28, a drive transistor 30, a timer capacitor 32, a charge / discharge circuit 34, an output voltage detection circuit 36, and a control current generation circuit 38. Yes.

  When the input voltage Vi is input, the starting circuit 26 is a circuit that charges between the gate and source of the main FET 14a to turn on the main FET 14a. For example, the start circuit 26 is simply configured with a resistor or a constant current circuit is used. .

  The positive feedback circuit 28 includes a capacitor and a resistor, and is a circuit that transmits a change in the voltage of the auxiliary winding 12c to the gate of the main FET 14a. The timing at which the main FET 14a turns on can be finely adjusted by changing the strength of the positive feedback signal from the positive feedback circuit 28.

  The drive transistor 30 is an NPN type transistor, the collector is connected to the gate of the main FET 14a, the emitter is connected to the ground 16, and the main FET 14a is turned off by short-circuiting between the gate and source of the main FET 14a at a predetermined timing. Work.

  The driving transistor 30 is driven by a timer capacitor 32 connected between the base and emitter, a charging / discharging circuit 34 for charging / discharging the timer capacitor 32, and a control current generating circuit 38 for supplying a predetermined control current Is to the timer capacitor 32. Is called. The charging / discharging circuit 34 is composed of, for example, a plurality of resistors and Zener diodes, and charges the timer capacitor 32 when the voltage of the auxiliary winding 12c is positive and discharges the timer capacitor 32 during the negative period.

The control current generation circuit 38 amplifies the difference between the output voltage signal Vo1 (voltage proportional to the output voltage Vo) output from the output voltage detection circuit 36 and the voltage corresponding to the target value of the output voltage Vo by the error amplification circuit 38a. The output signal is converted into a predetermined control current Is via a signal-insulating photocoupler 38b, and the control current Is flows into the timer capacitor 32 while the main FET 14a is on.

  When the voltage of the timer capacitor 32 is charged / discharged by the charging / discharging circuit 34 and further charged by the control current Is of the control current generating circuit 38 to have a sawtooth waveform, when the ON threshold voltage of the driving transistor 30 is reached, the driving transistor 30 turns on. Therefore, the timing at which the drive transistor 30 is turned on (the timing at which the main FET 14a turns off) changes as the control current Is increases or decreases. For example, when the control current Is increases, the rate of increase in the voltage of the timer capacitor 32 increases. The timing at which the main FET 14a turns off is advanced, and the output voltage signal Vo1 and the output voltage Vo decrease.

  A general snubber circuit 40 called a DCR snubber is provided at both ends of the input winding 12a. The snubber circuit 40 includes a snubber diode 40a, a snubber capacitor 40b, and a snubber resistor 40c. The snubber diode 40a has an anode connected to a connection point between the drain of the main FET 14a and the input winding 12a. Connected between the cathode of the diode 40b and the other end of the input winding 12a, the snubber resistor 40c is connected in parallel to the snubber capacitor 40b. The voltage V40 across the snubber capacitor 40 is a substantially constant DC voltage. When the voltage V14d between the drain and source of the main FET 14a exceeds the total value of the input voltage Vi and the voltage V40, the snubber diode 40a becomes conductive. That is, when the main FET 14a turns off, the surge voltage generated in the voltage V14d is clamped by the snubber capacitor 40b, and the energy of the surge component absorbed by the snubber capacitor 40b is lost by the snubber resistor 40c. By providing the snubber circuit 40, a surge voltage generated in the voltage V14d can be reduced, and circuit elements such as the main switching element 14 can be protected, or switching noise leaked from the apparatus to the outside can be reduced. it can.

  A ringing choke type switching power supply 42 shown in FIG. 19 is obtained by changing a part of the configuration of the switching power supply 10. Instead of the output voltage detection circuit 36 and the control current generation circuit 38, an output voltage is provided. A detection circuit 44 and a control current generation circuit 46 are provided. Other configurations are the same.

  The output voltage detection circuit 44 includes a diode 44a having a cathode connected to a terminal of the auxiliary winding 12c and a capacitor 44b having an anode of the diode 44a connected between the ground 16 and the diode 44a. . The diode 44a conducts during a period in which the main switching element 14 is off, and a voltage (voltage approximately proportional to the output voltage Vo) generated in the auxiliary winding 12c is generated in the capacitor 44b. Then, the negative DC voltage Vo1 generated in the capacitor 44b is output as an output voltage signal.

  The control current generation circuit 46 receives the output voltage signal Vo1, generates the control current Is so that the output voltage signal Vo1 approaches the target value, and outputs the control current Is to the timer capacitor 32 during the period when the main FET 14a is on. To do.

  Since the switching power supply device 42 indirectly detects the output voltage Vo on the input side, it can be configured without using the photocoupler 38b for signal insulation. Therefore, problems unique to photocouplers (signal transmission characteristics are relatively slow, current transfer rate CTR is highly variable, the outer shape of the element is large due to safety standards restrictions, and the withstand voltage of the light receiving transistor is often low. There is an advantage that it can be designed without worrying about being relatively expensive.

  As this type of switching power supply, there is a separately excited switching power supply using an IC for critical mode control, as disclosed in Patent Document 1. In this switching power supply device, a unique clamp circuit is provided in parallel with the input winding (primary winding) of the transformer. The clamp circuit is composed of a clamp element that connects or disconnects the series circuit of the first and second clamp capacitors to and from both ends of the input winding, and a second diode that short-circuits both ends of the second clamp capacitor. The operation of switching the C value of the capacitor component connected to the input winding is performed at an appropriate timing. The clamp circuit is provided for almost the same purpose as the above-described snubber circuit 40. By reducing the surge voltage generated at both ends of the main switching element, the main switching element and the like are protected or leaked from the device to the outside. Switching noise can be reduced. In addition, the soft switching of the main switching element can be easily controlled, and the cross loss of the main switching element can be reduced.

JP 2012-110117 A

  However, in the case of the conventional switching power supply devices 10 and 42, since a large loss occurs in the snubber resistor 40c of the snubber circuit 40, there is a problem that the power supply efficiency is lowered. Further, if the snubber circuit 40 is strengthened, various harmful effects (decrease in power supply efficiency, unstable operation when the input voltage or output current changes suddenly, etc.) may occur. It is difficult to make it much smaller. Therefore, particularly in the case of the switching power supply 42, the surge voltage component is generated in the auxiliary winding 12c, and the voltage including the surge voltage component is peak-held through the diode 40a, and the output voltage signal Vo1 generated in the capacitor 44b. Since the proportional relationship between the output voltage Vo and the output voltage Vo collapses, input fluctuations (changes in the output voltage Vo with respect to changes in the input voltage Vi) and load fluctuations (changes in the output voltage Vo with respect to changes in the output current Io) increase. Vo accuracy decreases.

  In the case of the switching power supply of Patent Document 1, the peak value of the surge voltage can be lowered by lowering the frequency (ringing frequency) of the surge voltage generated at both ends of the main switching element by the operation of the clamp circuit. . In addition, since a large loss does not occur unlike a DCR snubber, a decrease in power supply efficiency is small. However, this clamp circuit is strictly a circuit that lowers the peak value of the surge voltage (decreases the ringing amplitude), and a circuit that clamps the surge voltage (removes the peak) like a DCR snubber. Therefore, the effect of reducing the surge voltage is limited. Therefore, in the case of the switching power supply device disclosed in Patent Document 1 as well, especially when the output voltage is detected from the voltage of the auxiliary winding, although not as much as the switching power supply device 42, input fluctuations and load fluctuations increase, and the output voltage Vo. The accuracy of is reduced.

  The present invention has been made in view of the above-mentioned background art, and provides a flyback switching power supply device that has a simple circuit configuration and can suppress a surge voltage generated at both ends of a main switching element. With the goal.

The present invention includes a main switching element that interrupts an input voltage supplied from an input power supply, an input winding connected in series to the main switching element, and an output winding insulated from the input winding, During the ON period of the switching element, the input voltage is applied to the input winding to store excitation energy, and the cathode is connected to the input winding and the main switching element at both ends of the main switching element. An auxiliary diode connected to the output, an output rectifier that rectifies the voltage generated in the output winding during a period when the main switching element is off, and a rectified voltage output from the output rectifier, and is externally connected. An output smoothing capacitor for supplying an output voltage and an output current to a load, and turning on the main switching element so that the output voltage approaches a target value. And a critical mode control for quickly inverting the main switching element from off to on after the excitation energy accumulated in the transformer is released through the output rectifier. A flyback type switching power supply device including a switching control circuit,
A regenerative capacitor having one end connected to a connection point of the input winding and the main switching element, a regenerative switch connected between the other end of the regenerative capacitor and the other end of the input winding, and an anode A regenerative diode connected to both ends of the regenerative switch on the regenerative capacitor side, and a snubber circuit composed of a regenerative control circuit for controlling on / off of the regenerative switch,
After the regenerative control circuit turns on the regenerative switch while the main switching element is off, the voltage across the regenerative capacitor drops to a predetermined value before the main switching element turns from off to on. The regenerative switch is turned off to hold the voltage across the regenerative capacitor at the predetermined value, and then the main switching element turns from on to off, and the voltage across the regenerative capacitor rises above the predetermined value. Thus, the switching power supply device repeats the operation of turning on the regenerative switch every switching period of the main switching element when the current starts to flow through the regenerative diode and when the current ends.

  The regenerative switch is a regenerative FET that is an N-channel MOS FET having a source connected to the other end of the regenerative capacitor and a drain connected to the other end of the input winding, and the regenerative control circuit includes the regenerative control circuit, A series circuit of a drive resistor and a bias capacitor connected between a connection point of the input winding and the regenerative capacitor and the gate of the regenerative FET, and a discharge resistor for forming a discharge path of the bias capacitor , Connected between the gate and source of the regenerative FET, or a position corresponding to this, and conducts when the gate and source of the regenerative FET are biased in the negative direction, and the negative voltage generated between the gate and source becomes a predetermined value or more. A configuration including a negative voltage setting diode for clamping so as not to increase is preferable.

  In this case, a buffer circuit is inserted between one end of the series circuit of the drive resistor and bias capacitor and the gate of the regenerative FET, and the buffer circuit has one end of the series circuit of the drive resistor and bias capacitor. A charging diode connected to the gate of the regenerative FET, an emitter connected to the gate of the regenerative FET, a collector connected to the source of the regenerative FET, and a base connected to the anode of the charging diode. More preferably, the discharge transistor is a PNP transistor connected to the. Furthermore, a PN junction portion between the collector and base of the discharge transistor may operate as the negative voltage setting diode.

  Alternatively, a protective Zener diode for preventing an excessive voltage from being generated between the gate source of the regenerative FET is connected between the gate source of the regenerative FET or a position corresponding to the same. It may be configured to operate as a negative voltage setting diode.

  Further, the transformer is provided with an auxiliary winding insulated from the output winding, and the switching control circuit detects a change in voltage generated in the auxiliary winding, and based on the detection result, An on-timing setting circuit that determines the timing at which the main switching element turns from off to on is provided, and when the on-timing setting circuit operates, the voltage across the main switching element has decreased to a predetermined value or less. It may be configured to turn on at the timing.

  Further, the transformer is provided with an auxiliary winding insulated from the output winding, and the switching control circuit detects an output voltage detecting the voltage generated in the auxiliary winding while the main switching element is off. A circuit may be provided, and the switching control circuit may control the on-time and off-time of the main switching element by regarding the detected voltage as the output voltage.

  In the switching power supply device of the present invention, by providing a unique snubber circuit in parallel with the input winding of the transformer, the surge voltage generated at both ends of the main switching element can be remarkably reduced. In addition, this snubber circuit has a simple configuration and small self-loss, and performs an operation of regenerating the energy of the surge component absorbed by the regenerative capacitor to the output, so that a decrease in power supply efficiency can be minimized.

  In addition, by providing an auxiliary winding and an on-timing setting circuit so that the main switching element is turned on when the voltage across the main switching element drops below a certain value, soft switching or zero volt switching is possible. Cross loss and switching noise of the switching element can be reduced.

1 is a circuit diagram showing a first embodiment of a switching power supply device of the present invention. FIG. 2 is a block diagram (a) showing an internal configuration of a snubber circuit and a circuit diagram (b) showing a specific configuration example of a regeneration control circuit. It is a graph which shows the output current-output voltage characteristic of the switching power supply device of this embodiment. It is an operation | movement waveform of each part in the operating point A (at the time of heavy load) of FIG. 5 is an equivalent circuit showing a circuit operation in a period T1a in FIG. 5 is an equivalent circuit illustrating a circuit operation in a period T2a in FIG. 5 is an equivalent circuit illustrating a circuit operation in a period T3a in FIG. 5 is an equivalent circuit illustrating a circuit operation in a period T4a in FIG. 5 is an equivalent circuit showing a circuit operation in a period T5a in FIG. 5 is an equivalent circuit showing a circuit operation in a period T6a in FIG. 5 is an equivalent circuit showing a circuit operation in a period T7a in FIG. 5 is an equivalent circuit illustrating a circuit operation in a period T8a in FIG. 5 is an equivalent circuit showing a circuit operation in a period T9a in FIG. It is an operation | movement waveform of each part in the operating point B (at the time of light load) of FIG. It is circuit diagram (a), (b), (c) which shows the 1st-3rd modification of a regeneration control circuit. It is circuit diagram (a), (b), (c) which shows the 4th-6th modification of a regeneration control circuit. It is a circuit diagram which shows 2nd embodiment of the switching power supply device of this invention. It is a circuit diagram which shows an example of the conventional switching power supply device. It is a circuit diagram which shows the other example of the conventional switching power supply apparatus.

  Hereinafter, a first embodiment of a switching power supply device of the present invention will be described with reference to FIGS. Here, the same components as those of the conventional switching power supply devices 10 and 42 are denoted by the same reference numerals and description thereof is omitted. The switching power supply device 48 of this embodiment is a ringing choke type power supply device that does not use a photocoupler, like the switching power supply device 42. The configuration differs from the switching power supply 42 in that a unique snubber circuit 50 is provided instead of the snubber circuit 40, and the other configurations are the same. In the switching power supply device 48, the positive feedback circuit 28 also operates as the on-timing setting circuit 52. Hereinafter, differences in configuration will be described.

  As shown in FIG. 2A, the snubber circuit 50 includes a regenerative capacitor 54, a regenerative element 56, and a regenerative control circuit 58. The regenerative capacitor 54 has one end connected to the connection point between the input winding 12 a and the main switching element 14, and the C value is a parasitic capacitor of each winding of the transformer 12 and a parasitic capacitor between the drain and source of the main switching element 14. Is set to a sufficiently large value.

  The regenerative element 56 is an N-channel MOS FET, and the FET element portion functions as a regenerative FET 56a which is a regenerative switch, and a parasitic diode existing between the drain and source functions as a regenerative diode 56b. The regenerative FET 56a has a source connected to the other end of the regenerative capacitor 54, a drain connected to the other end of the input winding 12a, and a regenerative diode 56b has an anode connected to the other end of the regenerative capacitor and a cathode connected to the input winding. 12a is connected to the other end.

  The regenerative control circuit 58 is a block that controls the on / off operation of the regenerative FET 56a. “After the regenerative FET 56a is turned on while the main FET 14a is off, the voltage V54 across the regenerative capacitor 54 decreases to a predetermined value. Before the FET 14a turns from off to on, the regenerative FET 56a is turned off. After that, the main FET 14a turns from on to off, and the voltage V54 across the regenerative capacitor 54 rises above a predetermined value, whereby a current flows through the regenerative diode 56b. At the beginning, when the current flow is finished, the operation of turning on the regenerative FET 56a is repeated every switching cycle Tsw of the main FET 14a. "

  The function of the regeneration control circuit 58 can be realized by the configuration of the regeneration control circuit 58 (1), for example. As shown in FIG. 2B, the regeneration control circuit 58 (1) includes a drive resistor 60 and a bias capacitor 62 connected between the connection point of the input winding 12a and the regeneration capacitor 54 and the gate of the regeneration FET 56a. Are connected in parallel with the bias capacitor 62 and a discharge resistor 64 for forming a discharge path of the bias capacitor 62 is provided. The C value of the bias capacitor 62 is smaller than the regenerative capacitor 54 and larger than a parasitic capacitor 56c (gs) of a regenerative FET 56a described later.

  A buffer circuit 66 composed of a charging diode 66a and a discharging transistor 66b is inserted between one end of a series circuit of the driving resistor 60 and the bias capacitor 62 and the gate of the regenerative FET 56a. The charging diode 66a has an anode connected to one end of a series circuit of the driving resistor 66 and the bias capacitor 62, and a cathode connected to the gate of the regenerative FET 56a. The discharge transistor 66b is a PNP transistor, and has an emitter connected to the gate of the regenerative FET 56a, a collector connected to the source of the regenerative FET 56a, and a base connected to the anode of the charge diode 66a. In the discharging transistor 66b, the PN junction between the collector and the base operates as a negative voltage setting diode. The negative voltage setting diode will be described later in the explanation of the operation.

  In this embodiment, the positive feedback circuit 28 detects a change in the voltage generated in the auxiliary winding 12c, and determines the timing at which the main FET 14a turns on based on the detection result. For example, when the positive feedback circuit 28 is a series circuit of a capacitor and a resistor, if the value of the resistor is increased to weaken the positive feedback signal, the timing at which the main FET 14a is turned off can be delayed, and conversely, the value of the resistor is decreased. If the positive feedback signal is strengthened, the timing at which the main FET 14a is turned off can be advanced. The on-timing setting circuit 52 is adjusted so that the main FET 14a is turned on when the voltage across the main FET 14a drops below a predetermined value. Details will be described later in the explanation of the operation.

  Next, the operation of the switching power supply device 48 will be described. FIG. 3 is a graph showing the output current Io-output voltage Vo characteristics. The solid line is the characteristic of the switching power supply device 48, which is superior to the characteristic of the conventional switching power supply device 42 shown by the broken line. Hereinafter, the operation at the operating point A (at the time of heavy load) and the operation at the operating point B (at the time of light load) when the regeneration control circuit 58 (1) is used as the regeneration control circuit 58 will be described in order.

  As shown in FIG. 4, the operation at the operating point A can be described by dividing one switching period Tsw into periods T1a to T9a. Here, the current I14 is a current that flows through the main FET 14a and the auxiliary diode 14b, and does not include a current that flows through the parasitic capacitor 14c (ds). Similarly, the current I56 is a current that flows through the regenerative FET 56a and the regenerative diode 56b, and does not include a current that flows through a parasitic capacitor 56c (ds) described later.

  The current flow and voltage polarity of each part in each period T1a to T9a can be expressed as the equivalent circuits in FIGS. The equivalent circuits in FIGS. 5 to 13 include circuit elements that are not described in the circuit diagrams in FIGS. 1 and 2 and that relate to the explanation of the circuit operation. Specifically, the parasitic capacitor 14c (ds) that exists between the drain and source of the main switching element 14, and the parasitic capacitor 56c (ds) that exists between the drain and source, the gate source, and the drain gate of the regeneration element 56, respectively. , 56c (gs), 56c (dg), and the leakage dacter 68 of the transformer 12 described at a position in series with the input winding 12a. Further, the main FET 14a and the regenerative FET 56a are represented by switch symbols and indicate an on or off state.

  Further, the numbers of turns of the input winding 12a, the output winding 12b, and the auxiliary winding 12c of the transformer 12 are Na, Nb, and Nc, respectively. In addition, the impedance (or voltage drop) when the transistor element of each part is turned on and the impedance (or voltage drop) when the diode element is conducted are assumed to be sufficiently small, and are ignored except when special explanation is added. To do.

  The period T1a starts at the timing when the voltage V14d between the drain and source of the main FET 14 drops to zero in the period T9a. As shown in FIG. 5, the auxiliary diode 14b is turned on, and the negative current I14 flows through the main switching element 14. Flows. The output rectifier 20 is reverse-biased and non-conductive.

  When the on-timing setting circuit 52 operates, the main FET 14a enters the period T1a in the off state, and turns on at an appropriate timing while the negative current I14 is flowing. That is, since the main FET 14a performs the zero volt switching operation, the cross loss of the main FET 14a is very small. Even if the main FET 14a is turned on, the path of the current I14 is merely switched from the auxiliary diode 14b to the main FET 14a, so that no significant change occurs in circuit operation.

  The value of the voltage V54 across the regenerative capacitor 54 is V54 (min). This V54 (min) is slightly lower than a value Vo · (Na / Nb) obtained by multiplying the output voltage Vo by the turn ratio of the input winding 12a and the output winding 12b. The both-ends voltage V60 of the bias capacitor 60 is slightly higher than V54 (min), and hardly changes even when it shifts to another period. The regenerative FET 56a is off because the voltage V56g between the gate and the source is almost zero. The regenerative diode 56b is reverse-biased and nonconductive. The period T1a ends when the negative current I14 becomes zero.

  Even in the period T2a, each circuit element continues to operate in the period T1a. As shown in FIG. 6, the current I14 is in the positive direction with substantially the same slope as the period T1a and continues to flow to the main FET 14a. Excitation energy is accumulated in the transformer 12 by the current I14 in the periods T1a and T2a. The period T2a ends when the drive transistor 48 is turned on by the control current Is output from the control current generation circuit 54 and the main FET 14a is turned off.

  When the period T3a is entered, the main FET 14a is turned off, so that a current for releasing excitation energy starts to flow from the input winding 12a. Then, as shown in FIG. 7, the parasitic capacitor 14c (ds) of the main switching element 14 is charged, and the voltage V14d increases toward the input voltage Vi. The output rectifier 20 is reverse-biased and non-conductive.

  The current that the input winding 12a releases the excitation energy includes the regenerative capacitor 54, the negative voltage setting diode (PN junction between the collector base of the discharge transistor 66b), the charging diode 66a, and the parasitic capacitor 56c of the regenerative element 56 ( The voltage V56g between the gate and source of the regenerative FET 56a becomes a negative voltage lower than zero by the forward voltage of the negative voltage setting diode. The voltage V54 of the regenerative capacitor 54 is held substantially at V54 (min), and the voltage V60 of the bias capacitor 60 hardly changes. The period T3a ends when the voltage V14d rises to the input voltage Vi.

  Even in the period T4a, each circuit element continues to operate in the period T3a. The voltage V14d rises with a slope similar to that of the period T3a and, as shown in FIG. 8, the positive and negative voltages of the input winding 12a and the output winding 12b are reversed, but there is no particular change in circuit operation. The period T4a ends when the voltage V14d reaches the total value of the input voltage Vi and the voltage V54 (min) of the regenerative capacitor 54.

  In the period T5a, as shown in FIG. 9, the regenerative diode 56b is forward-biased and becomes conductive, and the current at which the input winding 12a releases the excitation energy begins to flow through the path of the regenerative capacitor 54 and the regenerative diode 56b. A negative current is generated in the current I56 waveform of the regenerative element 56. This current is a current that mainly absorbs a surge voltage (ringing) generated in the voltage V14d, and the voltage V54 of the regenerative capacitor 54 gradually increases in the same manner as a so-called DCR snubber capacitor absorbs the surge voltage. . The main FET 14a continues to be off, and the voltage V14d rises with substantially the same slope as the voltage V54 rises. The parasitic capacitor 56c (gs) of the regenerative element 56 is charged through the bias capacitor 62, the drive resistor 60, and the charging diode 66a as the voltage V54 increases, and the voltage V56g also increases. The slope of the increase of the voltage V56g is gentle due to the time constants of the drive resistor 60 and the parasitic capacitor 56c (gs), and therefore does not reach the ON threshold value Vth of the regenerative FET 56a, and the regenerative FET 56a is off.

  When the voltage V14d rises slowly, the voltage of the output winding 12b also rises. Immediately after the period T5a starts, the output rectifier 20 is forward-biased and becomes conductive, and the current I20 waveform of the output rectifier 20 becomes the output winding 12b. Generates a current that releases the excitation energy. The period T5a ends when the current of the regenerative diode 56b finishes flowing.

  In the period T6a, the regenerative diode 56b becomes non-conductive, and the voltage V54 of the regenerative capacitor 54 is held at a value V54 (max) slightly higher than Vo · (Na / Nb). The voltage V56g continues to rise, but does not reach the ON threshold value Vth of the regenerative FET 56a. Further, since the regenerative diode 56b becomes non-conductive and the main FET 14a and the regenerative FET 56a continue to be turned off, as shown in FIG. 10, the input winding 12c, the regenerative capacitor 54, and the parasitic capacitor 54c (ds) of the regenerative element 54 And a path including the parasitic capacitor 14c (ds) of the main switching element 14 causes a resonance current to flow, and a small oscillating voltage is generated in the voltage V14d. In the voltage V14d, the resonance voltage is quickly attenuated and converges toward the total value of the input voltage Vi and the voltage Vo · (Na / Nb). The output rectifying element 20 continues to conduct, and the current I20 that discharges the excitation energy from the output winding 12b continues to flow. The period T6a ends when the voltage V56g increases to reach the ON threshold value Vth of the regenerative FET 56a, the regenerative FET 56a turns on, and a positive current I56 is generated in the regenerative element 56.

  Even during the period T7a, the voltage V56g continues to rise with a predetermined time constant, and the regenerative FET 56a continues to be turned on as shown in FIG. The reason why the voltage rise temporarily slows down in the waveform of the voltage V56g is that the parasitic capacitor 56c (dg) is connected in parallel to the parasitic capacitor 56c (gs). The main FET 14a continues to be turned off as in the period T6a. The output rectifying element 20 is also continuously conducted, and the current I20 that discharges the excitation energy from the output winding 12b continues to flow.

  When the regenerative FET 56a is turned on, a voltage difference between the voltage V54 (max) of the regenerative capacitor 54 and the voltage Vo · (Na / Nb) of the input winding 12c is generated at both ends of the leakage dactor 68, and the current I56 of the regenerative element 56 As a result, a current that discharges the charge of the regenerative capacitor 54 flows through the path of the regenerative FET 56 a, the regenerative capacitor 54, the input winding 12 c, and the leakage dactor 68. This current is a current that regenerates energy that has absorbed the surge voltage (ringing) generated in the voltage V14d in the period T5a in the circuit on the output winding 12c side. However, during the period T7a, since the output rectifying element 20 is conductive, the current I56 is relatively small, and the voltage V54 of the regenerative capacitor 54 is maintained at approximately V54 (max). The period T7a ends when the current that causes the output winding 12b to release the excitation energy stops flowing and the output rectifier 20 becomes non-conductive.

  Even in the period T8a, as shown in FIG. 12, each circuit element other than the output rectifying element 20 continues the operation state in the period T3a. When the period T8a is entered, the output rectifying element 20 becomes non-conductive, and the current I56 that discharges the charge of the regenerative capacitor 54 becomes larger than the period T7a. Along with this, the voltage V54 of the regenerative capacitor 54 gradually decreases, and the voltage V14d of the main FET 14a also gradually decreases. During the period T8a, the voltage V54 decreases to V54 (min), the discharge transistor 66b is turned on to discharge the parasitic capacitor 56c (gs), and the regenerative FET 56a is turned off to end the period T8a.

  When the period T9a is entered, the regenerative FET 56a is turned off, so that the path of the current flowing through the leakage dacter 68 is switched. In the period T9a, the main FET 14a continues to be turned off similarly to the period T8a, and the output rectifying element 20 also continues to be non-conductive. Therefore, as shown in FIG. (ds), and flows through the path of the input winding 12a and the leakage dactor 68. Due to this current, the parasitic capacitor 14c (ds) is discharged, and the voltage V14d of the main FET 14a rapidly decreases to zero. Then, when the voltage V14d decreases to zero, the period T9a ends and returns to the above-described period T1a. The above is the operation at the operating point A (at the time of heavy load).

  As shown in FIG. 14, the operation at the operating point B (light load) can be described by dividing one switching period Tsw into periods T1b to T6a, T8b, and T9b. The periods T1b to T6b, T8b, and T9b correspond to the periods T1a to T6a, T8a, and T9a at the operating point A. The operating point B has a shorter cycle Tsw than the operating point A. The circuit operation in each period is almost the same as the operation point A, but the periods T5b and T6b are slightly different from the circuit operations in the periods T5a and T6a of the operation point A. Further, at the operating point B, there is no period corresponding to the period T7a of the operating point A. Hereinafter, of the circuit operation at the operating point B, the points different from the operating point A will be described in order.

  First, the period T5b is described. In the case of the operating point A described above (during heavy load), the regenerative diode 56b becomes conductive and the current I56 begins to flow, the period T5a starts, and the current I20 begins to flow to the output rectifying element 20 at substantially the same timing. The currents I56 and I20 in the period T5a are both currents from which the transformer 12 emits excitation energy. In the case of the operating point A, the timings at which the currents I56 and I20 start to flow are almost the same.

  On the other hand, in the case of the operating point B (light load), after the regenerative diode 56b becomes conductive and the current I56 starts to flow and the period T5b starts, the current I20 starts to flow after a delay. This is because, since the output current Io supplied to the load 22 is small, for a while after the period T5b starts, the current at which the input winding 12a releases the excitation energy is concentrated toward the regenerative diode 56b. Further, since the output current Io supplied to the load 22 is small at the operating point B, the current I20 flows until the period T5b ends, and the output rectifying element 20 becomes non-conductive when the period T6b is reached.

  Next, the period T6b will be described. In the case of the operating point A described above (at the time of heavy load), when a period T6a is entered, a small oscillating voltage is superimposed on the voltage V14d, and as a result, an oscillating voltage is also generated on the voltage V56g of the regenerative FET 56. However, since the amplitude of the oscillating voltage of the voltage V56g is small at the operating point A, the peak of the oscillating voltage does not exceed the ON threshold value Vth of the regenerative FET 56a. Therefore, the time until the voltage V56g reaches the ON threshold value Vth (that is, the time of the period T6a) is determined by the time constants of the driving resistor 60 and the parasitic capacitor 56c (gs), and is a relatively long time.

  On the other hand, the operating point B (at light load) has the property that the amplitude of the oscillating voltage of the voltage V56g is larger than that of the operating point A, and the peak of the oscillating voltage instantaneously exceeds the ON threshold value Vth of the regenerative FET 56a. The period T6b ends in a short time. With this operation, the regenerative FET 56a can be turned on at an appropriate timing even at the operating point B where the switching cycle Tsw is short. Further, when the current I56 (current in the positive direction) starts to flow through the regenerative FET 56a and the period T6b ends, the output rectifying element 20 is already non-conductive, so that the period T7b (period corresponding to the period T7a of the operating point A) ) Does not occur and enters the next period T8b.

  As described above, the switching power supply 48 is provided with the unique snubber circuit 50 in parallel with the input winding 12 a of the transformer 12, thereby suppressing the surge voltage generated at the both-ends voltage V <b> 14 d of the main switching element 14 remarkably. As the main switching element 14, a high-performance element with a low withstand voltage can be used. The snubber circuit 50 can operate properly from light load to heavy load, has a simple configuration and low self-loss, and regenerates the energy of the surge component absorbed by the regenerative capacitor to the output winding 12b side. Therefore, a decrease in power supply efficiency can be minimized.

  Further, by providing the snubber circuit 50, the surge voltage generated in the auxiliary winding 12c is also significantly reduced in the range from light load to heavy load. Therefore, the output voltage detection circuit 44 can accurately detect the voltage Vo · (Nc / Nb) substantially proportional to the output voltage Vo from the auxiliary winding 12c, and the load of the output voltage Vo as shown in FIG. Variation can be reduced. Similarly, the input fluctuation can be reduced.

  Further, the on-timing setting circuit 58 (positive feedback circuit 28) that operates in response to the voltage change of the auxiliary winding 12c turns on the main FET 14a when the voltage V14d across the main switching element 14 is held at zero. Since it is adjusted, ideal zero volt switching can be performed, and cross loss and switching noise of the main switching element 14 can be suppressed to be small.

  Next, a modified example of the regeneration control circuit 58 will be described. As described above, the regenerative control circuit 58 is a block that controls the on / off operation of the regenerative FET 56a. “After turning on the regenerative FET 56a while the main FET 14a is off, the voltage V54 across the regenerative capacitor 54 is a predetermined value. The main FET 14a is turned off before the main FET 14a turns from off to on, and then the main FET 14a turns from on to off, and the voltage V54 across the regenerative capacitor 54 rises above a predetermined value to increase the regenerative diode. When the current starts to flow through 56b and the current flow ends, the operation of turning on the regenerative FET 56a is repeated every switching cycle Tsw of the main FET 14a. " The function of the regeneration control circuit 58 can also be realized by a configuration other than the regeneration control circuit 58 (1) shown in FIG. Hereinafter, six preferred modifications will be described.

  Unlike the above-described regeneration control circuit 58 (1), the regeneration control circuit 58 (2) which is the first modification is for forming a discharge path of the bias capacitor 62 as shown in FIG. A discharge resistor 64 is connected in parallel to both ends of the series circuit of the starting resistor 60 and the bias capacitor 62. Even with this configuration, it is possible to obtain substantially the same operation and effect as the regeneration control circuit 58 (1).

  Unlike the above-described regeneration control circuit 58 (1), the regeneration control circuit 58 (3) as the second modified example has a diode element between the collector base of the discharge transistor 66b as shown in FIG. The negative voltage setting diode 70 is connected in parallel. In the case of the regeneration control circuit 58 (1), the portion of the PN junction between the collector and base of the discharge transistor 66b is used as a negative voltage setting diode. However, like the regeneration control circuit 58 (2), the negative voltage setting diode is used. By providing the diode 70 separately, the stress applied to the discharge transistor 66b can be reduced.

  Unlike the regeneration control circuit 58 (3) of the second modified example, the regeneration control circuit 58 (4) of the third modified example, as shown in FIG. 15C, between the collector and base of the discharge transistor 66b. In addition, a negative voltage setting diode 72 which is a Zener diode element is connected in parallel. According to this configuration, when the negative voltage setting diode 72 conducts in the forward direction, the same effect as that of the negative voltage setting diode 70 can be obtained, and by conducting in the reverse direction, the gate-source between the regenerative FET 56a can be obtained. It is possible to prevent an abnormal high voltage from being generated and to protect the regenerative FET 56a.

  Unlike the regeneration control circuit 58 (4) of the third modified example, the regeneration control circuit 58 (5) of the fourth modified example is provided with a buffer circuit 74 instead of the buffer circuit 66. As shown in FIG. 16A, the buffer circuit 74 includes a charging diode 66a and a discharging transistor 74b that is a P-channel MOS FET. Even with this configuration, it is possible to obtain substantially the same operation and effect as the regeneration control circuit 58 (4).

  Unlike the regeneration control circuit 58 (4) of the third modified example, the regeneration control circuit 58 (6) of the fifth modified example is provided with a buffer circuit 76 instead of the buffer circuit 66. As shown in FIG. 16B, the buffer circuit 76 is composed of a charging diode 66a and a discharging transistor 76b formed by inverting Darlington connection of PNP and NPN transistors. Even with this configuration, it is possible to obtain substantially the same operation and effect as the regeneration control circuit 58 (4).

  Unlike the regeneration control circuit 58 (4) of the third modified example, the regeneration control circuit 58 (7) of the sixth modified example omits the buffer circuit 66 as shown in FIG. Discharge diodes 78 for quickly decreasing the voltage V56g between the gate and source of the regenerative FET 56a are provided at both ends of the resistor 60. Even with this configuration, it is possible to obtain substantially the same operation and effect as the regeneration control circuit 58 (4).

  In addition to the above modification, for example, a buffer circuit for charging the parasitic capacitor 56c (gs) is provided at the gate of the regenerative FET 56a, or the same function as the discharge diode 78 of the regenerative control circuit 58 (7) is provided. A speed-up capacitor may be provided. In addition, a discharge resistor may be added between the gate and source of the regenerative FET 56a or a gate resistor may be inserted so as not to cause abnormal vibration at the gate of the regenerative FET 56a within a range that does not hinder the above operation. .

  Next, 2nd embodiment of the switching power supply device of this invention is described based on FIG. Here, the same components as those in the above embodiment are denoted by the same reference numerals and description thereof is omitted. The switching power supply 80 of this embodiment is a separately excited power supply using an IC for critical mode control.

  A snubber circuit 50 similar to that in the above embodiment is provided at both ends of the input winding 12a. Unlike the above-described embodiment, the auxiliary winding 12c is connected to the ground 16 at one end to which the dot is attached. Therefore, the output voltage detection circuit 44 outputs the positive voltage Vo1 as an output voltage signal.

  An error amplification circuit 82 is provided at the output of the output voltage detection circuit 44. The error amplification circuit 82 receives a control signal V82 obtained by amplifying the difference between the output voltage signal Vo1 and the reference voltage Vr corresponding to the target value of the output voltage Vo. Output. A modulation circuit 84 is provided at the output of the error amplification circuit 82. The modulation circuit 84 performs predetermined modulation based on the control signal V82, and the main FET 14a is turned on so that the output voltage signal Vo1 becomes equal to the reference voltage Vr. The time Ton and the off time Toff are determined. Also, an ON timing setting circuit 86 is provided at one end of the auxiliary winding 12c. The ON timing setting circuit 86 observes a voltage change in the auxiliary winding 12c, and the voltage V14d across the main FET 14a decreases to zero. The predetermined timing information is output to the modulation circuit 84 so that the main FET 14a is turned on.

  The modulation circuit 84 generates and outputs a drive pulse V84 that drives the main FET 14. Since the main FET 14 is an N-channel MOS FET, the drive pulse V84 is a pulse voltage that repeats a high level (time Ton) and a low level (time Toff), and the timing at which the high level starts is determined from the on-timing setting circuit 86. It is set based on the acquired timing information. The configurations of the error amplification circuit 82, the modulation circuit 84, and the on-timing setting circuit 86 can be easily realized by using a commercially available critical mode control IC or the like.

  The separately-excited switching power supply 80 can obtain the same effects as the switching power supply 48 (self-excited).

  The switching power supply device of the present invention is not limited to the above embodiment. For example, in the above embodiment, the main switching element is an N-channel MOS FET, and a parasitic diode between the drain and the source is used as an auxiliary diode. A diode may be used. In the above embodiment, the regenerative switch is an N-channel MOS type FET, and a parasitic diode between the drain and the source is used as the regenerative diode. In addition to this, a fast recovery diode or the like is connected in parallel. It is good. In addition, in the equivalent circuits of FIGS. 5 to 13, a leakage dactor, a parasitic capacitor of a main FET, and a parasitic capacitor of a regenerative FET are shown as circuit elements that do not appear in a normal circuit diagram. An inductor element or a capacitor element may be attached to each corresponding position, and the L value or C value may be adjusted so that good circuit operation is performed.

  For the regenerative switch, an element other than the regenerative FET 56a (N-channel MOS FET) may be used. In this case, another regeneration control circuit different from the regeneration control circuits 58 (1) to 58 (7) is set in accordance with the characteristics of the elements to be used.

  The on-timing setting circuit of the above embodiment is for turning on the main switching element when the voltage across the main switching element is zero (zero volt switching operation). However, in order to simplify the on-timing setting circuit, a predetermined low You may make it turn on (soft switching operation | movement) at the timing which fell to the voltage. Further, if a zero volt switching operation or a soft switching operation is unnecessary, the on timing setting circuit may be omitted.

  The output voltage detection circuit of the above embodiment is configured to indirectly detect the output voltage on the input side (no photocoupler is used), but when a photocoupler can be used, as in the conventional switching power supply device 10 The output voltage can be detected directly on the output side.

10, 42, 48, 80 Switching power supply 12 Transformer 12a Input winding 12b Output winding 12c Auxiliary winding 14 Main switching element 14a Main FET
14b Auxiliary diode 20 Output rectifier 24 Output smoothing capacitor 44 Output voltage detection circuit 50 Snubber circuit 52 (28), 86 ON timing setting circuit 56 Regenerative element 56a Regenerative FET (regenerative switch)
56b Regenerative diodes 58, 58 (1) to 58 (7) Regenerative control circuit 60 Drive resistor 62 Bias capacitor 64 Discharge resistors 66, 74, 76 Buffer circuit 66a Charging diodes 66b, 74b, 76b Discharge transistors 70, 72 Negative voltage setting diode

Claims (7)

A main switching element for intermittently connecting an input voltage supplied from an input power supply; an input winding connected in series to the main switching element; and an output winding insulated from the input winding. During this period, the input voltage is applied to the input winding to store excitation energy, and the cathode is connected to both ends of the main switching element with the cathode connected to the connection point of the input winding and the main switching element. An auxiliary diode, an output rectifying element that rectifies the voltage generated in the output winding during a period when the main switching element is off, and a rectified voltage output from the output rectifying element is smoothed and output to an externally connected load An output smoothing capacitor that supplies a voltage and an output current; A circuit for controlling time, a switching control circuit for performing critical mode control for quickly inverting the main switching element from off to on after the excitation energy accumulated in the transformer is released through the output rectifying element In a flyback type switching power supply with
A regenerative capacitor having one end connected to a connection point of the input winding and the main switching element, a regenerative switch connected between the other end of the regenerative capacitor and the other end of the input winding, and an anode A regenerative diode connected to both ends of the regenerative switch on the regenerative capacitor side, and a snubber circuit composed of a regenerative control circuit for controlling on / off of the regenerative switch,
After the regenerative control circuit turns on the regenerative switch while the main switching element is off, the voltage across the regenerative capacitor drops to a predetermined value before the main switching element turns from off to on. The regenerative switch is turned off to hold the voltage across the regenerative capacitor at the predetermined value, and then the main switching element turns from on to off, and the voltage across the regenerative capacitor rises above the predetermined value. Thus, a current starts to flow through the regenerative diode, and when the current ends, the operation of turning on the regenerative switch is repeated every switching period of the main switching element. The regenerative switch is a regenerative FET that is an N-channel MOS FET having a source connected to the other end of the regenerative capacitor and a drain connected to the other end of the input winding.
The regeneration control circuit forms a discharge circuit of the bias capacitor and a series circuit of a drive resistor and a bias capacitor connected between a connection point of the input winding and the regeneration capacitor and a gate of the regeneration FET. Is connected between the discharge resistor and the gate source of the regenerative FET or a position corresponding thereto, and is conducted when the gate source of the regenerative FET is biased in the negative direction, and is generated between the gate source. 2. The switching power supply device according to claim 1, further comprising a negative voltage setting diode for clamping so that the negative voltage does not become larger than a predetermined value. A buffer circuit is inserted between one end of the series circuit of the driving resistor and the bias capacitor and the gate of the regenerative FET,
The buffer circuit has an anode connected to one end of a series circuit of the driving resistor and the bias capacitor, a cathode connected to the gate of the regenerative FET, and an emitter connected to the gate of the regenerative FET. 3. The switching power supply device according to claim 2, wherein a collector is connected to a source of the regenerative FET and a base is connected to a discharge transistor which is a PNP transistor connected to an anode of the charging diode.   4. The switching power supply device according to claim 3, wherein a portion of the PN junction between the collector base of the discharge transistor operates as the negative voltage setting diode. A protective Zener diode for preventing an excessive voltage from being generated between the gate source of the regenerative FET is connected between the gate source of the regenerative FET or a position corresponding thereto.
4. The switching power supply device according to claim 2 , wherein the protective Zener diode operates as the negative voltage setting diode.   The transformer is provided with an auxiliary winding insulated from the output winding, and the switching control circuit detects a change in voltage generated in the auxiliary winding, and based on the detection result, the main winding is detected. An on-timing setting circuit that determines the timing at which the switching element turns from off to on is provided, and when the on-timing setting circuit is operated, the main switching element has a timing at which the voltage at both ends of the main switching element drops below a predetermined value. The switching power supply device according to claim 1, wherein the switching power supply device is turned on.   The transformer is provided with an auxiliary winding insulated from the output winding, and the switching control circuit includes an output voltage detection circuit that detects a voltage generated in the auxiliary winding during a period in which the main switching element is off. The switching power supply device according to claim 1, wherein the switching control circuit controls the on-time and off-time of the main switching element by regarding the detected voltage as the output voltage.

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