JP6218131B2 - Semiconductor device and mounting method thereof - Google Patents

Semiconductor device and mounting method thereof Download PDF

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JP6218131B2
JP6218131B2 JP2012205447A JP2012205447A JP6218131B2 JP 6218131 B2 JP6218131 B2 JP 6218131B2 JP 2012205447 A JP2012205447 A JP 2012205447A JP 2012205447 A JP2012205447 A JP 2012205447A JP 6218131 B2 JP6218131 B2 JP 6218131B2
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conductive plate
electrode
semiconductor
semiconductor element
electrodes
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JP2014060319A (en
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高史 飯野
高史 飯野
宮下　純二
純二 宮下
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Citizen Electronics Co Ltd
Citizen Watch Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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Description

本発明は、基板上に素子電極面を載置して電気的接続を図る半導体素子及びその実装方法に関するものである。   The present invention relates to a semiconductor element for mounting an element electrode surface on a substrate for electrical connection and a mounting method thereof.

近年、ＬＥＤ等の半導体素子の小型化及び薄型化により、実装用の基板との電気的接続を図るための素子電極が微小になると共に、素子電極間同士の間隔も狭くなってきている。このような微小な素子電極を有する半導体素子を精度よく基板に実装するために、フリップチップ実装が用いられている。このフリップチップ実装は、ボール状のバンプが形成された素子電極面を基板に形成された外部電極に合わせてフェースダウンすることによって、電気的接続を図るものである（特許文献１，２）。   In recent years, with miniaturization and thinning of semiconductor elements such as LEDs, element electrodes for electrical connection with a mounting substrate have become minute and the distance between element electrodes has also become narrower. In order to mount a semiconductor element having such a small element electrode on a substrate with high accuracy, flip chip mounting is used. In this flip chip mounting, an element electrode surface on which ball-shaped bumps are formed is faced down with an external electrode formed on a substrate to achieve electrical connection (Patent Documents 1 and 2).

図６は、半導体素子１をフリップチップ実装する場合の従来の断面構造を示したものである。このフリップチップ実装用の基板６には、ポリイミド、ガラスエポキシ、ＢＴレジン等の樹脂が使用され、その上面には半導体素子１の素子電極３に対応する外部電極７がパターン形成されている。そして、半導体素子１の下面側に設けられている素子電極３の裏面にボール状のバンプ４を形成し、このバンプ４が形成された面を前記外部電極７に合わせて位置決め配置した後、リフロー処理等を施すことによって、素子電極３と外部電極７とが電気的に接続される。   FIG. 6 shows a conventional cross-sectional structure when the semiconductor element 1 is flip-chip mounted. A resin such as polyimide, glass epoxy, or BT resin is used for the flip chip mounting substrate 6, and an external electrode 7 corresponding to the element electrode 3 of the semiconductor element 1 is patterned on the upper surface thereof. Then, a ball-shaped bump 4 is formed on the back surface of the element electrode 3 provided on the lower surface side of the semiconductor element 1, and the surface on which the bump 4 is formed is positioned according to the external electrode 7 and then reflowed. By performing processing or the like, the element electrode 3 and the external electrode 7 are electrically connected.

図７は前記バンプ４を形成するための工程を示したものである。最初に、半導体素子１の下面側に、素子電極３の上方を露出開口するようにして保護膜９及びこの保護膜９上にレジスト５を所定の厚みに形成する（工程ａ）。次に、前記レジスト５の開口部５ａ内にブロック状のハンダメッキ層８を形成（工程ｂ）した後、レジスト５を除去する（工程ｃ）。最後に、前記ブロック状のハンダメッキ層８をリフロー炉で加熱し、ハンダメッキを一旦溶融することによってボール状のバンプ４が形成される（工程ｄ）。   FIG. 7 shows a process for forming the bump 4. First, a protective film 9 and a resist 5 are formed on the protective film 9 with a predetermined thickness on the lower surface side of the semiconductor element 1 so as to expose an opening above the element electrode 3 (step a). Next, after forming a block-like solder plating layer 8 in the opening 5a of the resist 5 (step b), the resist 5 is removed (step c). Finally, the block-shaped solder plating layer 8 is heated in a reflow furnace, and the solder plating is once melted to form ball-shaped bumps 4 (step d).

特開２００５−７９５５０号公報JP 2005-79550 A 特開２００８−２２６８６４号公報JP 2008-226864 A

バンプの形成工程は、半導体素子の形成工程の最終段階で最も重要なプロセスの一つであり、高い信頼性が要求されている。しかしながら、図７に示したように、バンプを形成するには、レジストの形成及び除去といった処理が必要となるなどの複数の工程を要していた。また、バンプを一定の厚みのボール状に成形するには時間がかかると共に、その厚みを一定にするには高度な精度が要求される。   The bump formation process is one of the most important processes in the final stage of the semiconductor element formation process, and high reliability is required. However, as shown in FIG. 7, in order to form a bump, a plurality of processes such as a process of forming and removing a resist are required. In addition, it takes time to form a bump into a ball having a constant thickness, and high accuracy is required to make the thickness constant.

特に、半導体素子の小型化等によって、素子電極の間隔が狭くなっているため、バンプの大きさや形成範囲を精度よくコントロールしないとショート等の電気的不具合に伴う製品不良が発生しやすいといった問題があった。   In particular, since the gap between the element electrodes is reduced due to miniaturization of the semiconductor element and the like, there is a problem that a product failure due to an electrical failure such as a short circuit is likely to occur unless the size and formation range of the bumps are accurately controlled. there were.

そこで、本発明の目的は、素子電極と基板側の外部電極に簡易且つ精度よく電気的接続を図るための導電板を備えた半導体素子及びその実装方法を提供することである。   Accordingly, an object of the present invention is to provide a semiconductor element provided with a conductive plate for easily and accurately connecting an element electrode and an external electrode on the substrate side, and a mounting method thereof.

上記課題を解決するために、本発明の半導体素子は、素子本体と、該素子本体の下面に設けられる平面四角形状からなる一対の素子電極と、該素子電極に接合され少なくとも前記素子電極の平面形状より小さい導電板とを備え、該導電板が離型シートを伴っていると共に、導電板は前記一対の素子電極の各外側縁部に寄せて配置され、各素子電極の内側縁部の上面が露出することを特徴とする。
In order to solve the above-described problems, a semiconductor element of the present invention includes an element body, a pair of planar electrodes formed on a lower surface of the element body, and a planar surface of the element electrode joined to the element electrode. A conductive plate smaller than the shape, the conductive plate is accompanied by a release sheet , and the conductive plate is disposed close to each outer edge of the pair of element electrodes, and the upper surface of the inner edge of each element electrode Is exposed .

また、本発明の半導体素子の実装方法は、複数の導電板が配置された大判の離型シートを用意し、それぞれの下面に素子電極を備えた複数の素子本体を前記大判の離型シート上に配置して、複数の素子本体のそれぞれの素子電極と複数の導電板とを接合し、複数の外部電極が形成された大判の基板上に素子本体を実装する際には前記離型シートを剥離し、対応する導電板と外部電極との導通接続を図った後、前記大判の基板を各素子本体に沿って分離することを特徴とする。   Further, the semiconductor element mounting method of the present invention provides a large release sheet having a plurality of conductive plates arranged thereon, and a plurality of element bodies each provided with an element electrode on the lower surface thereof are disposed on the large release sheet. When the element body is mounted on a large substrate on which a plurality of external electrodes are formed, the element sheet and the plurality of conductive plates are joined to each other. After peeling and achieving a conductive connection between the corresponding conductive plate and the external electrode, the large substrate is separated along each element body.

本発明に係る半導体素子によれば、予め離型シート上に配置された導電板を素子電極に合わせて接合するだけで、この導電板を介した基板への実装が可能となる。また、導電板を素子電極に合わせた形状や厚みに形成するのが容易となる。さらに、導電板を素子電極に接合した後は、導電板に伴う離型シートを剥離するだけでよいので、残留物も残らず後処理も容易である。   According to the semiconductor element of the present invention, it is possible to mount the conductive plate on the substrate via the conductive plate simply by joining the conductive plate previously arranged on the release sheet to the element electrode. In addition, it is easy to form the conductive plate in a shape and thickness that match the element electrode. Furthermore, after the conductive plate is bonded to the element electrode, it is only necessary to peel the release sheet associated with the conductive plate, so that no residue remains and post-processing is easy.

本発明に係る半導体素子の実装方法によれば、半導体素子の素子電極に対応する位置に導電板を配置した離型シートを用意し、該離型シート上に配置された導電板に合わせて素子電極を位置決め配置することによって、導電板を素子電極の裏面に精度よく短時間で接合させることができる。   According to the semiconductor element mounting method of the present invention, a release sheet in which a conductive plate is arranged at a position corresponding to the element electrode of the semiconductor element is prepared, and the element is aligned with the conductive plate arranged on the release sheet. By positioning and arranging the electrodes, the conductive plate can be bonded to the back surface of the element electrode with high accuracy in a short time.

また、大判の離型シートに半導体素子ごとの複数の導電板を配置させておくことによって、複数の半導体素子の素子電極に対して一括して導電板を接合することができるので、大量生産に適したものとなる。   In addition, by arranging a plurality of conductive plates for each semiconductor element on a large release sheet, the conductive plates can be collectively bonded to the element electrodes of the plurality of semiconductor elements. It will be suitable.

第１実施形態の半導体素子の斜視図である。It is a perspective view of the semiconductor element of a 1st embodiment. 上記半導体素子の断面図である。It is sectional drawing of the said semiconductor element. 上記半導体素子の形成工程及び実装工程を示す工程図である。It is process drawing which shows the formation process and mounting process of the said semiconductor element. 第２実施形態の半導体素子の斜視図及び断面図である。It is the perspective view and sectional drawing of the semiconductor element of 2nd Embodiment. 第３実施形態の半導体素子の斜視図及び断面図である。It is the perspective view and sectional drawing of the semiconductor element of 3rd Embodiment. 従来の半導体素子の実装形態を示す断面図である。It is sectional drawing which shows the mounting form of the conventional semiconductor element. 従来の半導体素子のバンプ形成工程を示す工程図である。It is process drawing which shows the bump formation process of the conventional semiconductor element.

以下、本発明に係る半導体素子の実施形態として、基本的なＰＮ接合によるダイオード素子を例にして説明する。図１及び図２は、本発明の第１実施形態の半導体素子１１を示したものである。素子本体１２は、窒化ガリウム系化合物半導体やアルミニウムガリウムヒ素あるいはガリウムヒ素リン系のチップで構成されている。この素子本体１２は、サファイアガラスからなるサブストレートと、このサブストレートの上にＰ型半導体、Ｎ型半導体を拡散成長させた拡散層（Ｐ層及びＮ層）とからなっている。前記Ｐ型半導体及びＮ型半導体はそれぞれＰ型電極，Ｎ型電極を備えており、このＰ型電極，Ｎ型電極の露出する部分が一対の素子電極１３となる。   Hereinafter, as an embodiment of a semiconductor device according to the present invention, a diode device having a basic PN junction will be described as an example. 1 and 2 show a semiconductor element 11 according to a first embodiment of the present invention. The element body 12 is composed of a gallium nitride compound semiconductor, an aluminum gallium arsenide, or a gallium arsenide phosphorus chip. The element body 12 includes a substrate made of sapphire glass and a diffusion layer (P layer and N layer) obtained by diffusing and growing a P-type semiconductor and an N-type semiconductor on the substrate. Each of the P-type semiconductor and the N-type semiconductor includes a P-type electrode and an N-type electrode, and the exposed portions of the P-type electrode and the N-type electrode serve as a pair of element electrodes 13.

前記一対の素子電極１３は、図１に示したように、素子本体１２の下面１２ａ側に対向するように平面状に設けられている。また、各素子電極１３の裏面には所定厚みの導電板１４が接合形成されている。この導電板１４は、従来のボール状のバンプに代わるものであり、銅（Ｃｕ）、銀（Ａｇ）又は金（Ａｕ）等の導電材料を各素子電極１３の形状や大きさに合わせて平板状に形成されている。また、半導体素子１１を実装用の基板に水平に実装するため、各導電板１３の厚みは略均一となっている。   As shown in FIG. 1, the pair of element electrodes 13 are provided in a planar shape so as to face the lower surface 12 a side of the element body 12. A conductive plate 14 having a predetermined thickness is bonded to the back surface of each element electrode 13. The conductive plate 14 is a substitute for a conventional ball-shaped bump, and a conductive material such as copper (Cu), silver (Ag), or gold (Au) is flattened according to the shape and size of each element electrode 13. It is formed in a shape. Further, since the semiconductor element 11 is mounted horizontally on the mounting substrate, the thickness of each conductive plate 13 is substantially uniform.

前記導電板１４は、図２に示したように、離型シート１５を伴っており、この離型シート１５に予め貼着配置されている。そして、この導電板１４の貼着面とは反対側の面に対して半導体素子１１の素子電極１３を対向させ、導電板１４に素子電極１３が一致するように半導体素子１１を配置し、導電板１４に素子電極１３を密着させる。そして、この状態で導電板１４と素子電極１３との間を熱圧着や超音波照射等による手段、あるいは、ロウ材を用いた溶接手段によって両者を接合させた後、半導体素子１１の実装時に離型シート１５を導電板１４から剥離する。   As shown in FIG. 2, the conductive plate 14 is accompanied by a release sheet 15, and is attached to the release sheet 15 in advance. Then, the element electrode 13 of the semiconductor element 11 is opposed to the surface opposite to the attachment surface of the conductive plate 14, and the semiconductor element 11 is arranged so that the element electrode 13 coincides with the conductive plate 14. The device electrode 13 is brought into close contact with the plate 14. In this state, the conductive plate 14 and the element electrode 13 are joined together by means such as thermocompression bonding, ultrasonic irradiation, or welding means using brazing material, and then separated when the semiconductor element 11 is mounted. The mold sheet 15 is peeled from the conductive plate 14.

次に、図３に基づいて、前記導電板１４の接合から半導体素子１１を基板上へ実装するまでの工程について説明する。最初に、半導体素子１１の素子電極１３の形状及び位置に合わせた導電板１４を離型シート１５上に配置したものを用意する（工程ａ）。この離型シート１５は、半導体素子１１が実装される基板と略同じ大きさに形成され、表面が離型剤を含有した材料でコーティングされている。前記導電板１４は、素子電極１３の形状や位置に対応する位置に離間可能となるように一時的に貼着される。   Next, based on FIG. 3, a process from joining the conductive plate 14 to mounting the semiconductor element 11 on the substrate will be described. First, a device in which a conductive plate 14 matched with the shape and position of the device electrode 13 of the semiconductor device 11 is arranged on the release sheet 15 is prepared (step a). The release sheet 15 is formed to be approximately the same size as the substrate on which the semiconductor element 11 is mounted, and the surface is coated with a material containing a release agent. The conductive plate 14 is temporarily attached so as to be separable at a position corresponding to the shape and position of the element electrode 13.

前記導電板１４が貼着された離型シート１５に向けて、素子電極１３が形成されている下面１２ａを下にして半導体素子１１を載置する（工程ｂ）。この載置は、導電板１４に素子電極１３一致するように重ね合わせ、熱圧着、超音波照射あるいはロウ材を介した溶接手段によって導電板１４を素子電極１３に接合させる（工程ｃ）。   The semiconductor element 11 is placed with the lower surface 12a on which the element electrode 13 is formed facing down to the release sheet 15 to which the conductive plate 14 is adhered (step b). In this placement, the conductive plate 14 is superposed on the conductive plate 14 so as to coincide with the conductive plate 14, and the conductive plate 14 is joined to the conductive electrode 13 by thermocompression bonding, ultrasonic irradiation, or welding means via a brazing material (step c).

前記導電板１４と素子電極１３との接合が終了した後、離型シート１５を導電板１４の裏面から剥離する（工程ｄ）。そして、外部電極１７が形成されている基板１６上に向けて半導体素子１１を移送した後、外部電極１７上に、対応する素子電極１３を位置決め載置し、導電板１４を介した熱圧着、超音波照射あるいはロウ材を介した溶接手段によって素子電極１３と外部電極１７とが電気的に接続される（工程ｅ）。   After the joining of the conductive plate 14 and the element electrode 13 is completed, the release sheet 15 is peeled from the back surface of the conductive plate 14 (step d). Then, after the semiconductor element 11 is transferred toward the substrate 16 on which the external electrode 17 is formed, the corresponding element electrode 13 is positioned and mounted on the external electrode 17, and thermocompression bonding via the conductive plate 14 is performed. The element electrode 13 and the external electrode 17 are electrically connected by ultrasonic irradiation or welding means via brazing material (step e).

本実施形態にあっては、素子電極１３と外部電極１７との間の略全面に導電板１４が均一な厚みで介在しているので、接合にムラがなく、接合強度も向上する。また、前記導電板１４が導電率の高いＣｕ、Ａｇ、Ａｕ等の材料で均一な平板状に形成されているため、導電効率の向上効果も得られる。   In the present embodiment, since the conductive plate 14 is interposed on the substantially entire surface between the element electrode 13 and the external electrode 17 with a uniform thickness, there is no unevenness in bonding and the bonding strength is improved. In addition, since the conductive plate 14 is formed in a uniform flat plate with a material such as Cu, Ag, or Au having high conductivity, an effect of improving the conductive efficiency can be obtained.

図４は第２実施形態の半導体素子２１を示したものである。この実施形態では、導電板２４の平面形状を素子電極１３の平面形状よりも小さくし、素子電極１３の四方の縁部を僅かに露出させて形成したものである。このため、半導体素子２１と導電板２４との位置合わせは、素子電極１３と導電板２４のそれぞれの中心部を一致させるようにして行う。この実施形態にあっては、導電板２４を素子電極１３より小さく形成してあるので、左右一対の導電板２４間の間隔が広がり、隣接する素子電極１３間でのショート等の電気的接合不良が起きにくくなる。また、導電板２４を熱、超音波あるいはロウ材を用いて接合する際に、素子電極１３の外側へのはみ出しを防止することができる。   FIG. 4 shows the semiconductor element 21 of the second embodiment. In this embodiment, the planar shape of the conductive plate 24 is made smaller than the planar shape of the element electrode 13 and the four edges of the element electrode 13 are slightly exposed. Therefore, the alignment of the semiconductor element 21 and the conductive plate 24 is performed so that the center portions of the element electrode 13 and the conductive plate 24 are aligned. In this embodiment, since the conductive plate 24 is formed to be smaller than the element electrode 13, the distance between the pair of left and right conductive plates 24 is widened, resulting in poor electrical connection such as a short circuit between adjacent element electrodes 13. Is less likely to occur. In addition, when the conductive plate 24 is bonded using heat, ultrasonic waves, or brazing material, it is possible to prevent the element electrode 13 from protruding to the outside.

図５は第３実施形態の半導体素子３１を示したものである。この実施形態では、導電板３４の平面形状を素子電極１３の平面形状よりも小さく形成すると共に、導電板３４を素子電極１３からはみ出さないように素子電極１３の外周縁部に寄せて接合したものである。前記第２実施形態の半導体素子２１と比較すると、左右一対の導電板３４間の間隔が広がるため、隣接する素子電極１３間でのショート等の電気的接合不良を起きにくくするという効果は共通であるが、各導電板３４の対向する側を除いた外周部が各素子電極１３の外周部までをカバーしているので、実装する基板側の外部電極との密着性及び導電性が高まる。   FIG. 5 shows a semiconductor element 31 of the third embodiment. In this embodiment, the planar shape of the conductive plate 34 is formed smaller than the planar shape of the element electrode 13, and the conductive plate 34 is joined to the outer peripheral edge of the element electrode 13 so as not to protrude from the element electrode 13. Is. Compared with the semiconductor element 21 of the second embodiment, since the distance between the pair of left and right conductive plates 34 is widened, the effect of making it difficult to cause an electrical connection failure such as a short circuit between adjacent element electrodes 13 is common. However, since the outer peripheral portion excluding the opposing side of each conductive plate 34 covers up to the outer peripheral portion of each element electrode 13, the adhesion and conductivity with the external electrode on the substrate side to be mounted are improved.

上記第１乃至第３実施形態で示したように、導電板１４，２４，３４が素子電極１３の形状に合わせて一様な厚みに形成できるので、外部電極１７との接合が従来のボール状のバンプに比べてより確実になる。また、素子電極１３の形状や大きさに適合するように、精度よく導電板を形成することができる。   As shown in the first to third embodiments, the conductive plates 14, 24, 34 can be formed to have a uniform thickness according to the shape of the element electrode 13, so that the bonding with the external electrode 17 is a conventional ball shape. It will be more reliable than the bumps. In addition, the conductive plate can be formed with high accuracy so as to match the shape and size of the element electrode 13.

上記実施形態では、導電板１４，２４，３４を素子電極１３の平面形状と同一かそれより小さい平板で一定の厚みの形成したが、一定の導電率が確保できるだけの密着した平面領域があればよい。このため、全てフラットな平面でなくてもよく、例えば、複数のドットによる点接触の集合体となるような凸状パターンのとして形成することもできる。   In the above embodiment, the conductive plates 14, 24, and 34 are flat plates having the same thickness as or smaller than the planar shape of the element electrode 13 and have a constant thickness. Good. For this reason, it does not have to be a flat plane at all. For example, it can be formed as a convex pattern that forms an aggregate of point contacts of a plurality of dots.

上記図３では、単体の半導体素子１１を単体の基板１６に実装する工程を示したが、複数の導電板を所定位置に配置した大判の離型シートを用意し、この大判の離型シート上に前記各導電板と対応する素子電極を有する複数の素子本体を載置することによって、複数の素子本体に対して導電板を一括して接合することができる。そして、複数の素子本体の素子電極に対応する外部電極が複数配列形成された大判の基板上に前記大判の離型シートが剥離された素子電極を位置決め載置して、それぞれの素子電極と外部電極との導通接続を図った後、各素子本体に沿って大判の基板をダイシングによって分離する。これによって、単体の基板上に単体の半導体素子を実装してなる半導体チップを一括して量産することができる。   In FIG. 3, the process of mounting the single semiconductor element 11 on the single substrate 16 is shown. However, a large release sheet having a plurality of conductive plates arranged at predetermined positions is prepared, and the large release sheet is formed on the large release sheet. By mounting a plurality of element bodies having element electrodes corresponding to the respective conductive plates, the conductive plates can be collectively bonded to the plurality of element bodies. Then, the element electrode from which the large release sheet is peeled is positioned and mounted on a large substrate on which a plurality of external electrodes corresponding to the element electrodes of the plurality of element bodies are formed, and each element electrode and the external electrode After the conductive connection with the electrode is achieved, a large substrate is separated by dicing along each element body. Thus, it is possible to mass-produce semiconductor chips in which a single semiconductor element is mounted on a single substrate.

１ 半導体素子
３ 素子電極
４ バンプ
５ レジスト
５ａ 開口部
６ 基板
７ 外部電極
８ ハンダメッキ層
９ 保護膜
１１ 半導体素子
１２ 素子本体
１２ａ 下面
１３ 素子電極
１４ 導電板
１５ 離型シート
１６ 基板
１７ 外部電極
DESCRIPTION OF SYMBOLS 1 Semiconductor element 3 Element electrode 4 Bump 5 Resist 5a Opening 6 Substrate 7 External electrode 8 Solder plating layer 9 Protective film 11 Semiconductor element 12 Element main body 12a Lower surface 13 Element electrode 14 Conductive plate 15 Release sheet 16 Substrate 17 External electrode

Claims (6)

素子本体と、該素子本体の下面に設けられる平面四角形状からなる一対の素子電極と、該素子電極に接合され少なくとも前記素子電極の平面形状より小さい導電板とを備え、該導電板が離型シートを伴っていると共に、導電板は前記一対の素子電極の各外側縁部に寄せて配置され、各素子電極の内側縁部の上面が露出することを特徴とする半導体素子。 An element body, a pair of element electrodes having a planar square shape provided on a lower surface of the element body, and a conductive plate that is bonded to the element electrode and is at least smaller than the planar shape of the element electrode, and the conductive plate is released A semiconductor element having a sheet, wherein the conductive plate is disposed close to each outer edge of the pair of element electrodes, and an upper surface of the inner edge of each element electrode is exposed . 前記素子電極は素子本体の下面に平面状に設けられ、この素子電極と密着するように導電板が接合される請求項１に記載の半導体素子。   The semiconductor element according to claim 1, wherein the element electrode is provided in a planar shape on the lower surface of the element body, and a conductive plate is bonded so as to be in close contact with the element electrode. 前記導電板は、銅、銀又は金を厚みが均一となるように平板状に形成される請求項１又は２に記載の半導体素子。   The semiconductor element according to claim 1, wherein the conductive plate is formed in a flat plate shape such that copper, silver, or gold has a uniform thickness. 前記素子電極は、前記導電板を介して外部電極と導通する請求項１又は２に記載の半導体素子。   The semiconductor element according to claim 1, wherein the element electrode is electrically connected to an external electrode through the conductive plate. 前記導電板は、前記素子電極に対して、熱圧着、超音波あるいはロウ材を介した溶融手段によって接合される請求項１又は２に記載の半導体素子。 The semiconductor element according to claim 1, wherein the conductive plate is bonded to the element electrode by thermocompression bonding, ultrasonic waves, or melting means via a brazing material. 複数の導電板が配置された大判の離型シートを用意し、
それぞれの下面に素子電極を備えた複数の素子本体を前記大判の離型シート上に配置して、複数の素子本体のそれぞれの素子電極と複数の導電板とを接合し、
複数の外部電極が形成された大判の基板上に素子本体を実装する際には前記離型シートを剥離し、
対応する導電板と外部電極との導通接続を図った後、
前記大判の基板を各素子本体に沿って分離することを特徴とする半導体素子の実装方法。 Prepare a large release sheet with a plurality of conductive plates,
A plurality of element bodies having element electrodes on their lower surfaces are arranged on the large release sheet, and the element electrodes and the plurality of conductive plates of the plurality of element bodies are joined together,
When mounting the element body on a large substrate on which a plurality of external electrodes are formed, the release sheet is peeled off,
After connecting the corresponding conductive plate and external electrode,
A method for mounting a semiconductor device, comprising separating the large substrate along each device body.
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