JP6215537B2 - Manufacturing method of semiconductor device using carbon nanotube bundle group suitable for semiconductor device, and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device using a carbon nanotube bundle group suitable for a semiconductor device such as a field effect transistor, and a semiconductor device.

Control of an electric vehicle requires a transistor with high output and low power consumption. In particular, in recent years, there is a great need for a transistor capable of controlling a current of 0.1 ampere level. In addition, there is a high need for a transistor that suppresses a current (leakage current) that flows when the transistor is turned off from the viewpoint of effective use of the battery.
Here, in order to control a high output, that is, a large current with a transistor, it is effective to reduce the channel resistance value by reducing the channel length. In addition, it is also effective to increase the number of carriers flowing in the channel by increasing the cross-sectional area of the channel. In addition, when a liquid electrolyte consisting of an electrolyte or ionic liquid is used for the gate, the contact area between the liquid electrolyte and the channel surface increases, and the gate insulating layer can be instantaneously and collectively applied to the surface of multiple channels. Since a functioning electric double layer can be generated and the responsiveness as a switching element is improved, it is effective to employ a liquid electrolyte as the gate.
In Patent Document 1, a plurality of short columnar semiconductors are arranged between a source electrode and a drain electrode facing each other to shorten the channel length and ensure a large cross-sectional area of the channel. A transistor with a liquid filled gate is disclosed.

On the other hand, a field effect transistor (hereinafter referred to as “FET”) using carbon nanotubes (hereinafter referred to as “CNT”) having higher electron (hole) mobility than silicon that is widely used as a semiconductor material in recent years. ") Is being studied.
The CNT has a shape in which a sheet-like substance called a graphene sheet, which forms a honeycomb structure having a hexagonal carbon atom with a thickness of one atom, is wound in a cylindrical shape. Of the four outermost electrons of a carbon atom, three are used for covalent bonds with adjacent carbon atoms, but the fourth unbonded electron is above and below the plane of the graphene sheet. It exists in a vertically extending orbit. This orbit extends throughout the graphene sheet. Since electrons spreading above and below the sheet can move close to ballistic conduction (electrons travel without scattering) without colliding with obstacles, CNT has high electron (hole) mobility. And has a property of low electrical resistance. In fact, the electron mobility of CNT is about 1.0 × 10 ⁵ cm ² / V · s compared to the electron mobility of silicon is about 1.5 × 10 ⁴ cm ² / V · s, About 10 times larger.

  By the way, the length of CNT obtained by using a laser ablation method, an arc plasma method, a chemical vapor deposition method (CVD method) or the like widely known as a CNT synthesis method is about several μm. When this CNT is used as a columnar semiconductor channel in Patent Document 1 and an attempt is made to connect the source electrode and the drain electrode with a single continuous CNT, the distance between the source electrode and the drain electrode is several μm or less. It is necessary to. However, if the distance between the source electrode and the drain electrode is too short, the leakage current due to the tunnel effect increases, and it does not serve as a current switching element that is the main purpose of the FET.

  Here, when the above-described CNT is used for a channel, if a continuous metallic CNT is connected between the source electrode and the drain electrode, a leakage current is generated, and the ON / OFF ratio as a transistor is lowered, and the switching element As a result, the performance will deteriorate.

The field effect transistors described in Patent Document 2 and Patent Document 3 have a channel structure in which a plurality of short CNTs shorter than the distance between the source electrode and the drain electrode are dispersed. There is no single metallic CNT continuous between the two. For this reason, there exists an advantage that the leakage current which flows through metallic CNT with small resistance can be suppressed. However, since a plurality of short CNTs are dispersed with a dispersion liquid to form a channel, the channel is 1) a dispersion liquid that obstructs electron (hole) transport remains in the channel. The contact resistance increases because there are many contacts. 3) The density of CNTs is limited in order to highly disperse CNTs in the dispersion, and the contact area with the electrodes is small because they are dispersed in random directions. For this reason, the resistance of the channel and the resistance of the channel-electrode interface may increase. That is, since the properties 1) to 3) act in the direction of increasing the electrical resistance between the source electrode and the drain electrode, the current between the source electrode and the drain electrode is at most 120 μA / mm (drain electrode). Between the source electrode and the source electrode: V _DS = 5.0 V, and the voltage between the gate electrode and the source electrode: V _GS = 7.0 V), and a current of 0.1 ampere to several amperes level It cannot be used for power devices for electric vehicles that require control.

Below, the manufacturing method of CNT in a prior art (for example, patent document 2 and patent document 3) is demonstrated, referring FIG.
FIG. 17 is a schematic view showing a conventional method for manufacturing an FET.

  The creation of the FET in the prior art is executed by the following procedure.

  In step S101, the gate length is set. There is no particular limitation on the gate length, and it can be designed freely according to requirements. Accordingly, the density and length of the CNT are determined.

  In step S102, CNTs are prepared. As a method for synthesizing CNT, any of a general laser ablation method, an arc plasma method, and a chemical vapor deposition method (CVD method) may be used, but the length of CNT obtained by any method is several. The ratio of semiconductor CNT to metallic CNT is about 2: 1.

  In step S103, the density and length of the CNT are determined. The range of CNT density and length is uniquely defined by calculation based on the gate length and the ratio of semiconducting CNT to metallic CNT.

  In step S104, a CNT dispersion is prepared. In adjusting the length of CNTs, a CNT dispersion is prepared by dispersing CNT groups in an organic solvent or an aqueous solvent. This dispersion contains a surfactant for promoting dispersion, metal fine particles for promoting fragmentation, and the like.

  In step S105, CNT fragmentation processing is performed. The CNT dispersion is subjected to ultrasonic treatment to fragment the CNT.

  In step S106, CNTs are separated. A CNT having a length longer than necessary is separated by a filter. Solvents, surfactants, metal fine particles, and the like are also separated by a process such as centrifugation.

  In step S107, a CNT dispersion is prepared. At this time, the CNT concentration is set to be equal to or lower than the concentration determined in step S103. This dispersion contains a surfactant for promoting dispersion.

  In step S108, a channel layer is formed. Examples of the method for forming the channel layer include coating the CNT dispersion on the substrate by a technique such as spin coating, and this is repeated until the concentration determined in step S103 is reached.

  Among the above steps, steps S104 to S108 have the following problems.

[Problem of Step S104]
The CNT dispersion includes a dispersion solvent composed of an organic solvent or an aqueous solvent, a surfactant for promoting dispersion, and metal fine particles for promoting fragmentation. It is not easy to completely remove them in step S106, and they are included in the channel layer formed in step S108. When such impurities remaining in the channel act as a transistor, there is a serious obstacle to carrier transport, and there is a possibility that the channel conduction characteristics deteriorate, and further, the current value that can be controlled as a transistor is greatly reduced.

[Problem of Step S105]
The fragmentation process causes unnecessary defects on the sidewalls of the CNTs and deteriorates the conductive properties. In addition, it is not technically easy to align the lengths with the accuracy of the micro order with respect to the length defined in step S103.

[Problem of Step S106]
As described in step S104, it is not easy to completely separate the dispersion solvent, the surfactant, and the metal fine particles from the CNTs. Furthermore, the man-hours, time, and cost for semiconductor device creation are greatly increased. Further, the treatment of the removed CNT, the dispersion solvent, the surfactant, and the metal fine particles can be a problem in actual production.

[Problem of Step S107]
Also in this step, since the dispersion liquid is prepared by mixing CNT, the dispersion solvent, and the surfactant, these impurities may remain in the channel in forming the channel layer in step S108.

[Problem of Step S108]
A channel layer is formed on the substrate by coating on the substrate by a technique such as spin coating. In order to obtain the concentration determined in step S103, it is necessary to repeat this step a plurality of times depending on the concentration of the dispersion. There is. However, in order to uniformly disperse the CNTs in the dispersion, the concentration of CNTs in the dispersion is inevitably thin, and since a method of uniformly applying and forming channels is adopted, There is also a limit to the amount of dispersion that can be applied at one time. Therefore, it is necessary to repeat this step several tens to several hundreds of times depending on the design of the transistor, which may significantly increase the man-hours, time, and cost for manufacturing the semiconductor device.

International Publication No. 2009/1333891 Japanese Patent No. 4666270 International Publication No. 2011/090029

  The present invention has been made in view of such a situation, and provides a method for manufacturing a semiconductor device using a bundle of CNTs that do not include a dispersion, metal fine particles, and defective CNTs in a semiconductor device such as a transistor. Another object of the present invention is to provide a field effect transistor which is one of semiconductor devices capable of controlling a current of 0.1 to ampere level while suppressing leakage current using the same.

(1) The present invention is a method for manufacturing a semiconductor device comprising a source electrode, a drain electrode, a gate, and a channel provided between the source electrode and the drain electrode, and the density is 1 A substrate as the channel so that a bundle of CNTs of 0.0 × 10 ⁹ pieces / cm ² or more is oriented in a predetermined direction with respect to a straight line forming the shortest distance between the source electrode and the drain electrode. There is provided a method for manufacturing a semiconductor device, comprising: a step disposed on the substrate; and a step of forming the source electrode, the drain electrode, and the gate on the substrate. .
According to the invention of (1), with this configuration, electrons (holes) transported between the source electrode 3 and the drain electrode 4 move between CNTs adjacent to each other with high density, so that excellent conductivity is achieved. It is possible to control the current value by configuring a channel having the property and changing the orientation.

(2) The present invention is characterized in that the bundle group of CNTs is manufactured to satisfy the following requirements (a) to (c).
(A) The bundle group of CNTs satisfies Lgate ≦ Lcnt (1) that satisfies the following formula (1):
In the above formula (1),
Lgate indicates the length of the gate,
Lcnt is a number indicating the average length of CNTs constituting the bundle group of CNTs.
(B) The density of the bundle group of the CNTs is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(C) The orientation of the CNT bundle group is parallel to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4.
According to the invention of (2), since the long CNT bridges between the source electrode and the drain electrode, the electrical resistance value of the channel is small, and furthermore, the electrode and the channel are in good contact at the interface. Since the state is realized, the electric resistance between the channel and the electrode is small, and a large ampere level current can be controlled.

(3) The present invention is characterized in that the bundle group of CNTs is manufactured to satisfy the following requirements (d) to (f).
(D) The CNT bundle group satisfies the following formula (2): Wgate ≦ Lcnt (2)
In the above formula (2),
Wgate indicates the width of the gate;
Lcnt is a number indicating the average length of the CNTs constituting the bundle of carbon nanotubes.
(E) The density of the bundle group of the CNTs is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(F) The orientation of the bundle group of CNTs is orthogonal to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4.
According to the invention of (3), continuous connection of metallic CNTs between the source electrode and the drain electrode can be avoided as much as possible, and leakage current can be suppressed.

(4) The present invention is characterized in that the gate is made of a liquid electrolyte.
According to the invention of (4), when the surface of the channel is impregnated with the liquid electrolyte with good adhesion and a voltage is applied to the gate reference electrode, the surface of the liquid electrolyte and each channel is instantaneously and collectively formed as a gate insulating layer. Since a functioning electric double layer is generated, a current of 0.1 ampere level can be controlled with low power consumption.

(5) The present invention is characterized in that the step of preparing the bundle group of CNTs includes the step of preparing the bundle group of CNTs by a tip discharge radical CVD method.
According to the invention of (5), since a CNT having a length longer than that capable of continuously connecting the source electrode and the drain electrode can be synthesized, a channel of the field effect transistor can be manufactured without using a dispersion.

(6) The present invention is a semiconductor device including a source electrode, a drain electrode, a gate, and a channel provided between the source electrode and the drain electrode, and has a density of 1.0 × A group of CNT bundles of 10 ⁹ pieces / cm ² or more is arranged on the substrate as the channel so as to be oriented in a predetermined direction with respect to a straight line forming the shortest distance between the source electrode and the drain electrode. The source electrode, the drain electrode, and the gate are formed on the substrate.
According to the invention of (6), with this configuration, electrons (holes) transported between the source electrode 3 and the drain electrode 4 move between CNTs adjacent to each other with high density, and thus have excellent conductivity. It is possible to control the current value by configuring a channel having the property and changing the orientation.

(7) The present invention is characterized in that the bundle of CNTs satisfies the following requirements (a) to (c).
(A) The bundle group of CNTs satisfies Lgate ≦ Lcnt (1) that satisfies the following formula (1):
In the above formula (1),
Lgate indicates the length of the gate,
Lcnt is a number indicating the average length of CNTs constituting the bundle group of CNTs.
(B) The density of the bundle group of the CNTs is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(C) The orientation of the CNT bundle group is parallel to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4.
According to the invention of (7), since the long CNT bridges between the source electrode and the drain electrode, the electrical resistance value of the channel is small, and furthermore, the electrode and the channel are in good contact at the interface. Since the state is realized, the electrical resistance between the channel and the electrode is small, and a large ampere level current can be controlled.

(8) The present invention is characterized in that the bundle of CNTs satisfies the following requirements (d) to (f).
(D) The CNT bundle group satisfies the following formula (2): Wgate ≦ Lcnt (2)
In the above formula (2),
Wgate indicates the width of the gate;
Lcnt is a number indicating the average length of CNTs constituting the bundle group of CNTs.
(E) The density of the bundle group of the CNTs is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(F) The orientation of the bundle group of CNTs is orthogonal to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4.
According to the invention of (8), it is possible to avoid the continuous connection of metallic CNT between the source electrode and the drain electrode as much as possible, and to suppress the leakage current from flowing.

(9) The present invention is characterized in that the gate is made of a liquid electrolyte.
According to the invention of (9), when the surface of the channel is impregnated with the liquid electrolyte with good adhesion and a voltage is applied to the gate reference electrode, the surface of the liquid electrolyte and each channel is instantaneously and collectively formed as a gate insulating layer. Since a functioning electric double layer is generated, a current of 0.1 ampere level can be controlled with low power consumption.

(10) The present invention is characterized in that the bundle of CNTs is synthesized by a tip discharge radical CVD method.
According to the invention of (10), since a CNT having a length longer than that capable of continuously connecting the source electrode and the drain electrode can be synthesized, the channel of the field effect transistor can be manufactured without using a dispersion.

  According to the present invention, a field effect transistor using a CNT structure obtained by a plasma CVD method for a channel is specialized for a current value configuration and a switching action only by changing the orientation of the CNT in the channel. The configuration can be provided very simply.

It is a schematic diagram which shows the structural difference between metallic CNT and semiconducting CNT. It is a schematic diagram which shows the structure of the field effect transistor as one Embodiment concerning this invention. It is a conceptual diagram explaining the orientation and geometric requirements of CNT arranged parallel to the electron (hole) transport direction as a channel. It is a conceptual diagram explaining the difference of the channel structure of a prior art and this invention. It is the schematic of the plasma CVD apparatus which synthesize | combines CNT used for the field effect transistor as one Embodiment concerning this invention. It is a figure which shows the SEM image of CNT synthesize | combined using plasma CVD method as one Embodiment which concerns on this invention. It is a figure which shows the TEM image of CNT synthesized using plasma CVD method as one Embodiment which concerns on this invention. It is a flowchart which shows the manufacture procedure of the field effect transistor as one Embodiment concerning this invention. It is a flowchart which shows the manufacture procedure of the channel layer of the field effect transistor as one Embodiment concerning this invention. It is the schematic which shows the manufacturing method of the field effect transistor as one Embodiment concerning this invention. It is a figure which shows the performance evaluation of the field effect transistor as one Embodiment concerning this invention. It is a conceptual diagram which shows the electron (hole) transport path | route by the bundle structure of CNT used for the field effect transistor as one Embodiment concerning this invention. It is a schematic diagram which shows the structure of the field effect transistor as one Embodiment concerning this invention. It is a conceptual diagram explaining the orientation and geometric requirement of CNT arrange | positioned as a channel in the direction orthogonal to an electron (hole) transport direction. It is a conceptual diagram which shows the electron (hole) transport path | route by the bundle structure of CNT used for the field effect transistor as one Embodiment concerning this invention. It is a figure which shows the performance evaluation of the field effect transistor as one Embodiment concerning this invention. It is a flowchart which shows the manufacture procedure of the channel layer of the field effect transistor which concerns on a prior art.

[First embodiment]
A field effect transistor 1 according to an embodiment of the present invention (hereinafter referred to as “FET 1” as necessary) will be described with reference to the drawings as appropriate.

[Constitution]
FIG. 2 is a schematic diagram of a configuration of the field effect transistor 1 according to an embodiment of the present invention.
An FET 1 according to an embodiment of the present invention includes a substrate 2, a source electrode 3, a drain electrode 4, a conductive resin 5, an insulating resin 6, a channel 7, a gate 8, a gate reference electrode 9, and a wiring 10. .

The substrate 2 is made of glass, but may be a resin film such as polyethylene naphthalate or a plastic, for example.
In a partial region on the substrate 2, a source electrode 3 and a drain electrode 4 each having a rectangular parallelepiped shape are arranged so as to face each other. Each of the source electrode 3 and the drain electrode 4 is composed of titanium and a titanium covered with gold.
The conductive resin 5 is made of a conductive epoxy resin or silver paste, and is disposed so as to cover the periphery of the source electrode 3 and the drain electrode 4.
The insulating resin 6 is made of an insulating epoxy resin and is disposed so as to cover the outer periphery of the conductive resin 5.

Here, the length of the CNT constituting the channel 7 of the present invention is at least longer than the distance between the source electrode 3 and the drain electrode 4, and the CNT is between the source electrode 3 and the drain electrode 4. Are connected continuously. In addition, the CNTs constituting the channel 7 of the present invention are formed at a high density of 1.0 × 10 ^{9 to} 1.0 × 10 ¹² / cm ² per unit area.
In this way, the CNTs that are longer than the distance between the source electrode 3 and the drain electrode 4 and have a higher density than the ratio of the number of channels of the conventional FET device using CNTs are used for the channel 7. In the FET 1, the role as an FET can be given without performing a dispersion process (a process of forming a channel 7 by dispersing a plurality of short CNTs with a dispersion) as in the conventional example.
In the FET 1 of the present invention, no dispersion liquid that obstructs electron (hole) transport remains in the channel 7, and the channel 7 is efficiently impregnated in the gate 8, so that the channel 7 and the gate 8 are not impregnated. Therefore, when a voltage is applied to the gate reference electrode 9, an electric double layer is easily generated on the surfaces of the gate 8 and the channel 7. Further, the source electrode 3, the drain electrode 4, and the channel 7 are Since a good contact state is realized at the interface, the electrical resistance between the channel and the channel-electrode is small, and a large ampere level current can be controlled.

FIG. 3A is a schematic view of a CNT used for a channel of a field effect transistor as an embodiment according to the present invention. The channel 7 is arranged so that the extending direction of the aggregate of CNT bundles composed of a plurality of CNTs oriented in the same direction is parallel to a straight line that is the shortest distance between the source electrode 3 and the drain electrode 4.
Here, as shown in FIG. 3B, the length Lgate of the straight line that is the shortest distance between the source electrode 3 and the drain electrode 4 is referred to as “gate length”. A direction parallel to the plane of the substrate 2 and perpendicular to the straight line that is the shortest distance between the source electrode 3 and the drain electrode 4 is called a “gate width direction”, and the length Wgate of the channel 7 in the gate width direction is This is called “gate width”. The average length of the plurality of CNTs used as the channel 7 (hereinafter referred to as “average length of a bundle of carbon nanotubes”), that is, the average length Lcnt is referred to as “channel length”. Further, the direction perpendicular to the plane of the substrate 2 is called “gate height direction”, and the dimension of the channel 7 in the gate height direction is called “gate thickness”.
In this embodiment, for example, the gate length Lgate and the gate width Wgate are both 1 mm, and the thickness of the gate (the thickness in the direction perpendicular to the plane of the substrate 2) is 300 μm. Alternatively, the gate length Lgate may be about 1 inch (2.54 mm). Note that the channel 7 may be formed by plating the surface of the channel 7.

It can be said that the channel 7 of the present invention is desirably formed so that the orientation of the CNTs is parallel to the transport direction of electrons (holes) between the source electrode 3 and the drain electrode 4. That is, it is desirable that the orientation of the CNTs be parallel to a straight line that is the shortest distance between the source electrode 3 and the drain electrode 4.
The more the orientation of the CNT becomes parallel to the transport direction of electrons (holes) between the source electrode 3 and the drain electrode 4, the more electrons (holes) transported between the source electrode 3 and the drain electrode 4 This is because it becomes easier to move on (or in the vicinity of) the metallic CNT, and the resistance of the channel 7 is reduced by the amount of movement between adjacent CNTs. Therefore, in order to obtain a high-power FET 1, it is desirable that the orientation of the CNTs is parallel to the electron (hole) transport direction between the source electrode 3 and the drain electrode 4.

  Here, although one CNT is macroscopically long enough, it is not strictly a “straight line” (for example, as shown as a partially enlarged view of FIG. 6 described later). “Orientation” is defined in advance. That is, from the viewpoint of the CNT manufacturing process, the orientation of the CNT is a direction perpendicular to the plane of the substrate 33 when the CNT is synthesized by the tip discharge radical CVD method using the plasma CVD apparatus 30 described later. means. Or, from the viewpoint of considering that CNT may not grow strictly vertically, it means the growth direction (long direction) of CNT.

Further, when the structure of the channel 7 of the present invention is viewed from another viewpoint, the CNTs constituting the bundle structure are configured to include those in which the CNTs continuously connect the source electrode 3 and the drain electrode 4. It can be said that it is desirable.
When the source electrode 3 and the drain electrode 4 are connected by one continuous CNT, there is no contact resistance between the CNTs as compared with the case where a plurality of short CNTs are connected as in the conventional example. This is because the resistance of the channel 7 is reduced. That is, from the viewpoint of obtaining a high-power FET 1, it is also important that the bundle group of CNTs includes a CNT that continuously connects the source electrode 3 and the drain electrode 4.

Returning to FIG. 2 again, the configuration of the field effect transistor 1 according to the first embodiment of the present invention will be described. The gate 8 is a saline solution, and is filled in the liquid layer so as to touch the substrate 2, the insulating resin 6, and the channel 7. In particular, for the channel 7, since the channel 7 of the present invention is not subjected to the dispersion processing as in the conventional example, the gate 8 is efficiently in the thickness direction of the channel 7 (direction perpendicular to the plane of the substrate 2) Impregnated. The gate 8 is a phosphate buffered saline (PBS or a solution obtained by adding hydrogen chloride / sodium hydroxide, etc.), potassium hydroxide, oxalate, phthalate, medium, instead of saline. Electrolytic solutions and ionic liquids such as a solution of basic phosphate and borate may be used.
The gate reference electrode 9 is a silver-silver chloride electrode configured to cover the periphery of silver with silver chloride, and is immersed in the liquid electrolyte solution of the gate 8.
When a voltage is applied to the gate reference electrode 9, a gate insulating layer 13 made of an electric double layer is formed so as to cover the outer periphery of the CNT.

Next, the structure of the channel 7 will be described with reference to FIG.
FIG. 4 is a conceptual diagram illustrating a channel structure used for a channel according to an embodiment of the prior art and the present invention.
FIG. 4A is a conceptual diagram of channels described in the prior art (for example, Patent Document 2 and Patent Document 3). FIG. 4B is a conceptual diagram of a channel as one embodiment (first embodiment) of the present invention. FIG.4 (c) is a conceptual diagram of the channel as one Embodiment (2nd Embodiment mentioned later) of this invention.
The channel shown in FIG. 4 (a) contains semiconducting CNT11, metallic CNT12, and impurities such as dispersion solvent 14, surfactant 15 and metal fine particles 16 derived from fragmentation treatment and dispersion treatment. Including. Furthermore, in the fragmentation process, cracks or the like are likely to occur on the side walls of the CNTs, so the channel shown in FIG. 4A includes the defective CNTs 17. These impurities and defective CNTs cause deterioration in conductive characteristics and switching characteristics. Furthermore, in the prior art channel, the density of CNTs is limited because CNTs are highly dispersed in the dispersion, and since the CNTs are dispersed in a random direction, the contact area with the electrode is reduced, resulting in a large size. The current cannot be controlled.

On the other hand, the channel 7 as one embodiment (first embodiment) of the present invention shown in FIG. 4B is composed of only the semiconducting CNTs 11 and the metallic CNTs 12, as shown in FIG. Does not contain impurities other than CNT. Furthermore, since the fragmentation process is unnecessary, the number of defective CNTs is reduced. Due to these effects, excellent conductive properties are exhibited. Therefore, when a liquid electrolyte is used as the gate 8, the gate 8 can be efficiently impregnated in the thickness direction of the channel 7, and the contact area between the channel 7 and the gate 8 can be increased. Further, since the channel 7 is oriented, the source electrode and the drain electrode and the channel 7 realize a good contact state at the interface, and thus the electrical resistance between the channel and the electrode is small. As described above, in the FET 1 of the present invention, in addition to the large contact area between the channel and the gate and between the channel and the electrode, the CNT having high electron mobility in the channel has a number per unit area of 1.0 ×. Since the channel 7 has a small resistance because it is formed at a high density of 10 ^{9 to} 1.0 × 10 ¹² lines / cm, it is possible to control a large ampere level current.

  On the other hand, the channel 7 of one embodiment of the present invention (second embodiment to be described later) shown in FIG. 4C is composed of only semiconductor CNTs 11 and metallic CNTs 12 as in FIG. 4B. As shown in FIG. 4A, the number of CNTs having impurities or defects other than CNTs decreases. Similarly to FIG. 4A, since the channel 7 is oriented, the source and drain electrodes and the channel 7 realize a good contact state at the interface, and therefore the electrical resistance between the channel and the electrode is small. By these actions, excellent conductive properties are exhibited. For this reason, when a liquid electrolyte is used as the gate 8, the gate 8 can efficiently impregnate in the thickness direction of the channel 7, and the contact area between the CNT and the gate 8 can be increased. Therefore, the ampere level current can be controlled in the FET 1 of the present invention.

  Here, one CNT is macroscopically straight enough, but strictly speaking, it is not a "straight line" because of bending and twisting (for example, as shown in a partially enlarged view of FIG. 6 described later). Therefore, “CNT orientation” is defined. That is, from the viewpoint of the CNT manufacturing process, the orientation of the CNT is a direction perpendicular to the plane of the substrate 33 when the CNT is synthesized by the tip discharge radical CVD method using the plasma CVD apparatus 30 described later. means. Or, from the viewpoint of considering that CNT may not grow strictly vertically, it means the growth direction (long direction) of CNT.

In the present embodiment, as will be described later, a transistor is created by transferring and fixing a bundle of CNTs grown in the vertical direction on the substrate to the substrate. As shown, a transistor in which a channel is oriented in a direction parallel to the electron (hole) moving direction can be formed. The following requirements (a) to (c) are required for a bundle of CNTs used for a channel to realize such a channel.
(A) It is desirable that the CNT used in the channel satisfy the following formula (1) using the symbols shown in FIG.
Lgate ≦ Lcnt (1)
(B) The density of the CNT used for the channel is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(C) The orientation of the bundle group of CNTs is parallel to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4.

The requirements (a) to (c) will be described below.
The requirement (a) means that the average length Lcnt of the CNT used for the channel is not less than the gate length Lgate. Although the CNTs used for the channels are macroscopically straight, the individual CNTs constituting the channel are not straight because they are bent or twisted. Therefore, the average length Lcnt of the CNT of the present invention is necessarily longer than the gate length Lgate. Therefore, it is desirable to have such a requirement in order to ensure an effective gate length Lgate of the channel 7 portion.

The requirement (b) is that the number density of bundles of CNTs used for the channel 7 is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² / cm ² . The bundle of CNTs used in the channel 7 of the present invention is synthesized by a tip discharge radical CVD method described later. With this configuration, electrons (holes) between the source electrode 3 and the drain electrode 4 are likely to form a transmission distance shortcut path, a high-conductivity channel shift path, a defective channel bypass path, and the like, which will be described later. In order to contribute to reducing the resistance value, it can be said that the drain-source current increases dramatically due to these effects.

  Furthermore, the requirement (c) is that the orientation of the CNT bundle group is parallel to a straight line forming the shortest distance between the source electrode 3 and the drain electrode 4. By satisfying this requirement, the bundle group of CNTs continuously connects between the source electrode and the drain electrode, so that the electrical resistance value of the channel can be reduced, and the FET 1 according to the present embodiment. Can control a large ampere level current.

[Production method]
Next, the manufacturing method of FET1 is demonstrated, referring FIGS.
FIG. 5 is a schematic view of a plasma CVD apparatus for synthesizing CNTs used in a field effect transistor as one embodiment according to the present invention.
The channel 7 in this embodiment is composed of CNT synthesized by a tip discharge radical CVD method (hereinafter referred to as “plasma CVD method”). The plasma CVD apparatus 30 is an apparatus for synthesizing CNTs by plasma CVD in this embodiment. As shown in FIG. 5, the plasma CVD apparatus 30 includes a chamber 31, a substrate heating unit 32, a substrate 33, a substrate holder 34, a microwave waveguide 35, and an antenna 36 extending from the microwave waveguide 35. The The chamber 31 includes a source gas introduction unit 38 that is an inlet for introducing the source gas 37 therein, and a source gas discharge unit 39 for discharging the source gas 37 to the outside.

Here, the manufacturing method of CNT using the plasma CVD apparatus 30 is demonstrated.
The source gas 37 is a hydrocarbon gas, and methane, acetylene, or the like is preferable.
First, the catalyst 40 such as iron particles is arranged on the substrate 33 at a high density. The catalyst 40 may be an alloy of cobalt and iron, or an alloy of nickel and iron. Next, plasma is generated at the tip 41 of the antenna 36 away from the substrate 33, and the plasma decomposes the source gas 37 in the plasma generation region 42, thereby synthesizing CNTs on the substrate 33.
Since this plasma CVD apparatus is designed so that the antinode of the microwave standing wave is located at the front end 41 of the antenna 36, it can be discharged with a low power of 60W. Further, since the distance d between the substrate 33 and the tip portion 41 of the antenna 36 can be freely adjusted by the substrate holder 34 that is movable up and down, plasma can be generated at a location away from the catalyst 40. For this reason, the catalyst 40 is not easily damaged by the plasma, and the active time of the catalyst 40 is extended. Therefore, the catalyst 40 is oriented as long and vertically as several mm, and the number per unit area is 1.0 × 10 ⁹ to A high-density CNT of 1.0 × 10 ¹² / cm ² can be synthesized.

By performing the synthesis of CNTs in the above-described plasma CVD method under the conditions of 690 ° C., 20 Torr, and 60 W, long CNTs can be synthesized.
FIG. 6 is a view showing an SEM (Scanning Electron Microscopy) image of CNT synthesized using the plasma CVD method as one embodiment according to the present invention. Note that the upper right photograph in FIG. 6 is a partially enlarged view of this SEM image.
It can be seen that free-standing CNT (called a forest) grown in a direction perpendicular to the substrate is synthesized. In the conventional method, the length of the CNT is at most several μm, whereas according to the plasma CVD method, it is found that the CNT grows to a thickness of about 1 mm as shown in FIG. And from the partial enlarged view of the CNT in the upper right of FIG. 6, each CNT extends in the direction perpendicular to the substrate.

  FIG. 7 is a diagram showing a TEM (Transmission Electron Microscopy) image of CNT synthesized using a plasma CVD method as an embodiment according to the present invention. From FIG. 7, a plurality of CNTs form a bundle structure in a bundle.

  The composition ratio of the long CNT synthesized by the above plasma CVD method is 82% for single-walled CNT and 18% for double-walled CNT. The average diameter of single-walled CNTs was 2.2 nm, and the average diameter of double-walled CNTs was 3.7 nm.

Next, the manufacturing method of FET1 which concerns on one Embodiment of this invention is demonstrated, referring FIG.8, FIG.9 and FIG.10.
FIG. 8 is a flowchart showing a manufacturing procedure of the method for manufacturing the field effect transistor 1 according to the first embodiment of the present invention.
FIG. 9 is a flowchart showing a procedure for manufacturing a channel layer used in the FET 1 according to the embodiment of the present invention. FIG. 10 shows a schematic diagram of a method of manufacturing the FET 1 according to one embodiment of the present invention. 10A to 10D are views of the FET 1 viewed from above, and FIGS. 10A to 10E are views of the FET 1 viewed from the side. FIGS. 10A to 10D correspond to FIGS. 10A to 10E, respectively. Further, step S12 in FIG. 8 is shown in FIGS. 10A and 10A, step S13 in FIG. 8 is shown in FIGS. 10B and 10B, and step S14 in FIG. 8, steps S15 and S16 in FIG. 8 correspond to FIGS. 10 (d) and 10 (d ′), and step S17 in FIG. 8 corresponds to FIG. 10 (e ′).

The method of manufacturing the field effect transistor according to the present invention will be described in detail later. First, differences from the prior art will be briefly described with reference to FIGS. 9 and 17.
Compared with the manufacturing method of Patent Document 2 shown in FIG. 17, the manufacturing method of the channel layer of FET 1 according to the first embodiment of the present invention shown in FIG. There is no need for steps S104 to S107, which cause defects on the CNT side walls. Furthermore, since a bundle of vertically aligned CNTs in which a channel made of CNTs is grown on the substrate may be transferred to the transistor substrate, the number of steps, time, and cost in manufacturing the transistor are greatly reduced, and the transistor is very simple. Can be provided.

Hereinafter, the procedure for creating the FET 1 according to the first embodiment of the present invention will be described with reference to FIG.
The creation of the FET 1 according to the first embodiment of the present invention is executed by the following procedure.

  In step S11 shown in FIG. 8 (corresponding to steps S01 to S08 in FIG. 9), the plasma CVD apparatus 30 synthesizes CNTs having a length of about 3 to 5 times the gate length Lgate.

  In step S12, the CNT synthesized in step 11 is peeled off from the substrate 33 so as to be about twice as long as the gate length Lgate, and an insulating resin (not shown) is used on the substrate 2 made of glass. And fix. This fixed CNT is the channel 7 (see FIGS. 10A and 10A).

  In step S13, the source electrode 3 and the drain electrode 4 configured by covering titanium with gold are deposited so that the distance between the source electrode 3 and the drain electrode 4 (that is, the gate length) is 1 mm. (Refer to Drawing 10 (b) and (b ')).

  In step S14, the CNT channel 7, the source electrode 3 and the drain electrode 4 prepared in step S13 are transferred onto another glass substrate 2 (see FIGS. 10C and 10C).

  In step S15, the wiring 10 is electrically joined to the source electrode 3 and the drain electrode 4 with a conductive resin 5 (conductive epoxy resin or silver paste), respectively (see FIGS. 10D and 10D).

  In step S16, the source electrode 3, the drain electrode 4 and the wiring 10 are covered with the insulating resin 6 (insulating epoxy resin) to prevent direct exposure to the gate 8 made of a liquid electrolyte (FIG. 10 (d) and (See (d ′)).

  In step S17, the wall 20 made of the insulating resin 6 is provided to form a liquid tank in which the liquid electrolyte can be stored, and the gate reference electrode 9 is immersed in the gate 8 made of the liquid electrolyte (see FIG. 10 (e ')).

[Operation]
Next, the operation of the FET 1 created using the CNT synthesized by the plasma CVD method as described above will be described.
When a voltage is applied to the gate reference electrode 9 from a state in which the voltage is zero, a gate insulating layer 13 of an electric double layer is formed at the interface between each CNT of the channel 7 and the liquid electrolyte of the gate 8. Since the gate 8 is a liquid electrolyte, it has good adhesion to the CNTs, and an electric field can be applied to the channel 7 easily and uniformly, so that the gate insulating layer 13 can be formed at high speed.
Since an electric field acts on the CNT channel 7 via the gate insulating layer 13, if a voltage is applied between the source electrode 3 and the drain electrode 4 at this time, the source electrode 3 and the drain electrode 4 Current flows between the two.

FIG. 11 is a diagram showing a performance evaluation of a field effect transistor as an embodiment according to the present invention.
Voltage between gate reference electrode 9 and source electrode 3 (hereinafter referred to as “gate reference electrode-source electrode voltage”) V _{GS is set} to 0V, 0.5V, 1.0V, 1.5V, 2.0V The current flowing between the drain electrode 4 and the source electrode 3 (hereinafter referred to as “drain”) when a voltage V _DS between the drain electrode 4 and the source electrode 3 (hereinafter referred to as “drain-source electrode voltage”) V _DS is applied. (Referred to as “source-source current”) _IDS is shown in FIG.
There is no significant difference between the drain-source electrode current I _DS between the gate reference electrode-source electrode voltage V _GS = 0 V and the gate reference electrode-source electrode voltage V _GS = 0.5 V. This is presumably because the electric double layer is not sufficiently formed in the channel 7 when the gate reference electrode-source electrode voltage V _GS is in the range of 0.0 V to 0.5 V.
Thereafter, when the gate reference electrode-source electrode voltage V _GS becomes 1.0 V or more, FIG. 11 shows that the drain-source electrode current I _DS flows better as the gate reference electrode-source electrode voltage V _GS increases. ing. That is, when the gate reference electrode-source electrode voltage V _GS is 0.5 V or higher, the gate reference electrode-source electrode voltage V _GS increases in the order of 0.5 V, 1.0 V, 1.5 V, and 2.0 V. The resistance (V _DS / I _DS ) between the source electrode 3 and the drain electrode 4 decreases in the order of 3.1Ω, 1.8Ω, 1.2Ω, and 1.0Ω, and the FET 1 of the present invention functions as a transistor. I understand that.
Note that the on-resistance value of the FET 1 when the gate reference electrode-source electrode voltage V _GS is 0.5 V, 1.0 V, 1.5 V, and 2.0 V is the actual gate width Wgate of the FET 1 used for the measurement, When converted into volume resistivity in consideration of thickness and gate length Lgate, 1.2 × 10 ⁻³ Ω · cm, 7.0 × 10 ⁻⁴ Ω · cm, 4.7 × 10 ⁻⁴ Ω · cm, 4 0.0 × 10 ⁻⁴ Ω · cm.
As described above, in the FET 1 of the present invention, the drain-source electrode current I _DS = 2 at the drain-source electrode voltage V _DS = 2.0 V and the gate reference electrode-source electrode voltage V _GS = 2.0 V. It is possible to control a current of 0.0 A / mm, that is, a large current of an ampere level.

As described above, the FET 1 of the present invention using the CNT synthesized by the plasma CVD method for the channel 7 has the following characteristics.
(1) Since the number of CNTs per unit area is as high as 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ^2, the number of channels per unit area of the entire FET 1, source and gate is dramatically increased. The current value and the current density can be greatly improved.
(2) Since each CNT is as long as several millimeters, it is possible to connect the drain-source electrodes by continuous CNTs. For this reason, the channel resistance can be greatly reduced by the amount of no contact resistance compared to the case where a plurality of short CNTs are connected.
(3) The channel 7 forms a plurality of bundle structures in which a plurality of CNTs are bundled, and the electron (hole) transport path is expected to be optimized in each bundle.
(4) Dispersion treatment is not performed on the channel 7 and a liquid electrolyte is used for the gate 8, so that the gate 8 can be efficiently impregnated in the thickness direction of the channel 7 and the contact area between the CNT and the gate 8 can be increased. it can. For this reason, an electric double layer is formed on the surface of each CNT constituting the channel 7, and an ampere level large current can be controlled between the drain and source electrodes, and an FET capable of controlling this can be provided. it can.

FIG. 12 is a conceptual diagram showing optimization of an electron (hole) transport path by a CNT bundle structure of a field effect transistor as one embodiment according to the present invention.
By forming a gate with an electric double layer around the bundle structure of CNTs, the following effects appear.
1. Transmission distance shortcut path The CNT of the present invention has a high density of 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pcs / cm ² per unit area. In such a high-density CNT bundle structure, there are many contacts where semiconducting CNTs contact each other. Electrons (holes) select a path that has the shortest transport distance from the source electrode to the drain electrode every time the contact is branched, and as a result, a shortcut path is formed.
2. High-conducting channel shift path In the bundle structure of high-density CNTs as described above, there are many contacts at which semiconducting CNTs and metallic CNTs are in contact. A path is formed in which electrons (holes) transported from the semiconducting CNTs by the electric double layer formed in the channel 7 are shifted to a metallic channel having higher conductivity at a certain contact point.
3. Defect channel detour path By adopting a high-density CNT bundle structure as described above, even if there is a defect CNT with a break point or the like that cannot originally transport electrons (holes) In the branch by the contact point between the CNTs, a path detouring to the CNT having no defect is formed.

In the FET 1 of the present invention, the above-mentioned transmission distance shortcut path, high-conductivity channel shift path, and defective channel bypass path contribute to reduce the resistance value of the current of the entire channel. It can be said that it will increase dramatically.
As described above, by using the CNT synthesized by the plasma CVD method for the channel 7, it is possible to control a large ampere level current between the drain and source electrodes, and it is possible to create an FET capable of controlling this.

As described above, the field effect transistor 1 according to this embodiment includes the source electrode 3 and the drain electrode 4, and the channel 7 made of a plurality of long CNTs provided between the source electrode 3 and the drain electrode 4. The CNT bundle group includes the CNTs that continuously connect the source electrode 3 and the drain electrode 4.
For example, the channel 7 of the field effect transistor 1 of the present invention has a volume resistivity of 1.3 × 10 ⁻³ Ω · cm or less when the voltage between the gate and the drain electrode is zero. Further, the bundle group of CNTs constituting the channel 7 of the present invention is oriented in parallel to the straight line forming the shortest distance between the source electrode and the drain electrode, and the average length of the bundle group of carbon nanotubes. (Lcnt) is greater than or equal to the gate length (Lgate).
And since it has such a structure, even when the field effect transistor 1 is turned on, the volume resistivity is small, and a large ampere level current can be controlled. Further, since the gate is a liquid electrolyte, an electric double layer is easily generated on the surface of the liquid electrolyte and the channel 7 even at a low voltage, and a large ampere level current can be controlled with low power consumption. Furthermore, since the gate is a liquid electrolyte, the adhesion between the surface of the channel 7 made of CNT and the liquid electrolyte is good, high electron (hole) mobility is brought about, and a highly responsive transistor is realized. can do.

  In short, in this embodiment, the field effect transistor is formed from a long and high-density bundle of CNTs including a gate 8 made of a liquid electrolyte and CNTs that continuously connect the source electrode 3 and the drain electrode 4. Therefore, high output, low power consumption, and high-speed response are realized.

  A channel made of CNT by applying a relatively large voltage between the source electrode 3 and the drain electrode 4 between step S15 and step S16 in the manufacturing procedure of the FET 1 according to the embodiment of the present invention described above. It is possible to appropriately perform the initialization process for selectively removing the metallic CNTs and controlling the ratio of the metallic CNTs in the channel 7 by controlling a relatively large current.

[Second Embodiment]
Hereinafter, a field effect transistor 2 (hereinafter referred to as “FET2” as necessary) according to a second embodiment of the present invention will be described with reference to the drawings as appropriate.

[Constitution]
The FET 2 according to the second embodiment of the present invention has the same elements as the FET 1 according to the first embodiment, that is, the substrate 2, the source electrode 3, the drain electrode 4, the conductive resin 5, the insulating resin 6, the channel 7, and the gate. 8, a gate reference electrode 9, and a wiring 10. The same reference numerals as those in the first embodiment are assumed to have the same configuration, and the description thereof is omitted.
FIG. 13 is a schematic diagram of a configuration of the field effect transistor 2 according to the second embodiment. The FET 2 according to the second embodiment is different in that the bundle group of CNT used for the channel 27 is different from the orientation of the bundle group of CNT used for the channel 7 of the FET 1 according to the first embodiment.
Here, the orientation of the channel of the FET 2 according to the second embodiment will be described.

FIG. 14A is a conceptual diagram illustrating the orientation and geometric requirements of CNTs arranged in a direction orthogonal to the electron (hole) transport direction as a channel.
As shown in FIG. 14A, in the CNT bundle group used for the channel 27 of the FET 2 according to the second embodiment, the extending direction of the CNT is orthogonal to a straight line that is the shortest distance between the source electrode 3 and the drain electrode 4. It is formed from CNTs having such an orientation.
Since it can be said that the direction of the straight line connecting the source electrode 3 and the drain electrode 4 is almost the electron (hole) transport direction, the CNT in FIG. It can be said that they are arranged with an orthogonal orientation.
Further, the CNT bundle group used for the channel 27 of the FET 2 according to the second embodiment is a long and high-density CNT bundle group synthesized by the plasma CVD method, as in the first embodiment. For this reason, the conductivity is higher than that of the channel using the conventional dispersion (FIG. 4A). In addition, the CNT according to the second embodiment shown in FIG. 4C can reduce the number of conductive paths formed by the metallic CNT compared to the first embodiment of FIG. Can be suppressed.

Moreover, when the structure of the channel 27 of this embodiment is seen from another viewpoint, it can be said that the CNT used for the channel 27 satisfies the following requirements (a) to (c).
(A) The CNT used in the channel 27 preferably satisfies the following formula (1).
Wgate ≦ Lcnt (1)
The average length Lcnt and gate width Wgate of the CNTs constituting the bundle group of CNTs are as conceptually shown in FIG.
(B) The number density of the bundle group of CNT used for the channel 27 is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(C) The orientation of the bundle group of CNTs is perpendicular to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4.

The requirements (a) to (c) will be described below.
The requirement (a) means that the average length Lcnt of the CNTs constituting the CNT bundle group used for the channel 27 is a long CNT longer than the gate width Wgate. Strictly speaking, the individual CNTs constituting the channel are not straight because there are bends and twists. Accordingly, the average length Lcnt of the CNTs constituting the CNT bundle group of the present invention is necessarily longer than the gate width Wgate. Therefore, it is desirable to have such a requirement in order to ensure an effective channel width (gate width) of the channel 27 portion.

The requirement (b) is that the number density of CNTs used for the channel 27 is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² / cm ² . The CNT used in the channel 27 of the present invention is synthesized by a tip discharge radical CVD method described later. With this configuration, electrons (holes) transported between the source electrode 3 and the drain electrode 4 move between the CNTs adjacent to each other at a high density, and therefore between the source electrode 3 and the drain electrode 4. Since there are fewer paths for metallic CNT, leakage current can be suppressed.

Furthermore, requirement (c) is a requirement regarding the orientation of the bundle group of CNTs.
By making the orientation of the bundle group of CNTs orthogonal to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4, metallic CNTs are continuously formed between the source electrode 3 and the drain electrode 4. Connection can be avoided as much as possible, and leakage current can be suppressed from flowing.

[Production method]
Next, the manufacturing method of the FET 2 according to the second embodiment is the same as the manufacturing method of the FET 1 according to the first embodiment, but is different in that the orientation of the CNT used for the channel 27 to be arranged is different. That is, the channel 27 of the FET 2 according to the second embodiment is formed of a bundle of CNTs having an orientation such that the extending direction of the CNTs is orthogonal to a straight line that is the shortest distance between the source electrode 3 and the drain electrode 4.

[Operation]
Next, the operation of the FET 2 according to the second embodiment will be described with reference to FIGS. 15 and 16.
FIG. 15 is a conceptual diagram showing formation of an electron (hole) transport path by a CNT bundle structure of a field effect transistor as an embodiment according to the present invention.
In the transistor according to an embodiment of the present invention, electrons (holes) move between the source electrode 3 and the drain electrode 4 while moving on the CNT side wall while moving to adjacent CNTs. Since the channel 27 is oriented in the gate width direction, there are fewer paths due to only the metallic CNT 12 between the source electrode 3 and the drain electrode 4 than in the case where the channel 27 is oriented in the gate length direction. Therefore, when no voltage is applied between the gate reference electrode 9 and the source electrode 3, as shown in FIG. 15A, the electric double layer is not formed, and the leakage current is suppressed.

  On the other hand, when a voltage is applied between the gate reference electrode 9 and the source electrode 3, the electric double layer 19 is formed at the interface with the gate 8 made of a liquid electrolyte all together and uniformly with respect to each CNT channel 27. The By applying an electric field to the CNT channel 27 through the electric double layer 19, it is possible to control the current flowing between the source electrode 3 and the drain electrode 4. As shown in FIG. 15B, an electric double layer 19 is formed around the surface of the semiconducting CNT 11, and electrons (holes) are transported between the source electrode 3 and the drain electrode 4 while moving to adjacent CNTs. The With these effects, a switching action is realized and high output control can be performed.

FIG. 16 is a diagram showing a performance evaluation of a field effect transistor as an embodiment according to the present invention.
Voltage between gate 8 and source electrode 3 (hereinafter referred to as “gate reference electrode-source electrode voltage”) V _{GS is set} to 0.0 V, 0.5 V, 1.0 V, 1.5 V, and 2.0 V The voltage between the drain electrode 4 and the source electrode 3 (hereinafter referred to as “drain-source electrode voltage”) V _DS when the voltage V _DS is applied (hereinafter referred to as the current flowing between the drain electrode 4 and the source electrode 3). It referred to as - "drain source electrode between current") I _DS is shown in Figure 16.
There is no significant difference between the drain-source electrode current I _DS between the gate reference electrode-source electrode voltage V _GS = 0.0 V and the gate reference electrode-source electrode voltage V _GS = 0.5 V. This is presumably because the electric double layer is not sufficiently formed in the channel 27 when the gate reference electrode-source electrode voltage V _GS is in the range of 0.0 V to 0.5 V.
Thereafter, it can be seen from FIG. 16 that when the gate reference electrode-source electrode voltage V _GS becomes 1.0 V or more, the drain-source electrode current I _DS flows better as the gate reference electrode-source electrode voltage V _GS increases. . That is, when the gate reference electrode-source electrode voltage V _GS is 0.5 V or higher, the gate reference electrode-source electrode voltage V _GS increases in the order of 0.5 V, 1.0 V, 1.5 V, and 2.0 V. The resistance (V _DS / I _DS ) between the source electrode 3 and the drain electrode 4 decreases in the order of 2.0 × 10 ² Ω, 1.0 × 10 ² Ω, 55.5Ω, 21.1Ω, It can be seen that the FET 2 of the embodiment functions as a transistor.
Note that the on-resistance value of the FET 2 when the gate reference electrode-source electrode voltage V _GS is 0.5 V, 1.0 V, 1.5 V, and 2.0 V is the actual gate width Wgate of the FET 2 used for the measurement, When converted to volume resistivity in consideration of thickness and gate length Lgate, 7.8 × 10 ⁻² , 4.0 × 10 ⁻² Ω · cm, 2.2 × 10 ⁻² Ω · cm, 8.0 × 10 ⁻³ Ω · cm.
As described above, in the FET 2 of the second embodiment, when the drain-source electrode voltage V _DS = 2.0 V and the gate reference electrode-source electrode voltage V _GS = 2.0 V, the drain-source electrode current I _DS = 95 mA / mm current, that is, a current of 0.1 ampere level can be controlled.
In the second embodiment, when no voltage is applied to the gate reference electrode 9, even if a voltage is applied between the source electrode 3 and the drain electrode 4, almost no current (so-called leak current) is generated in the channel 27. It does not flow (drain-source electrode voltage V _DS = 2.0 V, gate reference electrode-source electrode voltage V _GS = 2.0 V, drain-source electrode current I _DS = about 10 mA or less). This is because in the FET 1 of the present invention, the CNTs of the channel 27 are arranged with an orientation in the gate width direction.
As described above, the FET 2 of the second embodiment can control a current of 0.1 ampere level while suppressing the leakage current.

  As described above, in the second embodiment, similarly to the first embodiment, the field effect transistor 2 includes the source electrode 3, the drain electrode 4, the gate 8, and the source electrode 3 and the drain electrode 4. Since the CNTs used for the channels 27 are self-standing CNTs (CNTs that have not been processed using a dispersion liquid), the dispersion is performed. Since no liquid is used and there are no impurities, the conductive characteristics are good, and a larger current can be controlled than in the channel 27 using a dispersion liquid. Furthermore, since it is arranged so as to be orthogonal to the straight line that is the shortest distance between the source electrode 3 and the drain electrode 4, the metallic CNT is not continuously connected between the source electrode 3 and the drain electrode 4, It has an effect that the leakage current can be further suppressed.

  In short, in the second embodiment, self-standing CNTs (CNTs that have not been processed using the dispersion liquid) are arranged so as to be orthogonal to the straight line that is the shortest distance between the source electrode 3 and the drain electrode 4. Thus, a field effect transistor capable of controlling a current of 0.1 ampere level and suppressing a leakage current is realized.

[Third embodiment]
A field effect transistor according to a third embodiment of the present invention will be described.
The third embodiment of the present invention is further different from the FET 1 according to the first embodiment and the FET 2 according to the second embodiment in the orientation of CNTs serving as channels.
That is, although not shown, the channel of the field effect transistor of the third embodiment is parallel to the straight line in which the orientation of the bundle group of CNTs is the shortest distance between the source electrode 3 and the drain electrode 4 (first embodiment). ) Or orthogonal (second embodiment), but has an intermediate orientation between them.
For this reason, if the CNT bundle group has an intermediate orientation that is close to the parallel direction, the ampere level current can be controlled by the field effect transistor, while the orientation is set to the orthogonal direction. When approaching, current control of 0.1 ampere level and low leakage current can be achieved.
Therefore, the orientation of the CNT serving as a channel may be appropriately selected according to the specifications required for the field effect transistor.
In addition, regarding the manufacturing method of the field effect transistor in this case, in step S12 of FIG. 9, the CNT bundle group cut shape and the fixing direction on the substrate 2 are appropriately set so as to achieve the desired orientation. Adjustments can be made.
As described above, in the field effect transistor according to the third embodiment, it is possible to provide a configuration specialized for the current value and a configuration specialized for the switching action by simply changing the orientation of the channel CNT. it can.

  In the manufacturing procedure of each embodiment of the present invention described above, a relatively large voltage is applied between the source electrode 3 and the drain electrode 4 between the step S15 and the step S16, and the channel 27 made of CNT is applied. It is possible to appropriately perform the initializing process for selectively removing the metallic CNTs and reducing the ratio of the metallic CNTs in the channel 27 by flowing a relatively large current.

  Furthermore, it is possible to selectively remove metallic CNTs and use only semiconducting CNTs as the channel 27. In this case, it is necessary to initialize such that a voltage large enough to burn all the metallic CNTs is applied. Leakage current can be suppressed by using CNTs made only of this semiconducting CNT for the channel 27.

  As mentioned above, although embodiment of this invention was described, this embodiment is only an illustration and does not limit the technical scope of this invention. The present invention can take other various embodiments, and various modifications such as omission and replacement can be made without departing from the gist of the present invention. These embodiments and modifications thereof are included in the scope and gist of the invention described in this specification and the like, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Field effect transistor 2 ... Substrate 3 ... Source electrode 4 ... Drain electrode 5 ... Conductive resin 6 ... Insulating resin 7 ... Channel 8 ... Gate 9. ..Gate reference electrode 10 ... wiring 11 ... semiconductor CNT
12 ... Metal CNT
13 ... Gate insulating layer 14 ... Dispersing solvent 15 ... Surfactant 16 ... Metal fine particle 17 ... Defective CNT
18 ... Electron (hole) moving direction 19 ... Electric double layer 20 ... Wall 30 ... Plasma CVD apparatus 31 ... Chamber 32 ... Substrate heating unit 33 ... Substrate 34 ..Substrate holder 35 ... microwave waveguide 36 ... antenna 37 ... source gas 38 ... source gas introduction part 39 ... source gas discharge part 40 ... catalyst 41 ... tip part 42 ... Plasma generation region

Claims (5)

A method of manufacturing a semiconductor device comprising a source electrode, a drain electrode, a gate, and a channel provided between the source electrode and the drain electrode,
A bundle of carbon nanotubes having a density of 1.0 × 10 ⁹ pieces / cm ² or more is oriented in a predetermined direction with respect to a straight line forming the shortest distance between the source electrode and the drain electrode. Being disposed on a substrate as the channel;
Forming the source electrode, the drain electrode, and the gate on the substrate;
Tona is,
The carbon nanotube bundle group is manufactured so as to satisfy the following requirements (d) to (f) .
(D) The bundle of carbon nanotubes satisfies the following formula (2):
Wgate ≦ Lcnt (2)
In the above formula (2),
Wgate indicates the width of the gate;
Lcnt is a number indicating the average length of carbon nanotubes constituting the bundle group of carbon nanotubes.
(E) The density of the carbon nanotube bundle group is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(F) The orientation of the bundle of carbon nanotubes is orthogonal to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4. The method of manufacturing a semiconductor device according to claim 1, wherein the gate is manufactured to be made of a liquid electrolyte. In preparing a bundle group of the carbon nanotube manufacturing method of the tip discharge type radical containing CVD method to prepare the bundle group of carbon nanotubes by step, the semiconductor device according to claim 1 or 2, characterized . A semiconductor device comprising a source electrode, a drain electrode, a gate, and a channel provided between the source electrode and the drain electrode,
The bundle of carbon nanotubes having a density of 1.0 × 10 ⁹ pieces / cm ² or more is oriented in a predetermined direction with respect to a straight line forming the shortest distance between the source electrode and the drain electrode. Placed on the substrate as a channel,
On the substrate, the source electrode, the drain electrode, and the gate are formed,
The bundle of carbon nanotubes satisfies the following requirements (d) to (f):
(D) The bundle of carbon nanotubes satisfies the following formula (2):
Wgate ≦ Lcnt (2)
In the above formula (2),
Wgate indicates the width of the gate;
Lcnt is a number indicating the average length of the carbon nanotubes constituting the bundle of carbon nanotubes.
(E) The density of the carbon nanotube bundle group is 1.0 × 10 ^{9 to} 1.0 × 10 ¹² pieces / cm ² .
(F) The orientation of the bundle of carbon nanotubes is orthogonal to the straight line forming the shortest distance between the source electrode 3 and the drain electrode 4. The semiconductor device according to claim 4 , wherein the gate is made of a liquid electrolyte.