JP6204131B2

JP6204131B2 - Light emitting device and manufacturing method thereof

Info

Publication number: JP6204131B2
Application number: JP2013196716A
Authority: JP
Inventors: 孝治松本
Original assignee: Stanley Electric Co Ltd
Current assignee: Stanley Electric Co Ltd
Priority date: 2013-09-24
Filing date: 2013-09-24
Publication date: 2017-09-27
Anticipated expiration: 2033-09-24
Also published as: JP2015065204A

Description

本発明は、発光素子及びその製造方法に関し、特に、成長基板上に成長した半導体発光層を支持基板に貼り合わせた後、成長基板を除去して形成される発光ダイオード（ＬＥＤ：Light Emitting Diode）素子及びその製造方法に関する。 The present invention relates to a light emitting device and a method for manufacturing the same, and more particularly, a light emitting diode (LED) formed by bonding a semiconductor light emitting layer grown on a growth substrate to a support substrate and then removing the growth substrate. The present invention relates to an element and a manufacturing method thereof.

近年、成長基板（又は仮基板）上にＭＯＣＶＤ（Metal-Organic Chemical Vapor Deposition）法などの気相成長法により成長した半導体発光積層体を、導電性の支持基板に貼り合わせ、その後、成長基板を除去した構成のＬＥＤ（メタルボンディング構造又はＭＢ構造ともいう）が用いられている。例えば、特許文献１には、成長基板を除去した構成のＬＥＤ素子であって、活性層よりも光取り出し面側の半導体層内に電極が埋設されているものが開示されている。 In recent years, a semiconductor light-emitting laminate that has been grown on a growth substrate (or temporary substrate) by a vapor phase growth method such as MOCVD (Metal-Organic Chemical Vapor Deposition) is bonded to a conductive support substrate, and then the growth substrate is attached. A removed LED (also referred to as a metal bonding structure or MB structure) is used. For example, Patent Document 1 discloses an LED element having a structure in which a growth substrate is removed, in which an electrode is embedded in a semiconductor layer closer to the light extraction surface than the active layer.

特表２０１０−５２５５８５Special table 2010-525585

しかしながら、上記したような発光素子では、導電性の成長基板上に作製されたＬＥＤに比べると、半導体層の膜厚がチップサイズに比べ薄いため、水平方向（面内方向）に電流が拡散しにくく電流の集中が生じやすい。特に、特許文献１に開示されているような構成のＬＥＤ素子においては、活性層よりも光取り出し面側の半導体層内に埋設されている電極の周囲に電流が集中し、ＬＥＤ素子の発光効率の低下や信頼性の低下が発生する。 However, in the light emitting element as described above, the current is diffused in the horizontal direction (in-plane direction) because the film thickness of the semiconductor layer is thinner than the chip size as compared with the LED fabricated on the conductive growth substrate. Difficult to concentrate current. In particular, in an LED element having a configuration as disclosed in Patent Document 1, current concentrates around an electrode embedded in a semiconductor layer closer to the light extraction surface than the active layer, and the luminous efficiency of the LED element. Decrease in reliability and reliability.

本発明は、上述した点に鑑みてなされたものであり、面内の電流拡散が良好になされ、発光効率及び信頼性が高い高性能な発光素子及びその製造方法を提供することにある。 The present invention has been made in view of the above-described points, and an object thereof is to provide a high-performance light-emitting element having good in-plane current diffusion, high luminous efficiency and high reliability, and a method for manufacturing the same.

本発明の発光素子は、第１の半導体層、活性層及び当該第１の半導体層とは反対の導電型の第２の半導体層が順次積層された半導体構造層を有し、当該第１の半導体層の表面を光取り出し面とする発光素子であって、当該第２の半導体層側から当該第２の半導体層及び当該活性層を貫通し、当該第１の半導体層内に達する溝と、当該溝から露出している当該第２の半導体層及び当該活性層を覆う絶縁層と、当該溝の底部から露出している当該第１の半導体層に接して形成された第１のオーミック電極と、当該第２の半導体層の表面に形成されている第２のオーミック電極と、有し、当該第１の半導体層は、当該オーミック電極に接して当該第１の半導体層内に部分的に形成され、かつ当該第１の半導体層の他の部分よりも電気抵抗率の低い第１の低抵抗領域を含んでいることを特徴とする。 The light-emitting element of the present invention includes a semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked. A light-emitting element having a surface of the semiconductor layer as a light extraction surface, a groove penetrating the second semiconductor layer and the active layer from the second semiconductor layer side and reaching the first semiconductor layer; An insulating layer covering the second semiconductor layer and the active layer exposed from the trench; a first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the trench; A second ohmic electrode formed on the surface of the second semiconductor layer, and the first semiconductor layer is partially formed in the first semiconductor layer in contact with the ohmic electrode And having a lower electrical resistivity than other portions of the first semiconductor layer. Wherein the of containing the low-resistance region.

また、本発明の発光素子の製造方法は、第１の基板上に第１の半導体層、活性層及び当該第１の半導体層とは反対導電型の第２の半導体層が順次積層された半導体構造層を形成するステップと、当該第２の半導体層から当該第２の半導体層及び当該活性層を貫通して当該第１の半導体層内に達する溝を形成するステップと、当該溝から露出している当該第２の半導体層及び当該活性層を覆う絶縁層を形成するステップと、当該溝の底部において当該絶縁層に当該第１の半導体層を露出させる開口部を形成し、当該開口部に当該第１の半導体層に接続された第１のオーミック電極を形成するステップと、当該第２の半導体層上に第２のオーミック電極を形成する工程と、当該第１の半導体層にイオン注入を行って当該第１の半導体層内の当該第１のオーミック電極に接する領域に当該第１の半導体層の他の部分よりも電気抵抗率の低い低抵抗領域を形成するステップと、を含むことを特徴とする。 In the method for manufacturing a light-emitting element according to the present invention, a semiconductor in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked on a first substrate. Forming a structural layer; forming a groove extending from the second semiconductor layer through the second semiconductor layer and the active layer into the first semiconductor layer; and exposing from the groove Forming an insulating layer covering the second semiconductor layer and the active layer, and forming an opening exposing the first semiconductor layer in the insulating layer at the bottom of the groove, Forming a first ohmic electrode connected to the first semiconductor layer; forming a second ohmic electrode on the second semiconductor layer; and implanting ions into the first semiconductor layer. Go in the first semiconductor layer in the Characterized in that it comprises forming a low resistance region having low electrical resistivity than the rest of the the region in contact with the first ohmic electrode and the first semiconductor layer.

本発明の実施例１である発光素子の断面図である。It is sectional drawing of the light emitting element which is Example 1 of this invention. 図２（ａ）−（ｅ）は図１に示す発光素子の各製造工程を示す断面図である。2A to 2E are cross-sectional views showing respective manufacturing steps of the light emitting device shown in FIG. 本発明の実施例２である発光素子の断面図である。It is sectional drawing of the light emitting element which is Example 2 of this invention. 図４（ａ）及び（ｂ）は上記実施例１の変形例である発光素子の断面図である。4A and 4B are cross-sectional views of light-emitting elements that are modifications of the first embodiment. 図５（ａ）及び（ｂ）は上記実施例２の変形例である発光素子の断面図である。5A and 5B are cross-sectional views of light-emitting elements that are modifications of the second embodiment.

以下に説明する実施例においては、説明及び理解の容易さのため、半導体構造層が第１の半導体層、発光層及び第２の半導体層からなる場合について説明するが、第１の半導体層及び／又は第２の半導体層、並びに発光層はそれぞれ複数の層から構成されていてもよい。例えば、当該半導体層には、キャリア注入層、キャリアオーバーフロー防止のための障壁層、電流拡散層、オーミック接触性向上のためのコンタクト層、バッファ層などが含まれていてもよい。また、第１の半導体層及び第２の半導体層の導電型はそれぞれ下記実施例とは反対の導電型であってもよい。 In the examples described below, the case where the semiconductor structure layer is composed of a first semiconductor layer, a light emitting layer, and a second semiconductor layer will be described for ease of explanation and understanding. Each of the second semiconductor layer and the light emitting layer may be composed of a plurality of layers. For example, the semiconductor layer may include a carrier injection layer, a barrier layer for preventing carrier overflow, a current diffusion layer, a contact layer for improving ohmic contact, a buffer layer, and the like. Further, the conductivity types of the first semiconductor layer and the second semiconductor layer may be opposite to those of the following embodiments.

以下においては、本発明の好適な実施例について説明するが、これらを適宜改変し、組合せてもよい。また、以下の説明及び添付図面において、実質的に同一又は等価な部分には同一の参照符を付して説明する。 In the following, preferred embodiments of the present invention will be described, but these may be appropriately modified and combined. In the following description and the accompanying drawings, substantially the same or equivalent parts will be described with the same reference numerals.

図１は、本発明の実施例１である発光素子１０の断面図である。図１においては、発光素子１０内の電極間に流れる電流を一点鎖線矢印で示している。発光素子１０は、発光素子構造体２０と支持体３０とが接合層３５を介して接合された構造を有するＧａＮ系（Ａｌ_xＩｎ_yＧａ_1-x-yＮ（０≦ｘ≦１、０≦ｙ≦１））の発光ダイオード（ＬＥＤ）である。 FIG. 1 is a cross-sectional view of a light-emitting element 10 that is Embodiment 1 of the present invention. In FIG. 1, the current flowing between the electrodes in the light emitting element 10 is indicated by a one-dot chain arrow. The light-emitting element 10 includes a GaN-based (Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y) having a structure in which the light-emitting element structure 20 and the support 30 are bonded via a bonding layer 35. ≦ 1)) light emitting diode (LED).

より詳細には、発光素子構造体（以下、単に素子構造体ともいう）２０は、第１の導電型の第１の半導体層１１と、活性層１３と、第１の導電型とは反対導電型の第２の導電型の第２の半導体層１５とが積層されてなる発光機能層である半導体構造層１７を有する。本実施例においては、第１の半導体層１１がｎ型半導体層であり、第２の半導体層１５がｐ型半導体層である場合を例に説明する。 More specifically, the light-emitting element structure (hereinafter, also simply referred to as an element structure) 20 has a first conductivity type first semiconductor layer 11, an active layer 13, and a conductivity opposite to the first conductivity type. The semiconductor structure layer 17 is a light emitting functional layer in which a second semiconductor layer 15 of a second conductivity type is stacked. In this embodiment, a case where the first semiconductor layer 11 is an n-type semiconductor layer and the second semiconductor layer 15 is a p-type semiconductor layer will be described as an example.

第１の半導体層１１は、Ｓｉのようなｎ型ドーパントが添加されたｎ型半導体層を含む層である。活性層１３は、ＧａＮの層とＩｎ_xＧａ_1-xＮ（０≦ｘ≦１、０≦ｙ≦１）の層が繰り返し積層されることで構成された多重量子井戸構造を有する。第２の半導体層１５は、Ｍｇのようなｐ型ドーパントが添加されたｐ型半導体層である。第１の半導体層１１の表面１１Ｓ（すなわち、半導体構造層１７の上面）が光取り出し面として機能する。 The first semiconductor layer 11 is a layer including an n-type semiconductor layer to which an n-type dopant such as Si is added. The active layer 13 has a multiple quantum well structure configured by repeatedly laminating a GaN layer and an In _x Ga _1-x N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) layer. The second semiconductor layer 15 is a p-type semiconductor layer to which a p-type dopant such as Mg is added. The surface 11S of the first semiconductor layer 11 (that is, the upper surface of the semiconductor structure layer 17) functions as a light extraction surface.

半導体構造層１７の下面には、第２の半導体層１５から活性層１３を貫通して第１の半導体層１１に至る溝１７Ｇが形成されている。第２の半導体層１５の下面には、第２の半導体層１５の上に、例えばＴｉ／ＡｇまたはＩＴＯ／Ａｇがこの順に積層されたｐ電極１９が形成されている。キャップ層２１は、第２の半導体層１５の下面にｐ電極１９を埋設するように形成されており、例えばＴｉＷからなっている。 On the lower surface of the semiconductor structure layer 17, a groove 17 G extending from the second semiconductor layer 15 through the active layer 13 to the first semiconductor layer 11 is formed. On the lower surface of the second semiconductor layer 15, a p-electrode 19 in which, for example, Ti / Ag or ITO / Ag is stacked in this order is formed on the second semiconductor layer 15. The cap layer 21 is formed so as to bury the p-electrode 19 on the lower surface of the second semiconductor layer 15 and is made of, for example, TiW.

絶縁層２３は、半導体構造層１７が露出する表面及びキャップ層２１を覆うように形成されている絶縁性を有する層であり、例えばＳｉＯ₂またはＳｉＮ等からなっている。絶縁層２３は溝１７Ｇの底面を露出する開口部２３Ａを有し、かつ発光素子１０の端部領域にあるキャップ層２１を露出する開口部２３Ｂを有している。 The insulating layer 23 is an insulating layer formed so as to cover the surface from which the semiconductor structure layer 17 is exposed and the cap layer 21, and is made of, for example, SiO ₂ or SiN. The insulating layer 23 has an opening 23 A that exposes the bottom surface of the groove 17 G, and an opening 23 B that exposes the cap layer 21 in the end region of the light emitting element 10.

オーミック電極としてのｎ電極２５は、溝１７Ｇの底面において開口部２３Ａから露出した第１の半導体層１１に接続され、かつ溝１７Ｇの側面上に形成された絶縁層２３上に形成されている。また、開口部２３Ｂから露出するキャップ層２１に接続されたｐ給電電極２７が形成されている。ｎ給電電極２９は、ｐ給電電極２７が形成されている端部領域以外の領域において絶縁層２３及びｎ電極２５を覆うように形成されている。ｎ給電電極２９はｐ給電電極２７と離間して形成されており、ｐ給電電極２７とは電気的に絶縁されている。なお、ｐ給電電極２７及びｎ給電電極２９は、発光素子１０の外部にある電流供給源に各々接続される。すなわち、発光素子１０において、半導体構造層１７への電流の供給は、ｐ給電電極２７及びｎ給電電極２９からそれぞれｐ電極１９及びｎ電極２５を介して行われる。 The n-electrode 25 as an ohmic electrode is connected to the first semiconductor layer 11 exposed from the opening 23A on the bottom surface of the groove 17G, and is formed on the insulating layer 23 formed on the side surface of the groove 17G. A p-feed electrode 27 connected to the cap layer 21 exposed from the opening 23B is formed. The n power supply electrode 29 is formed so as to cover the insulating layer 23 and the n electrode 25 in a region other than the end region where the p power supply electrode 27 is formed. The n power supply electrode 29 is formed away from the p power supply electrode 27 and is electrically insulated from the p power supply electrode 27. Note that the p-feed electrode 27 and the n-feed electrode 29 are each connected to a current supply source outside the light-emitting element 10. That is, in the light emitting element 10, the current is supplied to the semiconductor structure layer 17 from the p feeding electrode 27 and the n feeding electrode 29 through the p electrode 19 and the n electrode 25, respectively.

第１の半導体層１１内には、ｎ電極２５上にｎ電極２５に接して、第１の半導体層１１の他の領域よりもキャリア濃度が高く、電気抵抗率が低い低抵抗領域１１Ａが形成されている。すなわち、低抵抗領域１１Ａは、ｎ電極２５が第１の半導体層１１に接する面を覆うように形成されている。換言すれば、低抵抗領域１１Ａは、第１の半導体層１１内に、溝１７Ｇの各々の底部に接して部分的に設けられている。つまり、低抵抗領域１１Ａの各々は、互いに離間して設けられ、隣接する低抵抗領域１１Ａの間には第１の半導体層１１の低抵抗領域１１Ａよりも電気抵抗率が高い他の領域が存在している。また、低抵抗領域１１Ａは、ｎ電極２５に接する深さｄ１から、第１の半導体層１１の表面１１Ｓに達しない深さｄ２まで形成されている（図２（ｅ））。すなわち、低抵抗領域１１Ａは、上記したように、第１の半導体層１１内で、第１の半導体層１１の面内方向においても、また深さ方向においても部分的に形成されている。 In the first semiconductor layer 11, a low resistance region 11 A having a higher carrier concentration and lower electrical resistivity than the other region of the first semiconductor layer 11 is formed on the n electrode 25 in contact with the n electrode 25. Has been. That is, the low resistance region 11 A is formed so as to cover the surface where the n electrode 25 is in contact with the first semiconductor layer 11. In other words, the low resistance region 11A is partially provided in the first semiconductor layer 11 in contact with the bottom of each of the grooves 17G. That is, each of the low resistance regions 11A is provided so as to be separated from each other, and there is another region having a higher electrical resistivity than the low resistance region 11A of the first semiconductor layer 11 between the adjacent low resistance regions 11A. doing. The low resistance region 11A is formed from a depth d1 in contact with the n-electrode 25 to a depth d2 that does not reach the surface 11S of the first semiconductor layer 11 (FIG. 2E). That is, the low resistance region 11A is partially formed in the first semiconductor layer 11 both in the in-plane direction and in the depth direction of the first semiconductor layer 11 as described above.

支持体３０は、図１に示すように、Ｓｉ等の放熱性の良好な支持基板３１と、支持基板３１の発光素子構造体２０と対向する面上に形成された絶縁層３３とを有し、絶縁層３３上に形成された金属層である接合層３５によって素子構造体２０と接合されている。より詳細には、接合層３５は、ｎ給電電極２９が形成されている領域に対向した領域に形成された接合層３５Ａ及びｐ給電電極２７が形成されている領域に対向した領域に形成された接合層３５Ｂからなっている。なお、接合層３５Ａと接合層３５Ｂは離間して形成されており、互いに電気的に絶縁されている。 As shown in FIG. 1, the support 30 has a support substrate 31 with good heat dissipation such as Si, and an insulating layer 33 formed on the surface of the support substrate 31 facing the light emitting element structure 20. The element structure 20 is bonded by a bonding layer 35 which is a metal layer formed on the insulating layer 33. More specifically, the bonding layer 35 is formed in a region facing the region where the bonding layer 35A formed in the region facing the region where the n feeding electrode 29 is formed and the region where the p feeding electrode 27 is formed. It consists of a bonding layer 35B. Note that the bonding layer 35A and the bonding layer 35B are formed apart from each other and are electrically insulated from each other.

実施例１の発光素子１０では、ｎ電極２５に接して第１半導体層１１の他の領域よりもキャリア濃度が高い低抵抗領域１１Ａが配されている。これによりｎ電極２５と第１の半導体層１１との間の接触抵抗を低く抑えることができる。従って、ｎ電極２５から第１の半導体層１１へ電流が注入される際にｎ電極２５と第１の半導体層１１との間で発生するジュール損を抑制して、半導体構造層１７への電流注入効率を向上させ、発光効率を向上させることが可能である。また、電流経路に電気抵抗率が低い低抵抗領域１１Ａが形成されている故に、発光素子１０の電流経路全体の抵抗値を低くすることができ、動作抵抗を低下させることが可能である。 In the light emitting element 10 of Example 1, the low resistance region 11A having a higher carrier concentration than the other regions of the first semiconductor layer 11 is disposed in contact with the n electrode 25. Thereby, the contact resistance between the n-electrode 25 and the first semiconductor layer 11 can be kept low. Therefore, the Joule loss generated between the n electrode 25 and the first semiconductor layer 11 when current is injected from the n electrode 25 to the first semiconductor layer 11 is suppressed, and the current to the semiconductor structure layer 17 is reduced. It is possible to improve injection efficiency and light emission efficiency. Further, since the low resistance region 11A having a low electrical resistivity is formed in the current path, the resistance value of the entire current path of the light emitting element 10 can be lowered, and the operating resistance can be lowered.

また、実施例１の発光素子１０では、ｎ電極２５から第１の半導体層１１内に注入された電流は、まず他の領域より電気抵抗率が低い低抵抗領域１１Ａ内で拡散する。その後に、電流は、ｎ電極２５と第１の半導体層１１との界面よりも大きな面積を有する低抵抗領域１１Ａの表面全体から第１の半導体層１１の他の領域に注入される。それ故、図１の一点鎖線矢印に示すように、電流は第１の半導体層１１内で良好に拡散され、発光素子１０内での電流集中が防止されて発光素子の発光効率が向上される。 In the light emitting device 10 of Example 1, the current injected from the n-electrode 25 into the first semiconductor layer 11 is first diffused in the low resistance region 11A having a lower electrical resistivity than the other regions. Thereafter, a current is injected into the other region of the first semiconductor layer 11 from the entire surface of the low resistance region 11A having an area larger than the interface between the n-electrode 25 and the first semiconductor layer 11. Therefore, as shown by a one-dot chain line arrow in FIG. 1, the current is diffused well in the first semiconductor layer 11, current concentration in the light emitting element 10 is prevented, and the light emission efficiency of the light emitting element is improved. .

［発光素子１０の製造方法］
実施例１である発光素子１０の製造方法について、以下に詳細に説明する。図２（ａ）−（ｅ）は、実施例１の発光素子１０の各製造工程を示す断面図である。 [Method for Manufacturing Light-Emitting Element 10]
The manufacturing method of the light emitting element 10 which is Example 1 is demonstrated in detail below. 2A to 2E are cross-sectional views illustrating each manufacturing process of the light-emitting element 10 of Example 1. FIG.

［発光素子構造体の形成］
まず、ＭＯＣＶＤ（Metal-Organic Chemical Vapor Deposition）法を用いて結晶成長を行い、半導体構造層１７を形成する。具体的には、サファイア基板等の成長基板３７をＭＯＣＶＤ装置に投入し、サーマルクリーニング後、第１の半導体層１１、活性層１３、及び第２の半導体層１５を順に成膜する。 [Formation of light emitting element structure]
First, crystal growth is performed using a MOCVD (Metal-Organic Chemical Vapor Deposition) method to form the semiconductor structure layer 17. Specifically, the growth substrate 37 such as a sapphire substrate is put into an MOCVD apparatus, and after the thermal cleaning, the first semiconductor layer 11, the active layer 13, and the second semiconductor layer 15 are sequentially formed.

次に、図２（ａ）に示すように、ｐ電極１９及びキャップ層２１を形成する。ｐ電極１９は、第２の半導体層１５の上に順にＴｉ／ＡｇまたはＩＴＯ／Ａｇ等を、例えばスパッタ法または電子ビーム（ＥＢ）蒸着法で１００−３００ｎｍ程度の厚さで成膜し、所定の形状にパターニングすることで形成する。キャップ層２１は、ｐ電極１９を埋設するようにＴｉＷを、例えばスパッタ法または電子ビーム（ＥＢ）蒸着法で成膜し、ｐ電極と同様の所定の形状にパターニングすることで形成する。なお、ｐ電極１９の配線抵抗を良好にするために、ｐ電極１９上にＴｉＷ／Ｔｉ／Ｐｔ／Ａｕ／Ｔｉをこの順に成膜してキャップ層２１を形成してもよい。 Next, as shown in FIG. 2A, a p-electrode 19 and a cap layer 21 are formed. The p-electrode 19 is formed by sequentially depositing Ti / Ag or ITO / Ag or the like on the second semiconductor layer 15 to a thickness of about 100 to 300 nm by, for example, sputtering or electron beam (EB) evaporation. It is formed by patterning to the shape. The cap layer 21 is formed by forming a TiW film so as to embed the p-electrode 19 by, for example, a sputtering method or an electron beam (EB) vapor deposition method, and patterning it into a predetermined shape similar to the p-electrode. In order to improve the wiring resistance of the p electrode 19, the cap layer 21 may be formed by depositing TiW / Ti / Pt / Au / Ti on the p electrode 19 in this order.

次に、図２（ｂ）に示すように、第２の半導体層１５の表面及びキャップ層２１を覆うように絶縁膜３９を形成する。この絶縁膜３９は、ＳｉＯ₂またはＳｉＮ等の絶縁性材料を、例えばスパッタ法またはＣＶＤ（Chemical Vapor Deposition）法等で成膜することによって形成される。 Next, as illustrated in FIG. 2B, an insulating film 39 is formed so as to cover the surface of the second semiconductor layer 15 and the cap layer 21. The insulating film 39 is formed by forming an insulating material such as SiO ₂ or SiN by, for example, sputtering or CVD (Chemical Vapor Deposition).

次に、図２（ｃ）に示すように、第１の半導体層１１に溝を形成し、絶縁膜３９の一部を除去して絶縁層２３を完成させた後、ｎ電極２５を形成する。具体的には、まず、ｐ電極１９及びキャップ層２１の各々の間の領域において、絶縁膜３９、第２の半導体層１５及び活性層１３を貫通して第１の半導体層１１を露出するように溝１７Ｇを形成する。溝１７Ｇは、例えば絶縁膜３９、第２の半導体層１５及び活性層１３を反応性イオンエッチング（ＲＩＥ）等でドライエッチングすることで形成する。その後、溝１７Ｇの側面から露出している活性層１３及び第２の半導体層１５を覆うようにＳｉＯ₂またはＳｉＮ等の絶縁性材料からなる絶縁膜を絶縁膜３９と同様に形成し、絶縁層２３を完成する。その後、溝１７Ｇの底部にある開口部２３Ａから露出している第１の半導体層１１の表面を覆い、絶縁層２３の溝１７Ｇの側面に形成された部分を覆うようにｎ電極２５を形成する。ｎ電極２５は、第１の半導体層１１の表面からＴｉ／ＡｌまたはＴｉ／Ａｇの順に、例えば３００ｎｍ以上の厚さに成膜した後にパターニングすることで形成する。 Next, as shown in FIG. 2C, a groove is formed in the first semiconductor layer 11, a part of the insulating film 39 is removed to complete the insulating layer 23, and then an n-electrode 25 is formed. . Specifically, first, in the region between each of the p-electrode 19 and the cap layer 21, the first semiconductor layer 11 is exposed through the insulating film 39, the second semiconductor layer 15, and the active layer 13. A groove 17G is formed in the groove. The groove 17G is formed, for example, by dry etching the insulating film 39, the second semiconductor layer 15, and the active layer 13 by reactive ion etching (RIE) or the like. Thereafter, an insulating film made of an insulating material such as SiO ₂ or SiN is formed in the same manner as the insulating film 39 so as to cover the active layer 13 and the second semiconductor layer 15 exposed from the side surface of the groove 17G. 23 is completed. Thereafter, the n-electrode 25 is formed so as to cover the surface of the first semiconductor layer 11 exposed from the opening 23A at the bottom of the groove 17G and to cover the portion formed on the side surface of the groove 17G of the insulating layer 23. . The n electrode 25 is formed by patterning after forming a film in a thickness of, for example, 300 nm or more in the order of Ti / Al or Ti / Ag from the surface of the first semiconductor layer 11.

次に、図２（ｄ）に示すように、ｐ給電電極２７及びｎ給電電極２９を形成する。具体的には、まず、ｐ給電電極２７を形成する領域のキャップ層２１の一部を露出させる開口部２３Ｂを形成する。開口部２３Ｂは、絶縁層２３をウェットエッチングまたはドライエッチングで一部除去することで形成する。次に、絶縁層２３及びｎ電極２５並びに開口部２３Ｂから露出したキャップ層２１を覆うように、例えばＴｉ／Ｐｔ／Ａｕをこの順にＥＢ蒸着法等で成膜した後に所定形状にパターニングすることでｐ給電電極２７及びｎ給電電極２９を形成する。この際、ｐ給電電極２７とｎ給電電極２９が互いに離間して電気的に絶縁されるようにパターニングする。以上の工程で発光素子構造体２０が完成する。なお、複数の発光素子構造体２０を１枚の成長基板上に複数形成している場合には、発光素子構造体２０を、例えばドライエッチングで個片化する。
［支持体の形成及び支持体との接着］
まず、Ｓｉ等の支持基板３１の一方の面に例えばＳｉＯ₂またはＳｉＮからなる絶縁層３３を形成して支持体３０を形成する。その後、支持体３０の絶縁層３３上に発光素子構造体２０との接合層としてＡｕからなる接合層３５Ａ及び３５Ｂを形成する。接合層３５Ａ及び３５Ｂの形成には、例えば、抵抗加熱及びＥＢ蒸着法、スパッタ法などから適当な手法を用いることが出来る。 Next, as shown in FIG. 2D, a p-feed electrode 27 and an n-feed electrode 29 are formed. Specifically, first, an opening 23B that exposes a part of the cap layer 21 in a region where the p-feed electrode 27 is to be formed is formed. The opening 23B is formed by partially removing the insulating layer 23 by wet etching or dry etching. Next, for example, Ti / Pt / Au is deposited in this order by EB vapor deposition or the like so as to cover the insulating layer 23, the n-electrode 25, and the cap layer 21 exposed from the opening 23B, and then patterned into a predetermined shape. A p-feed electrode 27 and an n-feed electrode 29 are formed. At this time, the p-feed electrode 27 and the n-feed electrode 29 are patterned so as to be separated from each other and electrically insulated. The light emitting element structure 20 is completed through the above steps. When a plurality of light emitting element structures 20 are formed on one growth substrate, the light emitting element structures 20 are separated into pieces by, for example, dry etching.
[Formation of support and adhesion to support]
First, the support 30 is formed by forming the insulating layer 33 made of, for example, SiO ₂ or SiN on one surface of the support substrate 31 made of Si or the like. Thereafter, bonding layers 35 A and 35 B made of Au are formed as a bonding layer with the light emitting element structure 20 on the insulating layer 33 of the support 30. For forming the bonding layers 35 A and 35 B, an appropriate method can be used from, for example, resistance heating, EB vapor deposition, and sputtering.

次に、素子構造体２０と支持体３０を、たとえば熱圧着により接合させる。より詳細には、素子構造体２０のｐ給電電極２７及びｎ給電電極２９の最表層にあるＡｕと接合層３５Ａ及び３５Ｂを形成するＡｕとを熱圧着して、いわゆるＡｕ／Ａｕ接合を行った。なお、接合方法及び材料は上記の方法及び材料に限定されるものではなく、例えばＡｕＳｎ等を用いた共晶接合を用いた接合を行ってもよい。 Next, the element structure 20 and the support body 30 are joined by, for example, thermocompression bonding. More specifically, so-called Au / Au bonding was performed by thermocompression bonding of Au, which is the outermost layer of the p-feed electrode 27 and the n-feed electrode 29 of the element structure 20, and Au forming the bonding layers 35A and 35B. . Note that the bonding method and materials are not limited to the above-described methods and materials, and for example, bonding using eutectic bonding using AuSn or the like may be performed.

［成長基板の除去］
素子構造体２０と支持体３０とを接合した後、成長基板３７を除去する。成長基板３７の除去により第１の半導体層１１の表面１１Ｓが露出し、光取り出し面となる。成長基板３７の除去は、レーザリフトオフ法を用いて行った。なお、成長基板３７の除去は、レーザリフトオフに限らず、ウエットエッチングドライエッチング、機械研磨法、化学機械研磨（CMP）もしくはそれらのうち少なくとも1つの方法を含む組合せにより行ってもよい。 [Removal of growth substrate]
After bonding the element structure 20 and the support 30, the growth substrate 37 is removed. By removing the growth substrate 37, the surface 11S of the first semiconductor layer 11 is exposed and becomes a light extraction surface. The growth substrate 37 was removed using a laser lift-off method. The removal of the growth substrate 37 is not limited to laser lift-off, and may be performed by wet etching / dry etching, mechanical polishing, chemical mechanical polishing (CMP), or a combination including at least one of them.

［低抵抗領域の形成］
成長基板３７の除去後、低抵抗領域１１Ａを形成する。低抵抗領域１１Ａは、第１の半導体層１１に、例えばメタルマスクを用いたイオン注入法を用いて不純物（Ｓｉ）ドーピングを行うことにより形成する。イオン注入法を用いることで、半導体構造層１７の結晶性を低下させずに、第１の半導体層の所望の領域に所望量（例えば、通常の半導体層成長工程でドーピングできる量の１０倍程度まで）の不純物をドーピングすることが可能である。イオン注入においては、ｎ電極２５が第１の半導体層１１に接する領域に不純物がドーピングされるように、すなわちｎ電極２５に接して低抵抗領域１１Ａが形成されるように加速電圧を調整する。より詳細には、加速電圧の調整によって、前述のようにｎ電極２５に接する深さｄ１から第１の半導体層１１の表面１１Ｓから所定の深さｄ２（図２（ｅ））までの領域を低抵抗領域１１Ａとすることができる。また、イオン注入によって低抵抗領域１１Ａを形成した後に、アニール処理を行い注入された不純物であるＳｉを活性化させ、低抵抗領域１１Ａの抵抗をさらに低下させることができる。 [Formation of low resistance region]
After removing the growth substrate 37, the low resistance region 11A is formed. The low resistance region 11A is formed by doping impurities (Si) into the first semiconductor layer 11 using, for example, an ion implantation method using a metal mask. By using the ion implantation method, a desired amount (for example, about 10 times the amount that can be doped in a normal semiconductor layer growth step) is added to a desired region of the first semiconductor layer without reducing the crystallinity of the semiconductor structure layer 17. It is possible to dope impurities). In the ion implantation, the acceleration voltage is adjusted so that the region where the n electrode 25 is in contact with the first semiconductor layer 11 is doped with impurities, that is, the low resistance region 11A is formed in contact with the n electrode 25. More specifically, by adjusting the acceleration voltage, a region from the depth d1 in contact with the n electrode 25 to the predetermined depth d2 (FIG. 2E) from the surface 11S of the first semiconductor layer 11 as described above is obtained. The low resistance region 11A can be obtained. In addition, after the low resistance region 11A is formed by ion implantation, annealing, which is an implanted impurity, can be activated to further reduce the resistance of the low resistance region 11A.

以下に、本発明の実施例２である発光素子４０について図３を参照して説明する。図３においては、発光素子４０の電極間に流れる電流を一点鎖線矢印で示している。発光素子４０は、低抵抗領域の構成が異なる以外は実施例１である発光素子１０と同様の構成を有している。 Hereinafter, a light-emitting element 40 that is Embodiment 2 of the present invention will be described with reference to FIG. In FIG. 3, the current flowing between the electrodes of the light emitting element 40 is indicated by a one-dot chain arrow. The light emitting element 40 has the same configuration as that of the light emitting element 10 according to the first embodiment except that the configuration of the low resistance region is different.

発光素子４０では、低抵抗領域４１が第１の低抵抗領域４１Ａ及び第２の低抵抗領域４１Ｂからなっている。第１の低抵抗領域４１Ａは、実施例１である発光素子１０の低抵抗領域１１Ａと同様の低抵抗領域である。すなわち、第１の低抵抗領域４１Ａは、ｎ電極２５の第１の半導体層１１に対して露出している面に接して形成されており、第１の半導体層１１の他の領域よりもキャリア濃度が高く、電気抵抗率が低い領域である。低抵抗領域４１Ａは、第１の半導体層１１内の低抵抗領域４１Ａが形成されている深さの領域において、部分的に形成されている。すなわち、第１の半導体層１１は、低抵抗領域４１Ａが形成されている深さの領域において、低抵抗領域４１Ａと、低抵抗領域４１Ａよりも電気抵抗率が高い他の領域とを含んでいる。 In the light emitting element 40, the low resistance region 41 includes a first low resistance region 41A and a second low resistance region 41B. The first low resistance region 41A is a low resistance region similar to the low resistance region 11A of the light emitting element 10 according to the first embodiment. That is, the first low-resistance region 41A is formed in contact with the surface exposed to the first semiconductor layer 11 of the n-electrode 25, and has more carriers than the other regions of the first semiconductor layer 11. This is a region where the concentration is high and the electrical resistivity is low. The low resistance region 41A is partially formed in a region having a depth where the low resistance region 41A in the first semiconductor layer 11 is formed. That is, the first semiconductor layer 11 includes a low resistance region 41A and another region having a higher electrical resistivity than the low resistance region 41A in the depth region where the low resistance region 41A is formed. .

第２の低抵抗領域４１Ｂは、第１の半導体層１１のうち第１の低抵抗領域４１Ａを除く部分よりもキャリア濃度が高く、電気抵抗率が低い領域である。第１の半導体層１１の表面１１Ｓ、すなわち光取り出し面全面に渡って、光取り出し面から第１の低抵抗領域４１Ａの上面に達する深さまで形成されている。換言すれば、第２の低抵抗領域４１Ｂは、第１の低抵抗領域の４１Ａの各々がその上面において第２の低抵抗領域４１Ｂに接続されている。 The second low resistance region 41B is a region having a higher carrier concentration and a lower electrical resistivity than the portion of the first semiconductor layer 11 excluding the first low resistance region 41A. The surface 11S of the first semiconductor layer 11, that is, the entire surface of the light extraction surface, is formed from the light extraction surface to a depth reaching the upper surface of the first low resistance region 41A. In other words, in the second low resistance region 41B, each of the first low resistance regions 41A is connected to the second low resistance region 41B on the upper surface thereof.

上記した構成の低抵抗領域４１を形成することにより、実施例１である発光素子１０と同様に、ｎ電極２５と第１の半導体層１１との間の接触抵抗を低く抑え、ｎ電極２５と第１の半導体層１１との間で発生するジュール損を防止して、半導体構造層１７への電流注入効率を向上させ、発光効率を向上させることが可能である。また、発光素子１０の電流経路全体の抵抗値を低くすることができ、動作抵抗を低下させることが可能である。 By forming the low-resistance region 41 having the above-described configuration, the contact resistance between the n-electrode 25 and the first semiconductor layer 11 is kept low, similarly to the light-emitting element 10 according to the first embodiment. It is possible to prevent Joule loss that occurs between the first semiconductor layer 11 and the current injection efficiency into the semiconductor structure layer 17, thereby improving the light emission efficiency. Further, the resistance value of the entire current path of the light emitting element 10 can be lowered, and the operating resistance can be lowered.

さらに、発光素子４０においては、図３の一点鎖線矢印に示すようにｎ電極２５から第１の低抵抗領域４１Ａに注入された電流は、第１の低抵抗領域４１Ａから、他の領域よりも低抵抗な第２の低抵抗領域４１Ｂにまず流入する。その後、電流は第２の低抵抗領域４１Ｂ内で発光素子４０の面内方向に拡散し、第２の低抵抗領域４１Ｂの下面全体からｐ電極１９に向けて半導体構造層１７内を電流が流れる。従って、第１の半導体層１１内において面内方向に十分に拡散し、半導体構造層１７における電流拡散が促進される。なお、第２の低抵抗領域４１Ｂは、ｎ電極２５及び第１の低抵抗領域４１Ａよりもｐ電極１９から離間しており、このことによっても実施例１の発光素子１０に比して半導体構造層１７における電流拡散が促進される。これにより、発光素子４０によれば、発光効率が向上し、発光素子の光取り出し面における発光ムラも防止することが可能である。 Furthermore, in the light emitting element 40, the current injected from the n electrode 25 into the first low resistance region 41A as shown by the one-dot chain line arrow in FIG. 3 is greater than the other regions from the first low resistance region 41A. First, it flows into the second low-resistance region 41B having low resistance. Thereafter, the current diffuses in the in-plane direction of the light emitting element 40 in the second low resistance region 41B, and the current flows in the semiconductor structure layer 17 from the entire lower surface of the second low resistance region 41B toward the p-electrode 19. . Accordingly, the first semiconductor layer 11 is sufficiently diffused in the in-plane direction, and current diffusion in the semiconductor structure layer 17 is promoted. Note that the second low resistance region 41B is farther from the p electrode 19 than the n electrode 25 and the first low resistance region 41A, and this also causes a semiconductor structure as compared with the light emitting element 10 of Example 1. Current spreading in layer 17 is facilitated. Thereby, according to the light emitting element 40, light emission efficiency improves and it is possible to prevent light emission unevenness on the light extraction surface of the light emitting element.

低抵抗領域４１Ｂは、実施例１の発光素子１０の低抵抗領域１１Ａと同様にｎ電極２５に接して低抵抗領域４１Ａを形成した後に形成される。低抵抗領域４１Ｂは、イオン注入によって、第１の半導体層１１の光取り出し面の全面に光取り出し面から低抵抗領域４１Ａの上面に至るまで不純物を注入することで形成される。低抵抗領域４１Ｂの形成位置（深さ領域）は、加速電圧の調整によって行うことができる。低抵抗領域４１Ａ及び４１Ｂを形成後、実施例１の製造方法と同様にアニール処理を行うことで低抵抗領域４１内の不純物を活性化させ、発光素子４０が完成する。 The low resistance region 41B is formed after the low resistance region 41A is formed in contact with the n-electrode 25 in the same manner as the low resistance region 11A of the light emitting element 10 of the first embodiment. The low resistance region 41B is formed by implanting impurities into the entire surface of the light extraction surface of the first semiconductor layer 11 from the light extraction surface to the upper surface of the low resistance region 41A by ion implantation. The formation position (depth region) of the low resistance region 41B can be performed by adjusting the acceleration voltage. After forming the low resistance regions 41A and 41B, annealing in the same manner as in the manufacturing method of Example 1 activates the impurities in the low resistance region 41, and the light emitting element 40 is completed.

上記実施例において、第１の半導体層１１の表面１１Ｓ（光取り出し面）に光り取り出し効率向上のための凹凸構造を形成してもよい。このような凹凸構造は、成長基板３７の除去後、低抵抗領域１１Ａ、４１を形成する前または低抵抗領域１１Ａ、４１の形成後に第１の半導体層１１の光取り出し面をＴＭＡＨによってウェットエッチングして形成する。なお、フォトリソグラフィ、ＥＢリソグラフィ、ＥＢ描画、ナノインプリント、レーザ露光などの方法及びリフトオフ法によりｎクラッド層１２上に人工的周期構造のマスクパターンを形成後にドライエッチングして形成して凹凸構造を形成してもよい。 In the above embodiment, a concavo-convex structure for improving the light extraction efficiency may be formed on the surface 11S (light extraction surface) of the first semiconductor layer 11. Such a concavo-convex structure is obtained by wet etching the light extraction surface of the first semiconductor layer 11 with TMAH after the growth substrate 37 is removed, before the low resistance regions 11A and 41 are formed, or after the low resistance regions 11A and 41 are formed. Form. In addition, a mask pattern having an artificial periodic structure is formed on the n-clad layer 12 by a method such as photolithography, EB lithography, EB drawing, nanoimprinting, laser exposure, and the lift-off method, followed by dry etching to form a concavo-convex structure. May be.

実施例１において、低抵抗領域１１Ａは、ｎ電極２５の第１の半導体層１１に接する表面上の領域にのみ形成されているように図示されているが、低抵抗領域１１Ａの形成範囲は図示された態様に限定されない。例えば、図４（ａ）に示すように発光素子１０の面内方向に伸張し、第１の半導体層１１と平行な面内において、ｎ電極２５の第１の半導体層１１に接する表面よりも広い領域に形成されていてもよい。また、図４（ｂ）に示すように、低抵抗領域１１Ａが上方に伸張して第１の半導体層１１の光取り出し面に達していてもよい。このように、低抵抗領域１１Ａが発光素子１０の面内方向または面内方向と垂直な方向に伸張する構成とすることで、半導体構造層１７内における電流拡散をさらに良好にすることが可能である。 In Example 1, the low resistance region 11A is illustrated as being formed only in the region on the surface of the n-electrode 25 that is in contact with the first semiconductor layer 11, but the formation range of the low resistance region 11A is illustrated. It is not limited to the embodiment. For example, as shown in FIG. 4A, the light emitting element 10 extends in the in-plane direction, and in a plane parallel to the first semiconductor layer 11, the surface of the n-electrode 25 is in contact with the first semiconductor layer 11. It may be formed in a wide area. In addition, as shown in FIG. 4B, the low resistance region 11A may extend upward to reach the light extraction surface of the first semiconductor layer 11. As described above, by configuring the low resistance region 11A to extend in the in-plane direction of the light emitting element 10 or the direction perpendicular to the in-plane direction, current diffusion in the semiconductor structure layer 17 can be further improved. is there.

実施例２において、第２の低抵抗領域４１Ｂは、第１の半導体層４１Ｂの発光素子４０の面内方向全体に光取り出し面まで達して形成されているように図示されているが、第２の低抵抗領域４１Ｂの形成範囲は図示された態様に限定されない。第２の低抵抗領域４１Ｂは、第１の低抵抗領域４１Ａよりも第１の半導体層１１の光取り出し面側に、第１の低抵抗領域４１Ａに接して形成され、上面視において（光取り出し面と垂直な方向から見て）すなわち第１の低抵抗領域４１Ａよりも第１の半導体層１１に平行な面内において広い領域に形成されていればよい。例えば、図５（ａ）に示すように、第２の低抵抗領域４１Ｂが第１の半導体層１１の表面１１Ｓ（光取り出し面）から離間した深さ領域に形成されていてもよい。また、図５（ｂ）に示すように不連続、すなわち互いに離間して複数の第２の低抵抗領域４１Ｂとして形成されてもよい。また、第２の低抵抗領域４１Ｂは、第１の低抵抗領域４１Ａの上面よりも深い領域にまで形成されていてもよい。 In the second embodiment, the second low resistance region 41B is illustrated as reaching the light extraction surface in the entire in-plane direction of the light emitting element 40 of the first semiconductor layer 41B. The formation range of the low resistance region 41B is not limited to the illustrated embodiment. The second low resistance region 41B is formed closer to the light extraction surface side of the first semiconductor layer 11 than the first low resistance region 41A, in contact with the first low resistance region 41A. That is, it is only necessary to be formed in a wider area in the plane parallel to the first semiconductor layer 11 than the first low resistance area 41A (viewed from the direction perpendicular to the plane). For example, as shown in FIG. 5A, the second low resistance region 41B may be formed in a depth region separated from the surface 11S (light extraction surface) of the first semiconductor layer 11. Further, as shown in FIG. 5B, the second low resistance regions 41B may be formed discontinuously, that is, separated from each other. Further, the second low resistance region 41B may be formed to a region deeper than the upper surface of the first low resistance region 41A.

なお、上記した実施例は適宜組み合わせ、又は改変して適用することができる。また、上記した材料、数値等は例示に過ぎない。 The above-described embodiments can be applied by appropriately combining or modifying them. Moreover, the above-described materials, numerical values, and the like are merely examples.

１０、４０発光素子
１１第１の半導体層
１１Ａ低抵抗領域
１１Ｓ表面
１３活性層
１５第２の半導体層
１７半導体構造層
１７Ｇ溝
１９ｐ電極
２１キャップ層
２３、３３絶縁層
２３Ａ、２３Ｂ開口部
２５ｎ電極
２７ｐ給電電極
２９ｎ給電電極
３０支持体
３１支持基板
３５接合層
３７成長基板
３９絶縁膜
４１低抵抗領域
４１Ａ第１の低抵抗領域
４１Ｂ第２の低抵抗領域 DESCRIPTION OF SYMBOLS 10, 40 Light emitting element 11 1st semiconductor layer 11A Low resistance area | region 11S Surface 13 Active layer 15 2nd semiconductor layer 17 Semiconductor structure layer 17G Groove 19 P electrode 21 Cap layer 23, 33 Insulating layer 23A, 23B Opening 25 n Electrode 27 p power supply electrode 29 n power supply electrode 30 support 31 support substrate 35 bonding layer 37 growth substrate 39 insulating film 41 low resistance region 41A first low resistance region 41B second low resistance region

Claims

A semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer are sequentially stacked, and the surface of the first semiconductor layer is a light extraction surface; A light emitting element
A groove that penetrates through the second semiconductor layer and the active layer from the second semiconductor layer side and reaches the first semiconductor layer;
An insulating layer covering the second semiconductor layer and the active layer exposed from the groove;
A first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the groove;
A second ohmic electrode formed on the surface of the second semiconductor layer,
It said first semiconductor layer, said partially formed in contact with the first ohmic electrode on the first semiconductor layer, and a low electrical resistivity than the rest of the first semiconductor layer the look including a first low resistance region, the first low resistance region is wider than said first exposed surface on a semiconductor layer of a first of said semiconductor layer parallel to a plane first ohmic electrode A light-emitting element formed in a region .

A semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer are sequentially stacked, and the surface of the first semiconductor layer is a light extraction surface; A light emitting element
  A groove that penetrates through the second semiconductor layer and the active layer from the second semiconductor layer side and reaches the first semiconductor layer;
  An insulating layer covering the second semiconductor layer and the active layer exposed from the groove;
  A first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the groove;
  A second ohmic electrode formed on the surface of the second semiconductor layer,
  The first semiconductor layer is partly formed in the first semiconductor layer in contact with the first ohmic electrode, and has a lower electrical resistivity than the other part of the first semiconductor layer. 1. A light-emitting element including one low-resistance region, wherein the first low-resistance region reaches the surface of the first semiconductor layer.

A semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer are sequentially stacked, and the surface of the first semiconductor layer is a light extraction surface; A light emitting element
  A groove that penetrates through the second semiconductor layer and the active layer from the second semiconductor layer side and reaches the first semiconductor layer;
  An insulating layer covering the second semiconductor layer and the active layer exposed from the groove;
  A first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the groove;
  A second ohmic electrode formed on the surface of the second semiconductor layer,
  The first semiconductor layer is partly formed in the first semiconductor layer in contact with the first ohmic electrode, and has a lower electrical resistivity than the other part of the first semiconductor layer. 1 low resistance region,
  The first semiconductor layer is formed on the surface side of the first semiconductor layer with respect to the first low resistance region and in contact with the first low resistance region, and is formed on the first semiconductor layer. A second electrode having a lower electric resistance than a portion of the first semiconductor layer excluding the first low-resistance region, which is formed in a region wider than the first low-resistance region in a parallel plane. A light-emitting element including the low-resistance region.

4. The light emitting device according to claim 1, wherein the first low resistance region is formed to a depth that does not reach a surface of the first semiconductor layer. 5.

  Forming a semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked on a first substrate;
  Forming a groove extending from the second semiconductor layer through the second semiconductor layer and the active layer into the first semiconductor layer;
  Forming an insulating layer covering the second semiconductor layer and the active layer exposed from the trench;
  Forming an opening exposing the first semiconductor layer in the insulating layer at the bottom of the groove, and forming a first ohmic electrode connected to the first semiconductor layer in the opening;
  Forming a second ohmic electrode on the second semiconductor layer;
  A low resistance region having a lower electrical resistivity than other portions of the first semiconductor layer in a region in contact with the first ohmic electrode in the first semiconductor layer by performing ion implantation in the first semiconductor layer Forming, and
  The low resistance region is formed in a region wider than a surface exposed to the first semiconductor layer of the first ohmic electrode in a plane parallel to the first semiconductor layer. Production method.

Forming a semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked on a first substrate;
Forming a groove extending from the second semiconductor layer through the second semiconductor layer and the active layer into the first semiconductor layer;
Forming an insulating layer covering the second semiconductor layer and the active layer exposed from the trench;
Forming an opening exposing the first semiconductor layer in the insulating layer at the bottom of the groove, and forming a first ohmic electrode connected to the first semiconductor layer in the opening;
Forming a second ohmic electrode on the second semiconductor layer;
A low resistance region having a lower electrical resistivity than other portions of the first semiconductor layer in a region in contact with the first ohmic electrode in the first semiconductor layer by performing ion implantation in the first semiconductor layer look including the steps of: forming a,
A method for manufacturing a light-emitting element, characterized in that the low-resistance region reaches the surface of the first semiconductor layer .