JP6202842B2 - 半導体集積回路および制御方法 - Google Patents

半導体集積回路および制御方法 Download PDF

Info

Publication number
JP6202842B2
JP6202842B2 JP2013055577A JP2013055577A JP6202842B2 JP 6202842 B2 JP6202842 B2 JP 6202842B2 JP 2013055577 A JP2013055577 A JP 2013055577A JP 2013055577 A JP2013055577 A JP 2013055577A JP 6202842 B2 JP6202842 B2 JP 6202842B2
Authority
JP
Japan
Prior art keywords
power
information
circuit block
acquired
power information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013055577A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014183400A5 (cg-RX-API-DMAC7.html
JP2014183400A (ja
Inventor
幹雄 加藤
幹雄 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2013055577A priority Critical patent/JP6202842B2/ja
Publication of JP2014183400A publication Critical patent/JP2014183400A/ja
Publication of JP2014183400A5 publication Critical patent/JP2014183400A5/ja
Application granted granted Critical
Publication of JP6202842B2 publication Critical patent/JP6202842B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2013055577A 2013-03-18 2013-03-18 半導体集積回路および制御方法 Expired - Fee Related JP6202842B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013055577A JP6202842B2 (ja) 2013-03-18 2013-03-18 半導体集積回路および制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013055577A JP6202842B2 (ja) 2013-03-18 2013-03-18 半導体集積回路および制御方法

Publications (3)

Publication Number Publication Date
JP2014183400A JP2014183400A (ja) 2014-09-29
JP2014183400A5 JP2014183400A5 (cg-RX-API-DMAC7.html) 2016-04-21
JP6202842B2 true JP6202842B2 (ja) 2017-09-27

Family

ID=51701741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013055577A Expired - Fee Related JP6202842B2 (ja) 2013-03-18 2013-03-18 半導体集積回路および制御方法

Country Status (1)

Country Link
JP (1) JP6202842B2 (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7314533B2 (ja) * 2019-03-07 2023-07-26 富士フイルムビジネスイノベーション株式会社 画像処理装置およびプログラム
CN116011379B (zh) * 2023-03-28 2023-08-15 长鑫存储技术有限公司 仿真方法、装置、电子设备及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4749793B2 (ja) * 2004-08-05 2011-08-17 パナソニック株式会社 省電力処理装置、省電力処理方法、及び省電力処理プログラム
JP4838240B2 (ja) * 2005-04-27 2011-12-14 パナソニック株式会社 情報処理装置における電力制御装置
US9043795B2 (en) * 2008-12-11 2015-05-26 Qualcomm Incorporated Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor
JP2010206052A (ja) * 2009-03-05 2010-09-16 Fuji Xerox Co Ltd 半導体装置、半導体装置を搭載した電子機器、プログラム
JP2012138020A (ja) * 2010-12-27 2012-07-19 Panasonic Corp マルチチップシステム、通信機器、映像音声装置および自動車

Also Published As

Publication number Publication date
JP2014183400A (ja) 2014-09-29

Similar Documents

Publication Publication Date Title
JP6621929B2 (ja) 電圧低下のデジタル検出及び制御のための方法並びに装置
CN108474820B (zh) 用于计量系统的参考电路
US11274971B2 (en) Temperature sensor
KR101999076B1 (ko) 온칩 파라미터 측정
CN107707118B (zh) 包括电源管理集成电路的电子装置
JP5024389B2 (ja) 半導体集積回路
JP4942990B2 (ja) 半導体記憶装置
Lee et al. A self-tuning IoT processor using leakage-ratio measurement for energy-optimal operation
WO2020230130A1 (en) Determination of unknown bias and device parameters of integrated circuits by measurement and simulation
JP2013149093A (ja) 制御装置、制御方法、プログラムおよび電子機器
JP2023101509A (ja) 半導体装置、およびバッテリの残量の検出方法
JP6202842B2 (ja) 半導体集積回路および制御方法
JP5893336B2 (ja) 電源制御装置、電源制御装置の制御方法、およびプログラム
US10197455B2 (en) Thermal oscillator
CN103257669A (zh) 具有超频模式的电子装置及方法
US20190041889A1 (en) Reference voltage generating apparatus and method
US11619982B2 (en) Efficient calibration of circuits in tiled integrated circuits
JP6373751B2 (ja) 半導体装置
CN104914914B (zh) 电路结构及其控制方法
JP5697777B2 (ja) データ処理システム
JP5643046B2 (ja) 容量センサ回路
JP2011198466A (ja) 半導体記憶装置
CN112104349B (zh) 上电复位电路及芯片
CN109508464B (zh) 非给定电压的标准单元库的构建方法和装置
KR102499010B1 (ko) 로직 블록의 데이터를 유지시키기 위한 파워 게이팅 회로

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160308

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160308

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20161226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170801

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170829

R151 Written notification of patent or utility model registration

Ref document number: 6202842

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees