JP6198522B2 - Fabrication techniques to increase pressure uniformity in an anodic bonded vapor cell. - Google Patents

Description

Cross-reference of related applications
[0001] This application is a continuation-in-part of US patent application Ser. No. 12 / 879,394, filed Sep. 10, 2010, which is a provisional patent application filed on Feb. 4, 2010. Claims the benefit of 61 / 301,497. Both applications are hereby incorporated by reference.
Government license
[0002] The US Government shall have certain rights in this invention as set forth in the provisions of the Government Contract Number FA8650-07-C-1125 with the US Air Force.

  [0003] A chip-scale atomic clock (CSAC) includes a vapor cell containing an alkali metal vapor such as rubidium (Rb). Typically, the vapor cell also contains a buffer gas, such as an argon nitrogen mixed buffer gas. A standard technique for fabricating a vapor cell involves anodic bonding of two glass wafers on either side of a silicon wafer having a plurality of cell structures defining a cavity. Alkali metal vapor and buffer gas are confined in the cavity of the cell structure between two glass wafers.

  [0004] Anodically bonded joints begin at a position where they are initially in contact between wafers and spread as the surfaces approach each other with electrostatic potential. Thus, if there is a delay in the front surface of the junction for each region, a pressure difference may occur in the steam cell. Furthermore, in order to use a material having a low boiling temperature such as Rb, it is necessary to perform bonding at the lowest possible temperature. Otherwise, the generated surface may contaminate the bonding surface. Therefore, in order to be able to form a bond as quickly as possible, it is necessary to apply a higher voltage as the wafer gets hot. As a result, the vapor cell can be sealed at different times and therefore at different temperatures, which creates a pressure differential within the vapor cell and also over cells fabricated in parallel on the same wafer. It can happen.

  [0005] Furthermore, due to the overall thickness variation of the two glass wafers, some of the vapor cells will be hermetically sealed before other vapor cells on the same set of wafers. This problem is exacerbated as the temperature gradually increases in the bonding equipment, as some of the trapped gas is pushed out of the vapor cell to be bonded late. Furthermore, there is no path for easily escaping the buffer gas confined in the delayed bonded area, which can cause a pressure differential in the vapor cell.

  [0006] Finally, due to the presence of the buffer gas, the voltage applied to achieve anodic bonding can cause gas breakdown, and a discharge or arc is generated through the gas to ground, essentially joining the process. May be short-circuited.

US patent application Ser. No. 12 / 873,441 US Patent Application Publication No. 2011/0187464

  [0007] A method of fabricating one or more vapor cells includes forming one or more vapor cell dies in a first wafer having a first diameter, and a first wafer over the vapor cell dies. Anodically bonding a second wafer to the first side of the second wafer, the second wafer having a second diameter. On the vapor cell die, a third wafer is positioned on a second surface of the first wafer opposite to the second wafer, the third wafer having a third diameter. A sacrificial wafer is disposed on the third wafer, the sacrificial wafer having a diameter greater than the first, second, and third diameters. A metallized bonding plate is placed on the sacrificial wafer. The third wafer is anodically bonded to the second surface of the first wafer when a voltage is applied to the metallized bonding plate while the sacrificial wafer is in place.

  [0008] The features of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings. With the understanding that the drawings depict only typical embodiments and therefore should not be considered as limiting the scope, the invention will be described with additional specificity and detail by using the accompanying drawings. .

[0009] FIG. 1 is a schematic cross-sectional view of a physics package for a chip scale atomic clock including a vapor cell according to one embodiment. [0010] FIG. 1 is a schematic diagram of one embodiment of a vapor cell die for a chip scale atomic clock formed on a wafer layer. [0011] FIG. 2 is a partial plan view of a wafer having a plurality of vapor cell dies and vent channels according to one embodiment. [0012] FIG. 5 is a schematic cross-sectional view of a physics package for a chip scale atomic clock including a vapor cell according to another embodiment. [0013] FIG. 3 illustrates a wafer configuration for anodic bonding using a sacrificial wafer. [0014] FIG. 6 is a schematic diagram of another embodiment of a vapor cell die for a chip scale atomic clock formed on a wafer layer. [0015] FIG. 6 is a partial plan view of a wafer having a plurality of vapor cell dies and vent channels according to another embodiment.

  [0016] In the following detailed description, embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that other embodiments may be utilized without departing from the scope of the present invention. The following detailed description is, therefore, not to be construed in a limiting sense.

  [0017] Fabrication techniques are provided to increase gas pressure uniformity in an anodically bonded vapor cell used in a chip scale atomic clock (CSAC). Typically, a vapor cell is fabricated by anodic bonding a pair of optically clear glass wafers on both sides of a substrate such as a silicon wafer having a plurality of cell structures. After these vapor cells are fabricated, they are assembled in a physical package for CSAC.

  [0018] One approach to increasing gas pressure uniformity during the fabrication of a vapor cell incorporates design features in the wafer surface that form interconnected vent channels, thereby allowing each vapor cell die in the wafer to move from the wafer to the wafer. A route to the perimeter is provided. These vent channels allow a gas near the inside of the wafer and a gas outside the wafer to be in a substantially continuous pressure equilibrium during anodic bonding. In another approach to increasing gas pressure uniformity, the anodic bonding process is modified to constantly increase the pressure as the temperature increases.

  [0019] The above approaches can also be combined, and therefore, by utilizing a vent channel in the silicon wafer surface with increased pressure, a vapor cell that is later sealed during processing and thus at a higher temperature is more It is also possible to have a high gas pressure. When cooled to room temperature, the vapor cell sealed at a higher temperature will have a lower pressure than the vapor cell sealed at a lower temperature. If the gas pressure is higher, the late sealed steam cell can be compensated so that the final pressure of all the steam cells is approximately the same at room temperature.

[0020] Further details of the fabrication technique are described below with reference to the drawings.
[0021] FIG. 1 illustrates a CSAC physics package 100 according to one embodiment, which may use a vapor cell fabricated according to the present technique. The physical package 100 includes a housing 102 that houses the various mechanical and electronic components of the physical package 100. These components can be fabricated as wafer level microelectromechanical system (MEMS) devices and then assembled in the housing 102. Typically, CSAC components in the physical package 100 include a laser die 110 such as a vertical cavity surface emitting laser (VCSEL), a quarter wave plate 120 in optical communication with the laser die 110, and a quarter wave plate 120. A vapor cell 130 in optical communication with the optical detector 140 and an optical detector 140 in optical communication with the vapor cell 130.

  [0022] The laser beam 112 emitted from the laser die 110 is directed to travel through the quarter wave plate 120 and the vapor cell 130 to the optical detector 140 during operation of the physics package 100. As shown in FIG. 1, the quarter wave plate 120, the vapor cell 130, and the optical detector 140 can be mounted in the package 102 at various tilt angles with respect to the optical path of the laser beam 112. Tilting these components reduces reflection coupling back into the VCSEL, thereby increasing CSAC stability.

  [0023] Various components within the physical package 100 are positioned at different levels within the housing 102 by a set of scaffolding structures. As shown in FIG. 1, a lower scaffold 150 is attached to the bottom surface 104 in the housing 102. The lower scaffold 150 supports a lower layer 152 that supports the laser die 110, an intermediate layer 154 that supports the quarter wave plate 120 above the laser die 110, and a vapor cell 130 above the quarter wave plate 120. And an upper layer 156. An upper scaffold structure 160 is attached to the upper surface 106 in the housing 102. The optical detector 140 is attached to the upper scaffold structure 160 above the vapor cell 130.

  [0024] The vapor cell 130 includes a pair of optically transparent wafers 132 and 134, such as glass wafers, which are anodically bonded to both sides of a substrate 136, such as a silicon wafer. Exemplary glass wafers include Pyrex glass or similar glass. At least one chamber 138 defined within the vapor cell 130 provides an optical path for the laser beam 112 between the laser die 110 and the optical detector 140.

  [0025] In one approach to fabricating the vapor cell 130 and then assembling it within the physics package 100, the wafer 132 is first anodically bonded to the bottom side of the substrate 136 and then rubidium or other alkali metal (liquid or solid state). ) In the chamber 138. The wafer 134 is then anodically bonded to the opposite side of the substrate 136 to form the vapor cell 130. Typically, such bonding is achieved at a temperature of about 250 ° C to about 400 ° C. The bonding process is performed in a state where the wafers 132 and 134 and the substrate 136 are under a high vacuum, or in a state where they are back-filled with a buffer gas such as an argon / nitrogen mixed gas. When buffer gas is used, the buffer gas is backfilled into the chamber 138 after the manufacturing equipment containing components for the vapor cell 130 has been evacuated. Thus, when the joining is complete and the vapor cell 130 is sealed, the alkali metal and optional buffer gas are confined within the chamber 138.

  [0026] During the anodic bonding process, a glass wafer containing mobile ions such as sodium contacts the silicon wafer and electrical contacts to both the glass wafer and the silicon wafer are obtained. Both glass and silicon wafers are heated to at least about 200 ° C., and the glass wafer electrode is at least about 200V negative with respect to the silicon wafer. This moves the sodium in the glass towards the negative electrode, allowing further voltage drops across the gap between the glass and silicon, resulting in a closer contact. At the same time, oxygen ions are released from the glass and flow towards the silicon, facilitating the formation of a bridge between the silicon in the glass and the silicon in the silicon wafer, thereby forming a very strong bond. The anodic bonding process can be operated with a wide variety of background gases and pressures well above the atmosphere to high vacuum. The higher the gas pressure, the better the heat transfer and the faster the process. In the case of an Rb vapor cell, it is desirable to form a junction at the lowest possible temperature in the presence of a buffer gas.

  [0027] Although the anodic bonding process can be improved by applying a higher voltage during the bonding process, increasing the voltage in the presence of gas can cause an arc. The arc is generated depending on the type of gas, the pressure, and the distance between the electrodes. Arcing can be mitigated by making the path to ground larger and thus increasing the potential required for arcing.

  [0028] If the gas type and pressure cannot be changed, increasing the distance between the electrodes can provide a way to apply a higher voltage. This can be done by using a sacrificial glass wafer inserted between the upper glass wafer of the vapor cell and the high voltage source. The sacrificial glass wafer has a larger diameter than the vapor cell wafer. This allows a much higher applied voltage at the start of the process and provides a much improved bonding environment. For example, the higher applied voltage can be about 800 volts to about 1200 volts.

  [0029] The sacrificial glass wafer is of the same type as the vapor cell glass wafer used for bonding to silicon, thus allowing current to flow through the mobile ions. By using a larger diameter for the sacrificial wafer, the distance between the high voltage electrode and the top surface of the silicon wafer close to ground potential is increased. This makes it possible to bring the junction at a higher voltage without generating an arc. Further, since sodium ions can enter the sacrificial glass wafer, there is minimal excess sodium that would otherwise accumulate on the upper glass wafer of the vapor cell. This eliminates the pitting corrosion that would otherwise be seen on a glass wafer and makes the optical path through the glass clearer. Further details on the sacrificial glass wafer are described below with respect to FIG.

  [0030] FIG. 2 illustrates one embodiment of a vapor cell die 200 for a CSAC physical package formed on a wafer layer. The vapor cell die 200 includes a silicon substrate 205, and a first chamber 210, a second chamber 220, and at least one connection path 215 are formed in the silicon substrate 205. Chambers 210, 220 and path 215 are sealed within the vapor cell die 200 between glass wafers (such as glass wafers 132, 134) using the anodic bonding described above.

  [0031] For the embodiment shown in FIG. 2, chamber 210 forms part of the optical path for the physical package and needs to be maintained free of contaminants and deposits. Rubidium or other alkali metal (generally indicated at 235) is deposited in the chamber 220 as a liquid or solid. The connection path 215 establishes a “winding path” (generally indicated at 230) for alkali metal vapor molecules to travel from the second chamber 220 to the first chamber 210. Due to the dynamics of gas molecules, alkali metal vapor molecules do not flow smoothly through the path 215, but often bounce off the walls of the path 215 and become immobile. In one embodiment, the second chamber 220 is separated from the path 215 except for the shallow trench 245 to further slow the alkali metal vapor from the second chamber 220.

  [0032] Further details regarding the fabrication of vapor cells suitable for use in CSAC physics packages are described in US patent application Ser. No. 12 / 873,441, filed Sep. 1, 2010. This application is published as US Patent Application Publication No. 2011/0187464, the disclosure of which is incorporated herein by reference.

  [0033] As previously discussed, anodic bonding joints begin at a position where they are initially in contact between wafers and spread as the surfaces approach each other at electrostatic potential. Thus, if there is a delay in the front surface of the bonding for each region, a pressure difference may occur when the front surface of the bonding moves together and there is no path for gas to exit between the wafers. As a result, the uniformity of the buffer gas may be insufficient in the manufactured vapor cell.

  [0034] Furthermore, the use of materials with low melting temperatures, such as Rb, requires that bonding be performed at the lowest possible temperature, otherwise the bonding surface can be contaminated by the generated steam. There is. Therefore, in order to be able to form a bond as quickly as possible, it is necessary to apply a higher voltage as the wafer gets hot. As a result, the steam cell can be sealed at different times and therefore at different temperatures, which can cause pressure differences within the fabricated steam cell. The problem of insufficient buffer gas uniformity within the fabricated vapor cell can be solved using the techniques discussed below.

  [0035] In one approach, vent channels are formed in the surface of the silicon wafer to provide a path for gas to escape to the periphery of the wafer during anodic bonding. This technique is shown in FIG. FIG. 3 shows a wafer 300 that produces a vapor cell for use in a CSAC. Wafer 300 includes a plurality of vapor cell dies 302 and vent channels 304 surrounding and interconnected with vapor cell dies 302. The vapor cell die 302 and the vent channel 304 are located in the internal surface region 306 of the wafer 300. Vent channel 304 can be formed by the same process used to form vapor cell die 302.

  [0036] The vent channel 304 provides at least one path for the gas from each vapor cell die to travel outside the outer periphery 308 of the wafer 300. The vent channel 304 allows the gas to the inner surface region 306 to be in a pressure equilibrium that is substantially continuous with the gas outside the outer periphery 308 while anodizing the glass wafer to both sides of the wafer 300.

  [0037] In another approach to increasing gas pressure uniformity, the anodic bonding process is modified to constantly increase the pressure as the temperature (measured in Kelvin or absolute) increases. In this approach, anodic bonding of a first wafer, such as a silicon wafer, increases the temperature of the first wafer at a predetermined rate while anodically bonding the first wafer to a second wafer, such as a glass wafer. Implemented by: A silicon wafer has a plurality of dies, each die having at least one chamber. As the temperature increases during anodic bonding, the gas pressure between the first wafer and the second wafer also increases at a predetermined rate.

  [0038] For example, in one implementation, as the temperature increases from about 150 ° C. (423 ° K) to about 250 ° C. (523 ° K) during anodic bonding, the pressure increases from about 100 Torr to about 600 Torr. In another example, the pressure start value can be about 100-300 torr and the end value can be about 500-600 torr.

  [0039] The above approaches can also be combined, thus utilizing a vent channel in the wafer surface with increased pressure will result in a higher vapor cell that is lately sealed during processing and therefore at a higher temperature. It is also possible to have gas pressure. When cooled to room temperature, the vapor cell sealed at a higher temperature will have a lower pressure than the vapor cell sealed at a lower temperature. If the gas pressure is higher, the late sealed steam cell can be compensated so that the final pressure of all the steam cells is approximately the same at room temperature. By keeping the pressure to temperature ratio constant, n (molar density of gas in the cell) is maintained constant throughout the wafer according to the ideal gas law.

  [0040] FIG. 4 shows a CSAC physical package 400 according to another embodiment. The physical package 400 includes a housing 402 that houses the various mechanical and electronic components of the CSAC. These components can be fabricated as wafer level microelectromechanical system (MEMS) devices and then assembled in the physical package 400. Typically, CSAC components within the physics package 400 include a laser die 410, such as a vertical cavity surface emitting laser (VCSEL), a quarter wave plate 420 in optical communication with the laser die 410, and a quarter wave plate 420. And a first optical detector 440 in optical communication with the vapor cell 430. Laser beam 412 emitted from laser die 410 is directed to travel through quarter wave plate 420 and vapor cell 430 to optical detector 440 during CSAC operation.

  The housing 402 includes a body 403 that defines a cavity 404 that holds the components of the physical package 400. The housing 402 also includes a lid 405 that is configured to fit over the cavity 404 to seal components within the cavity 404. Solder 406 can be used to seal lid 405 to body 403. The cavity 404 is defined by a side surface 407 and a bottom surface 411 within the body 403. The side 407 has a lower step 408 and an upper step 409, which, together with the bottom surface 411, support the various components of the CSAC in an elevated position, as will be described further below. The housing 402 can be made from a ceramic material, such as, for example, a high temperature cofire ceramic (HTCC) material.

  [0042] The various components of the physical package 400 are positioned at different levels within the housing 402 by a set of scaffolding structures. These scaffold structures typically include a membrane such as a tether suspended between frames and a reinforcing member such as a die attached to the membrane. For example, the frame and the reinforcing member can be made of silicon, and the membrane can be made of polyimide.

  [0043] As shown in FIG. 4, the lower scaffold structure 450 is attached to the bottom surface 411 in the main body 403. Lower scaffold structure 450 includes a scaffold die 452 coupled to a tether 454 that is attached to a frame 455. The laser die 410 is attached to the top surface of the die 452, along with other electronic components including a second optical detector 442 and a resistor 444 such as a surface mount technology (SMT) resistor. Lower scaffold structure 450 and components thereon are electrically connected to body 403 by a plurality of wire bonds 456 connected to respective pads on lower step 408.

  [0044] The intermediate scaffold structure 460 includes a scaffold die 462 coupled to a tether 464 that is attached to a frame 465. The scaffold die 462 has an opening that allows the laser beam 412 to pass through. The intermediate scaffold structure 460 has a tilt feature 466 on which the quarter-wave plate 420 is attached with an adhesive or the like. As shown in FIG. 4, the quarter wave plate 420 can be mounted on the tilt feature 466 at a preselected tilt angle with respect to the optical path of the laser beam 412. The intermediate scaffold structure 460 has an upper surface 467, and a vapor cell 430 is attached on the upper surface 467 by an adhesive or the like. The intermediate scaffold structure 460 is attached to the lower surface 472 of the spacer 470 by an adhesive such as epoxy or other suitable attachment method.

  [0045] The upper scaffold structure 480 includes a scaffold die 482 positioned on the spacer 470 and coupled to a tether 484 attached to the frame 485. Optical detector 440 is attached to die 482 above vapor cell 430. The vapor cell 430 is also attached to the die 482 by a plurality of solder balls 484 that maintain the optical detector 440 and the vapor cell 430 spaced from each other. The upper scaffold structure 480 is attached to the upper surface 474 of the spacer 470 by an adhesive such as epoxy or other suitable attachment method.

  [0046] The spacer 470 may be in the form of a washer that defines an opening 476 in which the vapor cell 430 is located. Spacer 470 includes interconnect wiring 477 that provides electrical contacts to upper scaffold structure 480 and intermediate scaffold structure 460. The spacer 470 also includes a magnetic coil winding 478 that provides a bias magnetic field to the vapor cell 430. The spacer 470 is attached to the upper step 409 of the housing 402 by an adhesive such as epoxy. A plurality of metal stud bumps 479, such as gold stud bumps, provide an electrical connection from the spacer 470 to the housing 402 and the scaffold structure 460, 480. The spacer 470 can be made from a ceramic material, such as a low temperature cofire ceramic (LTCC) material.

  [0047] The vapor cell 430 includes a pair of optically transparent glass wafers including a lower glass wafer 432 and an upper glass wafer 434, the lower glass wafer 432 and the upper glass wafer 434 being a substrate such as a silicon wafer 436. Anodized on both sides. At least one chamber 438 in the vapor cell 430 provides an optical path for the laser beam 412 between the laser die 410 and the optical detector 440.

  [0048] To make the vapor cell 430 and then assemble it in the housing 402, first the lower glass wafer 432 is anodically bonded to the bottom side of the substrate 436, and then rubidium or other alkali metal is introduced into the chamber 438. Deposit. Next, the upper glass wafer 434 is anodically bonded to the opposite side of the substrate 436 to form a vapor cell 430. The bonding process is performed with wafer glass 432, 434 and silicon wafer 436 under high vacuum, or optionally backfilled with buffer gas. When the bonding is complete and the vapor cell 430 is sealed, the alkali metal and optional buffer gas are trapped within the chamber 438.

  [0049] As discussed above, anodic bonding of glass wafers can be enhanced by using a sacrificial glass wafer inserted between the upper glass wafer of the vapor cell and the high voltage source. FIG. 5 shows a wafer configuration 500 used in an improved anodic bonding technique. A vapor cell 502 is partially formed and includes a first wafer 504 such as a silicon wafer and a second wafer 506 such as a glass wafer anodically bonded to one side of the first wafer 504. On the opposite side of the first wafer 504, a third wafer 508 such as a glass wafer is positioned. As shown in FIG. 5, the first wafer 504, the second wafer 506, and the third wafer 508 all have substantially the same diameter D-1.

  [0050] A sacrificial wafer 510, such as a sacrificial glass wafer, is inserted between the third wafer 508 and the metallized bonding plate 512 connected to a high voltage source. The sacrificial wafer 510 has a diameter D-2 that is larger than the diameter D-1. By using a larger diameter for the sacrificial wafer, the distance from the exposed portion 514 of the metallized bonding plate 512 to the bonding surface of the silicon wafer near ground potential is increased. The diameter D-2 of the sacrificial wafer 510 is large enough to prevent arcing when the third wafer 508 is anodically bonded to the first wafer 504.

  [0051] FIG. 6 illustrates one embodiment of a vapor cell die 600 for a CSAC physics package formed on a wafer layer. The vapor cell die 600 includes a substrate 605 such as a silicon substrate, and a first chamber 610, a second chamber 615, and at least one connection path 620 are formed in the substrate 605. Chambers 610, 615 and path 620 can be sealed within the vapor cell die 600 between glass wafers using the anodic bonding described above. The first chamber 610 constitutes a part of an optical path for CSAC. Connection path 620 establishes a “winding path” for alkali metal vapor molecules to travel from second chamber 615 to first chamber 610.

  [0052] As described above, vent channels can be formed in the surface of the silicon wafer to provide a path for gas to escape to the outer periphery of the wafer during anodic bonding. FIG. 7 shows another embodiment of this approach. In this embodiment, a silicon wafer 700 is used to fabricate the vapor cell. Wafer 700 includes a plurality of vapor cell dies 702 and vent channels 704 surrounding and interconnected with vapor cell dies 702. The vapor cell die 702 and the vent channel 704 are located in the internal surface region 706 of the wafer 700. Vent channel 704 can be formed by the same process used to form vapor cell die 702.

  [0053] The vent channel 704 provides a plurality of paths for the gas from each vapor cell die to travel outside the outer periphery 708 of the wafer 700. Vent channel 704 allows a gas in internal surface region 706 and a gas outside outer periphery 708 to be in a substantially continuous pressure equilibrium while anodically bonding the glass wafer to both sides of wafer 700.

Exemplary Embodiment
[0054] Example 1 includes a method of fabricating one or more vapor cells, wherein the method includes one in a first wafer having an inner surface region and an outer periphery and having a first diameter. Or forming a plurality of vapor cell dies, anodically bonding a second wafer having a second diameter to the first surface of the first wafer on the vapor cell dies, and on the vapor cell die, Positioning a third wafer having a third diameter on a second surface of the first wafer opposite to the second wafer; and on the third wafer, the first, Placing a sacrificial wafer having a diameter greater than the second and third diameters, placing a metallized bond plate on the sacrificial wafer, and applying a voltage to the metallized bond plate while the sacrificial wafer is in place. Is applied, the first A third wafer to the second surface of Eha and a step of anodic bonding.

[0055] Example 2 includes the method described in Example 1, wherein the first wafer constitutes a silicon wafer and the second and third wafers each constitute a glass wafer.
[0056] Example 3 includes the method of any of Examples 1 and 2, wherein the sacrificial wafer comprises a glass wafer.

  [0057] Example 4 includes the method of any of Examples 1-3, wherein the sacrificial wafer diameter is sufficient to prevent arcing when a voltage is applied to the metallized bonded plate. It ’s so big.

  [0058] Example 5 includes the method of any of Examples 1-4, further comprising forming one or more interconnected vent channels in the first wafer, and The vent channel provides at least one path for gas from one or more vapor cell dies to travel outside the outer circumference of the first wafer.

  [0059] Example 6 includes the method of Example 5, wherein the gas in the inner surface area of the first wafer is anodic bonded by the vent channel to the first and second wafers. And a gas outside the outer periphery of the first wafer can be brought into a substantially continuous pressure equilibrium state.

[0060] Example 7 includes the method described in any of Examples 1-6, wherein the one or more vapor cells are configured for a physical package of a chip scale atomic clock.
[0061] Example 8 includes the method of any of Examples 1-7, wherein the one or more vapor cell dies each comprise a substrate, the substrate comprising a first chamber and a second chamber. And at least one connection path between the first chamber and the second chamber.

[0062] Example 9 includes the method of any of Examples 1-8, wherein the temperature of the first wafer increases at a predetermined rate during anodic bonding.
[0063] Example 10 includes the method described in Example 9, wherein the gas pressure increases at a predetermined rate as the temperature increases.

[0064] Example 11 includes the method described in Example 10, wherein the gas pressure is increased from about 100 torr to about 600 torr during anodic bonding.
[0065] Example 12 includes a wafer configuration that produces a vapor cell comprising a plurality of vapor cell dies, a first wafer having an inner surface region and an outer periphery, and having a first diameter. A second wafer having a second diameter substantially the same as the first diameter is anodically bonded onto the first surface of the first wafer on the vapor cell die. On the vapor cell die, a third wafer having a third diameter substantially the same as the first and second diameters on a second surface of the first wafer opposite the second wafer. Be placed. A sacrificial wafer having a diameter greater than the first, second, and third diameters is disposed on the third wafer. The diameter of the sacrificial wafer is large enough to prevent arcing when the third wafer is anodically bonded to the first wafer.

  [0066] Example 13 includes the wafer configuration described in Example 12, wherein the first wafer constitutes a silicon wafer and the second and third wafers each constitute a glass wafer.

[0067] Example 14 includes the wafer configuration described in any of Examples 12 and 13, wherein the sacrificial wafer comprises a glass wafer.
[0068] Example 15 includes the wafer configuration of any of Examples 12-14, further comprising a plurality of interconnected vent channels in the first wafer, the vent channels providing a vapor cell die. At least one path is provided for the gas from to travel outside the outer circumference of the first wafer.

  [0069] Example 16 includes the wafer configuration described in Example 15, wherein the inner surface area of the first wafer when the second and third wafers are anodically bonded to the first wafer by the vent channel. And the gas outside the outer periphery of the first wafer can be brought into a substantially continuous pressure equilibrium state.

[0070] Example 17 includes the wafer configuration of any of Examples 12-16, wherein a sacrificial wafer is disposed between the third wafer and the metallized bonding plate.
[0071] Example 18 includes the wafer configuration described in any of Examples 12-17, and the vapor cell die is configured for a physical package of a chip scale atomic clock.

  [0072] Example 19 includes a wafer configuration as described in any of Examples 12-18, each of the vapor cell dies comprising a substrate, the substrate comprising a first chamber, a second chamber, and a first chamber At least one connection path between the first chamber and the second chamber.

  [0073] Example 20 includes a method of fabricating a plurality of vapor cells, the method comprising forming a plurality of vapor cell dies in a silicon wafer having a first diameter, and a silicon wafer on the vapor cell dies. Anodic bonding a first glass wafer having a second diameter substantially the same as the first diameter to the first surface of the silicon wafer, and on the vapor cell die, the first glass wafer of the silicon wafer is Positioning a second glass wafer having a third diameter substantially the same as the first and second diameters on an opposite second surface; and on the second glass wafer, Placing a sacrificial glass wafer having a diameter greater than the second and third diameters, placing a metallized bonding plate on the sacrificial glass wafer, and placing the sacrificial glass wafer in place Anodic bonding a second glass wafer to the second surface of the silicon wafer when a voltage is applied to the metallized bonding plate during the process, wherein the diameter of the sacrificial glass wafer is Large enough to prevent arcing when voltage is applied.

[0074] The present invention may be embodied in other specific forms without departing from the essential characteristics thereof. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
[Form 1]
A method of making one or more steam cells, comprising:
Forming one or more vapor cell dies in a first wafer having an inner surface area and an outer periphery, wherein the first wafer has a first diameter;
Anodically bonding a second wafer to a first surface of the first wafer over the vapor cell die, the second wafer having a second diameter;
Positioning a third wafer on the vapor cell die on a second surface of the first wafer opposite the second wafer, wherein the third wafer is a third wafer; A step having a diameter;
Disposing a sacrificial wafer on the third wafer, the sacrificial wafer having a diameter greater than the first, second, and third diameters;
Placing a metallized bonding plate on the sacrificial wafer;
Anodic bonding the third wafer to the second surface of the first wafer when a voltage is applied to the metallized bonding plate while the sacrificial wafer is in place. .
[Form 2]
The method of embodiment 1, further comprising the step of forming one or more interconnected vent channels in the first wafer, wherein the vent channels cause gas from the one or more vapor cell dies. At least one path is provided to travel outside the outer circumference of the first wafer, and the second and third wafers are anodically bonded to the first wafer by the vent channel. A method that allows gas to the inner surface region of one wafer to be in a pressure equilibrium that is substantially continuous with gas outside the outer periphery of the first wafer.
[Form 3]
A wafer configuration for producing a vapor cell,
A first wafer comprising a plurality of vapor cell dies, wherein the first wafer has an inner surface region and an outer periphery and has a first diameter;
A second wafer anodically bonded to the first surface of the first wafer on the vapor cell die, the second wafer having a second diameter substantially the same as the first diameter;
A third wafer disposed on a second surface of the first wafer opposite to the second wafer on the vapor cell die, wherein the third wafer is substantially the same as the first and second diameters; A third wafer having the same third diameter above;
A sacrificial wafer disposed on the third wafer, the sacrificial wafer having a diameter greater than the first, second, and third diameters;
A metallized bonding plate on the sacrificial wafer,
A wafer configuration wherein the diameter of the sacrificial wafer is large enough to prevent arcing when the third wafer is anodically bonded to the first wafer.

100 CSAC physical package 102 housing 104 bottom surface 106 top surface 110 laser die 112 laser beam 120 quarter wave plate 130 vapor cell 132 wafer 134 wafer 136 substrate 138 chamber 140 optical detector 150 lower scaffold 152 lower layer 154 intermediate layer 156 upper layer 160 upper scaffold structure 200 vapor cell die 205 silicon substrate 210 first chamber 215 connection path 220 second chamber 230 tortuous path 235 rubidium or other alkali metal 245 shallow trench 300 wafer 302 vapor cell die 304 vent channel 306 internal surface region 308 Peripheral 400 CSAC physical package 402 Case 403 Main body 404 Cavity 405 Lid 406 Solder 407 Side 408 Lower step 409 Upper step 410 Laser die 411 Bottom surface 412 Laser beam 420 Quarter wave plate 430 Vapor cell 432 Lower glass wafer 434 Upper glass wafer 436 Silicon wafer 438 Chamber 440 First optical detector 442 Second optical detector 444 Resistor 450 Lower scaffolding structure 452 Scaffolding die 454 Tether 455 Frame 456 Wire bond 460 Intermediate scaffolding structure 462 Scaffolding die 464 Tether 465 Frame 466 Inclined feature 467 Upper surface 470 Spacer 472 Lower surface 474 Upper surface 476 Opening 479 Magnetic wiring 479 Interconnection wiring 479 480 Upper scaffold structure 482 Scaffolding die 484 Tether 485 Frame 500 Wafer configuration 502 Vapor cell 504 First wafer 506 Second wafer 08 third wafer 510 sacrificial wafer 512 metallization bonding plate 514 exposed portion of the 600 steam cell dies 605 substrate 610 first chamber 615 second chamber 620 connection path 700 silicon wafer 702 vapor cell die 704 venting channels 706 inside surface region 708 periphery

Claims (3)

A method of making one or more steam cells, comprising:
Forming one or more vapor cell dies in a first wafer having an inner surface area and an outer periphery, wherein the first wafer has a first diameter;
Anodically bonding a second wafer to a first surface of the first wafer over the vapor cell die, the second wafer having a second diameter;
Positioning a third wafer on the vapor cell die on a second surface of the first wafer opposite the second wafer, wherein the third wafer is a third wafer; A step having a diameter;
Disposing a sacrificial wafer on the third wafer, the sacrificial wafer having a diameter greater than the first, second, and third diameters;
Placing a metallized bonding plate on the sacrificial wafer;
Anodic bonding the third wafer to the second surface of the first wafer when a voltage is applied to the metallized bonding plate while the sacrificial wafer is in place. .   The method of claim 1, further comprising forming one or more interconnected vent channels in the first wafer, the vent channels from the one or more vapor cell dies. At least one path is provided for gas to travel outside the outer periphery of the first wafer, while the second and third wafers are anodic bonded to the first wafer by the vent channel, A method that allows the gas to the inner surface region of the first wafer to be in a pressure equilibrium that is substantially continuous with the gas outside the outer periphery of the first wafer. A first wafer, a second wafer anodically bonded to the first surface of the first wafer, and an anodically bonded to the second surface of the first wafer opposite the second wafer A wafer configuration used to fabricate a vapor cell having a third wafer ,
A first wafer comprising a plurality of vapor cell dies, have an inner surface area and the outer circumference, said first wafer having a first diameter,
A second wafer that is anodically bonded to the first surface of the first wafer on the vapor cell dies, the second having the first diameter substantially the same second diameter Wafers,
On the vapor cell dies, a third wafer, which is disposed in front SL on the second surface of the first wafer, said first and second diameter substantially the same third diameter Said third wafer comprising:
A sacrificial wafer disposed on the third wafer, the sacrificial wafer having a diameter greater than the first, second, and third diameters;
A metallized bonding plate on the sacrificial wafer,
A wafer configuration wherein the diameter of the sacrificial wafer is large enough to prevent arcing when the third wafer is anodically bonded to the first wafer.

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