JP6190740B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  2. Description of the Related Art Conventionally, a semiconductor provided with an outer peripheral tapered region formed in a region reaching a depth position exceeding a boundary surface between a p-type semiconductor layer and an n-type semiconductor layer in a region surrounding a mesa region on the first main surface side of a semiconductor substrate An apparatus is known (for example, refer to Patent Document 1).

FIG. 10 is a diagram for explaining a conventional semiconductor device 900. In FIG. 10, reference numeral 950 denotes an anode electrode layer.
FIG. 11 is a diagram for explaining a conventional method of manufacturing a semiconductor device. FIG. 11A to FIG. 11D are process diagrams. In FIG. 11, reference numeral 926 denotes an oxide film.

  In this specification, the main surface on the side where the second semiconductor layer is formed is referred to as a first main surface, and the main surface on the side where the third semiconductor layer is formed is referred to as a second main surface.

As shown in FIG. 10, the conventional semiconductor device 900 is formed on the first main surface side of the n ⁻ type silicon substrate body 912 (first semiconductor layer) and the n ⁻ type silicon substrate body 912 containing n-type impurities. A p ⁺ -type anode layer 914 (second semiconductor layer) containing a p-type impurity and an n ⁻ type silicon substrate main body 912 formed on the second main surface side and having a higher concentration of n than the n ⁻ type silicon substrate main body 912. A semiconductor substrate 910 having an n ⁺ -type cathode layer 916 (third semiconductor layer) containing a type impurity, and an n ⁻ -type silicon substrate body 912 in a region surrounding the mesa region 922 on the first main surface side of the semiconductor substrate 910. And an outer peripheral taper region 920 formed in a region reaching a depth position exceeding a boundary surface (pn junction surface) between the p ⁺ type anode layer 914 and the second main surface side of the semiconductor substrate 910, and an n ⁺ type Caso And a cathode electrode layer 960 to form an ohmic junction with the de layer 916.

  In the conventional semiconductor device 900, a passivation film 940 for protecting the pn junction surface is formed in the outer peripheral taper region 920.

  According to the conventional semiconductor device 900, since the passivation film 940 for protecting the pn junction surface is formed in the outer peripheral taper region 920, a highly reliable semiconductor device is obtained.

  Such a semiconductor device 900 is manufactured by the following manufacturing method (conventional semiconductor device manufacturing method).

A conventional method for manufacturing a semiconductor device includes an n ⁻ -type silicon substrate body 912 (first semiconductor layer) containing n-type impurities and a p-type impurity formed on the first main surface side of the n ⁻ -type silicon substrate body 912. P ⁺ -type anode layer 914 (second semiconductor layer) and n ⁻ -type silicon substrate body 912 formed on the second main surface side and containing n-type impurities at a higher concentration than n ⁻ -type silicon substrate body 912. A semiconductor substrate preparation step (see FIG. 11A) for preparing a semiconductor substrate 910 having an n ⁺ -type cathode layer 916 (third semiconductor layer), and a mesa region 922 on the first main surface side of the semiconductor substrate 910. A groove forming step (see FIG. 11B) for forming a groove 928 having a depth exceeding the boundary surface between the n ⁻ type silicon substrate body 912 and the p ⁺ type anode layer 914 in the surrounding region, and the inside of the groove 928 Passive A passivation film forming step of forming a passivation film 940 (see FIG. 11 (c).), On the surface of the second main surface side whole area of the semiconductor substrate 910, an ohmic junction with the n ⁺ -type cathode layer 916 An electrode layer forming step for forming the cathode electrode layer 960 (see FIG. 11C) and a semiconductor substrate separating step for manufacturing the semiconductor device 900 by separating the semiconductor substrate 910 along the groove 928 (FIG. 11D). )) In this order.

  In the electrode layer forming step, the anode electrode layer 950 is formed on a part of the first main surface side surface of the semiconductor substrate 910 in the mesa region 922. In the semiconductor substrate separation step, the semiconductor substrate 910 is separated by dicing from the first main surface side.

  According to the conventional method for manufacturing a semiconductor device, the semiconductor device 900 described above can be manufactured.

JP 2010-212316 A

  In recent years, in the field of semiconductor device technology, there has been a demand for a semiconductor device having a high temperature reverse bias tolerance and a high surge withstand voltage during forward bias.

  Accordingly, an object of the present invention is to provide a semiconductor device having a high high temperature reverse bias tolerance and a high surge withstand voltage during forward bias. Moreover, it aims at providing the manufacturing method of the semiconductor device which manufactures such a semiconductor device.

[1] A semiconductor device of the present invention includes a first semiconductor layer containing a first conductivity type impurity, a second conductivity type formed on the first main surface side of the first semiconductor layer and having a conductivity type opposite to the first conductivity type impurity. A second semiconductor layer containing a conductivity type impurity, and a third semiconductor layer formed on the second main surface side of the first semiconductor layer and containing a first conductivity type impurity at a higher concentration than the first semiconductor layer. And a semiconductor substrate having a semiconductor substrate and a region surrounding the first mesa region on a first main surface side of the semiconductor substrate, in a region reaching a depth position exceeding a boundary surface between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the first outer peripheral tapered region and a region surrounding the second mesa region formed at a position corresponding to the first mesa region on the second main surface side of the semiconductor substrate. Formed in the region reaching the depth position exceeding the boundary surface with the three semiconductor layers An outer peripheral tapered region, a second Mesa region, and a second outer peripheral tapered region formed on a surface of the semiconductor substrate, forming a Schottky junction with the first semiconductor layer, and the third semiconductor layer And an electrode layer forming an ohmic junction with the electrode.

[2] In the semiconductor device of the present invention, the area of the surface on the first main surface side of the semiconductor substrate in the second mesa region is the surface area on the second main surface side of the semiconductor substrate in the first mesa region. It is preferable that it is larger than the area.

[3] In the semiconductor device of the present invention, it is preferable that an opening width of the second outer peripheral tapered region is in a range of 50 to 70% of an opening width of the first outer peripheral tapered region.

  In the present specification, “the opening width of the first (second) outer peripheral tapered region” means the first main surface side surface of the semiconductor substrate in the first mesa region (second mesa region) in plan view. The width from the end of (second main surface side surface) to the outer edge of the semiconductor device.

[4] In the semiconductor device of the present invention, the thickness of the first semiconductor layer between the deepest portion of the first outer peripheral taper region and the deepest portion of the second outer peripheral taper region may be 80 μm or less. preferable.

[5] In the semiconductor device of the present invention, the semiconductor device is preferably resin-sealed.

[6] A method of manufacturing a semiconductor device according to the present invention includes a first semiconductor layer containing a first conductivity type impurity, a conductivity type opposite to the first conductivity type impurity formed on the first main surface side of the first semiconductor layer. A second semiconductor layer containing the second conductivity type impurities, and a third semiconductor layer formed on the second main surface side of the first semiconductor layer and containing the first conductivity type impurities at a higher concentration than the first semiconductor layer. A semiconductor substrate preparation step for preparing a semiconductor substrate having a semiconductor layer, and a boundary surface between the first semiconductor layer and the second semiconductor layer in a region surrounding the first mesa region on the first main surface side of the semiconductor substrate. And a region surrounding the second mesa region formed at a position corresponding to the first mesa region on the second main surface side of the semiconductor substrate. And a depth exceeding a boundary surface between the first semiconductor layer and the third semiconductor layer. A groove forming step including a second groove forming step for forming the second groove, and a Schottky junction with the first semiconductor layer on the surface of the semiconductor substrate in the second mesa region and the second groove. Forming an electrode layer for forming an ohmic junction with the third semiconductor layer, and separating the semiconductor substrate along the first groove and the second groove It includes a semiconductor substrate separation step for manufacturing a semiconductor device in this order.

[7] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first groove forming step and the second groove forming step are collectively performed in the groove forming step.

[8] In the method for manufacturing a semiconductor device of the present invention, it is preferable that in the semiconductor substrate separation step, the semiconductor substrate is separated by braking without making a cut.

[9] In the method for manufacturing a semiconductor device of the present invention, it is preferable that the semiconductor substrate is separated by dicing from the second main surface side in the semiconductor substrate separation step.

[10] In the method for manufacturing a semiconductor device of the present invention, in the groove forming step, the first groove and the second groove are formed such that an opening width of the second groove is narrower than an opening width of the first groove. It is preferable to form a groove.

[11] In the method for manufacturing a semiconductor device of the present invention, it is preferable that the second groove is formed by etching in the second groove forming step.

[12] In the method for manufacturing a semiconductor device of the present invention, in the groove forming step, the thickness of the first semiconductor layer between the deepest portion of the first groove and the deepest portion of the second groove is 80 μm. It is preferable to form the first groove and the second groove so as to be as follows.

  According to the semiconductor device of the present invention, since the electrode layer that is formed on the surface of the semiconductor substrate in the second outer peripheral tapered region and forms a Schottky junction with the first semiconductor layer is provided, Electrons near the boundary between the semiconductor layer and the first outer peripheral tapered region (see the region surrounded by the broken line A in FIG. 6) are compared with the conventional semiconductor device 900 (see FIG. 6B). It becomes difficult to move to the second main surface side of the base (see FIG. 6A). Therefore, since the formation of the inversion layer can be suppressed in the vicinity of the boundary, an increase in leakage current can be suppressed, and as a result, a semiconductor device having a higher high temperature reverse bias tolerance than the conventional semiconductor device 900 is obtained.

  In addition, according to the semiconductor device of the present invention, since the electrode layer formed on the surface of the semiconductor substrate in the second outer peripheral taper region and forming the Schottky junction with the first semiconductor layer is provided, the electrode layer and the third The area of the “region for forming an ohmic junction” with the semiconductor layer becomes narrower than that of the conventional semiconductor device 900 (see FIG. 7B) (see FIG. 7A). Therefore, a straight line connecting the end portion on the first main surface side in the first mesa region to the end portion of the “region for forming an ohmic junction” (end portion of the third semiconductor layer in the second mesa region) and the semiconductor substrate Is smaller than that of the conventional semiconductor device 900 (see FIG. 7). Therefore, during forward bias, the current path of the current flowing from the end on the first main surface side in the first mesa region to the end of the “region for forming the ohmic junction” extends from the first outer tapered region to the conventional semiconductor device 900. (See the region surrounded by the broken line B in FIG. 7), the surge withstand voltage at the time of forward bias is improved as compared with the conventional semiconductor device 900.

  Furthermore, according to the semiconductor device of the present invention, the second outer peripheral tapered region is formed in the region surrounding the second mesa region formed at the position corresponding to the first mesa region. The thickness of the first semiconductor layer (remaining silicon thickness) between the deepest portion of the first outer peripheral taper region and the deepest portion of the second outer peripheral tapered region is reduced, and the semiconductor substrate can be easily separated in the process of manufacturing the semiconductor device.

  According to the method for manufacturing a semiconductor device of the present invention, an electrode layer that forms an electrode layer that forms a Schottky junction with the first semiconductor layer on the surface of the semiconductor substrate (the inner surface of the second groove) in the second groove. Since the manufacturing process is included, in the manufactured semiconductor device, electrons near the boundary between the first semiconductor layer and the first outer peripheral tapered region (see the region surrounded by the broken line A in FIG. 6A) are reversed. At the time of bias, compared to the conventional semiconductor device 900, it becomes difficult to move to the second main surface side of the semiconductor substrate. Therefore, since the formation of the inversion layer can be suppressed in the vicinity of the boundary, an increase in leakage current can be suppressed, and as a result, a semiconductor device having a higher high-temperature reverse bias tolerance than the conventional semiconductor device 900 can be manufactured.

  In addition, the method for manufacturing a semiconductor device of the present invention includes an electrode layer forming step of forming an electrode layer that forms a Schottky junction with the first semiconductor layer on the surface of the semiconductor substrate in the second groove. In the manufactured semiconductor device, the area of the “region for forming an ohmic junction” between the electrode layer and the third semiconductor layer is smaller than that of the conventional semiconductor device 900 (see FIG. 7B) (see FIG. 7). 7 (a).) Therefore, a straight line connecting the end portion on the first main surface side in the first mesa region to the end portion of the “region for forming an ohmic junction” (end portion of the third semiconductor layer in the second mesa region) and the semiconductor substrate Is smaller than that of the conventional semiconductor device 900 (see FIG. 7). Therefore, in the manufactured semiconductor device, during forward bias, the current path of the current flowing from the end on the first main surface side in the first mesa region to the end of the “region for forming the ohmic junction” is the first outer periphery. The taper region is farther than the conventional semiconductor device 900 (see the region surrounded by the broken line B in FIG. 7). Therefore, it is possible to manufacture a semiconductor device having a surge withstand voltage at the time of forward bias improved compared to the semiconductor device 900.

  Furthermore, according to the method of manufacturing a semiconductor device of the present invention, in the second groove forming step, the second groove is formed in a region surrounding the second mesa region formed at a position corresponding to the first mesa region. The thickness (remaining silicon thickness) of the first semiconductor layer between the deepest portion of the first groove and the deepest portion of the second groove is reduced, and the semiconductor substrate is easily separated in the semiconductor substrate separation step.

1 is a diagram for explaining a semiconductor device 100 according to a first embodiment. 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is a top view shown in order to demonstrate groove | channel formation process S20. FIG. 4 is a diagram for explaining a high temperature reverse bias tolerance of the semiconductor device 100 according to the first embodiment. 6 is a diagram for explaining a surge withstand voltage at the time of forward bias in the semiconductor device 100 according to the first embodiment. FIG. FIG. 6 is a diagram for explaining a semiconductor device 102 according to a second embodiment. It is a figure shown in order to demonstrate the semiconductor device 800 which concerns on a comparative example. 1 is a diagram illustrating a conventional semiconductor device 900. FIG. It is a figure shown in order to demonstrate the manufacturing method of the conventional semiconductor device.

  Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device of the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. Configuration of Semiconductor Device 100 According to First Embodiment FIG. 1 is a diagram for explaining the semiconductor device 100 according to the first embodiment.

  As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 110, a first outer peripheral taper region 120, a second outer peripheral taper region 130, a passivation film 140, an anode electrode layer 150, and a cathode. An electrode layer 160.

The semiconductor substrate 110 includes an n ⁻ type silicon substrate body 112 (first semiconductor layer) containing n-type impurities and a p ⁺ type formed on the first main surface side of the n ⁻ type silicon substrate body 112 and containing p type impurities. the anode layer 114 (second semiconductor layer), and, n ^- -type silicon substrate is formed on the second main surface side of the main body 112 n ^- -type than the silicon substrate main body 112 containing a high concentration n-type impurity of the n ⁺ -type cathode The layer 116 (third semiconductor layer) is included.

The thickness of the semiconductor substrate 110 is, for example, 240 μm. The thickness of the n ⁻ -type silicon substrate body 112 is, for example, 140 μm, the thickness of the p ⁺ -type anode layer 114 is, for example, 60 μm, and the thickness of the n ⁺ -type cathode layer 116 is, for example, 40 μm.

The impurity concentration of the n ⁻ type silicon substrate main body 112 is, for example, 1 × 10 ¹⁴ cm ⁻³ . The surface impurity concentration of the n ⁺ -type cathode layer 116 is, for example, 1 × 10 ²⁰ cm ⁻³ . The surface impurity concentration of the p ⁺ -type anode layer 114 is, for example, 1 × 10 ²⁰ cm ⁻³ .

As the semiconductor substrate 110, an n ⁺ type silicon substrate (third semiconductor layer), an n ⁻ type epitaxial layer (first semiconductor layer) containing an n type impurity at a lower concentration than the n ⁺ type silicon substrate, and a p type impurity. P ⁺ -type anode layer (second semiconductor layer) containing p ⁺ -type anode layer, n ⁻ -type epitaxial layer, and n ⁺ -type silicon substrate from the first main surface side toward the second main surface side May be used in this order.

The first outer peripheral taper region 120 exceeds the boundary surface 124 between the n ⁻ type silicon substrate body 112 and the p ⁺ type anode layer 114 in a region surrounding the first mesa region 122 on the first main surface side of the semiconductor substrate 110. It is formed in a region reaching the depth position. The first outer peripheral taper region 120 is formed by etching. The depth of the deepest portion of the first outer peripheral taper region 120 on the basis of the surface on the first main surface side of the semiconductor substrate 110 is 120 to 150% (for example, 72 μm to 90 μm) with respect to the thickness of the p ⁺ -type anode layer 114. ), For example, 80 μm. The opening width of the first outer peripheral tapered region is, for example, in the range of 150 μm to 200 μm.

  In addition, the opening width of the first outer peripheral taper region is set in the range of 150 μm to 200 μm when the opening width of the first outer peripheral taper region is less than 150 μm when the high temperature state occurs during the reverse bias. This is because the leakage current tends to flow due to the depletion layer reaching the deepest portion of the first outer peripheral taper region quickly, and the semiconductor device may be destroyed. This is because the effective area of the device is reduced because the area of the first main surface side surface of the semiconductor substrate 110 in the first mesa region 122 is reduced when the opening width exceeds 200 μm.

The second outer peripheral taper region 130 is formed in a region surrounding the second mesa region 132 formed at a position corresponding to the first mesa region 122 on the second main surface side of the semiconductor substrate 110, and the n ⁻ type silicon substrate body 112. It is formed in a region reaching a depth position exceeding the boundary surface 134 with the n ⁺ -type cathode layer 116. Similarly to the first outer peripheral tapered region 120, the second outer peripheral tapered region 130 is also formed by etching. The second outer peripheral tapered region 130 is formed in the same process as the first outer peripheral tapered region 120 as will be described later.

The depth of the deepest portion of the second outer peripheral taper region 130 with reference to the surface on the second main surface side of the semiconductor substrate 110 (hereinafter simply referred to as “depth of the deepest portion of the second outer peripheral taper region 130”). The same as the depth of the deepest portion of the first outer peripheral tapered region 120 with reference to the surface on the first main surface side of the semiconductor substrate 110 (hereinafter simply referred to as “depth of the deepest portion of the first outer peripheral tapered region 120”). For example, it is 80 μm.
The opening width of the second outer peripheral tapered region 130 is in the range of 50 to 70% of the opening width of the first outer peripheral tapered region 120, for example, in the range of 75 μm to 140 μm.

  When the opening width of the second outer peripheral taper region 130 is less than 50% of the opening width of the first outer peripheral taper region 120, the second main surface side of the semiconductor substrate 110 becomes smaller as the opening width becomes smaller. This is because the depth of the deepest portion of the second outer peripheral tapered region 130 with respect to the surface becomes shallow, so that the residual silicon thickness becomes thick as described later, and it is difficult to divide by braking. Further, when the opening width of the second outer peripheral taper region 130 exceeds 70% of the opening width of the first outer peripheral taper region 120, the second mesa region becomes smaller (the rectification area becomes smaller), so that the allowable current amount It is because there exists a possibility that may become small.

The thickness of the n ⁻ -type silicon substrate body 112 between the deepest portion of the first outer peripheral tapered region 120 and the deepest portion of the second outer peripheral tapered region 130 (hereinafter also referred to as residual silicon thickness) is 80 μm or less. Preferably there is. In the present embodiment, the thickness of the semiconductor substrate 110 is, for example, 240 μm, and the depth of the deepest portion of the first outer peripheral tapered region 120 and the depth of the deepest portion of the second outer peripheral tapered region 130 are both, for example, 80 μm. Therefore, the remaining silicon thickness is, for example, 80 μm. In the process of manufacturing the semiconductor device, the remaining silicon thickness is 40 μm to 40 μm to prevent the semiconductor substrate from being separated when it is unexpected (when a process other than the semiconductor substrate separation process described later is performed). It is preferable that it is 80 micrometers.

  The area of the first main surface side surface of the semiconductor substrate 110 in the second mesa region 132 is larger than the area of the second main surface side surface of the semiconductor substrate 110 in the first mesa region 122.

The passivation film 140 is formed on at least the inner surface of the first outer peripheral tapered region 120 and the surface of the semiconductor substrate 110 in the vicinity thereof. The passivation film 140 protects a boundary surface (pn junction surface) between the n ⁻ type silicon substrate body 112 and the p ⁺ type anode layer 114 and the like. As the passivation film 140, glass, resin, or the like can be used.

  The anode electrode layer 150 is formed on a part of the surface of the semiconductor substrate 110 in the first mesa region. The anode electrode layer 150 is made of metal (for example, nickel). The thickness of the anode electrode layer 150 is, for example, 1 μm.

  The cathode electrode layer 160 is formed on the surface of the semiconductor substrate 110 in the second mesa region 132 and the second outer peripheral tapered region 130. The cathode electrode layer 160 is made of a metal (for example, nickel). The thickness of the cathode electrode layer 160 is 1 μm, for example.

The cathode electrode layer 160 forms a Schottky junction with the n ⁻ type silicon substrate body 112. The cathode electrode layer 160 forms an ohmic junction with the n ⁺ type cathode layer 116.

2. Manufacturing process Figure 2 of a semiconductor device according to Embodiment 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to the first embodiment.
FIG. 3 is a diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. 3A to 3D are process diagrams.
FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. 4A to 4D are process diagrams.
FIG. 5 is a plan view for explaining the groove forming step S20. FIG. 5A is a plan view of the semiconductor substrate 110 after the groove forming step S20 is viewed from the first main surface side, and FIG. 5B is a second main substrate 110 after the groove forming step S20 is performed. It is the top view seen from the surface side. In FIG. 5, a region surrounded by a square denoted by reference numeral 100 indicates a region that becomes a semiconductor device after the semiconductor substrate separation step S <b> 60 described later.

  The semiconductor device according to the first embodiment can be manufactured by the following manufacturing method (the manufacturing method of the semiconductor device according to the first embodiment).

  As shown in FIG. 2, the semiconductor device manufacturing method according to the first embodiment includes a semiconductor substrate preparation step S10, a groove formation step S20, a passivation film formation step S30, an oxide film removal step S40, and an electrode layer formation step. S50 and semiconductor substrate separation step S60 are included in this order. Hereinafter, the manufacturing method of the semiconductor device according to the first embodiment will be described along the steps.

(1) Semiconductor substrate preparation step S10
First, an n ⁻ -type silicon substrate body 112 (first semiconductor layer) containing n-type impurities and a p ⁺ -type anode layer 114 containing p-type impurities formed on the first main surface side of the n ⁻ -type silicon substrate body 112. (second semiconductor layer), and, n ^- is formed on the second main surface side of -type silicon substrate main body 112 n ^- -type silicon substrate ^{n +} -type cathode layer 116 than the body 112 containing a high concentration n-type impurity ( A semiconductor substrate 110 having a third semiconductor layer) is prepared.

The thickness of the semiconductor substrate 110 is, for example, 240 μm. The thickness of the n ⁻ -type silicon substrate body 112 is, for example, 140 μm, the thickness of the p ⁺ -type anode layer 114 is, for example, 60 μm, and the thickness of the n ⁺ -type cathode layer 116 is, for example, 40 μm.

The semiconductor substrate 110 forms a p ⁺ -type anode layer 114 from the first main surface side of the n ⁻ -type silicon substrate body 112 by diffusion of p-type impurities, and from the second main surface side of the n ⁻ -type silicon substrate body 112. The n ⁺ type cathode layer 116 is formed by diffusion of n type impurities.

In addition, after forming an n ⁻ type epitaxial layer (first semiconductor layer) on an n ⁺ type silicon substrate (third semiconductor layer) as the semiconductor substrate 110, diffusion of p type impurities from the surface of the n ⁻ type epitaxial layer is performed. A semiconductor substrate manufactured by forming a p ⁺ type anode layer (second semiconductor layer) may be used.

(2) Groove forming step S20
Next, a groove forming step S20 is performed. The groove forming step S20 includes a first groove forming step S21 and a second groove forming step S22. In the groove forming step S20, the first groove forming step S21 and the second groove forming step S22 are performed collectively. Therefore, the depth of the deepest portion of the first groove 128 to be described later with reference to the surface on the first main surface side of the semiconductor substrate 110 and the second to be described later with reference to the surface on the second main surface side of the semiconductor substrate 110. The depth of the deepest part of the groove 138 is the same depth.

In the first groove forming step S21, at least the boundary surface 124 between the n ⁻ -type silicon substrate body 112 and the p ⁺ -type anode layer 114 is formed in a region surrounding the first mesa region 122 on the first main surface side of the semiconductor substrate 110. This is a step of forming the first groove 128 having a depth exceeding that. The depth of the deepest portion of the first groove 128 with respect to the surface on the first main surface side of the semiconductor substrate 110 is, for example, 80 μm.

Further, the second groove forming step S22, at the second main surface side of the semiconductor substrate 110, the region surrounding the second mesa region 132 formed in a position corresponding to the first mesa region 122, n ^- -type silicon substrate body This is a step of forming a second groove 138 having a depth at least exceeding the boundary surface 134 between 112 and the n ⁺ -type cathode layer 116. The depth of the deepest portion of the second groove 138 with respect to the surface on the second main surface side of the semiconductor substrate 110 is, for example, 80 μm.

Specifically, first, an oxide film 126 is formed on the surface on the first main surface side of the semiconductor substrate 110 (the surface of the p ⁺ -type anode layer 114) by thermal oxidation, and the second main surface side of the semiconductor substrate 110 is formed. An oxide film 136 is formed on the surface (the surface of the n ⁺ -type cathode layer 116).

  Next, a predetermined opening is formed in a predetermined portion of the oxide films 126 and 136 by a photoetching method (see FIG. 3B). Both the opening on the first main surface side and the opening on the second main surface side are formed at corresponding positions (positions along the outer edge of the semiconductor device 100 to be manufactured).

Next, the semiconductor substrate 110 is etched using the opened oxide films 126 and 136 as a mask, and an n ⁻ -type silicon substrate body 112 is formed in a region surrounding the first mesa region 122 on the first main surface side of the semiconductor substrate 110. First groove 128 having a depth exceeding the boundary surface 124 (depth is, for example, 60 μm) between p ⁺ type anode layer 114 and first mesa region 122 on the second main surface side of semiconductor substrate 110. In a region surrounding the second mesa region 132 formed at a position corresponding to the depth of the boundary surface 134 (depth is, for example, 40 μm) between the n ⁻ type silicon substrate body 112 and the n ⁺ type cathode layer 116. A second groove 138 is formed (see FIG. 3C).

The depth of the first groove 128 (hereinafter, simply referred to as “depth of the first groove 128”) with reference to the surface on the first main surface side of the semiconductor substrate 110 is the thickness of the p ⁺ -type anode layer 114. On the other hand, it is in the range of 120 to 150% (for example, 72 μm to 90 μm), for example, 80 μm. The depth of the second groove 138 with reference to the surface on the second main surface side of the semiconductor substrate 110 (hereinafter simply referred to as “depth of the second groove 138”) is the same as the depth of the first groove 128. For example, 80 μm.

In the groove forming step S20, the thickness (residual silicon thickness) of the n ⁻ type silicon substrate body 112 between the deepest part of the first groove 128 and the deepest part of the second groove 138 is 80 μm or less. A first groove 128 and a second groove 138 are formed. In this embodiment, the thickness of the semiconductor substrate 110 is, for example, 240 μm, and the depth of the first groove 128 and the depth of the second groove 138 are both 80 μm, so that the remaining silicon thickness is, for example, 80 μm. is there.

  In the groove forming step S <b> 20, the first groove 128 and the second groove 138 are formed so that the opening width of the second groove 138 is narrower than the opening width of the first groove 128. The opening width of the first groove 128 is, for example, in the range of 300 μm to 400 μm. The opening width of the second groove 138 is in the range of 50% to 70% of the opening width of the first groove 128. Specifically, the opening width of the second groove is in the range of 150 μm to 280 μm.

  At this time, the first mesa region 122 is formed in the region surrounded by the first groove 128 on the first main surface side, and the second mesa region 122 is formed in the region surrounded by the second groove 138 on the second main surface side. A mesa region 132 is formed. Here, since the opening width of the second groove 138 is narrower than the opening width of the first groove 128 as described above, the second mesa region 132 (see FIG. 5B) is the first mesa region 122 (see FIG. 5). (See 5 (a).) Therefore, in the manufactured semiconductor device 100, the area of the second main surface side surface of the semiconductor substrate 110 in the second mesa region 132 is larger than the area of the first main surface side surface of the semiconductor substrate 110 in the first mesa region 122. Also grows.

(3) Passivation film forming step S30
Next, a passivation film 140 (eg, glass, resin, etc.) is formed on the inner surface of the first groove 128 and the surface of the semiconductor substrate 110 in the vicinity thereof by chemical vapor deposition or electrophoresis (FIG. 3D). )reference.).

(4) Oxide film removal step S40
Next, after forming a protective film (not shown) so as to cover the surface of the passivation film 140, the oxide films 126 and 136 are etched using the protective film as a mask, and the oxide film 126 on the first main surface side. Then, the oxide film 136 on the second main surface side is removed (see FIG. 4A).

(5) Electrode layer forming step S50
Next, after removing the protective film (not shown), nickel plating is applied to the first main surface and the second main surface of the semiconductor substrate 110. Thus, the anode electrode layer 150 is formed on the surface of the semiconductor substrate 110 in the first mesa region 122, and the cathode electrode layer 160 is formed on the surface of the semiconductor substrate 110 in the second mesa region 132 and the second groove 138 (see FIG. (Refer FIG.4 (b).). The cathode electrode layer 160 forms a Schottky junction with the n ⁻ type silicon substrate body 112 and forms an ohmic junction with the n ⁺ type cathode layer 116. The anode electrode layer 150 and the cathode electrode layer 160 may be formed by a vapor phase method such as vapor deposition or sputtering instead of nickel plating.

(6) Semiconductor substrate separation step S60
Next, the semiconductor substrate 110 is separated along the first groove 128 and the second groove 138 (see FIG. 4C), thereby manufacturing the semiconductor device 100 (see FIG. 4D). In the semiconductor substrate separation step S60, the semiconductor substrate 110 is separated by braking without making a cut. As a result, a gap between the deepest portion of the first groove 128 and the deepest portion of the second groove 138 is broken, so that the semiconductor device 110 can be manufactured by separating the semiconductor substrate 110 for each chip.

3. Effects of Semiconductor Device 100 and Semiconductor Device Manufacturing Method According to First Embodiment FIG. 6 is a diagram for explaining the high-temperature reverse bias tolerance of the semiconductor device 100 according to the first embodiment.
6A is a diagram for explaining the high temperature reverse bias tolerance of the semiconductor device 100, and FIG. 6B is a diagram for explaining the high temperature reverse bias tolerance of the conventional semiconductor device 900. As shown in FIG. In FIG. 6, symbol Wd indicates a depletion layer.
FIG. 7 is a view for explaining the surge withstand voltage at the time of forward bias in the semiconductor device 100 according to the first embodiment. FIG. 7A is a diagram for explaining the surge withstand voltage when the semiconductor device 100 is forward biased, and FIG. 7B is a diagram for explaining the surge withstand voltage when the conventional semiconductor device 900 is forward biased. FIG. In FIG. 7, symbol i indicates a part of the current path during forward bias.

Incidentally, the conventional semiconductor device 900 includes a cathode electrode layer 960 that is formed over the entire second main surface side of the semiconductor substrate 910 and forms an ohmic junction with the n ⁺ -type cathode layer 916 (FIG. 6B). ) And FIG. 10.) Therefore, from the position immediately below the boundary between the n ⁻ -type silicon substrate body 912 and the outer peripheral tapered region 920 (see the region surrounded by the broken line A in FIG. 6B) during reverse bias. A bias is applied, and electrons near the boundary move directly below the boundary (see FIG. 6B).

On the other hand, according to the semiconductor device 100 according to the first embodiment, the Schottky junction is formed with the n ⁻ type silicon substrate body 112 formed on the surface of the semiconductor substrate 110 in the second outer peripheral tapered region 130. Since the cathode electrode layer 160 is provided, electrons in the vicinity of the boundary between the n ⁻ -type silicon substrate body 112 and the first outer peripheral tapered region 120 (see the region surrounded by the broken line A in FIG. 6A) at the time of reverse bias. However, compared with the conventional semiconductor device 900, it becomes difficult to move to the second main surface side of the semiconductor substrate 110 (see FIG. 6A). Therefore, since the formation of the inversion layer can be suppressed in the vicinity of the boundary, an increase in leakage current can be suppressed, and as a result, a semiconductor device having a higher high temperature reverse bias tolerance than the conventional semiconductor device 900 is obtained.

Further, according to the semiconductor device 100 according to the first embodiment, the cathode electrode layer that is formed on the surface of the semiconductor substrate 110 in the second outer peripheral tapered region 130 and forms a Schottky junction with the n ⁻ -type silicon substrate body 112. 160, the area of the “region for forming an ohmic junction” between the cathode electrode layer 160 and the n ⁺ -type cathode layer 116 is smaller than that of the conventional semiconductor device 900 (see FIG. 7B) (see FIG. 7B). (See FIG. 7 (a)). Therefore, the first mesa region 122 is connected from the end on the first main surface side to the end of the “region for forming an ohmic junction” (the end of the n ⁺ -type cathode layer 116 in the second mesa region 132). An angle θi formed by the straight line and a straight line perpendicular to the surface of the semiconductor substrate 110 is smaller than that of the conventional semiconductor device 900 (see FIG. 7). Therefore, during forward bias, the current path of the current flowing from the end on the first main surface side in the first mesa region 122 to the end of the “region for forming the ohmic junction” is changed from the first outer tapered region 120 to the conventional semiconductor. It becomes farther than the device 900 (see the region surrounded by the broken line B in FIG. 7), and the surge withstand voltage at the time of forward bias is improved as compared with the conventional semiconductor device 900.

Further, according to the semiconductor device 100 according to the first embodiment, the second outer peripheral tapered region 130 is formed in a region surrounding the second mesa region 132 formed at a position corresponding to the first mesa region 122. In the process of manufacturing the semiconductor device 100, the thickness (remaining silicon thickness) of the n ⁻ -type silicon substrate body 112 between the deepest portion of the first outer peripheral tapered region 120 and the deepest portion of the second outer peripheral tapered region 130 is reduced. The semiconductor substrate 110 can be easily separated.

  Further, according to the semiconductor device 100 according to the first embodiment, the area of the second main surface side surface of the semiconductor substrate 110 in the second mesa region 132 is equal to the first main surface side surface of the semiconductor substrate 110 in the first mesa region 122. Therefore, the allowable current amount is not reduced due to the area of the second mesa region 132 being too small.

  Moreover, according to the semiconductor device 100 according to the first embodiment, the opening width of the second outer peripheral tapered region 130 is in the range of 50 to 70% of the opening width of the first outer peripheral tapered region 120, and thus the semiconductor device is manufactured. In this process, it is possible to prevent difficulty in dividing by braking and to prevent the allowable current amount from being reduced.

  When the opening width of the second outer peripheral taper region 130 is less than 50% of the opening width of the first outer peripheral taper region 120, the second main surface side of the semiconductor substrate 110 becomes smaller as the opening width becomes smaller. Since the depth of the deepest portion of the second outer peripheral tapered region 130 with respect to the surface becomes shallow, the residual silicon thickness becomes thick, and it may be difficult to divide by braking. Further, when the opening width of the first outer peripheral taper region 120 exceeds 70%, the second mesa region is small (the rectification area is small), and thus the allowable current amount may be small.

Further, according to the semiconductor device 100 according to the first embodiment, the thickness (residual silicon) of the n ⁻ -type silicon substrate body 112 between the deepest portion of the first outer peripheral tapered region 120 and the deepest portion of the second outer peripheral tapered region 130. Therefore, when the semiconductor device 100 is manufactured by separating the semiconductor substrate 110 along the first groove 128 and the second groove 138, the semiconductor substrate 110 can be easily separated.

According to the method for manufacturing a semiconductor device according to the first embodiment, the cathode electrode layer 160 that forms a Schottky junction with the n ⁻ -type silicon substrate body 112 is formed on the surface of the semiconductor substrate 110 in the second groove 138. Since the electrode layer forming step S50 is included, in the manufactured semiconductor device 100, the vicinity of the boundary between the n ⁻ -type silicon substrate body 112 and the first outer peripheral tapered region 120 (the region surrounded by the broken line A in FIG. 6A) ) Is less likely to move to the second main surface side of the semiconductor substrate 110 when compared with the conventional semiconductor device 900 at the time of reverse bias. Therefore, since the formation of the inversion layer can be suppressed in the vicinity of the boundary, an increase in leakage current can be suppressed, and as a result, a semiconductor device having a higher high-temperature reverse bias tolerance than the conventional semiconductor device 900 can be manufactured.

Further, according to the method of manufacturing a semiconductor device according to the first embodiment, the cathode electrode layer 160 that forms a Schottky junction with the n ⁻ type silicon substrate body 112 is formed on the surface of the semiconductor substrate 110 in the second groove 138. Since the electrode layer forming step S50 to be formed is included, the manufactured semiconductor device 100 is located between the cathode electrode layer 160 and the n ⁺ -type cathode layer 116 more than the conventional semiconductor device 900 (see FIG. 7B). The area of the “region for forming the ohmic junction” is reduced (see FIG. 7A). Therefore, the first mesa region 122 is connected from the end on the first main surface side to the end of the “region for forming an ohmic junction” (the end of the n ⁺ -type cathode layer 116 in the second mesa region 132). An angle θi formed by the straight line and a straight line perpendicular to the surface of the semiconductor substrate 110 is smaller than that of the conventional semiconductor device 900. Therefore, in the manufactured semiconductor device 100, during forward bias, the current path of the current flowing from the end on the first main surface side in the first mesa region 122 to the end of the “region for forming an ohmic junction” is It is farther from the first outer peripheral tapered region 120 than the conventional semiconductor device 900 (see the region surrounded by the broken line B in FIG. 7). Therefore, it is possible to manufacture a semiconductor device having a surge breakdown voltage at the time of forward bias improved compared to the conventional semiconductor device 900.

  Further, according to the method of manufacturing a semiconductor device according to the first embodiment, in the second groove forming step S22, the second groove is formed in a region surrounding the second mesa region 132 formed at a position corresponding to the first mesa region 122. 138 is formed, the thickness (remaining silicon thickness) of the semiconductor substrate 110 between the deepest portion of the first groove 128 and the deepest portion of the second groove 138 is reduced. In the semiconductor substrate separation step S60, the semiconductor substrate 110 is formed. It becomes easy to separate.

  Further, according to the method of manufacturing a semiconductor device according to the first embodiment, in the groove forming step S20, the first groove forming step S21 and the second groove forming step S22 are performed in a lump. In comparison, the semiconductor device 100 can be manufactured with high productivity.

  In addition, according to the semiconductor device manufacturing method according to the first embodiment, in the semiconductor substrate separation step S60, the semiconductor substrate 110 is separated by braking, so that a large amount of the semiconductor device 100 can be manufactured with higher productivity. The apparatus 100 can be manufactured.

  Further, according to the method for manufacturing a semiconductor device according to the first embodiment, in the semiconductor substrate separation step S60, the semiconductor substrate 110 is separated by breaking without making a cut, so that the semiconductor substrate 110 is irradiated by laser irradiation or the like. It is possible to omit the step of making a cut, and it is possible to manufacture the semiconductor device 100 with higher productivity.

  Further, according to the method for manufacturing the semiconductor device according to the first embodiment, in the groove forming step S20, the first groove 128 and the first groove 128 are formed such that the opening width of the second groove 138 is narrower than the opening width of the first groove 128. In order to form the two grooves 138, the area of the second main surface side surface of the semiconductor substrate 110 in the second mesa region 132 is made larger than the area of the first main surface side surface of the semiconductor substrate 110 in the first mesa region 122. It becomes possible. As a result, in the manufactured semiconductor device 100, the allowable current amount does not decrease due to the area of the second mesa region 132 being too small.

  Further, according to the manufacturing method of the semiconductor device according to the first embodiment, in the second groove forming step S22, the second groove 138 is formed by etching, so that the second groove 138 is formed by dicing or the second groove. Compared to the case where 138 is formed by irradiating laser light, the second groove 138 can be easily formed.

Furthermore, according to the method of manufacturing a semiconductor device according to the first embodiment, in the groove forming step S20, the n ⁻ type silicon substrate body 112 between the deepest part of the first groove 128 and the deepest part of the second groove 138. Since the first groove 128 and the second groove 138 are formed so that the thickness (remaining silicon thickness) is 80 μm or less, the semiconductor substrate 110 can be easily separated in the semiconductor substrate separation step S60.

[Embodiment 2]
FIG. 8 is a diagram for explaining the semiconductor device 102 according to the second embodiment.

  The semiconductor device 102 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the semiconductor device 102 according to the first embodiment is different from the semiconductor device 100 according to the first embodiment in that the semiconductor device is sealed with resin. Not the case. That is, the semiconductor device 102 according to the second embodiment is resin-sealed with the resin 180 as shown in FIG.

  The semiconductor device 102 according to the second embodiment further includes a die pad portion 170 made of a steel material. The cathode electrode layer 160 is electrically connected to the die pad unit 170 via the solder 172. Although not shown, the anode electrode layer 150 is electrically connected to an external terminal. The solder 172 enters the space between the second outer peripheral tapered region 130 and the die pad portion 170.

As described above, the semiconductor device 102 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in that the semiconductor device is sealed with resin, but the semiconductor device 100 according to the first embodiment is different. Similarly, the cathode electrode layer 160 formed on the surface of the semiconductor substrate 110 in the second outer peripheral tapered region 130 and forming a Schottky junction with the n ⁻ -type silicon substrate body 112 is provided. Electrons in the vicinity of the boundary between the n ⁻ -type silicon substrate body 112 and the first outer peripheral tapered region 120 (see the region surrounded by the broken line A in FIG. 6A) are compared with the semiconductor device 900 of the related art. It becomes difficult to move to the second main surface side of the base 110. Therefore, since the formation of the inversion layer can be suppressed in the vicinity of the boundary, an increase in leakage current can be suppressed, and as a result, a semiconductor device having a high high temperature reverse bias tolerance can be obtained.

  Further, according to the semiconductor device 102 according to the second embodiment, since the semiconductor device 102 is resin-sealed, the semiconductor device is resistant to external impact.

FIG. 9 is a diagram for explaining a semiconductor device 800 according to a comparative example.
The semiconductor device 800 according to the comparative example basically has the same configuration as that of the conventional semiconductor device 900, but includes a die pad portion, the semiconductor substrate is electrically connected to the die pad portion via solder, and The semiconductor device is different from the conventional semiconductor device 900 in that the semiconductor device is sealed with resin. In other words, as shown in FIG. 9, the semiconductor device 800 according to the comparative example includes a die pad portion 870 made of a steel material, and the semiconductor substrate 810 is disposed on the second main surface side of the semiconductor substrate 810 via the solder 872. The semiconductor device 800 is resin-sealed with a resin 880.

  In the semiconductor device 800 according to the comparative example, since the second outer peripheral tapered region is not formed, the remaining silicon thickness is larger than that in the semiconductor device 102 according to the second embodiment. For this reason, in the process of manufacturing the semiconductor device 800, the semiconductor substrate 110 is cut by irradiating the laser beam to reduce the remaining silicon thickness. Here, since there is no mark for irradiating the laser beam on the second main surface side, when irradiating the laser beam from the second main surface side, the second main surface side corresponds to each semiconductor device. An oxide film 874 (for a mark) is formed in advance along the boundary line.

  However, in the semiconductor device 800 according to the comparative example, since the oxide film 874 is not wetted by the solder 872, a gap is formed between the oxide film 874 and the solder 872 (see a region indicated by a broken line C in FIG. 9). Therefore, when the resin finger is sealed, the finger 850 enters the gap, and the inserted finger 850 expands in a temperature cycle test or the like, which may cause a solder crack.

On the other hand, according to the semiconductor device 102 according to the second embodiment, the second outer peripheral tapered region 130 is formed in a region surrounding the second mesa region 132 formed at a position corresponding to the first mesa region 122, Since the thickness (remaining silicon thickness) of the n ⁻ -type silicon substrate body 112 between the deepest portion of the first outer peripheral tapered region 120 and the deepest portion of the second outer peripheral tapered region 130 is reduced, in the process of manufacturing the semiconductor device It is not necessary to reduce the remaining silicon thickness by irradiating laser light from the second main surface side. Therefore, it is not necessary to form a mark oxide film on the second main surface side in order to irradiate the laser beam. It is possible to prevent the occurrence of solder cracks due to the penetration of "."

  In addition, according to the semiconductor device 102 according to the second embodiment, since the second outer peripheral tapered region 130 is formed, the solder 172 enters the space between the second outer peripheral tapered region 130 and the die pad portion 170. It becomes. For this reason, compared with the conventional semiconductor device 900, the angle of the bottom part of the solder fillet with respect to the die pad part 170 becomes large, and the shape of the solder fillet tends to be favorable.

  The semiconductor device 102 according to the second embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except that the semiconductor device is resin-sealed, and thus the semiconductor device according to the first embodiment. 100 has a corresponding effect among the effects of 100.

  As mentioned above, although this invention was demonstrated based on said each embodiment, this invention is not limited to each said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) The number, material, shape, position, size, etc. of the constituent elements described in the above embodiments are merely examples, and can be changed within a range not impairing the effects of the present invention.

(2) In each of the above embodiments, in the semiconductor substrate separation step S60, the semiconductor substrate 110 is separated by braking without making a cut, but the present invention is not limited to this. For example, in the semiconductor substrate separation step S60, the semiconductor substrate 110 may be separated by dicing from the second main surface side.

(3) In each of the above embodiments, the first groove forming step S21 and the second groove forming step S22 are collectively performed in the groove forming step S20, but the present invention is not limited to this. For example, in the groove forming step S20, the first groove forming step S21 and the second groove forming step S22 may be performed separately.

(4) In each of the above embodiments, the depth of the deepest portion of the second outer peripheral tapered region 130 with respect to the surface on the second main surface side of the semiconductor substrate 110 is the surface on the first main surface side of the semiconductor substrate 110. However, the present invention is not limited to this. For example, the depth of the deepest portion of the second outer peripheral tapered region 130 may be deeper or shallower than the depth of the deepest portion of the first outer peripheral tapered region 120.

(5) In each of the above embodiments, a semiconductor substrate having a thickness of 240 μm is used, but the present invention is not limited to this. For example, a semiconductor substrate having a thickness greater than 240 μm may be used, or a semiconductor substrate having a thickness less than 240 μm may be used. In the case where a semiconductor substrate having a thickness greater than 240 μm is used, in order to make the remaining silicon thickness 80 μm or less, the second outer peripheral taper region 130 based on the surface on the second main surface side of the semiconductor substrate 110 is used. It is preferable to adjust the depth of the deepest part to a residual silicon thickness of 80 μm or less.

100, 102, 800, 900 ... semiconductor device, 110, 810, 910 ... semiconductor substrate, 112, 812, 912 ... n ^- type silicon substrate body (first semiconductor layer), 114, 814, 914 ... p ⁺ type anode layer (Second semiconductor layer), 116, 816, 916... N ⁺ type cathode layer (third semiconductor layer), 120 ... first outer peripheral taper region, 122 ... first mesa region, 124 ... (p ⁺ type anode layer and n ^-) boundary surface between -type silicon substrate body, 126,926 ... (first main surface side of) the oxide film, 128 ... first groove, 130 ... second outer peripheral tapered region, 132 ... second mesa region 134 ... ( Boundary surface of n ⁻ -type silicon substrate body and n ⁺ -type cathode layer, 136... (second main surface side) oxide film, 138... second groove, 140, 840, 940... passivation film, 150, 850, 950 ... A Node electrode layer, 160, 860, 960 ... cathode electrode layer, 170, 870 ... die pad part, 172, 872 ... solder, 874 ... (for mark) oxide film, 180, 880 ... resin, 920 ... outer peripheral taper region, 922 ... mesa region, 928 ... groove

Claims (12)

A first semiconductor layer containing a first conductivity type impurity, a second semiconductor layer formed on the first main surface side of the first semiconductor layer and containing a second conductivity type impurity opposite to the first conductivity type impurity And a semiconductor substrate having a third semiconductor layer formed on the second main surface side of the first semiconductor layer and containing a first conductivity type impurity at a higher concentration than the first semiconductor layer;
A first outer periphery formed on a region surrounding the first mesa region on a first main surface side of the semiconductor substrate, in a region reaching a depth position exceeding a boundary surface between the first semiconductor layer and the second semiconductor layer. A tapered region;
A region surrounding the second mesa region formed at a position corresponding to the first mesa region on the second main surface side of the semiconductor substrate exceeds the boundary surface between the first semiconductor layer and the third semiconductor layer. A second outer taper region formed in a region reaching a depth position;
Formed on the surface of the semiconductor substrate in the second mesa region and the second outer peripheral taper region, forms a Schottky junction with the first semiconductor layer, and ohmic with the third semiconductor layer A semiconductor device comprising: an electrode layer that forms a junction. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein an area of the second main surface side surface of the semiconductor substrate in the second mesa region is larger than an area of the first main surface side surface of the semiconductor substrate in the first mesa region. The semiconductor device according to claim 1 or 2,
An opening width of the second outer peripheral taper region is in a range of 50 to 70% of an opening width of the first outer peripheral taper region. The semiconductor device according to claim 1,
The thickness of the said 1st semiconductor layer between the deepest part of the said 1st outer periphery taper area | region and the deepest part of the said 2nd outer periphery taper area | region is 80 micrometers or less, The semiconductor device characterized by the above-mentioned. In the semiconductor device according to claim 1,
The semiconductor device is resin-sealed. A first semiconductor layer containing a first conductivity type impurity, a second semiconductor layer formed on the first main surface side of the first semiconductor layer and containing a second conductivity type impurity opposite to the first conductivity type impurity And a semiconductor substrate preparation step of preparing a semiconductor substrate having a third semiconductor layer formed on the second main surface side of the first semiconductor layer and containing a first conductivity type impurity having a higher concentration than the first semiconductor layer. When,
First groove formation for forming a first groove having a depth exceeding a boundary surface between the first semiconductor layer and the second semiconductor layer in a region surrounding the first mesa region on the first main surface side of the semiconductor substrate. And a region surrounding the second mesa region formed at a position corresponding to the first mesa region on the second main surface side of the semiconductor substrate, the first semiconductor layer and the third semiconductor layer A groove forming step including a second groove forming step of forming a second groove having a depth exceeding the boundary surface;
A Schottky junction is formed with the first semiconductor layer on the surface of the semiconductor substrate in the second mesa region and the second groove, and an ohmic junction is formed with the third semiconductor layer. An electrode layer forming step of forming an electrode layer;
A method of manufacturing a semiconductor device, comprising: a semiconductor substrate separation step of manufacturing a semiconductor device by separating the semiconductor substrate along the first groove and the second groove in this order. In the manufacturing method of the semiconductor device according to claim 6,
In the groove forming step, the first groove forming step and the second groove forming step are collectively performed. In the manufacturing method of the semiconductor device according to claim 6 or 7,
In the semiconductor substrate separating step, the semiconductor substrate is separated by braking without making a notch. In the manufacturing method of the semiconductor device according to claim 6 or 7,
In the semiconductor substrate separating step, the semiconductor substrate is separated by dicing from the second main surface side. In the manufacturing method of the semiconductor device in any one of Claims 6-9,
In the groove forming step, the first groove and the second groove are formed so that the opening width of the second groove is narrower than the opening width of the first groove. . In the manufacturing method of the semiconductor device in any one of Claims 6-10,
In the second groove forming step, the second groove is formed by etching. In the manufacturing method of the semiconductor device in any one of Claims 6-11,
In the groove forming step, the first groove and the second groove are formed such that a thickness of the first semiconductor layer between the deepest portion of the first groove and the deepest portion of the second groove is 80 μm or less. A method of manufacturing a semiconductor device, comprising forming a groove.

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