JP5755722B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a junction barrier Schottky diode using silicon carbide.

  Silicon carbide semiconductors (SiC) are promising as power devices because they have the characteristics that the band gap is larger than that of silicon semiconductors and the dielectric breakdown electric field is about one digit larger. In particular, a Schottky diode, which is a unipolar rectifier element that operates only by majority carriers, is effective as a power module loss reduction technique because a reverse current (recovery current) does not flow during switching operation due to the device configuration.

  The rectifying action of the Schottky diode is made by a Schottky barrier generated by the difference between the work function of the metal and the electron affinity of the semiconductor. By using a metal material having a high Schottky barrier height, the reverse leakage current can be reduced, but at the same time, the forward rise voltage is increased. In addition, by using a metal material having a low Schottky barrier height, the forward rise voltage can be lowered, but at the same time, the reverse leakage current is increased.

On the other hand, as a structure that suppresses reverse leakage current by relaxing an electric field applied to a metal / semiconductor interface (hereinafter referred to as a Schottky interface) when a reverse voltage is applied, a junction in which a plurality of junction barriers are provided at the Schottky interface. A structure called a barrier (Schottky diode) (hereinafter referred to as a JBS diode) has been proposed. When a reverse voltage is applied, a depletion layer extends from the junction barrier, and the electric field at the Schottky interface can be relaxed. This structure is illustrated in FIG. In FIG. 19, 1 indicates a silicon carbide n + substrate, 2 indicates an n ⁻ drift layer, 3 indicates a p + region, 5 indicates an anode electrode, and 6 indicates a cathode electrode. While the JBS diode can reduce the reverse leakage current, the area of the Schottky diode region that operates at a low voltage during forward operation is reduced, and thus the resistance during forward operation is increased. As a structure for suppressing an increase in resistance during forward operation in a JBS diode, a structure in which the impurity concentration in a region surrounded by a junction barrier is increased is disclosed (Patent Document 1). This structure is illustrated in FIG. A difference from FIG. 19 is that an n-type semiconductor region 4 having an impurity concentration higher than that of the n ⁻ drift layer is provided. With this structure, the resistance of the junction barrier forming region can be lowered.

Japanese Patent No. 3998795

However, these studies are effective methods only when an ideal Schottky interface can be formed. The reverse characteristics of the Schottky diode are very sensitive to the state of the Schottky interface, and if there is a foreign object or a defect near the interface, the reverse leakage current increases rapidly and the desired rectifying action cannot be obtained. In general, a non-defective product rate is low for a Schottky diode compared to a PN diode. Compared to PN diodes that form a junction barrier inside the drift layer by epitaxial growth or ion implantation, Schottky diodes that form a metal film on the surface of the drift layer are more susceptible to foreign matter and process defects during the manufacturing process. is there. Assuming that the distribution of foreign matters and defects is random, the non-defective product ratio Y (in this case, the probability that a chip can be produced without abnormality in the reverse direction characteristic) can be considered as a Poisson distribution and is expressed by the following equation.
(Formula)
Y = exp (-DA)
D: Density of foreign matters and defects that cause abnormal reverse characteristics A: Area of Schottky interface FIG. 21 shows the relationship between the non-defective product ratio Y and the area A of the Schottky interface shown in Equation 1 with respect to the defect density D. The plot is shown. For example, when the area A of the Schottky interface is 0.1 cm ^2, D = 1 piece / case yield rate Y of cm ² is of the order of 90% in the case of D = 10 pieces / cm ² Y 40% below It can be seen that it decreases significantly. A value obtained by multiplying this value by the non-defective rate corresponding to the total area of the junction barrier region used in the JBS structure and the electric field concentration relaxation structure formed around the chip can be considered as the non-defective rate of the JBS diode. .

  As described above, since the Schottky diode is sensitive to the Schottky interface characteristics, it is very difficult to manufacture a large-area voltage-resistant chip. Thus, in order to improve the yield rate, it is considered effective to increase the junction barrier region in the JBS structure and reduce the Schottky interface region as much as possible. However, in this case, there is a problem in that the current does not spread sufficiently under the junction barrier region during forward operation, and the on-voltage increases.

  The problem to be solved is that the on-voltage increases because the current does not spread sufficiently under the junction barrier region during the forward operation of the JBS diode.

In the present invention, in order to suppress an increase in on-resistance of the JBS structure diode, a structure having an n region having a relatively higher concentration than the n ⁻ -type drift layer concentration is provided below the junction barrier region. Representative inventions of the present invention are listed below.

  The present invention includes a first conductivity type silicon carbide substrate, a first conductivity type drift layer formed on the silicon carbide substrate and having a first impurity concentration, and formed on a surface in the drift layer at predetermined intervals. A plurality of first semiconductor regions having a second conductivity type opposite to the first conductivity type, a Schottky electrode that is Schottky connected to the drift layer, an ohmic electrode that is ohmically connected to the back surface of the silicon carbide substrate, and a first semiconductor A semiconductor device comprising: a second semiconductor region of a first conductivity type having a second impurity concentration higher than the first impurity concentration in a region between the region and the silicon carbide substrate.

  Another embodiment of the present invention is a first conductivity type silicon carbide substrate, a first conductivity type first semiconductor layer formed on the silicon carbide substrate and having a first impurity concentration, and formed on the first semiconductor layer. A first conductivity type second semiconductor layer having a second impurity concentration higher than the first impurity concentration and opposite to the first conductivity type formed at a predetermined interval on the surface in the second semiconductor layer. A semiconductor device comprising a plurality of first semiconductor regions having a second conductivity type, a Schottky electrode that is in Schottky connection with the second semiconductor layer, and an ohmic electrode that is in ohmic connection with the back surface of the silicon carbide substrate.

  Another embodiment of the present invention is a first conductivity type silicon carbide substrate, a first conductivity type first semiconductor layer formed on the silicon carbide substrate and having a first impurity concentration, and formed on the first semiconductor layer. A first conductivity type second semiconductor layer having a second impurity concentration higher than the first impurity concentration and opposite to the first conductivity type formed at a predetermined interval on the surface in the second semiconductor layer. A plurality of first semiconductor regions having a second conductivity type and a second semiconductor having a second conductivity type formed in the second semiconductor layer and disposed so as to surround the plurality of first semiconductor regions when viewed from above. The semiconductor device includes a region, a Schottky electrode that is Schottky-connected to the second semiconductor layer, and an ohmic electrode that is ohmic-connected to the back surface of the silicon carbide substrate.

Since the semiconductor device of the present invention has an n region having a resistance lower than that of the n ⁻ type drift layer at the lower part of the junction barrier region, the current spreads to the lower part of the junction barrier region, so that the on-voltage of the JBS diode is reduced. The rise can be suppressed.

FIG. 23 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view taken along the line A-A ′ of FIG. 22. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. FIG. 3 is an explanatory diagram of a cross-sectional structure in the manufacturing process of the semiconductor device, following FIG. 2; It is explanatory drawing which shows the relationship between the raise rate of drift layer resistance, and the ratio of a Schottky interface. It is explanatory drawing which shows the relationship between the raise rate of drift layer resistance, and junction barrier area | region width. It is explanatory drawing which shows the effect of Embodiment 1 of this invention. It is explanatory drawing which shows the effect of Embodiment 1 of this invention. It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 2 of this invention, and is sectional drawing in the BB 'cut surface of FIG. 22, (a) is a case where a Schottky electrode does not run over the insulating film 10 (B), It is sectional drawing in case a Schottky electrode runs on the insulating film 10. FIG. It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 3 of this invention. It is explanatory drawing which shows the cross-section of the other semiconductor device in Embodiment 3 of this invention. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 3 of this invention. FIG. 12 is an explanatory diagram of a cross-sectional structure during the manufacturing process of the semiconductor device following FIG. 11; It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 4 of this invention. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 4 of this invention. FIG. 15 is an explanatory diagram of a cross-sectional structure in the manufacturing process of the semiconductor device, following FIG. 14; It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 5 of this invention. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 5 of this invention. FIG. 17 is an explanatory diagram of a cross-sectional structure during the manufacturing process of the semiconductor device following FIG. 16; It is explanatory drawing which shows the cross-section of the conventional semiconductor device. It is explanatory drawing which shows the cross-section of the conventional semiconductor device. It is explanatory drawing which shows the relationship between a non-defective rate and the area of a Schottky interface. It is explanatory drawing which shows the upper surface structure of the semiconductor device in Embodiment 1 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In particular, for functions corresponding to different embodiments, the same reference numerals are given even if there are differences in shape, impurity concentration, crystallinity, and the like. Further, in the cross-sectional view, only the main part of the diode is shown, and the peripheral part including the electric field concentration mitigation structure normally formed around the chip is omitted. For convenience of explanation, only an example using an n-type semiconductor substrate will be described, but even a case using a p-type semiconductor substrate is included in the present invention. In this case, n-type may be read as p-type, and p-type may be read as n-type.

(Embodiment 1)
FIG. 1 is an explanatory view showing a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the first embodiment includes a first conductivity type low impurity concentration (n ⁻ type) SiC drift formed on a first conductivity type (n type) high impurity concentration (n ⁺ type) SiC substrate 1. Layer 2, second conductivity type (p-type) p-type semiconductor region 3, Schottky electrode 5 provided on the surface of n ⁻ drift layer 2, ohmic electrode 6 provided on the back surface of n ⁺ SiC substrate 1, It is a JBS diode provided with. Further, the diode has an n-type semiconductor region 4 having an impurity concentration higher than that of the n ⁻ drift layer 2 (n ⁻ SiC semiconductor layer 8) in a region below the p type semiconductor region 3 and between the SiC substrate. It has. For this reason, the current can sufficiently spread under the p-type semiconductor region 3 during the forward operation, and an increase in on-voltage can be suppressed. In the first embodiment, the n-type semiconductor region 4 below the p-type semiconductor region 3 is arranged in contact with the p-type semiconductor region 3, and the n-type semiconductor region 4 is the surface of the n ⁻ drift layer 2. Since it is formed as a whole, it also exists in the region between the p-type semiconductor regions 3. Note that W represents the thickness of the drift layer, S represents the interval between a plurality of p-type semiconductor regions 3 arranged, and P represents the width of the p-type semiconductor region 3.

  2 to 3 are cross-sectional structure explanatory views during the manufacturing process showing an example of the manufacturing process of the first embodiment.

First, ⁿ of low impurity concentration on the ⁿ + SiC substrate 1 as shown in FIG. 2 - the SiC layer ^8, n - n semiconductor region of higher impurity concentration than SiC layer 8 - relatively ⁿ on the SiC layer 8 A SiC substrate formed by epitaxial growth of 4 is prepared. Here, the laminated film of the n ⁻ SiC layer 8 and the n semiconductor region 4 is defined as the n ⁻ drift layer 2.

The impurity concentration of the n ⁺ SiC substrate 1 is in the range of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ . The (0001) plane, the (000-1) plane, the (11-20) plane, etc. are often used as the main surface of the SiC substrate, but the present invention is effective regardless of the selection of these main surfaces of the SiC substrate. Can be played.

The specifications of the n ⁻ SiC layer 8 on the n ⁺ SiC substrate 1 vary depending on the set withstand voltage specification, but the impurity concentration is 1 × 10 ¹⁵ to 4 × 10 ¹⁶ cm ⁻ with the same conductivity type as the substrate. ^In the range of about ³ , the thickness is used in the range of about ³ to 80 μm.

Next, as shown in FIG. 3, a pattern is formed on the mask material 7 by usual lithography and dry etching. Here, the mask material 7 uses SiO ₂ formed by a CVD (Chemical Vapor Deposition) method. Further, the mask material 7 is usually processed into a striped pattern, island pattern, polygonal pattern, lattice pattern, etc., but the present invention is not limited as long as it is patterned with a certain width and interval. The effect can be achieved even in the shape. After pattern formation on the mask material 7, a p-type semiconductor region 3 is formed on the surface of the n − drift layer 2 by implantation of ions 12. The impurity concentration of the p-type semiconductor region 3 is about 10 ¹⁸ to 10 ²⁰ cm ⁻³ and the junction depth is used in the range of about 0.3 to 2.0 μm. Usually, Al (aluminum) or B (boron) is used as the p-type dopant. Here, Al is used as a dopant, multi-stage implantation is performed with an acceleration energy of 35 to 145 keV with a total dose of 1.8 × 10 ¹⁴ cm ^−2, and an impurity concentration in the vicinity of the surface is about 9 × 10 ¹⁸ cm ⁻³ . The p-type semiconductor region 3 was formed to have a depth of about 0.55 to 0.7 μm.

After the p-type semiconductor region 3 was thus formed, a guard ring 9 made of p-type impurities was formed on the outer periphery of the chip in the same procedure as the formation of the p-type semiconductor region 3 (see FIG. 22). Furthermore, the normal activation annealing of the implanted impurities is performed, the ohmic electrode 6 on the back surface of the n ⁺ SiC substrate and the Schottky electrode 5 on the surface of the n ⁻ drift layer 2 are formed, and the Schottky electrode 5 is patterned to a desired size. By processing, the main part of the semiconductor device of the present invention shown in FIG. 1 is completed.

For the purpose of protecting the surface and preventing discharge from the electrode end, an insulating film 10 such as SiO ₂ is formed on the surface, and an opening 11 is formed by patterning a part of the upper portion of the electrode for the electrode terminal. Thus, the semiconductor device is completed (see FIG. 22). FIG. 22 is an explanatory view showing the top structure of the first embodiment. This top view shows the arrangement relationship of the main parts of the semiconductor device, and does not accurately show the positions and dimensions of all layers. Further, some layers such as electrodes are not shown in order to make the arrangement relationship easy to see. Here, a striped pattern in which the p-type semiconductor regions 3 are arranged in a line at regular intervals is shown as the JBS structure. However, as described above, island-shaped patterns and polygons generally used as the JBS structure are shown. It may be a shape pattern, a lattice pattern, or the like. The p-type semiconductor region 9 is formed so as to surround the plurality of p-type semiconductor regions 3. 1 is a cross-sectional view taken along the line AA ′ of FIG. Although only the main part of the diode has been described here, an electric field concentration mitigation structure such as FLR (Field Limiting Ring) and JTE (Junction Termination Extension) and a channel stopper, which are usually formed around the chip, are shown in FIG. Before or after the formation of the p-type semiconductor region 3 shown, it is formed using conventional lithography, dry etching, and ion implantation.

In the first embodiment, the SiC substrate in which the n semiconductor region 4 is formed by epitaxial growth is used. However, the n semiconductor region 4 may be formed by performing multistage ion implantation of n-type impurities into the n ⁻ drift layer 2. . As the n-type impurity, N (nitrogen) or P (phosphorus) is generally used, but any other element can be used as long as it contributes as an n-type dopant. In this case, the region where the n-type impurity is ion-implanted may be the entire surface of the SiC substrate, or may be limited to the region where the Schottky electrode is formed. The ion implantation of the n-type impurity may be performed before the implantation impurity activation annealing step, and the n semiconductor region 4 may be formed after the step of forming the p-type semiconductor region 3 of FIG. .

In the first embodiment, SiO ₂ is applied to the mask material. However, for example, a silicon nitride film or a resist material may be used, and any other material can be used as long as it is a material used as a mask during ion implantation.

In the first embodiment, the back surface and front surface electrodes are formed immediately after the implantation impurity activation annealing. However, after the implantation impurity activation annealing is performed, an oxidation treatment is performed to form n ^−. You may perform the sacrificial oxidation process which removes the damage layer which entered the surface of the drift layer 2. FIG.

In the first embodiment, the back and front electrodes are formed immediately after the implantation impurity activation annealing, but the surface of the n ⁻ drift layer 2 is protected by a CVD method such as SiO _2. A film may be formed to protect the surface of the n ⁻ drift layer 2. In this case, after the surface protective film is formed, processing is performed so that only the region where the Schottky electrode is formed is opened. Further, the surface protective film may be formed after performing the above-described sacrificial oxidation step. Next, an example of the effect of the present invention will be described with reference to the simulation results of FIGS. Here, n diode having a JBS structure ^- drift layer resistance R, Schottky diodes the n ^- drift layer resistance _R SBD, the width of the p-type semiconductor region 3 in the JBS structure P, and spacing S, n-drift The thickness of layer 2 is defined as W.

The n ⁻ drift layer 2 shows two types of specifications with different breakdown voltages. One is an n-drift layer having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a thickness of 5 μm assuming a breakdown voltage of 600 V, and the other is an impurity concentration of 3 × 10 ¹⁵ cm assuming a breakdown voltage of 3.3 kV. ^-3 , an n-drift layer having a thickness of 30 μm.

FIG. 4 shows the relationship between the resistance increase rate R / R _SBD of the conventional JBS diode and the Schottky interface ratio S / (S + P). The interval S between the p ⁺ junction regions is determined from the viewpoint of sufficiently relaxing the Schottky electrode interface electric field when the reverse voltage is applied and reducing the reverse leakage current. Here, in the specification of the n ⁻ drift layer 2 assuming a withstand voltage of 600V, S = 2 μm, and in the specification of the n ⁻ drift layer 2 assuming a withstand voltage of 3.3 kV, 3 μm is set as a standard dimension. In addition, for comparison of resistance change of the drift layer, the size of S = 6 μm was also calculated in the specification of the n ⁻ drift layer 2 with a withstand voltage of 600 V, but this specification of S considered the relaxation effect of the Schottky interface electric field. Not a value. As can be seen from FIG. 4, since the current path on the surface of the n − drift layer 2 is restricted by adopting the JBS structure, the resistance increase rate R / R _SBD increases as the ratio of the Schottky interface decreases. . However, depending on the specifications of the n ⁻ drift layer 2 and the size of the interval S, the sensitivity of the rate of increase of the drift layer resistance with respect to the ratio of the Schottky interface varies. That is, the current does not sufficiently spread to the lower part of the p-type semiconductor region, and the point at which the rate of increase in resistance R / R _SBD rapidly increases is not determined only by the ratio of the width P and the interval S of the p-type semiconductor region. Yes.

FIG. 5 shows the relationship between the resistance increase rate R / R _SBD of the conventional JBS diode and the ratio W / P of the junction region width to the drift layer thickness. In FIG. 5, when the value of W / P is large, the resistance increase rate R / R _SBD gradually increases at a substantially constant rate. However, when the value of W / P ≦ 4, the resistance increase rate R / R _It can be seen that the _SBD increases rapidly. This is because the factor that determines the increase in resistance of the JBS structure is determined by the width P of the p-type semiconductor region and the thickness W of the drift layer. In the relationship of P ≧ W / 4, the current reaches the lower portion of the p-type semiconductor region 3. It indicates that it will not spread sufficiently.

FIG. 6 shows an example of the effect when the structure of the first embodiment is applied. In FIG. 6, for simplicity, the n-type semiconductor region 4 is indicated as a current spreading layer, but the same layer is shown. That is, what is indicated as a current spreading layer is data when the n-type semiconductor region 4 according to the present invention is provided, and what is not indicated is a conventional SBD. The specification of the n ⁻ drift layer 2 assuming a withstand voltage of 600 V is that the n ⁻ SiC layer 8 is 5 μm thick with an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ , and the n-type semiconductor region 4 is 2 μm with 3 × 10 ¹⁶ cm ⁻³ . It is a laminated film. The specifications of the n ⁻ drift layer 2 assuming a breakdown voltage of 3.3 kV are as follows ^: the n ⁻ SiC layer 8 is 30 × m of 3 × 10 ¹⁵ cm ⁻³ , and the n-type semiconductor region 4 is 1.5 × 10 ¹⁶ cm ⁻³ . The laminated film is 2 μm. The rate of increase in resistance of the n ⁻ drift layer 2 to which the n-type semiconductor region 4 is added is normalized by the resistance R _SBD of the Schottky diode of the n ⁻ drift layer 2 when the n-type semiconductor region 4 is not present. For this reason, the resistance increase rate R / R _SBD when W / P is large varies depending on the specifications of the n ⁻ drift layer 2 due to the impurity concentration and thickness of the stacked film. However, in any of the specifications of the n ⁻ drift layer 2, it can be seen that the increase in resistance is suppressed as compared with the conventional structure when the resistance increase rate is smaller than the point W / P = 4. That is, it can be seen that when the n-type semiconductor region 4 according to the present invention is provided, the effect of suppressing an increase in resistance becomes remarkable particularly in a design where P is wider than 1/4 of W. Although a certain effect can be obtained by providing the n-type semiconductor region 4 regardless of the relationship between P and W, a more remarkable effect can be obtained by making P wider than 1/4 of W. It is desirable to make it wider than 1/4 times.

FIG. 7 shows an example of the effect when the structure of the first embodiment is applied. The resistance increase rate of the n ⁻ drift layer 2 to which the n-type semiconductor region 4 is added is equal to that of the same n ⁻ drift layer 2. The case is shown in which the Schottky diode resistance R _SBD of the structure is normalized. Regarding the specifications of each n ⁻ drift layer 2, it can be seen that the resistance increase rate R / R _SBD gradually increases at a substantially constant rate up to about W / P = 3. This is because the current is sufficiently spread to the bottom of the p-type semiconductor region 3 even if the width P of the p-type semiconductor region 3 is increased by the structure of the present invention in which the n-type semiconductor region 4 is added. Compared with the conventional structure, the increase in resistance is moderate even when the increase rate is smaller than the point W / P = 3 where the increase rate increases rapidly, and the increase rate of resistance is about 1.5 even when W / P = 1. Yes, it is limited to a practical range. That is, by providing the n-type semiconductor region 4 according to the present invention, the point of rapid increase in resistance, which was conventionally about W / P = 4, can be lowered to about W / P = 3. In addition, by providing the n-type semiconductor region 4 with a design value that is not practical due to the high rate of increase in resistance when the conventional W / P = 1, it is possible to keep the design value within a practical range. Therefore, when using the area before the rate of increase increases rapidly, it is desirable to set P to be larger than 1/4 times W and smaller than 1/3 times. Even if it is larger than / 3 times, this rate of increase can be kept low.

In the first embodiment, the case where the film thickness of the n-type semiconductor region 4 is 2 μm has been described, but the concentration and film thickness of the n-type semiconductor region 4 can be set to arbitrary values. That is, the concentration is set in a range where the concentration is higher than that of the n ^- SiC layer 8 and the reverse characteristics can exhibit a desired breakdown voltage. Similarly, the film thickness may be thin or thick.

In the first embodiment, the spacing S of the p-type semiconductor region 3 in the JBS structure, n assuming a breakdown voltage 600V ^- drift layer ^- n assuming the S = 2 [mu] m, the breakdown voltage 3.3kV in the specification of the drift layer 2 In the second specification, S is set to 3 μm. However, the interval S may be set to be narrow as long as the ON voltage does not increase excessively during forward operation. In the first embodiment, since the n-type semiconductor region 4 having a relatively high impurity concentration is provided on the surface of the n ⁻ drift layer 2, it can be set much narrower than the normal interval S.

(Embodiment 2)
In the second embodiment, the structure in the vicinity of the Schottky electrode 5 end in the first embodiment is further provided with an n-type semiconductor region 4. FIG. 8 is a cross-sectional view taken along the line BB ′ of FIG. 22 and shows a cross-sectional structure in the vicinity of the Schottky electrode 5 end of the JBS diode. As shown in FIG. 8, the structure of the end of the Schottky electrode 5 is as follows: (a) the Schottky electrode 5 is formed on the n ⁻ -type SiC drift layer 2, and on the p-type semiconductor region (guard ring) 9. A structure in which the electrode is processed so that the end portion is formed, and (b) the insulating film 10 formed on the n ⁻ -type SiC drift layer 2 is processed by usual lithography and dry etching or wet etching, and the Schottky electrode 5 In general, a structure is used in which an electrode is processed so that an end is formed on the insulating film 10 above the p-type semiconductor region (guard ring) 9. Here, the p-type semiconductor region (guard ring) 9 is provided so that the electric field does not concentrate at the end of the Schottky electrode 5 or at the boundary between the electrode and the insulating film 10. In any case, the end portion of the Schottky electrode or the boundary portion between the Schottky electrode and the insulating film 10 (end portion of the Schottky electrode) is disposed on the p-type semiconductor region. Here, the p-type semiconductor region (guard ring) 9 is shown as a region formed in a separate process from the p-type semiconductor region 3, but may be formed in the same step as the p-type semiconductor region 3. In any case, by forming the p-type semiconductor region (guard ring) 9 in the n-type semiconductor region 4, the current sufficiently spreads under the p-type semiconductor region (guard ring) 9 during forward operation. As in the effect of the first embodiment, an increase in on-voltage in the vicinity of the end of the Schottky electrode 5 can be suppressed.

In the first embodiment, SiO ₂ is applied to the insulating film 10, but any material having general insulating properties may be used. For example, a silicon nitride film, a polyimide, or a laminate made of these different insulating films is used. It may be a membrane.

(Embodiment 3)
FIG. 9 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the third embodiment of the present invention. FIG. 10 is an explanatory diagram of a cross-sectional structure of another semiconductor device according to the third embodiment. The difference from FIG. 9 is that the n-type semiconductor region 4 has the same width as the p-type semiconductor region 3. This difference can be realized by a slight change in the manufacturing process. The difference between the third embodiment and the first embodiment is that the n-type semiconductor region 4 is formed only in the lower region of the p-type semiconductor region 3, and the manufacturing process is different. However, the effect is essentially the same as that shown in the first embodiment although the degree is different.

  FIG. 11 to FIG. 12 are cross-sectional structure explanatory views in the manufacturing process showing an example of the manufacturing process of the third embodiment.

A SiC substrate in which a low impurity concentration n ⁻ drift layer 2 is formed by epitaxial growth on n ⁺ SiC substrate 1 is prepared in the same procedure as in the first embodiment. The n ⁺ SiC substrate 1 and the n ⁻ drift layer 2 use the same impurity concentration and thickness specifications as those in the first embodiment.

Next, as shown in FIG. 11, a pattern is formed on the mask material 7 by usual lithography and dry etching. The mask material 7 and its processing pattern are the same as those in the first embodiment. After pattern formation on the mask material 7, the p-type semiconductor region 3 is formed on the surface of the n ⁻ drift layer 2 by implantation of ions 12. The acceleration energy and the total dose amount at the time of ion implantation are the same as those in the first embodiment.

Next, the mask material 7 at the time of forming the p-type semiconductor region 3 is processed and reduced, and n-type impurity ions are implanted to form the n semiconductor region 4. Here, since the mask material 7 uses SiO ₂ formed by the CVD method, diluted hydrofluoric acid is used for processing. The etching amount of the mask material 7 is not particularly limited, and it is sufficient that the width of the n-type semiconductor region 4 is wider than the width of the p-type semiconductor region 3. The impurity concentration of the n-type semiconductor region 4 only needs to be relatively higher than the impurity concentration of the n − drift layer 2, and is set so that the peak impurity concentration is near the PN junction position below the p-type semiconductor region 3. . Usually, N (nitrogen) or P (phosphorus) is used as the n-type dopant. Here, N is used as a dopant, and a multi-dose implantation is performed with an acceleration energy of 360 to 480 keV with a total dose of 1.8 × 10 ¹² cm ^{−2 so} that the peak impurity concentration is about 7 × 10 ¹⁶ cm ^−3. An n-type semiconductor region 4 was formed. Further, in order to increase the width of the n-type semiconductor region 4 serving as the current spreading layer, multi-stage implantation may be performed with higher acceleration energy, for example, up to about 700 keV. It is necessary to determine the size of the PN junction leak when applying the reverse voltage.

After the n-type semiconductor region 4 is formed in this way, a normal activation impurity implantation annealing is performed to form the ohmic electrode 6 on the back surface of the n ⁺ SiC substrate and the Schottky electrode 5 on the surface of the n ⁻ drift layer 2. Then, the semiconductor device of the present invention shown in FIG. 9 is completed by patterning the Schottky electrode 5 to a desired size.

  Although only the main part of the diode has been described here, the electric field concentration relaxation structure usually formed around the chip is not limited to the conventional lithography and dry process before, during or after the manufacturing process shown in FIGS. It is formed using etching and ion implantation.

  In the third embodiment, the n-type semiconductor region 4 is formed after the p-type semiconductor region 3 is formed, but the formation order may be reversed. In that case, after the n-type semiconductor region 4 is formed, a mask material 7 is additionally deposited, and an etch-back process by a usual dry etching is performed, so that the p-type semiconductor region 3 having a narrower width than the n-type semiconductor region 4 is formed. A forming mask material 7 is formed.

  In the third embodiment, the width of the n-type semiconductor region 4 is formed wider than the width of the p-type semiconductor region 3, but may be formed with the same mask pattern. In this case, since the process of reworking the mask material 7 can be omitted, the process can be simplified. FIG. 10 illustrates a cross-sectional structure.

In the third embodiment, the back surface and front surface electrodes are formed immediately after the implantation impurity activation annealing. However, after the implantation impurity activation annealing is performed, the oxidation treatment is performed, and n ⁻ You may perform the sacrificial oxidation process which removes the damage layer which entered the surface of the drift layer 2. FIG.

In the third embodiment, the back and front electrodes are formed immediately after the implantation impurity activation annealing, but the surface of the n ⁻ drift layer 2 is protected by a CVD method such as SiO _2. A film may be formed to protect the surface of the n ⁻ drift layer 2. In this case, after the surface protective film is formed, processing is performed so that only the region where the Schottky electrode is formed is opened. Further, the surface protective film may be formed after performing the above-described sacrificial oxidation step.

(Embodiment 4)
FIG. 13 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the fourth embodiment of the present invention. The difference from FIG. 9 shown in the third embodiment is that the n-type semiconductor region 4 is also arranged on the side surface of the p-type semiconductor region 3 and is formed up to the surface of the n ⁻ drift layer 2 to be Schottky connected. It is. It is arranged with a predetermined distance from adjacent n-type semiconductor regions. However, the effect is essentially the same as that shown in the first embodiment although the degree is different.

  14 to 15 are explanatory views of a cross-sectional structure during the manufacturing process, showing an example of the manufacturing process of the fourth embodiment.

The difference from the third embodiment is the ion implantation conditions when forming the n-type semiconductor region 4 in FIG. By performing multistage implantation from low acceleration energy, the n-type semiconductor region 4 is formed up to the surface of the n ⁻ drift layer 2.

As another manufacturing method of the fourth embodiment, the n ⁻ drift layer 2 is processed into a trench shape by usual dry etching, and then the SiC layer that becomes the n-type semiconductor region 4 and the SiC that becomes the p-type semiconductor region 3 are obtained. There is a method in which a layer is epitaxially grown and planarization polishing is performed up to the surface of the n ⁻ drift layer 2 by CMP (Chemical Mechanical Polishing). In this case, since the n-type semiconductor region 4 and the p-type semiconductor region 3 can be formed without using ion implantation, the impurity concentration and the width thereof can be accurately controlled.

(Embodiment 5)
FIG. 16 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the fifth embodiment of the present invention. The difference from FIG. 9 shown in the third embodiment is that the n-type semiconductor regions 4 are formed as one layer without being divided. That is, it is disposed between the p-type semiconductor region 3 and also between the Schottky electrode 5 and the SiC substrate 1. Further, it is arranged at a predetermined distance from the Schottky electrode 5. However, the effect is essentially the same as that shown in the first embodiment although the degree is different.

  FIG. 17 to FIG. 18 are cross-sectional structure explanatory views in the manufacturing process showing an example of the manufacturing process of the fifth embodiment.

  The difference from the third embodiment is the implantation region when forming the n-type semiconductor region 4 of FIG. In the fifth embodiment, the n-type semiconductor region 4 is formed by ion-implanting n-type impurities over the entire region where the JBS structure is to be formed.

As another manufacturing method of the fifth embodiment, n ^- the surface of the drift layer 2, n-type semiconductor region 4, n ^- n impurity concentration of the same and the drift layer 2 ^- After the SiC layer was epitaxially grown, p There is a method of forming the type semiconductor region 3 by ion implantation. In this case, the impurity concentration and thickness of the n-type semiconductor region 4 can be formed with good control.

  The present invention has been described using the first to fifth embodiments. Although the second embodiment has been described using the first embodiment, the second embodiment can also be applied to the third to fifth embodiments. In this case, the p-type semiconductor regions 3 and p of FIG. The arrangement of the n-type semiconductor region 4 between the n-type semiconductor region 9 and the n-type semiconductor region 9 may be replaced with the arrangement of the n-type semiconductor region 4 of each of the third to fifth embodiments.

1 n ⁺ type SiC substrate 2 n ⁻ type SiC drift layer 3 p type semiconductor region 4 n type semiconductor region 5 Schottky electrode 6 ohmic electrode 7 mask material 8 n − type SiC layer 9 guard ring 10 insulating film 11 opening 12 ion

Claims (7)

A first conductivity type silicon carbide substrate;
A drift layer of the first conductivity type formed on the silicon carbide substrate and having a first impurity concentration;
A plurality of first semiconductor regions having a second conductivity type opposite to the first conductivity type, formed at a predetermined interval on a surface in the drift layer;
A Schottky electrode for Schottky connection with the drift layer;
An ohmic electrode in ohmic contact with the back surface of the silicon carbide substrate;
A second semiconductor region of the first conductivity type having a second impurity concentration higher than the first impurity concentration in a region between the first semiconductor region and the silicon carbide substrate;
A third conductive region of the first conductivity type having a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration in a region between the adjacent first semiconductor regions in the drift layer; ,
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the third semiconductor region is Schottky connected to the Schottky electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the Schottky electrode is also provided on a surface of the first semiconductor region. The semiconductor device according to claim 1,
The semiconductor device, wherein the second semiconductor region is disposed in contact with the first semiconductor region. The semiconductor device according to claim 1,
The semiconductor device, wherein the second semiconductor region has a width wider than that of the first semiconductor region. The semiconductor device according to claim 1,
The width of the first semiconductor region is wider than 1/4 of the thickness of the drift layer. The semiconductor device according to claim 1,
The third semiconductor region is in contact with both of the adjacent first semiconductor regions.

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