JP6179164B2 - Silicon carbide Schottky barrier diode. - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device.

  In recent years, semiconductors of a single crystal silicon carbide material (hereinafter referred to as SiC) having excellent characteristics not found in silicon semiconductors have attracted attention. Specifically, SiC has a band gap of about 3 times and a breakdown electric field of 5 times or more compared to silicon. For this reason, if SiC is used for the power device, a device having high performance can be expected, and some chips and devices have already begun to be sold.

  Known methods for producing single crystal SiC include the Atchison method, the Rayleigh method, the sublimation recrystallization method (improved Rayleigh method), and the solution growth method. It is manufactured by a crystal method. The sublimation recrystallization method is generally a production method in which a SiC powder raw material is filled in a lower part of a graphite crucible, heated and sublimated, and re-solidified on a seed crystal substrate disposed in the upper part of the crucible to grow a single crystal. Regarding polytypes, 4H, 6H, etc. can be produced separately according to process control conditions and the like. Generally, 4H polytype single crystals having excellent characteristics are used as materials for power devices.

  Regarding the polarity determination of the crystal material as a semiconductor, for example, nitrogen or phosphorus is used for n-type, and aluminum or boron or the like is used as an impurity in the crystal for p-type.

  The obtained crystal is processed into a substrate having a predetermined size and shape through a process similar to that of a silicon substrate. Specifically, after processing the outer periphery of the crystal, cutting with a wire saw, and further lapping each cut substrate with a polishing machine, a chemical machine to remove the damage layer on the substrate surface Polishing (CMP polishing) is performed to finish the substrate (bare substrate).

  Further, it is used as a device manufacturing substrate as a substrate (epi substrate) in which a SiC epitaxial film is formed on the bare substrate by a vapor phase epitaxial method (CVD method) or the like. In general, crystals manufactured by the modified Rayleigh method are difficult to control strictly the dope value required in the manufacture of devices, and therefore, an epitaxial layer is formed and a device structure is formed in the layer.

It is known that an epitaxial substrate manufactured by the above manufacturing method has some defects that are considered to be harmful to the device. Specifically, it is an epi surface defect group formed on the epi surface and having a shape such as an ellipse or a triangle and a concave shape (pit shape) on the epi surface. The size of the defect varies, but assuming a circle surrounding the defect, the diameter is about several tens of nanometers to several micrometers, and the depth is mostly 100 nm or less. There may be a density of several to several tens / cm ² per unit area in the substrate. Although the details of the formation process of these defects have not been elucidated yet, they can be observed using an optical microscope, an AFM (Atomic Force Microscope), or the like.

  It is known that when a Schottky Barrier Diode (hereinafter referred to as SBD) is formed based on an epitaxial substrate having surface defects and a reverse bias voltage is applied, current leakage due to the epi surface defects occurs. It becomes a cause of device failure (for example, refer nonpatent literature 1).

  In addition, there are macro defects such as epi-surface foreign matter called downfall and vacancy-like defects penetrating from the bare substrate to the epi layer called micropipes, but these are mainly due to breakdown voltage failure such as dielectric breakdown. It becomes a cause (for example, refer nonpatent literature 2).

  Schottky barrier diodes generally obtain a diode rectifying function by bonding a metal to an epitaxial layer of a semiconductor and providing a Schottky barrier. Examples of a Schottky metal for SiC include titanium, molybdenum, and nickel. Is used.

  Generally, it has a device structure in which current flows in the vertical direction from the epi layer to the bare substrate. The epi surface is the anode electrode (Schottky electrode) and the back surface of the bare substrate is the cathode electrode (ohmic electrode). The direction is the direction in which current flows from the anode to the cathode, and the reverse bias refers to applying a voltage in the direction opposite to the forward bias.

  A termination process called a guard ring is generally performed so that electric field concentration does not occur at the chip end of the Schottky metal. Specifically, a layer having a polarity different from that of the epi layer is generally provided around the end of the chip. For example, in the case of an n-type epi layer, impurities are implanted into the outer periphery of the chip by ion implantation or the like to form a p-type Form a layer. In order to further improve device characteristics, a JTE (Junction Termination Extension) structure in which a p-type layer having a slightly low impurity concentration is provided adjacent to the outside of the guard ring is known (see, for example, Patent Document 1).

JP 2011-233919

Fujiwara et al .: SiC and related wide band gap semiconductor workshop, 20th lecture, P17 Fujiwara et al .: SiC and related wide band gap semiconductor workshop, 19th lecture, P65

Although surface defects with a minute pit structure existing in SiC substrates are harmful to SBD, it is difficult to eradicate them with the current SiC epi substrate manufacturing method, and there is a constant density in commercially available SiC epi substrates. It exists, and its location differs between production lots and within lots, and the defect density also changes. Therefore, as a method of detecting an abnormality due to a surface defect, an electrical abnormality is detected in the final device energization test, or a device chip corresponding to the position of the surface defect measured on the substrate in advance is selected, There is a way to eliminate it. In such an SBD device manufacturing method, for example, when a small chip of 1 mm square size is manufactured, if a substrate having a surface defect density of 1 piece / cm ² is used, the theoretical yield is 99%. However, when a 10 mm square size large chip is manufactured, the theoretical yield is zero. The theoretical yield assumes the case where defects are evenly arranged in the substrate. If the defects are unevenly distributed, the yield of a large device may be improved, but the result is random and difficult to predict.

  Moreover, even if the other area in the large chip of about 10 mm square is healthy, the chip is discarded due to a device failure due to a leakage current generated due to the presence of only a few epi surface defects in the chip, for example. There is a problem that it becomes difficult to manufacture a large chip.

  In view of the above situation, an object of the present invention is to provide a Schottky barrier diode that operates normally even if it is a single crystal carbon SiC semiconductor substrate having an epi surface defect.

That is, the gist of the present invention is as follows.
(1) In a silicon carbide Schottky barrier diode in which a Schottky metal layer is provided on a p-type or n-type single crystal silicon carbide epitaxial layer formed on a single crystal silicon carbide substrate, a pit shape is formed in the silicon carbide epitaxial layer. The surface defect is three-dimensionally surrounded by a reverse polarity portion having a polarity opposite to that of the silicon carbide epitaxial layer in the width direction and the depth direction, and the reverse polarity portion is the surface defect. A silicon carbide Schottky barrier diode characterized in that it has an area that is twice or more in the width direction and a depth that is twice or more in the depth direction .
( 2 ) The silicon carbide Schottky barrier diode according to (1) , wherein the total area of reverse polarity sites on the surface of the silicon carbide epitaxial layer is within 0.1% of the chip area.
( 3 ) The silicon carbide Schottky barrier diode according to (1) or (2) , wherein the reverse polarity portion is a reverse polarity portion into which impurities are ion-implanted.
( 4 ) The silicon carbide Schottky barrier diode according to any one of (1) to (3) , wherein an impurity concentration of the reverse polarity portion is higher than an impurity concentration of the silicon carbide epitaxial layer.

  ADVANTAGE OF THE INVENTION According to this invention, the silicon carbide Schottky barrier diode which suppressed the current leak resulting from the surface defect of a single crystal silicon carbide epitaxial layer as much as possible can be obtained.

Schematic for explaining the first embodiment of the present invention Enlarged view for explaining a p-type reverse polarity region obtained by ion implantation for an epi surface defect FIG. 1 is an enlarged view schematically illustrating a p-type reverse polarity region when a reverse bias voltage is applied to the SBD shown in FIG. Schematic for demonstrating the manufacturing method of SBD which concerns on a 1st Example. Reverse bias characteristic of SBD according to first embodiment Schematic for explaining the second embodiment of the present invention. Enlarged view for explaining a p-type reverse polarity region obtained by ion implantation for an epi surface defect Schematic for demonstrating the manufacturing method of SBD which concerns on 2nd Example.

The present invention will be described in detail below.
The reason why the surface defects (epi surface defects) of the SiC epitaxial layer cause current leakage at the time of reverse biasing of the SBD is that there are abnormalities in the junction with the Schottky metal caused by the geometrical depression (pit shape) of the interface, It is estimated that electric field concentration is the main cause. Therefore, in the present invention, a depletion layer of a pn junction around the defect site is formed when a reverse bias voltage is applied to the SBD by forming a site having a reverse polarity to the epi layer with respect to the epi surface defect. It has been found that by spreading, the electric field at the defect site can be relaxed and reverse leakage current can be prevented.

  After the epi layer is formed, the surface is observed with an optical microscope, etc., the defect size and position are detected, and then ion implantation is performed on the site, so that the site having the opposite polarity to the epi layer around the surface defect Form. That is, if the epi layer is n-type, impurities are ion-implanted so that the portion containing the surface defect becomes p-type, and if the epi layer is p-type, the portion containing the surface defect becomes n-type. Impurities are ion-implanted. Preferably, ion-implantation is performed to form an area with the reverse polarity so that the area with the reverse polarity surrounds the epi surface defect three-dimensionally, with an area larger than the epi surface defect and a depth greater than the epi surface defect. Then, it is preferable to relax the electric field concentration on the defect surface by spreading of the depletion layer when the pn junction is reverse-biased.

  On the other hand, in the case of forward energization, the depletion layer at the pn junction portion does not spread, and therefore there exists a reverse polarity portion with almost the same area and depth of ion implantation. Also, SiC has a built-in voltage at the pn junction portion that is physically higher than that of silicon, and when a forward voltage is applied, the reverse polarity portion does not become an energized portion. For this reason, the effective area decreases during forward energization, and there is concern about an increase in on-resistance as an SBD. For example, there are about 100 circular reverse polarity parts with a diameter of 2 μm in the area of a 1 mm square chip. Even so, the ratio of the lost energized area is only 0.0003%, which is not a problem. The maximum value of the total area of the reverse polarity portion may be determined based on the allowable design range of the SBD forward resistance variation, but there is no practical problem as long as it is within 0.1% of the chip area.

  The shape and area of the reverse polarity region surrounding the defect depends on the size of the mask during ion implantation and the positioning accuracy of the stepper during exposure, but it is approximately the area of the diameter of the circle surrounding the defect. It is sufficient that the defect positioning accuracy is taken into consideration, and it is preferable that the margin of the area is twice or more.

  Further, the depth of the reverse polarity region may be equal to or greater than the depth of the surface defect, and preferably has a tolerance of not less than twice the depth. In addition, since the depletion layer at the pn junction portion spreads in a lower impurity concentration, the impurity concentration at the reverse polarity portion is preferably higher than the impurity concentration of the epi layer, and there is no problem if it is practically about 100 times or more. .

  In addition, surface defects can be observed with an optical microscope, but it is difficult to obtain information in the depth direction, so only the in-focus area is brightly imaged. Confocal (confocal) It is desirable to use an optical microscope. There is an advantage that an epi surface defect can be easily discriminated in the depth direction, in particular, unevenness, and can be automated by image processing.

  Furthermore, in the SBD diode, a process of forming a guard ring or the like around the chip periphery is required. However, in the present invention, the reverse polarity part can be formed in the same process of forming the guard ring. By doing so, it is possible to save the trouble of performing masks and ion implantation separately for forming the guard ring and for forming the reverse polarity region of the present invention.

Here, FIG. 1 is a block diagram (cross-sectional view and plan view) for explaining the first embodiment of the present invention.
Reference numeral 1 denotes an n-type SiC substrate (n +) containing nitrogen as an impurity, which has a thickness of about 350 μm and is slightly inclined by 4 ° in the <11-20> direction from the (0001) Si surface. Reference numeral 2 denotes an n-type epi layer (n−) containing nitrogen as an impurity, having a thickness of 10 μm and an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ , formed on the silicon surface of one bare substrate.

Reference numeral 3 denotes a Schottky metal layer made of titanium having a thickness of 0.1 μm, on which an aluminum metal 4 having a thickness of 1 μm is bonded as an electrode. A cathode electrode (back electrode) 5 is an ohmic electrode made of nickel metal or the like and has a thickness of 3 μm. 6 and 6 are guard rings provided around the Schottky metal layer, having a width of about 2 μm, a depth of about 0.5 μm, an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ , and p-type with an aluminum element as an impurity. The layer is formed. The total size of the chip was about 2 mm × 2 mm. 7-1 and 7-2 are p-type reverse polarity sites covering epi-surface defects.

FIG. 2 is an enlarged cross-sectional view and plan view of the p-type reverse polarity regions 7-1 and 7-2. 8-1 and 8-2 shown here are defect parts, respectively. Regarding the defect size, the diameter of the circle centered on the defect was 1 μm and 0.5 μm, respectively, and the depths were 40 nm and 30 nm. Sites opposite in polarity to the epi layer formed around these epi defects, that is, p-type reverse polarity sites 7-1 and 7-2 are formed, both of which have a diameter of 2 μm and a depth of 1.0 μm. In this region, the surface defect is surrounded three-dimensionally and the impurity concentration with aluminum as an impurity is a maximum of 1 × 10 ²⁰ cm ⁻³ . FIG. 3 shows a schematic diagram when a reverse bias voltage is applied to this state. The depletion layers 9-1 and 9-2 spread around the reverse polarity portions 7-1 and 7-2, and the electric fields of the reverse polarity portions 7-1 and 7-2 are relaxed. As a result, current leakage at the time of reverse bias can be avoided.

Next, the manufacturing method of this SBD is demonstrated using FIG.
First, with respect to the single crystal SiC substrate (4H-SiC), an epitaxial substrate is prepared in which the SiC epitaxial layer 2 is formed in a predetermined impurity concentration and thickness as shown in FIG. The position coordinates of the epi defects on the epi surface are measured with respect to the epi substrate. Defects were detected by detecting a confocal laser microscope. Specifically, a SICA6X device manufactured by Lasertec was used. The geometric position information of the defect obtained by this measurement was recorded as electronic data on an electronic medium such as a hard disk.

Subsequently, as shown in FIG. 4B, a SiO ₂ mask 10 is formed on the surface of the epitaxial substrate by low-temperature-oxide (LTO) as shown in FIG. Next, a device pattern is recorded in advance, and using a programmed electron beam apparatus, a beam is applied to a predetermined portion corresponding to a guard ring along the periphery of the chip, and a mask opening 11 is formed in a part of the mask 10. Form. At this time, by using the position DATA of the epi defect site measured in advance, circular openings 12-1 and 12-2 having a diameter of 2 μm centered on the geometric position of the epi surface defects 8-1 and 8-2 are formed. Form.

  Next, aluminum was ion-implanted into the openings 11, 12-1 and 12-2 described above in a multistage manner at an acceleration voltage of 30 to 150 KeV. Since it is known that different polytypes such as 3C are likely to be generated when SiC is ion-implanted at room temperature, in this embodiment, ion implantation was performed with the entire substrate preheated to 300 ° C. or higher. In order to activate the injected portion, heat treatment was performed for 10 minutes at a temperature of 1500 ° C. or higher in an argon atmosphere. The reverse polarity part and guard ring which cover an epi surface defect were formed in the above process. Thereafter, etching was performed with a hydrofluoric acid-based etching solution, and the mask 10 was completely removed. The basic structure (d) of the present invention is completed through the above steps.

  Thereafter, the structure may be formed by a conventional SBD process. Specifically, for example, a Schottky metal layer 3 of titanium is provided at a predetermined position by using a photolithography process and a sputtering apparatus to form a Schottky electrode. To do. An aluminum metal 4 is bonded thereon as an electrode. Furthermore, the ohmic electrode is formed by forming a metal layer 5 made of nickel or the like on the back side of the epitaxial substrate and performing heat treatment. Thereby, the SBD device shown in FIG. 1 is completed.

  A probe was applied to the chip obtained above, and a reverse bias voltage was applied to measure the reverse leakage current. The result is a curve 13 in the IV characteristic of FIG. The leakage current was 1 μA or less, which is a standard for the allowable reverse leakage current value, up to a voltage of 1 kV or more. As a comparison, the IV characteristic of a chip obtained without using the present invention and containing an epi surface defect is shown by a curve 14 in FIG. Current leakage exceeding 1 μA occurred at a low reverse bias voltage, which was found to be defective.

  In combination with the formation of the guard ring as in the present embodiment, by forming a reverse polarity site on the epi surface defect, the ion implantation process can be performed once and the process can be shortened.

  If the depth of the epi surface defect is close to 2 μm corresponding to 20% of 10 μm, which is the thickness of the epi layer of the present embodiment, or if it is a through defect such as a micropipe, the reverse polarity site is obtained by the ion implantation method. However, the defect cannot cover the defect, but in the case of such a defect, a breakdown voltage failure is a problem in the first place, rather than an abnormality of the Schottky interface. However, the depth of epi-surface defects is rarely 2 μm or more, and most of the defects are as shallow as several tens of nm. Therefore, it is considered that the defect relief according to the present invention is sufficiently effective.

FIG. 6 is a block diagram (cross-sectional view and plan view) for explaining a second embodiment of the present invention.
Reference numeral 21 denotes an n-type SiC substrate (n +) having nitrogen as an impurity, a thickness of about 250 μm, and a substrate (4H-SiC) slightly inclined by 8 ° in the <11-20> direction from the (0001) Si surface. It is. Reference numeral 22 denotes an n-type epitaxial layer (n−) containing nitrogen as an impurity, having a thickness of 15 μm and an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ , and was formed on the silicon surface of the bare substrate 21.

Reference numeral 23 denotes a Schottky metal layer made of molybdenum having a thickness of 0.1 μm, on which an aluminum metal 24 having a thickness of 1 μm is bonded as an electrode. A cathode electrode (back electrode) 25 is an ohmic electrode made of nickel metal or the like and has a thickness of 3 μm. 26 is a guard ring provided around the Schottky metal layer. The guard ring has a width of about 2 μm, a depth of about 1.0 μm, and an impurity concentration of 1 × 10 ²⁰ cm ⁻³ at the maximum. Forming a layer. The total size of the chip was about 5 mm × 5 mm. Reference numeral 27 denotes a p-type reverse polarity site covering the epi surface defect.

FIG. 7 is an enlarged cross-sectional view and plan view of 27 p-type reverse polarity region. 28 shown here is a defect group. About three defects existed, and those having a diameter of a circle at the center of 0.1 to 0.5 μm and a depth of 10 to 50 nm were close to each other. A portion having a reverse polarity to the epi layer formed around these epi defects, that is, a p-type reverse polarity portion 27 is formed, and a BOX having a long side of 5 μm, a short side of 3 μm, and a depth of 1.0 μm. This is a region having a structure (box structure) and three-dimensionally surrounding a surface defect group and having an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ with boron as an impurity.

  In the case of an epi-surface defect group in which a plurality of defects are close as in the present embodiment, the defect group may be collected and covered with one reverse polarity portion, that is, the shape is not necessarily circular, such as a BOX structure. Absent. However, the reverse polarity portion is preferably formed so as to be 0.1% or less of the total chip area so as not to affect the resistance value during forward energization.

Next, the manufacturing method of this SBD is demonstrated using FIG.
First, with respect to the single crystal SiC substrate (4H-SiC), an epi substrate having an epi layer 2 formed with a predetermined impurity concentration and thickness as shown in FIG. 8A is prepared. The position coordinates of epi surface defects on the epi surface of this epi substrate were measured using a SICA6X apparatus manufactured by Lasertec. The geometric position information of the defect obtained by this measurement was recorded as electronic data on an electronic medium such as a hard disk.

  Subsequently, as shown in FIG. 8B, a mask 30 is formed with silicon dioxide on the surface of the epitaxial substrate by low-temperature-oxide (LTO) as shown in FIG. Next, a device pattern is recorded in advance, and a mask opening 31 is formed by applying a beam to a predetermined portion corresponding to a guard ring along the periphery of the chip using a programmed electron beam apparatus. At this time, the rectangular opening 32 from which the above-described BOX structure is obtained is formed so as to cover the entire epi defect group 27 by using the position DATA of the epi defect site measured in advance.

  Next, boron was ion-implanted into the openings 31 and 32 described above in a multistage manner at an acceleration voltage of 30 to 150 KeV. In this example, ion implantation was performed with the entire substrate preheated to 500 ° C. or higher. In order to activate the injected portion, heat treatment was performed for 10 minutes at a temperature of 1500 ° C. or higher in an argon atmosphere. The reverse polarity part and guard ring which cover an epi surface defect were formed in the above process. Thereafter, etching was performed with a hydrofluoric acid-based etching solution, and the mask 30 was completely removed. The basic structure (d) of the present invention is completed through the above steps.

  Thereafter, a Schottky metal layer 23 formed of molybdenum is provided at a predetermined position by using a photolithography process and a sputtering apparatus to form a Schottky electrode. An aluminum metal 24 having a thickness of 1 μm is bonded thereon as an electrode. Furthermore, the ohmic electrode is formed by forming a metal layer 25 made of nickel or the like on the back side of the epitaxial substrate and performing heat treatment. Thereby, the SBD device shown in FIG. 6 is completed. A probe was applied to the chip and a reverse bias voltage was applied to measure the reverse leakage current. The leakage current was 1 μA or less, which is a guideline for the allowable reverse leakage current value, up to a voltage of 1.5 kV or more.

  As described above, the present invention can constitute an SBD having good electrical characteristics even when an SBD is manufactured using a silicon carbide substrate having an epi surface defect. The SBD manufacturing process shown in the embodiment is a general process procedure, but it is possible to change the Schottky metal, electrode, process procedure, conditions, and the like.

  In this embodiment, the reverse polarity region around the defect is formed in the same process as the guard ring formation process, but it may be a process when providing the JTE structure, and of course, the guard ring and the reverse polarity layer process are performed respectively. It doesn't matter. In addition, JBS (Junction Barrier) is provided in which layers with different polarities are alternately provided in the chip, and depletion layers spread around the parts with different polarities during reverse bias, reducing the electric field strength at the Schottky electrode interface and reducing the leakage current. The present invention can also be applied to an SBD structure called Controlled Schottky diode) or MPD, and a reverse polarity region that covers an epi surface defect may be formed so as to overwrite the structure.

  In this embodiment, the n-type epi substrate is readily available, but the present invention can be similarly applied to a p-type epi substrate.

1 SiC substrate 2 Epi layer 3 Schottky metal layer 4 Aluminum electrode 5 Back electrode (cathode electrode)
6 Guard ring
7-1, 7-2 p-type reverse polarity site
8-1, 8-2 Epi surface defects
9-1, 9-2 Depletion layer 10 Mask material 11 Opening
12-1, 12-2 Opening 13 Current-voltage curve 14 Current-voltage curve
15-1, 15-2 p-type reverse polarity site
16-1, 16-2 Epi surface defect 21 SiC substrate 22 Epi layer 23 Schottky metal layer 24 Aluminum electrode 25 Back electrode (cathode electrode)
26 guard ring 27 p-type reverse polarity region 28 epi-surface defect 30 mask (mask material)
31 Opening 32 Opening

Claims (4)

In a silicon carbide Schottky barrier diode in which a Schottky metal layer is provided on a p-type or n-type single crystal silicon carbide epitaxial layer formed on a single crystal silicon carbide substrate, a surface defect having a pit shape in the silicon carbide epitaxial layer Is surrounded three-dimensionally by a reverse polarity portion having a polarity opposite to that of the silicon carbide epitaxial layer with respect to the width direction and the depth direction, and the reverse polarity portion is in the width direction of the surface defect. A silicon carbide Schottky barrier diode characterized in that it has an area more than twice as large as that in the depth direction and a depth more than twice as large as the depth direction . 2. The silicon carbide Schottky barrier diode according to claim 1 , wherein the total area of the reverse polarity sites on the surface of the silicon carbide epitaxial layer is within 0.1% of the chip area. The reverse polarity sites, silicon carbide Schottky barrier diode according to claim 1 or 2, wherein the impurity is opposite polar moiety which is ion-implanted. The impurity concentration of the opposite polarity sites, silicon carbide Schottky barrier diode according to any one of claims 1 to 3, wherein the higher than the impurity concentration of the silicon carbide epitaxial layer.

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