JP6171969B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  As a structure of a semiconductor device (semiconductor device, semiconductor element), a trench gate structure in which a gate electrode is formed in a trench is known. In Patent Document 1 and Patent Document 2, in order to alleviate electric field concentration generated at the bottom of the trench in the trench gate structure, at least one of thermal diffusion and ion implantation is used, and a P-type semiconductor is formed in the vicinity of the bottom of the trench. The formation of a region (floating portion) is described. Thereby, the breakdown voltage of the semiconductor device can be improved.

JP 2009-267029 A Japanese Patent Laid-Open No. 10-98188

  In the technique of Patent Document 1, a floating portion is formed by thermally diffusing P-type impurities in a gallium nitride (GaN) -based semiconductor. However, this technique has a problem that the electrical characteristics of the N-type semiconductor layer deteriorate (for example, an increase in on-resistance) because heat treatment is performed at a relatively high temperature such as 900 degrees for 60 minutes. It was. In the technique of Patent Document 2, since the floating portion is formed by ion implantation, it is difficult to form a P-type semiconductor by ion implantation (for example, a group III nitride semiconductor represented by GaN). There was a problem that could not be applied. In addition, the techniques described in Patent Document 1 and Patent Document 2 have a problem that the number of manufacturing steps for forming the floating portion is increased as compared with a semiconductor device in which the floating portion is not formed. Therefore, a technique capable of improving the electrical characteristics of a semiconductor device having a trench and a technique for facilitating manufacture have been desired. In addition, in semiconductor devices, miniaturization, cost reduction, and improvement in durability have been desired.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
The first aspect of the present invention is a method for manufacturing a semiconductor device. The semiconductor device includes: a first semiconductor layer that is a first conductivity type semiconductor; a second semiconductor layer that is a second conductivity type semiconductor in contact with an upper surface of the first semiconductor layer; and an upper surface of the second semiconductor layer. A third semiconductor layer that is a semiconductor of a first conductivity type, and a stacked body that is sequentially stacked from the first semiconductor layer side; the first semiconductor layer penetrating from the upper surface of the third semiconductor layer through the second semiconductor layer; A gate trench comprising: a sub-trench reaching the semiconductor layer; and a convex portion surrounded by the sub-trench, wherein the second semiconductor layer is exposed on an upper surface of the convex portion; A recess reaching from the upper surface to the second semiconductor layer; the manufacturing method includes: (A) forming a recess in the stacked body and forming a protrusion in which the recess is formed; Covering the region and forming the sub-trench. Forming a first mask having an opening in a sub-trench formation region; (B) performing a dry etching after the step (A); (C) after the step (B); Among them, a step of forming a second mask by removing portions corresponding to the recess formation region and the convex portion formation region; (D) a step of performing dry etching after the step (C); In at least one of the step (B) and the step (D), dry etching is performed so that the lower surface of the sub-trench reaches the first semiconductor layer,
In the step (D), dry etching is performed so that the lower surface of the recess and the upper surface of the convex portion reach the second semiconductor layer.
The second aspect of the present invention is a method for manufacturing a semiconductor device. The semiconductor device includes: a first semiconductor layer that is a first conductivity type semiconductor; a second semiconductor layer that is a second conductivity type semiconductor in contact with an upper surface of the first semiconductor layer; and an upper surface of the second semiconductor layer. A third semiconductor layer that is a semiconductor of a first conductivity type, and a stacked body that is sequentially stacked from the first semiconductor layer side; the first semiconductor layer penetrating from the upper surface of the third semiconductor layer through the second semiconductor layer; A gate trench comprising: a sub-trench reaching the semiconductor layer; and a convex portion surrounded by the sub-trench, wherein the second semiconductor layer is exposed on an upper surface of the convex portion; And a manufacturing method comprising: (a) forming a recess formation region in which the recess is formed and a gate trench in which the gate trench is formed in the stacked body; 3rd cell with open area (B) a step of performing dry etching after the step (a); (c) a convex portion on which the convex portion is formed on the third mask after the step (b). Forming a fourth mask covering the formation region and the recess formation region; (d) performing a dry etching after the step (c); and in the step (b), a bottom surface of the recess In the step (d), dry etching is performed so that the lower surface of the sub-trench reaches the first semiconductor layer.
The present invention can also be applied as the following forms.

(1) According to one aspect of the present invention, a first semiconductor layer that is a first conductivity type semiconductor, a second semiconductor layer that is a second conductivity type semiconductor in contact with an upper surface of the first semiconductor layer, A stacked body in which a third semiconductor layer which is a first conductivity type semiconductor in contact with the upper surface of the second semiconductor layer is stacked in order from the first semiconductor layer side; and the second semiconductor from the upper surface of the third semiconductor layer A gate trench comprising: a sub-trench extending through the layer to reach the first semiconductor layer; and a protrusion surrounded by the sub-trench and having the second semiconductor layer exposed on an upper surface thereof; There is provided a method of manufacturing a semiconductor device having a recess extending from an upper surface to the second semiconductor layer. In this method of manufacturing a semiconductor device, (A) the stacked body covers a recess formation region where the recess is formed and a projection formation region where the projection is formed, and the sub-trench is formed. Forming a first mask having an opening in a trench formation region; (B) performing a dry etching after the step (A); (C) after the step (B), among the first masks; A step of forming a second mask by removing corresponding portions on the recess formation region and the convex formation region; and (D) a step of performing dry etching after the step (C). In the step (B) or the step (D), dry etching is performed so that the lower surface of the sub-trench reaches the first semiconductor layer; in the step (D), the previous step Lower and upper surfaces of the convex portions of the recesses by dry etching so as to reach the second semiconductor layer. According to the method for manufacturing a semiconductor device of this aspect, since the gate trench including the convex portion having the second conductivity type semiconductor layer is formed, the concentration of the electric field generated on the lower surface of the gate trench can be reduced. Therefore, the breakdown voltage performance of the semiconductor device can be improved. Further, in order to alleviate the concentration of the electric field generated on the lower surface of the gate trench, it is not necessary to perform ion implantation or impurity thermal diffusion treatment. Therefore, it is possible to suppress the impurities in the second semiconductor layer from diffusing into the first semiconductor layer and the like, thereby suppressing an increase in on-resistance. As a result, the electrical characteristics of the semiconductor device can be improved. In addition, after dry etching is performed using the first mask in which the sub-trench formation region is opened and the convex portion formation region is covered, in step (C), on the recess formation region and the convex portion formation region. By removing the corresponding part, the second mask is formed. Thereafter, in step (D), dry etching is performed on the recess formation region, the protrusion formation region, and the sub-trench formation region. Therefore, even if the dry etching is performed twice in total in the step (B) and the step (D) for the gate trench, the change in the dimension (width) of the sub-trench and the convex portion can be suppressed. Further, the convex portion having the second conductivity type semiconductor layer is formed by dry etching for forming the recess and the gate trench using the second conductivity type semiconductor layer before the gate trench is formed. be able to. Therefore, it is not necessary to separately provide a process for forming the convex portion, so that the process can be simplified and the manufacturing cost can be reduced. In addition, the depth of the sub-trench can be set to an appropriate depth by dry etching in the step (B) and the step (D).

(2) In the method of manufacturing a semiconductor device according to the above aspect, in the step (C); (C1) a resist pattern having openings in portions corresponding to the recess formation region and the protrusion formation region; A step of forming on the mask; and (C2) removing portions corresponding to the recess formation region and the convex formation region of the first mask by performing dry etching after the step (C1). And a step of performing. According to the method of manufacturing a semiconductor device of this aspect, the first mask is formed on the first mask by forming a resist pattern having openings in the corresponding portions on the recess formation region and the projection formation region. Can be used to form the second mask.

(3) In the method of manufacturing a semiconductor device according to the above aspect, in the step (C); (C1) a resist pattern having an opening in at least a part of the portion corresponding to the convex portion formation region of the first mask. A step of forming on the first mask; and (C2) a step of removing a portion of the first mask corresponding to the projection forming region by performing wet etching after the step (C1). And (C3) removing a portion corresponding to the recess formation region of the first mask by performing dry etching. According to the method for manufacturing a semiconductor device of this aspect, the resist pattern having an opening in at least a part of the portion corresponding to the convex portion formation region is formed on the first mask. The protrusion formation region can be removed from one mask. Therefore, even when the width of the gate trench is narrow, it is possible to suppress changes in the dimensions (width) of the sub-trench and the convex portion due to the dry etching twice in total in the step (B) and the step (D). . Therefore, the semiconductor device can be miniaturized.

(4) According to another aspect of the present invention, a first semiconductor layer that is a first conductivity type semiconductor, a second semiconductor layer that is a second conductivity type semiconductor in contact with the upper surface of the first semiconductor layer, A stacked body in which a third semiconductor layer, which is a first conductivity type semiconductor in contact with an upper surface of the second semiconductor layer, is stacked in order from the first semiconductor layer side; and from the upper surface of the third semiconductor layer to the second A gate trench comprising: a sub-trench extending through the semiconductor layer to reach the first semiconductor layer; and a protrusion surrounded by the sub-trench and having a second semiconductor layer exposed on an upper surface thereof; And a recess reaching from the upper surface to the second semiconductor layer. In this method of manufacturing a semiconductor device, (a) a step of forming, in the stacked body, a third mask in which a recess forming region in which the recess is formed and a gate trench forming region in which the gate trench is formed is opened; (B) a step of performing dry etching after the step (a); and (c) a convex portion forming region in which the convex portion is formed and the recess formation on the third mask after the step (b). A step of forming a fourth mask covering the region; and (d) a step of performing dry etching after the step (c); in the step (b), the lower surface of the recess and the upper surface of the convex portion In the step (d), dry etching is performed so that the lower surface of the sub-trench reaches the first semiconductor layer. According to the method for manufacturing a semiconductor device of this aspect, since the gate trench having the convex portion having the semiconductor layer of the second conductivity type is formed, the concentration of the electric field generated on the lower surface (bottom portion) of the gate trench is reduced. Can do. Therefore, the breakdown voltage performance of the semiconductor device can be improved. Further, in order to alleviate the concentration of the electric field generated on the lower surface (bottom portion) of the gate trench, it is not necessary to perform ion implantation or impurity thermal diffusion treatment. Therefore, it is possible to suppress the impurities in the second semiconductor layer from diffusing into the first semiconductor layer and the like, thereby suppressing an increase in on-resistance. As a result, the electrical characteristics of the semiconductor device can be improved. In addition, after the dry etching is performed using the third mask in which the recess formation region and the gate trench formation region are opened, in the step (c), the recess formation region and the convex formation region are covered, thereby The mask is formed. Thereafter, in step (d), dry etching is performed on the sub-trench formation region. Therefore, even if the dry etching is performed twice in total in the step (b) and the step (d), the change in the dimension (width) of the gate trench can be suppressed. Further, the convex portion having the second conductivity type semiconductor layer is formed by dry etching for forming the recess and the gate trench using the second conductivity type semiconductor layer before the gate trench is formed. be able to. Therefore, it is not necessary to separately provide a process for forming the convex portion, so that the process can be simplified and the manufacturing cost can be reduced. Further, the depth of the sub-trench can be set to an appropriate depth by dry etching in the step (b) and the step (d).

(5) In the method for manufacturing a semiconductor device according to the above aspect, a gallium nitride (GaN) based semiconductor layer may be used as the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. According to the method for manufacturing a semiconductor device of this aspect, in a GaN-based semiconductor device in which it is difficult to form a second conductivity type semiconductor layer by ion implantation, the concentration of the electric field generated on the lower surface of the gate trench is reduced. can do.

(6) According to another aspect of the present invention, there is provided a semiconductor device manufactured by the manufacturing method according to any one of the above aspects (1) to (5). According to the semiconductor device of this aspect, the concentration of the electric field generated on the lower surface of the gate trench can be reduced.

(7) In the semiconductor device of the above aspect, the lower surface of the recess and the upper surface of the convex portion may exist on the same surface. According to the semiconductor device of this aspect, the convex portion having the second conductivity type semiconductor layer can be formed using the second conductivity type semiconductor layer before the gate trench is formed. Therefore, it is not necessary to separately provide a process for forming the convex portion, so that the process can be simplified and the manufacturing cost can be reduced.

  A plurality of constituent elements of each aspect of the present invention described above are not indispensable, and some or all of the effects described in the present specification are to be solved to solve part or all of the above-described problems. In order to achieve the above, it is possible to appropriately change, delete, replace with another new component, and partially delete the limited contents of some of the plurality of components. In order to solve part or all of the above-described problems or to achieve part or all of the effects described in this specification, technical features included in one embodiment of the present invention described above. A part or all of the technical features included in the other aspects of the present invention described above may be combined to form an independent form of the present invention.

  The present invention can also be realized in various forms other than the semiconductor device described above and the method for manufacturing the semiconductor device. For example, power semiconductor devices used in applications that increase power efficiency, such as server power supplies and air conditioners equipped with semiconductor devices, power conditioners for solar power generation systems, quick chargers for electric vehicles (EVs), and power converters for railways Can be realized. Moreover, it is realizable with forms, such as a manufacturing apparatus which manufactures a semiconductor device.

  According to the present invention, since the gate trench having the convex portion having the semiconductor layer of the second conductivity type is formed, the concentration of the electric field generated on the lower surface of the gate trench can be reduced. Therefore, the breakdown voltage performance of the semiconductor device can be improved. Further, in order to alleviate the concentration of the electric field generated on the lower surface of the gate trench, it is not necessary to perform ion implantation or impurity thermal diffusion treatment. Therefore, it is possible to suppress the impurities in the second semiconductor layer from diffusing into the first semiconductor layer and the like, thereby suppressing an increase in on-resistance. As a result, the electrical characteristics of the semiconductor device can be improved. In addition, after dry etching is performed using the first mask in which the sub-trench formation region is opened and the convex portion formation region is covered, in step (C), on the recess formation region and the convex portion formation region. By removing the corresponding part, the second mask is formed. Thereafter, in step (D), dry etching is performed on the recess formation region, the protrusion formation region, and the sub-trench formation region. Therefore, even if the dry etching is performed twice in total in the step (B) and the step (D) for the gate trench, the change in the dimension (width) of the sub-trench and the convex portion can be suppressed. Further, the convex portion having the second conductivity type semiconductor layer is formed by dry etching for forming the recess and the gate trench using the second conductivity type semiconductor layer before the gate trench is formed. be able to. Therefore, it is not necessary to separately provide a process for forming the convex portion, so that the process can be simplified and the manufacturing cost can be reduced. In addition, the depth of the sub-trench can be set to an appropriate depth by dry etching in the step (B) and the step (D).

  According to another aspect of the present invention, after the dry etching is performed using the third mask in which the recess formation region and the gate trench formation region are opened, in the step (c), the recess formation region and the protrusion are formed. A fourth mask is formed by covering the formation region. Thereafter, in step (d), dry etching is performed on the sub-trench formation region. Therefore, even if the dry etching is performed twice in total in the step (b) and the step (d), the change in the dimension (width) of the gate trench can be suppressed. Further, the convex portion having the second conductivity type semiconductor layer is formed by dry etching for forming the recess and the gate trench using the second conductivity type semiconductor layer before the gate trench is formed. be able to. Therefore, it is not necessary to separately provide a process for forming the convex portion, so that the process can be simplified and the manufacturing cost can be reduced. Further, the depth of the sub-trench can be set to an appropriate depth by dry etching in the step (b) and the step (d).

FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment. 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the semiconductor device in the manufacture process in which the 1st mask was formed. The figure which shows the semiconductor device in the manufacture process in which the dry etching was performed. The figure which shows the semiconductor device in the manufacture process in which the resist pattern was formed. The figure which shows the semiconductor device in the manufacture process from which the mask on a recess formation area and a convex part formation area was removed. The figure which shows the semiconductor device in a manufacture process from which the resist pattern was removed and the 2nd mask was formed. The figure which shows the semiconductor device in a manufacture process in which dry etching was performed. The figure which shows the semiconductor device in a manufacture process from which the 2nd mask was removed. 9 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. The figure which shows the semiconductor device in a manufacture process in which the recess formation area | region was removed from the 1st mask. The figure which shows the semiconductor device in a manufacture process in which the resist pattern which has an opening was formed on the convex part formation area. 9 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. The figure which shows the semiconductor device in a manufacture process in which the 3rd mask was formed. The figure which shows the semiconductor device in a manufacture process in which dry etching was performed. The figure which shows the semiconductor device in a manufacture process in which the 4th mask was formed. The figure which shows the semiconductor device in a manufacture process in which dry etching was performed.

A. First embodiment:
A1. Semiconductor device configuration:
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 in the first embodiment. In FIG. 1, a part of the cross section of the semiconductor device 10 in the present embodiment is shown in a simplified manner. FIG. 1 is a diagram for clearly showing the technical features of the semiconductor device 10 and does not accurately show the dimensions of each part. FIG. 1 also shows XYZ axes orthogonal to each other for ease of explanation. The same applies to the subsequent drawings.

  The semiconductor device 10 in this embodiment is a gallium nitride (GaN) -based trench gate type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

  The semiconductor device 10 includes a substrate 110, a first semiconductor layer 120, a second semiconductor layer 130, a third semiconductor layer 140, a recess 220, a gate trench 250, an insulating film 260, a gate electrode 270, and a drain. Electrode 210, p-body electrode (hereinafter referred to as body electrode) 230, and source electrode 240 are provided. The semiconductor device 10 is an NPN-type semiconductor device, in which a first semiconductor layer 120 of an N-type semiconductor, a second semiconductor layer 130 of a P-type semiconductor, and a third semiconductor layer 140 of an N-type semiconductor are sequentially stacked. It has a structure. In the present embodiment, the “first conductivity type semiconductor” of the present application corresponds to an N-type semiconductor, and the “second conductivity type semiconductor” of the present application corresponds to a P-type semiconductor. The structure in which the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140 are stacked is also referred to as “stacked body 11”, and the + Z direction (the direction in which each layer is stacked) is “upward”. The −Z direction is also referred to as “downward”. Of the surfaces of the substrate 110, the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140, the upper surface is also referred to as “upper surface” and the lower surface is also referred to as “lower surface”. Further, the surface in the −Z direction of each of the recess 220 and the gate trench 250 is also referred to as a “lower surface”.

The substrate 110 of the semiconductor device 10 has a plate shape that extends along the XY plane. The substrate 110 is a GaN-based substrate and contains silicon (Si) as a dopant (donor). In the present embodiment, the average concentration of silicon in the entire region of the substrate 110 is 1.0 × 10 ¹⁸ cm ⁻³ .

The first semiconductor layer 120 is formed in a state of being stacked on the upper surface of the substrate 110. The first semiconductor layer 120 is a GaN-based semiconductor and contains Si as a dopant (donor) at a concentration lower than that of the substrate 110. In the present embodiment, the average concentration of silicon in the entire area of the first semiconductor layer 120 is 1.0 × 10 ¹⁶ cm ⁻³ . The thickness of the first semiconductor layer 120 in the + Z direction is 10 μm (micrometer).

The second semiconductor layer 130 is formed in a state of being stacked on the upper surface of the first semiconductor layer 120. The second semiconductor layer 130 is a GaN-based semiconductor and contains magnesium (Mg) as a dopant (acceptor). In the present embodiment, the average concentration of magnesium in the entire area of the second semiconductor layer 130 is 1.0 × 10 ¹⁸ cm ⁻³ . The thickness of the second semiconductor layer 130 in the + Z direction is 1.0 μm.

The third semiconductor layer 140 is formed in a state of being stacked on the upper surface of the second semiconductor layer 130. The third semiconductor layer 140 is a GaN-based semiconductor and contains silicon (Si) as a dopant (donor) at a higher concentration than the first semiconductor layer 120. In the present embodiment, the average concentration of silicon in the entire third semiconductor layer 140 is 3.0 × 10 ¹⁸ cm ⁻³ . The thickness of the third semiconductor layer 140 in the + Z direction is 0.3 μm.

  The recess 220 is a recess for forming the body electrode 230. The recess 220 is formed so as to reach the second semiconductor layer 130 from the upper surface of the third semiconductor layer 140 by dry etching the recess formation region 222 of the stacked body 11.

  The gate trench 250 includes a sub-trench 251 and a convex portion 300 surrounded by the sub-trench 251. The sub-trench 251 is formed so as to reach the first semiconductor layer 120 from the upper surface of the third semiconductor layer 140 through the second semiconductor layer 130 by dry etching the sub-trench formation region 253 of the stacked body 11. ing. The convex portion 300 is formed by dry etching the convex portion forming region 302 in the gate trench forming region 252. The convex part 300 has a second conductivity type semiconductor layer on the upper surface thereof. Hereinafter, the second conductivity type semiconductor layer included in the convex portion 300 is also referred to as a “floating portion 301”. In this embodiment, the width in the y direction of the sub-trench 251 and the width in the y direction of the protrusion 300 are each about 0.35 μm, and the width in the y direction of the gate trench 250 is about 1.05 μm. It is.

The floating part 301 alleviates the concentration of the electric field generated on the lower surface of the gate trench 250 (the lower surface of the sub-trench 251). The floating portion 301 is formed by performing at least one of dry etching for forming the sub-trench 251 and / or dry etching for forming the recess 220 on the stacked body 11 (details will be described later). Therefore, the floating portion 301 is the same GaN-based P-type semiconductor as the second semiconductor layer 130, and Mg is used as a dopant (acceptor) at the same concentration (1.0 × 10 ¹⁸ cm ⁻³ ) as the second semiconductor layer 130. contains. Further, the upper surface of the convex portion 300, that is, the upper surface of the floating portion 301 and the lower surface of the recess 220 are on the same plane.

The insulating film 260 is a film formed so as to continuously cover the gate trench 250 and the upper surface of the third semiconductor layer 140 at the periphery of the gate trench 250. In the present embodiment, the insulating film 260 is formed of silicon oxide (SiO ₂ ).

  The gate electrode 270 is an electrode formed so as to continuously cover the gate trench 250 and the upper surface of the third semiconductor layer 140 at the periphery of the gate trench 250 with the insulating film 260 interposed therebetween. In the present embodiment, the gate electrode 270 is made of aluminum (Al).

  The body electrode 230 is an electrode formed in the recess 220 so as to be in ohmic contact with the second semiconductor layer 130. In this embodiment, the body electrode 230 is formed by laminating a layer made of nickel (Ni) and a layer made of gold (Au) and then heat-treating, and the layer made of gold (Au) is positioned above. It has the structure to do.

  The source electrode 240 is an electrode formed so as to be connected to the third semiconductor layer 140. In this embodiment, the source electrode 240 is formed by laminating a layer made of aluminum (Al) and a layer made of titanium (Ti) and then heat-treating, and the layer made of aluminum (Al) faces upward. It has a positioned structure.

  The drain electrode 210 is an electrode formed on the lower surface of the substrate 110. In this embodiment, the drain electrode 210 is formed by laminating a layer made of titanium (Ti) and a layer made of (Al) and then performing heat treatment, and the layer made of titanium is located above (the lower surface side of the substrate 110). It has the structure located in.

A2. Manufacturing method of semiconductor device:
FIG. 2 is a flowchart showing a method for manufacturing the semiconductor device 10. In order to manufacture the semiconductor device 10, first, the stacked body 11 in which the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140 are stacked on the substrate 110 is prepared (step S100). The stacked body 11 is manufactured by sequentially stacking the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140 on the substrate 110 by crystal growth by MOCVD (Metal Organic Chemical Vapor Deposition) method. Is done.

Next, as shown in FIG. 3, a first mask 400 is formed on the stacked body 11 so as to cover the recess formation region 222 and the projection formation region 302 and open the sub-trench formation region 253 (Step S <b> 102). ). Specifically, in step S102, as shown in FIG. 3, the first trench having a sub-trench formation region 253 formed of a mask 401 covering the recess formation region 222 and a mask 402 covering the convex formation region 302 is opened. A mask 400 is formed. The first mask 400 is made of, for example, SiO ₂ . The first mask 400 defines the dimension (width) of the sub-trench 251 and the dimension (width) of the convex portion 300. Here, the dimension means the width in the xy plane (the width in the x direction and the width in the y direction). In the present embodiment, a photolithography apparatus having an alignment accuracy (α) of 0.1 μm or less and a resolution (β) of 0.35 μm is used. Step S102 corresponds to step (A) of the present application. FIG. 3 is a diagram illustrating the semiconductor device 12 in the manufacturing process in which the first mask 400 is formed.

Next, dry etching is performed on the semiconductor device 12 in the manufacturing process in which the first mask 400 is formed (step S104). FIG. 4 is a diagram showing the semiconductor device 13 in the manufacturing process in which dry etching has been performed. In step S104, dry etching is performed on the sub-trench formation region 253 from the opening of the first mask 400 using a chlorine-based gas (for example, a mixed gas of BCl ₃ and Cl ₂ ), so that the sub-trench is formed. The lower surface of 251 reaches the first semiconductor layer 120. Step S104 corresponds to step (B) of the present application. In the subsequent dry etching process (step S116), if the lower surface of the sub-trench 251 reaches the first semiconductor layer 120, the lower surface of the sub-trench 251 does not need to reach the first semiconductor layer 120 in step S104.

  Next, the second mask 410 (see FIG. 7) is formed by removing the masks on the recess formation region 222 and the convex formation region 302 from the first mask 400 (step S110). Specifically, in step S110, first, a resist pattern 500 (501, 502) having openings is formed on the recess formation region 222 and the convex formation region 302 (step S112).

  FIG. 5 is a diagram showing the semiconductor device 14 in the manufacturing process in which the resist pattern 500 is formed. As shown in FIG. 5, the resist pattern 502 on the upper surface of the first mask 401 reaches from the upper surface of the first mask 401 to the lower surface of the sub-trench 251 and covers a part of the lower surface of the sub-trench 251. However, the resist pattern 500 formed in step S <b> 112 may cover the entire lower surface of the sub-trench 251 as long as it has openings on the recess formation region 222 and the convex formation region 302. The resist pattern 500 formed in step S112 has openings on the recess formation region 222 and the convex formation region 302, and covers the first mask 401 to the sub-trench 251 formation region side. For example, it does not have to reach the lower surface of the sub-trench 251.

  When the resist pattern 500 is formed, as shown in FIG. 6, the masks on the recess formation region 222 and the projection formation region 302 are removed from the first mask 400 by, for example, dry etching with hydrofluoric acid gas ( Step S114), and thereafter, the resist pattern 500 is removed as shown in FIG. In this way, the second mask 410 is formed. FIG. 6 is a diagram illustrating the semiconductor device 15 in the manufacturing process in which the masks on the recess formation region 222 and the convex portion formation region 302 are removed. FIG. 7 is a diagram showing the semiconductor device 16 in the manufacturing process in which the resist pattern 500 is removed and the second mask 410 is formed. Step S110 corresponds to the process (C) of the present application, step S112 corresponds to the process (C1) of the present application, and step S114 corresponds to the process (C2) of the present application.

  Next, dry etching using a chlorine-based gas is performed on the semiconductor device 16 in the manufacturing process in which the second mask 410 is formed (step S116). FIG. 8 is a diagram showing the semiconductor device 17 in the manufacturing process in which dry etching is performed. In step S 116, dry etching is performed on the recess formation region 222, the convex formation region 302, and the sub-trench formation region 253 from the opening of the second mask 410. In step S <b> 116, dry etching is performed so that the lower surface of the recess 220 and the upper surface of the protrusion 300 reach the second semiconductor layer 130. In the recess formation region 222 and the convex formation region 302, dry etching is not performed in the above-described step S104, and dry etching is performed for the first time in step S116. Therefore, as shown in FIG. 8, the lower surface of the recess 220 and the upper surface of the convex portion 300 after the completion of step S116 are on the same plane. Step S116 corresponds to step (D) of the present application.

  Next, as shown in FIG. 9, the second mask 410 is removed from the semiconductor device 17 in the manufacturing process in which dry etching has been performed (step S118). FIG. 9 is a diagram illustrating the semiconductor device 18 in the manufacturing process from which the second mask 410 has been removed.

  Next, an insulating film 260 is formed on the upper surface of the semiconductor device 18 in the manufacturing process, and then the insulating film 260 on the recess 220 and the region where the source electrode 240 is to be formed is removed, and an electrode (gate electrode 270, The body electrode 230, the source electrode 240, and the drain electrode 210) are formed (step S120). Through the above steps, the semiconductor device 10 of this embodiment is manufactured.

A3. effect:
According to the method for manufacturing the semiconductor device 10 of the present embodiment, the gate trench 250 including the convex portion 300 is formed. Since the convex portion 300 includes the floating portion 301 which is the second conductivity type semiconductor layer, the concentration of the electric field generated on the lower surface (bottom portion) of the gate trench 250 can be reduced. Therefore, withstand voltage performance can be improved as compared with a semiconductor device that does not include the floating portion 301. Further, in order to reduce the concentration of the electric field generated on the lower surface (bottom portion) of the gate trench 250 by forming the floating portion 301, it is not necessary to perform ion implantation or thermal diffusion treatment of impurities. Therefore, it is possible to suppress the impurities in the second semiconductor layer from diffusing into the first semiconductor layer and the like, thereby suppressing an increase in on-resistance. As a result, the electrical characteristics of the semiconductor device 10 can be improved.

  In addition, according to the manufacturing method of the semiconductor device 10 of the present embodiment, in the GaN-based semiconductor device in which it is difficult to form the floating portion by ion implantation, the concentration of the electric field generated on the lower surface of the gate trench is reduced. Can do.

  In addition, after dry etching is performed using the first mask in which the sub-trench formation region 253 is opened and the convex formation region 302 is covered, the first mask 400 and the convex formation on the recess formation region 222 are formed. By removing the first mask 400 (402) over the region 302, the second mask 410 is formed. Thereafter, dry etching is performed on the recess formation region 222, the protrusion formation region 302, and the sub-trench formation region 253. Therefore, dry etching is performed on the stacked body 11 using the first mask 400 having an opening in the sub-trench formation region 253, whereby the dimensions of the sub-trench 251 and the dimensions of the convex portion 300 are determined. Therefore, even if dry etching is performed twice in total, changes in the dimensions of the sub-trench 251 and the convex portion 300 can be suppressed without considering the alignment accuracy for forming the mask pattern.

  Further, the protrusion 300 having the second conductivity type semiconductor layer is a dry layer for forming the recess 220 and the gate trench 250 using the second conductivity type semiconductor layer 130 before the gate trench 250 is formed. It can be formed by etching. Therefore, it is not necessary to separately provide a process for forming the convex portion 300, so that the process can be simplified and the manufacturing cost can be reduced. In addition, the depth of the sub-trench 251 can be adjusted to an appropriate depth by performing dry etching twice on the semiconductor layer (stacked body 11).

B. Second embodiment:
B1. Semiconductor device configuration:
Since the configuration of the semiconductor device in the second embodiment is the same as the configuration of the semiconductor device in the first embodiment, description thereof is omitted.

B2. Manufacturing method of semiconductor device:
FIG. 10 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment. The difference between the semiconductor device manufacturing method of the present embodiment and the semiconductor device manufacturing method of the first embodiment is the step of forming a second mask (FIG. 10: step S210, FIG. 2: step S110). The other processes of the second embodiment (FIG. 10: Steps S200 to S204, Steps S216 to S220) are the same as the processes of the first embodiment (FIG. 2: S100 to Step S104, Steps S116 to S120). Therefore, the description is omitted.

  Specifically, in the first embodiment, in the step of forming the second mask 410 (FIG. 2, step S110), the resist pattern 500 (having openings on the recess formation region 222 and the convex formation region 302) ( 501 and 502) are formed (FIG. 2, Step S112), and then the masks on the recess formation region 222 and the convex formation region 302 are removed from the first mask 400 by dry etching with hydrofluoric acid gas. Thus (FIG. 2, step S114), the second mask 410 was formed. In contrast, in the second embodiment, the second mask 410 is formed as follows.

  In the second embodiment, in the step of forming the second mask 410 (FIG. 10, step S210), the resist pattern 520 (521, 522) having an opening in the portion corresponding to the recess formation region 222 is replaced with the first mask 400. It is formed on top (step S211). Next, as shown in FIG. 11, the recess formation region 222 is removed from the first mask 400 by dry etching with hydrofluoric acid gas (step S212). FIG. 11 is a diagram illustrating the semiconductor device 19 in the manufacturing process in which the recess formation region 222 is removed from the first mask 400. FIG. 11 shows the masks 402, 411, and 412, and the resist pattern 520, in the first mask 400 from which the recess formation region 222 has been removed. Note that when the recess formation region 222 of the first mask 400 is removed, the resist pattern 520 is removed. Step S212 corresponds to the step (C3) of the present application.

  Next, a resist pattern 510 having an opening in at least a part of the corresponding portion on the convex formation region 302 and covering the recess formation region 222 is formed on the first mask 400 (FIG. 10, step S213). ). Step S213 corresponds to the step (C1) of the present application.

  FIG. 12 is a diagram showing the semiconductor device 20 in the manufacturing process in which a resist pattern 510 having an opening is formed on the convex portion formation region 302. As shown in FIG. 12, the resist pattern 510 has an opening in a portion corresponding to the convex portion formation region 302 and covers the recess formation region 222 and the sub-trench formation region 253. . If the resist pattern 510 covers the upper surface and side surfaces of the masks (411, 412) on the recess formation region 222 that define the dimension of the sub-trench 251, an opening is also formed on a part of the sub-trench formation region 253. You may have.

  When the resist pattern 510 is formed, the mask 402 on the convex portion formation region 302 is removed from the first mask 400 formed in step S202 by wet etching of a hydrofluoric acid solution (FIG. 10, step S214). ). In step S214, wet etching is performed from above the convex portion forming region 302, which is an opening of the resist pattern 510, so that the mask 402 on the convex portion forming region 302 is removed. Step S214 corresponds to the step (C2) of the present application. Thereafter, as in the first embodiment, the resist pattern 510 is removed (FIG. 7). In this way, the second mask 410 is formed.

  In the semiconductor device 20 shown in FIG. 12, the first mask 400 on the recess formation region 222 has already been removed by dry etching, and a resist pattern 510 is formed thereon. On the other hand, the resist pattern 510 may be formed while leaving the first mask 400 on the recess formation region 222. In this case, in the first mask 400 on the recess formation region 222, after wet etching (step S214), a resist pattern 520 having an opening is formed on the recess formation region 222, and dry etching with hydrofluoric acid gas is performed. May be removed by performing. That is, step S211 to step S212 may be performed after step S213 to step S214 are performed.

B3. effect:
According to the method for manufacturing a semiconductor device of the present embodiment, the gate trench 250 including the convex portion 300 is formed in the GaN-based semiconductor layer. Further, the protrusion 300 having the second conductivity type semiconductor layer is a dry layer for forming the recess 220 and the gate trench 250 using the second conductivity type semiconductor layer 130 before the gate trench 250 is formed. It can be formed by etching. Further, a second mask 410 is formed using the first mask 400. Therefore, the same effects as those of the first embodiment described above can be obtained.

  Generally, in a photolithography apparatus (stepper), when the alignment accuracy (α) is worse than the resolution (β) and the width of the sub-trench 251 is narrowed, the above-described first embodiment is used as shown in FIG. As described, it may be difficult to form the resist pattern 500 (502) that does not cover the convex portion formation region 302. Note that the alignment accuracy (α) is worse than the resolution (β) means that the alignment accuracy value is larger than the resolution value. As described above, when the alignment accuracy (α) is worse than the resolution (β) and the width (tw) of the sub-trench 251 is narrowed, the resist pattern 500 (502) is, for example, as shown in FIG. As shown, there is a case where a part on the convex portion forming region 302 is covered. In such a state, if the resist pattern is removed by dry etching as in the first embodiment described above, the width of the sub-trench 251 or the protrusion 300 may change in the subsequent etching of the semiconductor layer.

  However, in this embodiment, a resist pattern 510 having an opening is formed on the convex portion formation region 302 of the first mask 400, and then wet etching is performed. The first mask 400 (402) on the convex portion formation region 302 is removed by wet etching if the resist pattern 510 has an opening in at least a part of the portion corresponding to the convex portion formation region 302. The Therefore, even when the width of the sub-trench 251 is narrow, a change in the width of the sub-trench 251 due to the dry etching of the semiconductor layer (stacked body 11) twice in total can be suppressed. Therefore, the minimum dimension of the sub-trench (the width in the y direction in FIG. 1) can be formed at a level of the resolution (β) of the stepper, for example, 0.35 μm. Therefore, the semiconductor device can be miniaturized.

Hereinafter, the miniaturization of the semiconductor device using the manufacturing method of the present embodiment will be described in more detail. In general, the dimensions (width in the y direction) of the sub-trench 251 and the convex portion 300 can take values of the following formulas (1) and (2), respectively.
Stepper resolution (β) ≦ size of sub-trench 251 (sw) ≦ 5 μm (1)
Stepper resolution (β) ≦ dimension of projection 300 (tw) ≦ 5 μm (2)

  Here, when the alignment accuracy (α) of the stepper is better than the resolution (β), that is, when the value of the alignment accuracy (α) is smaller than the value of the resolution (β), the sub-trench 251 and The minimum dimension of the convex part 300 can be set to the value of the resolution (β). However, even when the alignment accuracy (α) of the stepper is worse than the resolution (β), the minimum dimension of the sub-trench 251 can be set to the value of the resolution (β) of the stepper by using the following method. it can.

  Specifically, the relationship between the width (sw + tw) of the width (sw) of the sub-trench formation region 253 and the width (tw) of the convex formation region 302 and the alignment accuracy (α) is as follows. The width (tw) of the convex portion forming region 302 is adjusted so as to satisfy Equation (3). Then, the width (γ) of the opening on the convex portion forming region 302 in the resist pattern 510 is adjusted so as to satisfy the following formula (4).

Sub-trench formation region 253 width (sw) + convex formation region 302 width (tw)> stepper alignment accuracy (α) Equation (3)
2 × (width of sub-trench formation region 253 (sw)) + width of projection formation region 302 (tw) −stepper alignment accuracy (α)> width of opening on projection formation region 302 in resist pattern 510 ( γ) Expression (4)

  In this way, even if misalignment occurs, at least a part of the opening in the resist pattern 510 is positioned on the convex portion formation region 302. Therefore, the first mask 400 (402) on the convex portion formation region 302 can be surely removed by wet etching.

C. Third embodiment:
C1. Semiconductor device configuration:
Since the configuration of the semiconductor device in the third embodiment is the same as the configuration of the semiconductor device in the first embodiment, description thereof is omitted.

C2. Manufacturing method of semiconductor device:
FIG. 13 is a flowchart showing a method for manufacturing a semiconductor device according to the third embodiment. Also in the present embodiment, similarly to the above-described embodiment, first, the stacked body 11 is prepared (step S300). Next, as shown in FIG. 14, a third mask 420 (421, 422) having an opening on the recess formation region 222 and the gate trench formation region 252 is formed on the stacked body 11 (step S302). The dimension of the recess 220 and the dimension of the gate trench 250 are determined by the third mask 420. FIG. 14 is a diagram showing the semiconductor device 21 in the manufacturing process in which the third mask 420 is formed. Step S302 corresponds to step (a) of the present application.

Next, dry etching is performed on the semiconductor device 21 in the manufacturing process in which the third mask 420 is formed (step S304). FIG. 15 is a diagram illustrating the semiconductor device 22 in the manufacturing process in which dry etching is performed. In step S304, dry etching is performed on the recess formation region 222 and the gate trench formation region 252 from the opening of the third mask 420 using a chlorine-based gas (for example, a mixed gas of BCl ₃ and Cl ₂ ). As a result, the lower surface of the recess 220 and the lower surface of the gate trench 250 (the upper surface of the convex portion 300) reach the second semiconductor layer 130. Step S304 corresponds to step (b) of the present application.

  Next, as shown in FIG. 16, on the third mask 420, the recess 220 (the recess formation region 222) and the convex formation region 302 are covered, and an opening is formed on the sub-trench formation region 253. Four masks 430 (431, 432) are formed (step S310). FIG. 16 is a diagram illustrating the semiconductor device 23 in the manufacturing process in which the fourth mask 430 is formed. Step S310 corresponds to step (c) of the present application.

  Next, dry etching using a chlorine-based gas is performed on the semiconductor device 23 in the manufacturing process in which the fourth mask 430 is formed (step S316). FIG. 17 is a diagram showing the semiconductor device 24 in the manufacturing process in which dry etching has been performed. In step S316, dry etching is performed on the sub-trench formation region 253 from the opening of the fourth mask 430. In step S 316, dry etching is performed so that the lower surface of the sub-trench formation region 253 reaches the first semiconductor layer 120. Step S316 corresponds to step (d) of the present application.

  Next, the third mask 420 and the fourth mask 430 are removed from the semiconductor device 24 in the manufacturing process that has been subjected to dry etching (step S318). After that, after the insulating film 260 is formed on the upper surface of the semiconductor device, the insulating film 260 on the recess 220 and the region where the source electrode 240 is formed is removed, and an electrode (gate) is formed. Electrode 270, body electrode 230, source electrode 240, drain electrode 210) are formed (step S320). The semiconductor device of this embodiment is manufactured through the above steps.

C3. effect:
According to the method for manufacturing a semiconductor device of the present embodiment, the gate trench 250 including the convex portion 300 is formed in the GaN-based semiconductor layer. Further, the protrusion 300 having the second conductivity type semiconductor layer is a dry layer for forming the recess 220 and the gate trench 250 using the second conductivity type semiconductor layer 130 before the gate trench 250 is formed. It can be formed by etching. Therefore, the same effects as those of the first embodiment described above can be obtained.

  In addition, after the dry etching is performed using the third mask 420 in which the recess formation region 222 and the gate trench formation region 252 are opened, the recess 220 (the recess formation region 222) and the convex portion formation region 302 are covered. A fourth mask 430 is formed. Thereafter, dry etching is performed on the sub-trench formation region 253. Therefore, dry etching is performed on the stacked body 11 using the third mask 420 having openings in the recess 220 (recess formation region 222) and the gate trench formation region 252, and the dimensions of the recess 220 and the gate trench A dimension of 250 is determined. Further, the fourth mask 430 determines the dimension of the convex portion 300 and the dimension of the sub-trench 251. Therefore, even if dry etching is performed twice in total, changes in the dimensions of the sub-trench 251 and the convex portion 300 can be suppressed without considering the alignment accuracy for forming the mask pattern.

D. Variations:
D1. Modification 1:
In the various embodiments described above, the convex portion 300 of the semiconductor device 10 is surrounded by the sub-trench 251. On the other hand, the convex part 300 (floating part 301) may be connected to the second semiconductor layer 130 in a region not shown in FIG.

D2. Modification 2:
The material for forming each semiconductor layer in the various embodiments described above is merely an example, and other materials can be used. For example, in the above-described embodiment, each semiconductor layer is mainly composed of gallium nitride (GaN). On the other hand, each semiconductor layer may be made of another material such as silicon carbide (SiC) or silicon (Si).

D3. Modification 3:
The semiconductor devices in the various embodiments described above are not limited to power devices, and may be used for other devices such as high-frequency devices for communication such as a microwave band, and high-speed devices for logic ICs.

D4. Modification 4:
In the various embodiments described above, the insulating film 260 is formed of silicon oxide (SiO ₂ ). On the other hand, the insulating film 260 may be formed of other materials such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN), hafnium oxide (HfO ₂ ), and zirconium oxide (ZrO ₂ ). The insulating film 260 may have a multilayer structure. For example, a ZrO ₂ / SiO ₂ structure in which ZrO ₂ is provided on SiO _2, a two-layer structure such as a HfO ₂ / SiO ₂ structure, an Al ₂ O ₃ / SiO ₂ structure, a SiO ₂ / SiN structure, A three-layer structure such as a ZrO ₂ / SiO ₂ / SiN structure in which SiO ₂ is provided thereon and further ZrO ₂ is provided thereon, and a HfO ₂ / Al ₂ O ₃ / SiO ₂ structure may be employed.

D5. Modification 5:
In the various embodiments described above, the gate electrode 270 is formed of aluminum (Al). On the other hand, the gate electrode 270 is at least one of conductive materials such as platinum (Pt), cobalt (Co), nickel (Ni), gold (Au), titanium (Ti), palladium (Pd), and polysilicon. The electrode containing may be sufficient. Further, the gate electrode 270 may be composed of a plurality of layers. For example, the gate electrode 270 may have a two-layer configuration such as an Au / Ni configuration, an Al / Ti configuration, or an Al / TiN configuration (Ni, Ti, and TiN are on the insulating film side, respectively). A three-layer structure such as an Al / TiN structure may be used.

D6. Modification 6:
In the various embodiments described above, the body electrode 230 is formed by laminating a layer made of nickel (Ni) and a layer made of gold (Au). On the other hand, the body electrode 230 may be an electrode including at least one of conductive materials such as platinum (Pt), cobalt (Co), and palladium (Pd).

D7. Modification 7:
In the various embodiments described above, the source electrode 240 is formed by laminating a layer made of aluminum (Al) and a layer made of titanium (Ti). On the other hand, the source electrode 240 may be an electrode made of at least one conductive material such as vanadium (V) or hafnium (Hf) instead of Ti.

D8. Modification 8:
In the various embodiments described above, the drain electrode 210 is formed by laminating a layer made of titanium (Ti) and a layer made of aluminum (Al). On the other hand, the drain electrode 210 may be an electrode made of at least one of conductive materials such as vanadium (V) and hafnium (Hf) instead of Ti.

D9. Modification 9:
In the various embodiments described above, the “first conductivity type” of the semiconductor device 10 is the N type, and the “second conductivity type” is the P type. On the other hand, the “first conductivity type” of the semiconductor device 10 may be P-type, and the “second conductivity type” may be N-type.

  The present invention is not limited to the above-described embodiments and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments and the modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 11 ... Laminated body 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ... Semiconductor device in manufacturing process 110 ... Substrate 120 ... First semiconductor layer 130 ... Second semiconductor layer 140 ... third semiconductor layer 210 ... drain electrode 220 ... recess 222 ... recess formation region 230 ... body electrode 240 ... source electrode 250 ... gate trench 251 ... sub-trench 252 ... gate trench formation region 253 ... sub-trench formation region 260 ... Insulating film 270 ... Gate electrode 300 ... Convex part 301 ... Floating part 302 ... Convex part forming region 400 (401, 402) ... First mask 410 (411, 412) ... Second mask 420 (421, 422) ... third mask 430 (431, 432) ... fourth mask 500 (501) , 502), 510, 520 (521, 522) ... resist pattern

Claims (6)

A method for manufacturing a semiconductor device, comprising:
The semiconductor device includes:
A first semiconductor layer that is a first conductivity type semiconductor, a second semiconductor layer that is a second conductivity type semiconductor in contact with the upper surface of the first semiconductor layer, and a first conductivity type in contact with the upper surface of the second semiconductor layer A stacked body in which the third semiconductor layer which is the semiconductor of the first semiconductor layer is stacked in order from the first semiconductor layer side;
A sub-trench extending from the upper surface of the third semiconductor layer to the first semiconductor layer through the second semiconductor layer, and a convex portion surrounded by the sub-trench, wherein the second surface is formed on the upper surface of the convex portion . A gate trench provided with a protruding portion from which the semiconductor layer is exposed;
A recess reaching from the upper surface of the third semiconductor layer to the second semiconductor layer,
(A) The laminated body covers a recess forming region where the recess is formed and a convex forming region where the convex is formed, and a first sub trench forming region where the sub trench is formed is opened. Forming a mask of
(B) After the step (A), a step of performing dry etching;
(C) After the step (B), a step of forming a second mask by removing portions corresponding to the recess formation region and the convex portion formation region of the first mask;
(D) a step of performing dry etching after the step (C),
In at least one step of the step (B) or the step (D), dry etching is performed so that the lower surface of the sub-trench reaches the first semiconductor layer,
In the step (D), dry etching is performed so that the lower surface of the recess and the upper surface of the convex portion reach the second semiconductor layer.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
In the step (C),
(C1) forming a resist pattern having an opening in a portion corresponding to the recess formation region and the convex portion formation region on the first mask;
(C2) A step of removing a portion of the first mask corresponding to the recess formation region and the projection formation region by performing dry etching after the step (C1). Device manufacturing method. A method of manufacturing a semiconductor device according to claim 1,
In the step (C),
(C1) forming a resist pattern having an opening in at least a part of a portion corresponding to the convex portion forming region of the first mask on the first mask;
(C2) removing the portion of the first mask corresponding to the protrusion forming region by performing wet etching after the step (C1);
(C3) removing the portion of the first mask corresponding to the recess formation region by performing dry etching;
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device, comprising:
The semiconductor device includes:
A first semiconductor layer that is a first conductivity type semiconductor, a second semiconductor layer that is a second conductivity type semiconductor in contact with the upper surface of the first semiconductor layer, and a first conductivity type in contact with the upper surface of the second semiconductor layer A stacked body in which the third semiconductor layer which is the semiconductor of the first semiconductor layer is stacked in order from the first semiconductor layer side;
A sub-trench extending from the upper surface of the third semiconductor layer to the first semiconductor layer through the second semiconductor layer, and a convex portion surrounded by the sub-trench, wherein the second surface is formed on the upper surface of the convex portion . A gate trench provided with a protruding portion from which the semiconductor layer is exposed;
A recess reaching from the upper surface of the third semiconductor layer to the second semiconductor layer,
(A) forming, in the stacked body, a third mask having a recess forming region in which the recess is formed and a gate trench forming region in which the gate trench is formed;
(B) a step of performing dry etching after the step (a);
(C) After the step (b), a step of forming a convex portion forming region where the convex portion is formed and a fourth mask covering the recess forming region on the third mask;
(D) a step of performing dry etching after the step (c),
In the step (b), dry etching is performed so that the lower surface of the recess and the upper surface of the convex portion reach the second semiconductor layer,
In the step (d), dry etching is performed so that the lower surface of the sub-trench reaches the first semiconductor layer.
A method for manufacturing a semiconductor device. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 4,
A method of manufacturing a semiconductor device, wherein a gallium nitride (GaN) based semiconductor layer is used as the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. A method of manufacturing a semiconductor device according to any one of claims 1 to 5 ,
Dry etching is performed on the second mask in the step (D), or dry etching is performed on the third mask in the step (b), and the fourth etching is performed in the step (d). by dry etching from the mask, the upper surface of the lower surface and the convex portion of the recess, causing on the same plane, a method of manufacturing a semiconductor device.

Images