JP6165076B2 - Application specific integrated circuits - Google Patents

Description

  The present invention relates to an application specific integrated circuit.

  When high functions and high speeds are required for signal processing or the like, a processing circuit is designed by an application specific integrated circuit (ASIC: ASIC) designed specifically for a specific application. There are many cases.

  For example, by introducing a reconfigurable system as described in Patent Document 1, it is possible to change the processing circuit in response to a specification change at the design stage of the electronic device. In view of the above, ASIC is preferable.

JP 2011-90671 A

  Since ASIC design usually takes several years, the external environment (peripheral circuits, etc.) of the ASIC has been changed due to changes in specifications at the design stage of electronic devices. What is the external environment that was assumed at the beginning of ASIC design? The ASIC may operate in a different external environment.

  As described above, a problem may easily occur in a specific part of the ASIC due to a change in the external environment from the time of design.

  The present invention has been made in view of the above problems, and an object of the present invention is to obtain an application specific integrated circuit capable of continuing operation even if a malfunction occurs.

An application specific integrated circuit according to the present invention performs a predetermined process on an input signal and outputs a result of the process as an output signal, and whether or not the levels of a plurality of monitoring parts are abnormal. A plurality of abnormality detection units that output a plurality of detection signals respectively, and a logical operation is performed on the plurality of detection signals output from the plurality of abnormality detection units, and a result of the logical operation is obtained from the processing circuit. An interruption determination unit that outputs a control signal indicating whether or not to interrupt the output signal; and an interruption unit that interrupts the output signal of the processing circuit based on the control signal output by the interruption determination unit. Prepare. The level of the monitoring site is fixedly at a high level or a low level when normal, and fluctuates when abnormal. The abnormality detection unit includes (a) a plurality of cascade-connected delay units, (b) the level of the monitoring part is input to the first stage of the plurality of delay units, and (c) is fixed when normal. When the level of the monitoring part that is at a high level is input, the logical product of the output signals of the plurality of delay units is output as the detection signal, and the monitoring part that is fixedly at a low level during normal operation Is input, the logical sum of the output signals of the plurality of delay units is output as the detection signal. Further, in the plurality of abnormality detection units, a first abnormality detection circuit to which a level of the monitoring part that is fixedly at a high level when normal is input, and a level of the monitoring part that is fixed to a low level when normal are provided. When the input second abnormality detection circuit coexists, the shutoff determination unit inverts the level of the detection signal of one of the first abnormality detection circuit and the second abnormality detection circuit as the logical operation. Thereafter, a logical sum of the plurality of detection signals or a logical product of the plurality of detection signals is performed.

  According to the present invention, it is possible to obtain an application specific integrated circuit capable of continuing operation even if a problem occurs.

FIG. 1 is a block diagram showing a configuration of an application specific integrated circuit (ASIC) according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram illustrating an example of the abnormality detection circuit 11 in FIG. 1 when the level of the monitored region is fixedly high when normal. FIG. 3 is a circuit diagram showing an example of the abnormality detection circuit 11 in FIG. 1 when the level of the monitored region is fixedly at a low level when normal. FIG. 4 is a block diagram showing a configuration of an application specific integrated circuit (ASIC) according to Embodiment 2 of the present invention. FIG. 5 is a block diagram showing a configuration of an application specific integrated circuit (ASIC) according to the third embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

  FIG. 1 is a block diagram showing a configuration of an application specific integrated circuit (ASIC) according to Embodiment 1 of the present invention.

  The ASIC shown in FIG. 1 includes a processing circuit 1, an alternative circuit 2, a demultiplexer 3, a multiplexer 4, a plurality of abnormality detection circuits 11, and a determination circuit 12.

  The processing circuit 1 performs predetermined processing on the input signal and outputs the result of the processing as an output signal.

  The alternative circuit 2 is an alternative circuit for the processing circuit 1.

  The processing circuit 1 is, for example, one of a series of processing circuits in the ASIC according to the first embodiment. Therefore, when an abnormal state is detected, the processing circuit 1 is disconnected from the series of processing circuits, and the ASIC operation is continued in the remaining processing circuits and the alternative circuit 2.

  The demultiplexer 3 switches the input destination of the input signal to the processing circuit 1 to the alternative circuit 2 based on the control signal output from the determination circuit 12. The multiplexer 4 selects and outputs the output signal of the alternative circuit 2 instead of the output signal of the processing circuit 1 based on the control signal output from the determination circuit 12.

  In the first embodiment, the demultiplexer 3 and the multiplexer 4 constitute blocking means for blocking the output signal of the processing circuit 1 based on the control signal output from the determination circuit 12.

  The plurality of abnormality detection circuits 11 each output a plurality of detection signals indicating whether or not the levels of the plurality of monitoring parts are abnormal.

  The level of each monitoring part is fixedly at a high level or a low level when normal, and fluctuates because the monitoring part is in a high impedance state when abnormal.

  That is, a portion that is fixedly at a high level or a low level when normal and that is in a high impedance state when abnormal is selected as a monitoring portion in the ASIC according to the first embodiment.

  FIG. 2 is a circuit diagram illustrating an example of the abnormality detection circuit 11 in FIG. 1 when the level of the monitored region is fixedly high when normal. FIG. 3 is a circuit diagram showing an example of the abnormality detection circuit 11 in FIG. 1 when the level of the monitored region is fixedly at a low level when normal.

  As shown in FIGS. 2 and 3, the abnormality detection circuit 11 includes (a) a plurality of delay circuits 21 and 31 connected in cascade, and (b) a monitoring portion at the first stage of the plurality of delay circuits 21 and 31. When a level is input and (c) the level of a monitoring part that is fixedly high when normal is input, the logical product of the output signals of the plurality of delay circuits 21 is calculated by the AND circuit 22 and detected. Output as a signal, and when the level of a monitoring part that is fixedly at a low level in normal operation is input, the OR of the output signals of the plurality of delay circuits 31 is calculated by the OR circuit 32 and output as a detection signal To do.

  One delay circuit 21, 31 holds the level of the input signal for a predetermined period (here, one clock). For example, flip-flops are used as the delay circuits 21 and 31. In the abnormality detection circuit 11 shown in FIGS. 2 and 3, the number of stages of the delay circuits 21 and 31 is 3, but it may be 2 or 4 or more.

  The abnormality detection circuit 11 receives a high level (fixed value, for example, a power supply potential) for a predetermined period when the power is turned on by the multiplexer 23 when a level of a monitoring part that is fixedly at a high level is input in a normal state. After the predetermined period ends, the output signal of the AND circuit 22 is selected to fix the detection signal at a high level during the predetermined period when the power is turned on.

  Further, the abnormality detection circuit 11 receives a low level (fixed value, for example, grounding) for a predetermined period when the power is turned on by the multiplexer 33 when a monitoring part level that is fixedly at a low level in normal operation is input. After the predetermined period, the output signal of the OR circuit 32 is selected to fix the detection signal at a low level during the predetermined period when the power is turned on.

  The determination circuit 12 performs a logical operation on a plurality of detection signals output from the plurality of abnormality detection circuits 11, and a control signal indicating whether or not the output signal of the processing circuit 1 is cut off based on the result of the logical operation. Output as. This logical operation is a logical sum of a plurality of detection signals, a logical product of a plurality of detection signals, or the like.

  This logical operation is determined based on conditions for a plurality of detection signals for switching from the processing circuit 1 to the alternative circuit 2.

  Also, an abnormality detection circuit 11 to which a level of a monitoring part that is fixedly at a high level is input in a normal state and an abnormality detection circuit 11 to which a level of a monitoring part that is fixed to a low level in a normal state are input. In this case, after inverting the level of one of the detection signals, a logical operation such as a logical sum of a plurality of detection signals or a logical product of the plurality of detection signals may be performed.

  Next, the operation of the ASIC according to the first embodiment will be described.

  In the ASIC according to the first embodiment, the plurality of abnormality detection circuits 11 monitor the levels of the plurality of monitoring parts.

  Each abnormality detection circuit 11 holds the level after the fluctuation for a period corresponding to the number of stages of the delay circuits 21 and 31 and outputs it as a detection signal when the monitoring part level fluctuates.

  Then, the determination circuit 12 performs a predetermined logical operation on the detection signals from the plurality of abnormality detection circuits 11, and outputs the result of the logical operation to the demultiplexer 3 and the multiplexer 4 as a control signal.

  Then, the demultiplexer 3 and the multiplexer 4 switch the circuit used for processing from the processing circuit 1 to the alternative circuit 2 in accordance with the control signal.

  As described above, according to the first embodiment, the plurality of abnormality detection circuits 11 each output a plurality of detection signals indicating whether or not the levels of the plurality of monitoring parts are abnormal. The determination circuit 12 performs a logical operation on a plurality of detection signals output from the plurality of abnormality detection circuits 11, and uses the result of the logical operation as a control signal indicating whether or not to cut off the output signal of the processing circuit 1. Output. The demultiplexer 3 and the multiplexer 4 block the output signal of the processing circuit 1 based on the control signal output from the determination circuit 12. The level of the monitoring site is fixedly at a high level or a low level when normal, and fluctuates when abnormal. The abnormality detection circuit 11 includes (a) a plurality of delay circuits 21 and 31 connected in cascade, (b) the level of the monitoring part is input to the first stage of the plurality of delay circuits 21 and 31, and (c) When the level of a monitoring part that is fixedly at a high level during normal operation is input, the logical product of the output signals of the plurality of delay circuits 21 is output as a detection signal, and monitoring that is fixed at a low level during normal operation. When the level of the part is input, the logical sum of the output signals of the plurality of delay circuits 31 is output as a detection signal.

  Thereby, even if a malfunction occurs in the ASIC, the processing circuit 1 is disconnected from the series of processing circuits in the ASIC, and the operation of the ASIC can be continued.

Embodiment 2. FIG.

  FIG. 4 is a block diagram showing a configuration of an application specific integrated circuit (ASIC) according to Embodiment 2 of the present invention.

  In the second embodiment, the demultiplexer 3 and the multiplexer 4 are not used, the clock generator 41 outputs a clock signal, and the demultiplexer 42 generates a clock based on the control signal output by the determination circuit 12. The signal input destination is switched from the processing circuit 1 to the alternative circuit 2. As a result, since only the processing circuit 1 and the alternative circuit 2 to which the clock signal is supplied operate, the switching from the processing circuit 1 to the alternative circuit 2 is performed by the control signal from the determination circuit 12. 1 is performed.

  Note that other configurations and operations of the ASIC according to the second embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

Embodiment 3 FIG.

  FIG. 5 is a block diagram showing a configuration of an application specific integrated circuit (ASIC) according to the third embodiment of the present invention.

  The ASIC according to Embodiment 3 does not use the demultiplexer 3 and the alternative circuit 2 but simply bypasses the processing circuit 1 based on the control signal from the determination circuit 12.

  That is, the multiplexer 4 selects and outputs one of the output signal of the processing circuit 1 and the input signal to the processing circuit 1 based on the control signal output from the determination circuit 12.

  Since the other configuration and operation of the ASIC according to the third embodiment are the same as those of the first embodiment, the description thereof is omitted.

  Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

  For example, in the first to third embodiments, the abnormality detection circuit 11 and the determination circuit 12 are replaced with a CPU (Central Processing Unit) or a microprocessor, and the same as the abnormality detection circuit 11 and the determination circuit 12 by software processing by the CPU or the microprocessor. You may make it perform the process of.

  The present invention is applicable to, for example, an ASIC incorporated in an electronic device.

DESCRIPTION OF SYMBOLS 1 Processing circuit 2 Alternative circuit 3,42 Demultiplexer (an example of a switching part, an example of interruption | blocking means)
4 Multiplexer (example of selection unit, example of blocking means)
11 Abnormality detection circuit (an example of abnormality detection unit)
12 determination circuit 21, 31 delay circuit (an example of a delay unit)
41 Clock generator

Claims (5)

A processing circuit that performs predetermined processing on the input signal and outputs the result of the processing as an output signal;
A plurality of anomaly detectors each outputting a plurality of detection signals indicating whether or not the levels of the plurality of monitoring sites are abnormal;
A logical operation is performed on the plurality of detection signals output from the plurality of abnormality detection units, and the result of the logical operation is output as a control signal indicating whether or not to cut off the output signal of the processing circuit. A blocking judgment unit;
Based on the control signal output by the shut-off determination unit, shut-off means for shutting off the output signal of the processing circuit,
With
The level of the monitoring site is fixed to a high level or a low level when normal, and fluctuates when abnormal,
The abnormality detection unit includes (a) a plurality of cascade-connected delay units, (b) the level of the monitoring part is input to the first stage of the plurality of delay units, and (c) is fixedly high during normal operation. When the level of the monitoring part that becomes a level is input, the logical product of the output signals of the plurality of delay units is output as the detection signal, and the level of the monitoring part that is fixedly at a low level when normal Is output as the detection signal, the logical sum of the output signals of the plurality of delay units ,
In the plurality of abnormality detection units, a first abnormality detection circuit to which a level of the monitoring part that is fixedly at a high level when normal is input, and a level of the monitoring part that is fixed to a low level at a normal time are input. When the second abnormality detection circuit coexists, the shutoff determination unit reverses the level of the detection signal of one of the first abnormality detection circuit and the second abnormality detection circuit as the logical operation. Performing a logical sum of the plurality of detection signals or a logical product of the plurality of detection signals;
Application specific integrated circuit characterized by   The abnormality detection unit (d) fixes the detection signal at a high level during a predetermined period when the power is turned on when a level of the monitoring portion that is fixedly at a high level is input when normal. 2. The application-specific integration according to claim 1, wherein when the level of the monitoring part that is fixedly at a low level is input, the detection signal is fixed at a low level during a predetermined period when the power is turned on. circuit. Further comprising an alternative circuit to the processing circuit;
The shut-off means switches the input destination of the input signal to the processing circuit to the alternative circuit based on the control signal output from the shut-off determining unit, and the control output from the shut-off determining unit A selection unit that selects and outputs the output signal of the alternative circuit instead of the output signal of the processing circuit based on a signal;
The application specific integrated circuit of claim 1. An alternative circuit for the processing circuit, and a clock generator that outputs a clock signal,
The blocking means includes a switching unit that switches the input destination of the clock signal from the processing circuit to the alternative circuit based on the control signal output by the blocking determination unit;
The application specific integrated circuit of claim 1.   The blocking means includes a selection unit that selects and outputs one of the output signal of the processing circuit and the input signal of the processing circuit based on the control signal output by the blocking determination unit. An application specific integrated circuit according to claim 1.

Images