JP2011222789A - Input protection circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the prevention of device malfunction and device fault resulting from signals input to input terminals, without providing analog current detection circuits for every input terminal.SOLUTION: An input protection circuit 2 comprises a switching circuit 21 provided between an input circuit 11 and a current source 12, a level change detection circuit 22 to detect logical-level changes in an input signal within a predetermined time period, a level change determination circuit 23 to count the number of times of changes in the logical-level detected by the level change detection circuit 22 and to determine whether or not the count value has exceeded a predetermined threshold, and an abnormality determination circuit 24 to determine whether or not the number of times the level change determination circuit 23 determined that the count value has exceeded the predetermined threshold within a predetermined time period longer than the above predetermined time period has exceeded a predetermined number of times and to set the switching circuit 21 to a cut-off state if it is determined that the predetermined number of times has been exceeded.

Description

  The present invention relates to an input protection circuit that is incorporated in an integrated circuit and performs processing for detecting an abnormality of an input signal and preventing an overcurrent from flowing through the input circuit, and a semiconductor integrated circuit incorporating the input protection circuit.

  If the potential of the input signal of a semiconductor integrated circuit (hereinafter referred to as a device), which is a digital circuit, becomes unstable or if noise that causes a change in data in a very short period is added to the input signal, it is connected to the input terminal. There is a possibility that a CMOS circuit as an input circuit performs a high-speed switching operation and an excessive current flows, thereby causing a malfunction in the device or a failure of the device (for example, see Patent Document 1). In order to eliminate such a possibility, a device incorporating an overcurrent detection circuit using an analog circuit may be used.

JP-A-6-61834

  However, when an overcurrent detection circuit using an analog circuit is employed, it is required to provide an analog circuit for all input terminals. That is, it is required to provide an analog circuit in the vicinity of each input buffer, and there is a problem that device design becomes difficult.

  Therefore, the present invention provides an input protection circuit capable of preventing device malfunction and device failure based on a signal input to the input terminal without providing an analog current detection circuit for all input terminals, and An object is to provide a semiconductor integrated circuit incorporating an input protection circuit.

  An input protection circuit according to the present invention includes a switch circuit provided between an input circuit to which an input signal that is a digital signal is input and a current supply source that supplies current to the input circuit, and a predetermined time in the input signal. Level change detection circuit that detects a change in the logic level of the signal, and a level change determination circuit that counts the number of changes in the logic level detected by the level change detection circuit and determines whether or not the count value exceeds a predetermined threshold value And the level change determination circuit determines whether or not the number of times the count value has determined to exceed a predetermined threshold in a predetermined period longer than the predetermined time exceeds the predetermined number. And an abnormality determination circuit that sets the switch circuit to a cut-off state when it is determined that the switch circuit is in a disconnected state.

  A semiconductor integrated circuit according to the present invention includes an input circuit to which an input signal that is a digital signal is input, a current supply source that supplies current to the input circuit, and an input that performs processing to prevent an overcurrent from flowing through the input circuit. A semiconductor integrated circuit including a protection circuit, wherein the input protection circuit detects a change in a logic level within a predetermined time in a switch circuit provided between the input circuit and a current supply source and an input signal The level change detection circuit, the level change determination circuit that counts the number of logical level changes detected by the level change detection circuit, and determines whether or not the count value exceeds a predetermined threshold value, and the level change determination circuit are described above. It is determined whether or not the number of times the count value is determined to exceed the predetermined threshold in a predetermined period longer than the predetermined time exceeds the predetermined number. Characterized in that it comprises an abnormality judging circuit for setting the switch circuit in the blocked state when the.

  According to the present invention, it is possible to prevent device malfunction and device failure based on a signal input to the input terminal without providing an analog current detection circuit.

It is a block diagram which shows the device by which an input protection circuit is mounted with an opposing device and a personal computer. It is a block diagram which shows the structural example of an indefinite detection circuit part. It is a timing diagram for demonstrating operation | movement of an input protection circuit. It is a flowchart which shows operation | movement of an input protection circuit. It is a block diagram which shows the principal part of the semiconductor integrated circuit which incorporates an input protection circuit. It is a block diagram which shows the principal part of the semiconductor integrated circuit incorporating the input protection circuit of another aspect.

  FIG. 1 is a block diagram showing a device 10 equipped with an input protection circuit according to the present invention together with a counter device 20 and a personal computer 30. In the example illustrated in FIG. 1, the device 10 inputs a signal from the opposite device 20. The personal computer 30 verifies the operation of the device via a JTAG (Joint European Test Action Group) port.

As illustrated in FIG. 1, in the device 10, signals 100 _{1 to} 100 _N output from the opposite device 20 to the device 10 are input to input circuits 200 ₁ to 200 _N. N is an arbitrary natural number. Input signals are transmitted from the input circuits 200 ₁ to 200 _N to the internal circuit of the device 10 through the wirings 300 _{1 to} 300 _N. In addition, each of the wirings 300 _{1 to} 300 _N is also connected to a corresponding indefinite detection circuit unit 400 _{1 to} 400 _N.

When the indefinite detection circuit units 400 _{1 to} 400 _N detect the logical inversion of the signals in the corresponding wirings 300 _{1 to} 300 _N , the indefinite detection circuit units 400 _{1 to} 400 _N output signals indicating that to the corresponding decoder units 500 _{1 to} 500 _N. The decoder units 500 _{1 to} 500 _N have a predetermined number of signals indicating that the logic inversion output from the indefinite detection circuit units 400 _{1 to} 400 _N has been detected, that is, the count value of the number of logic inversions. Compare with threshold. Then, the count value when exceeding the threshold value, relative to a corresponding decoder unit ₅₀₀ 1 to 500 _N in the connected protection stage unit ₆₀₀ 1 to 600 _N, and outputs one pulse signal.

Protection stage unit ₆₀₀ 1 to 600 _N, depending wirings 700 ₁ to the wiring 700 _N, is connected to the switch ₈₀₀ 1 to 800 _N of the current source connected to the input circuit ₂₀₀ 1 to 200 DEG _N. The decoder units 500 _{1 to} 500 _N and the protection stage number units 600 ₁ to 600 _N are also connected to the register unit 900 for JTAG monitoring.

The protection stage number units 600 ₁ to 600 _N count the number of pulse signals input from the corresponding decoder units 500 _{1 to} 500 _N over a predetermined period. When the count value is equal to or greater than a predetermined value, the corresponding current supply source switches 800 _{1 to} 800 _N are turned off.

The indefinite detection circuit units 400 _{1 to} 400 _N , the decoder units 500 _{1 to} 500 _N, and the protection stage number units 600 ₁ to 600 _N constitute an input signal abnormality detection circuit. The input protection circuit includes an input signal abnormality detection circuit and switches 800 _{1 to} 800 _N. FIG. 1 shows a configuration in which the input protection circuit also includes a JTAG monitor register unit 900.

Further, in this embodiment, the indeterminate detecting circuit unit ₄₀₀ 1 to 400 _N, but the input signal is input from the output side of the input circuit ₂₀₀ 1 to 200 DEG _N, indeterminate detected from the input side of the input circuit ₂₀₀ 1 to 200 DEG _N An input signal may be input to the circuit units 400 _{1 to} 400 _N.

Figure 2 is a block diagram showing a configuration example of the indefinite detecting circuit unit 400 _N. Each of the indefinite detection circuit units 400 _{1 to} 400 _(N−1) is also configured as shown in FIG.

As shown in FIG. 2, the indefinite detecting circuit unit 400 _N, wiring 300 _N is connected to the asynchronous latch circuit _{401 N ~40M} N. EN signal _{411 N ~41M} N output from the asynchronous latch circuits _{401 N ~40M} N is input to a decoder unit 500 _N. Note that M is an arbitrary natural number.

Next, the principle of operation of the input protection circuit will be described with reference to the timing chart of FIG.
(If the state nor no low level at a high level) signal outputted from the counter device may become unstable, as shown in FIG. 3 (A), the logic is speed switching in the input circuit 200 _N, fast logic inversion occurs in the signal at the line 300 _N. Asynchronous latch circuit ₄₀₁ N _~40M in indeterminate detecting circuit unit 400 _{N N} detects the logic inversion of the signal in line 300 _N. Incidentally, fast logic inversion occurring in the signal at the line 300 _N may also be due to noise.

For example, the enable terminal EN of the asynchronous latch circuit _{401 N ~40M} N is to become asserted at a low level. The initial value of each EN signal _{411 N ~41M} N which is the output of the asynchronous latch circuit _{401 N ~40M} N is assumed to be high level. The wiring 300 _N is connected to the data terminal Da of the asynchronous latch circuits _{401 N ~40M} N.

The asynchronous latch circuit 401 _N is a circuit for setting the EN signal 411 _N , which is an output, to a low level when the signal in the wiring 300 _N is at a low level (see FIG. 3B). The EN signal 411 _N is also input to the decoder unit 500 _N.

The asynchronous latch circuit 402 _{N in the} next stage is a circuit that sets the EN signal 412 _N that is an output to a low level when the logic level of the data terminal Da becomes a high level when the EN signal 411 _N is in a low level state. Yes (see FIG. 3C). The EN signal 412 _N is also input to the decoder unit 500 _N.

The next-stage asynchronous latch circuit 403 _N is a circuit for setting the EN signal 413 _N as an output to a low level when the logic level of the data terminal Da becomes a low level when the EN signal 412 _N is in a low level state. Yes (see FIG. 3D). The EN signal 413 _N is also input to the decoder unit 500 _N.

Similarly, the asynchronous latch circuits of even-numbered stages in the asynchronous latch circuit 404 _N ~40M _N stages later than the asynchronous latch circuit 403 _N, in the case EN signal input is a low level, the data terminals Da When the logic level becomes high, the EN signal is made low. Further, the odd-numbered asynchronous latch circuit sets the EN signal to the low level when the logic level of the data terminal Da becomes the low level when the input EN signal is in the low level state. EN signal output from each asynchronous latch circuits is input to the enable terminal EN of the next stage of the asynchronous latch circuit is inputted to the decoder unit 500 _N.

In this embodiment, the asynchronous latch circuits 401 _{N to} 40M _N set the output to the low level when the initial level of the output is high and the logical inversion generated in the wiring 300 _N is detected. level a low level, a logic inversion occurring in the wiring 300 _N may be configured such that the high level output is detected.

Further, as shown in FIG. 3, the asynchronous latch circuits 401 _{N to} 40M _N are reset when the operation clock signal 420 _N becomes high level, and the latch is released.

For example, when the frequency of the operation clock signal 420 _N is 10 MHz and the operation speed of the indefinite detection circuit unit 400 _N is a speed corresponding to 2 ns (for example, the operation clock signal 420 _N operates in synchronization with the clock signal of 2 ns). undefined detecting circuit unit 400 _N, in the operation clock signal 420 _N 50 ns is asserted period in one cycle of the (half period of one cycle), the logical inversion of the signal in line 300 _N can be detected up to 25 times.

The decoder unit 500 _N receives the EN signals 411 _{N to} 41M _N and counts the number of input signals that are at a low level within a half cycle of the operation clock signal 420 _N. Count the number of times and decode the count value. When the count value exceeds a predetermined value, in order to notify, to output one pulse signal to the protection stage unit 600 _N. Protection stage unit 600 _N is within a predetermined time period, when the number of pulses exceeding the protection stages has been detected, the high impedance input circuit 200 _N by blocking the switch 800 _N current sources in the input circuit 200 _N the state, so that excessive current does not flow in the input circuit 200 _N.

A decoder unit 500 _N and the protection stage unit 600 _N is connected to the JTAG monitor register unit 900 capable state is monitored by the personal computer 30 via the JTAG port. The count value of the counted logically inverted by the decoder unit 500 _N, and the switching state of the switch 800 _N which protection stage unit 600 _N to control is set to JTAG monitor register 900. Therefore, the personal computer 30 can monitor the count value and the switching state via the JTAG monitor register 900. The monitor is mainly used in the evaluation of the device 10. The switching state is set to JTAG monitor register 900 corresponds to the determination process in the determination result of the protection stage unit 600 _N.

Switching state of the switch 800 _N, the state of the signal input to the input circuit 200 _N are used to determine whether normal or not. That is, if the switching state is off, it is determined that the alarm state (ALM state) is present, and if the switching state is on, it is determined that the state is normal. The count value of the logic inversion is counted by the decoder unit 500 _N will be used to verify the behavior of the input signal in the interior of the device 10.

Next, the operation of the input protection circuit will be described with reference to the flowchart of FIG. Hereinafter will be described the operation of the indefinite detecting circuit unit 400 _N, indeterminate detecting circuit unit _{400 1 ~400 (N-1)} also operates in the same manner as indeterminate detecting circuit unit 400 _N.

Signal 100 _N outputted from the counter device 20 is input to the input circuit 200 _N.

In indeterminate detecting circuit unit 400 _N, asynchronous latch circuit _{401 N ~40M} N in a period half period of the operation clock signal 420 _N, sequentially detects the logic inversion of the signal in line 300 _N (Step S1: see Figure 3 ).

When the period of the half cycle of the operation clock signal 420 _N has passed, the decoder unit 500 _N counts the number of each EN signal ₄₁₁ N _~41M low level since it is the signal of the _N. For example, in the sequence of the EN signal _{411 N ~41M} N, a high level capturing a low level of "1" regarded as "0", and counts the number of "1". Then, it is determined whether or not the count value that is the result of counting exceeds a predetermined threshold value (step S2). When the count value exceeds a predetermined threshold, the decoder unit 500 _N outputs a pulse signal to the protection stage unit 600 _N.

If the count value is equal to or smaller than the predetermined threshold value, the decoder unit 500 _N is the JTAG monitor register 900, sets the state of the value of the logical inversion (status), and the worst value of the count value (e.g. , The maximum value) is left in the JTAG monitor register 900 (step S3). For example, when the count value at this time is larger than the count value already set in the JTAG monitor register 900, the count value set in the JTAG monitor register 900 is updated with the count value at this time. To do. Then, the process proceeds to step S7.

Also, if even the count value exceeds a predetermined threshold value, the decoder unit 500 _N is the JTAG monitor register 900, sets the state of the value of the logical inversion (status), and the worst count The value is left in the JTAG monitor register 900 (step S4). The protection stage unit 600 _N, in response to the pulse signal from the decoder unit 500 _N is output, increasing a value of 1 protection stage counter (step S5).

  If the predetermined period has not elapsed since the process of step S1 was started for the first time, the process after step S1 is executed again (step S6).

If the predetermined period has elapsed, protection stage unit 600 _N determines whether greater than the protective step number values of protection stages counter is predetermined (step S7). If the value of the protection stage counter is less protection stages is protection stage unit 600 _N maintains the switch 800 _N current sources in the input circuit 200 _N in a conductive state (step S8). Note that the protection stage number counter can be reset at any time, for example, when a predetermined period has elapsed.

If the value of the protection stage counter is greater than the protective step number, protection stage unit 600 _N will switch 800 _N current sources in the input circuit 200 _N to the cutoff state. Also, the ATAG state is set in the JTAG monitor register 900 (step S9).

  As described above, in this embodiment, it is possible to prevent an overcurrent from flowing to the device due to an indefinite input signal without an analog current detection circuit. That is, it is not necessary to mount an overcurrent detection analog circuit on all input terminals, and the design is simplified. Further, overcurrent detection can be performed individually for input terminals that require detection by the user.

  In addition, it is possible to monitor using the personal computer 30 whether the input terminal is not indefinitely connected or whether the behavior of the input signal is abnormal, and the problem occurring in the device 10 can be solved early. be able to.

FIG. 5 is a block diagram showing the main part of a semiconductor integrated circuit incorporating an input protection circuit. As shown in FIG. 5, the semiconductor integrated circuit ₁ </ b> A supplies a current to the input circuit 11 (corresponding to the input circuits 200 ₁ to 200 _N shown in FIG. 1) to which an input signal that is a digital signal is input. Current supply source 1 and an input protection circuit 2 that performs processing to prevent an overcurrent from flowing through the input circuit 11. The input protection circuit 2 is provided between the input circuit 11 and the current supply source 12. Switch circuit 21 (corresponding to the switches 800 _{1 to} 800 _N shown in FIG. 1) and the level change detection circuit 22 (asynchronous latch circuit 401 shown in FIG. 2) that detects a change in logic level in the input signal 11 within a predetermined time. _N to 401 and corresponds) in _N, it counts the number of changes in logic level level change detecting circuit 22 detects the count value is for determining whether the level change determining circuit exceeds a predetermined threshold 3 (corresponding to the decoder unit 411 _N ~41M _N shown in FIG. 2), the number of times the level change determining circuit 23 determines that the count value in the longer predetermined period than the predetermined time described above exceeds a predetermined threshold Is determined to be over the predetermined number of times, and when it is determined that the predetermined number of times is exceeded, the abnormality determination circuit 24 (protection stage number units 411 _{N to} 41M _N shown in FIG. 1) sets the switch circuit 21 to the cutoff state. Equivalent).

  FIG. 6 is a block diagram showing a main part of a semiconductor integrated circuit according to another aspect incorporating an input protection circuit. As shown in FIG. 6, in addition to the components shown in FIG. 5, the semiconductor integrated circuit 1B is provided with a register 25 for storing the count value by the level change determination circuit 23 and the determination result of the abnormality determination circuit 24. It has been.

  The above embodiment includes an input protection circuit configured as follows.

(1) The level change detection circuit 22 outputs a signal of a predetermined level (high level or low level) when the input signal changes from high level to low level or when the input signal changes from low level to high level. An input protection circuit including a plurality of latch circuits that perform latch output, wherein a value obtained by summing up the number of latch outputs from the plurality of latch circuits is a logic level change count.

(2) Further, an input protection circuit configured such that each of the plurality of latch circuits is reset by a clock signal having a predetermined frequency. The predetermined frequency is preferably lower than the operating frequency of the input protection circuit, and the reciprocal of the predetermined frequency, that is, the cycle, is preferably longer than the average cycle of the logical change assumed to appear in the input signal.

(3) An input protection circuit in which the level change determination circuit 22 is configured to set the maximum value of the plurality of count values in the register 25. According to such a configuration, when the contents of the register 25 are monitored, the device state can be grasped to some extent even when the abnormality determination circuit 24 does not determine that there is an abnormality.

  The present invention can be applied to general semiconductor integrated circuits including programmable semiconductor integrated circuits.

1A, 1B semiconductor integrated circuit 2 input protection circuit 10 device 11 input circuit 12 current source 20 facing the device 21 the switching circuit 22 level change detecting circuit 23 level change determining circuit 24 abnormality determination circuit 25 registers 30 the personal computer 100 ₁ to 100 _N signal 200 ₁ to 200 _N input circuit 300 _{1 to} 300 _N wiring 400 _{1 to} 400 _N indefinite detection circuit unit 401 _{N to} 40M _N asynchronous latch circuit 411 _{N to} 41M _N EN signal 420 _N operation clock signal 500 _{1 to} 500 _N decoder unit 600 ₁ to 600 _N protection stage number section 700 ₁ to wiring 700 _N wiring 800 _{1 to} 800 _N switch 900 JTAG monitor register section

Claims (8)

A switch circuit provided between an input circuit to which an input signal that is a digital signal is input and a current supply source that supplies current to the input circuit;
A level change detection circuit for detecting a change in logic level within a predetermined time in the input signal;
A level change determination circuit that counts the number of logical level changes detected by the level change detection circuit and determines whether the count value exceeds a predetermined threshold;
The number of times that the level change determination circuit determines that the count value exceeds a predetermined threshold in a predetermined period longer than the predetermined time is determined whether it exceeds the predetermined number, and exceeds the predetermined number of times. An input protection circuit comprising: an abnormality determination circuit that sets the switch circuit to a cut-off state when it is determined that Level change detection circuit
A plurality of latch circuits that latch and output a signal of a predetermined level when the input signal changes from a high level to a low level or when the input signal changes from a low level to a high level;
The input protection circuit according to claim 1, wherein a value obtained by summing up the number of latch outputs from the plurality of latch circuits is defined as the number of logic level changes. The input protection circuit according to claim 2, wherein each of the plurality of latch circuits is reset by a clock signal having a predetermined frequency. The input protection circuit according to any one of claims 1 to 3, further comprising a register that stores a count value obtained by the level change determination circuit and a determination result of the abnormality determination circuit. The input protection circuit according to claim 4, wherein the level change determination circuit sets a maximum value among the plurality of count values in the register. Semiconductor integrated circuit including an input circuit to which an input signal which is a digital signal is input, a current supply source for supplying current to the input circuit, and an input protection circuit for performing processing to prevent overcurrent from flowing in the input circuit A circuit,
The input protection circuit is
A switch circuit provided between the input circuit and the current supply source;
A level change detection circuit for detecting a change in logic level within a predetermined time in the input signal;
A level change determination circuit that counts the number of logical level changes detected by the level change detection circuit and determines whether the count value exceeds a predetermined threshold;
The number of times that the level change determination circuit determines that the count value exceeds a predetermined threshold in a predetermined period longer than the predetermined time is determined whether it exceeds the predetermined number, and exceeds the predetermined number of times. And an abnormality determination circuit that sets the switch circuit to a cut-off state when it is determined as a semiconductor integrated circuit. The level change detection circuit in the input protection circuit is
A plurality of latch circuits that latch and output a signal of a predetermined level when the input signal changes from a high level to a low level or when the input signal changes from a low level to a high level;
The semiconductor integrated circuit according to claim 6, wherein a value obtained by summing up the number of latch outputs from the plurality of latch circuits is defined as the number of logic level changes. The semiconductor integrated circuit according to claim 6, wherein the input protection circuit includes a register that stores a count value obtained by the level change determination circuit and a determination result of the abnormality determination circuit.

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