WO2013145196A1 - Connection device and failure detection method - Google Patents

Connection device and failure detection method Download PDF

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Publication number
WO2013145196A1
WO2013145196A1 PCT/JP2012/058266 JP2012058266W WO2013145196A1 WO 2013145196 A1 WO2013145196 A1 WO 2013145196A1 JP 2012058266 W JP2012058266 W JP 2012058266W WO 2013145196 A1 WO2013145196 A1 WO 2013145196A1
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WO
WIPO (PCT)
Prior art keywords
fan
circuit
counter
rotation pulse
signal
Prior art date
Application number
PCT/JP2012/058266
Other languages
French (fr)
Japanese (ja)
Inventor
晴彦 坂井
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富士通株式会社
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Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to PCT/JP2012/058266 priority Critical patent/WO2013145196A1/en
Publication of WO2013145196A1 publication Critical patent/WO2013145196A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/20009—Modifications to facilitate cooling, ventilating, or heating using a gaseous coolant in electronic enclosures
    • H05K7/20209—Thermal management, e.g. fan control

Definitions

  • the present invention relates to a connection device and an abnormality detection method.
  • the temperature of an electronic component in the electronic device rises and a failure may occur.
  • the electronic device sucks cooling air from the outside of the electronic device using a fan, and cools the electronic components that generate heat by the sucked cooling air.
  • the designer of the electronic device prevents the temperature of the electronic component from rising and prevents a failure from occurring.
  • FIG. 10 is a diagram illustrating an example of cooling of an electronic component using a fan in an electronic device.
  • FIG. 10 illustrates an information processing apparatus as an example of an electronic device.
  • the information processing apparatus 900 includes a power source 901, a power connector 902, an I / O (Input Output) device 903, a fan 904, a fan 905, a fan 906, a motherboard 910, and a fan 920.
  • I / O Input Output
  • the power source 901 supplies power to the information processing apparatus 900.
  • the power connector 902 supplies power from the power source 901 to the added device.
  • the I / O device 903 is a device that stores data on a medium such as a CD (Compact Disc).
  • the fan 904, the fan 905, and the fan 906 send cooling air sucked from the outside of the information processing apparatus 900 to the electronic components and cools them.
  • the motherboard 910 includes a fan connection port 911, a fan connection port 912, a fan connection port 913, a multiplexer 914, a counter 915, and a CPU (Central Processing Unit) 916.
  • Each fan connection port 911, fan connection port 912, and fan connection port 913 are connected to the fan 904, the fan 905, and the fan 906, and output a rotation pulse input from the fan to the multiplexer 914.
  • the multiplexer 914 selects one of the rotation pulses input from the fan 904, the fan 905, and the fan 906 and outputs the selected pulse to the counter 915.
  • the CPU 916 determines whether or not an abnormality has occurred in the fan 904, the fan 905, and the fan 906 by monitoring the rotation pulse counted by the counter 915.
  • Such an information processing apparatus 900 is provided with a spare fan connection port for which an additional fan is expected.
  • the fan connection port 913 corresponds to a spare fan connection port, and the fan 906 is added via the spare fan connection port 913.
  • the electronic component may emit a higher amount of heat than assumed at the beginning of the design.
  • a fan 920 is further added to the information processing apparatus 900 via the power connector 902.
  • the power connector 902 does not have a counter that counts the rotation pulses input from the added fan 920 and a CPU that monitors the rotation pulses counted by the counter, has an abnormality occurred in the added fan 920? Cannot determine whether or not. For this reason, when the added fan 920 fails, the temperature of the electronic component in the information processing apparatus 900 rises, causing a system down.
  • the user cannot specify whether the system down is caused by a failure of the fan 920 or a failure of another part of the information processing apparatus 900. As a result, it takes time for the user to investigate the cause of the system down.
  • an object of the present invention is to provide a connection device and an abnormality detection method that can identify an abnormality of an added fan.
  • the connection device includes a first connection unit that connects the first fan and the second fan, a second connection unit that connects the electronic device, a first fan and a second fan.
  • a monitoring circuit for monitoring the operation includes a receiving unit, a first counter, a second counter, a switching circuit, and an output unit.
  • the receiving unit receives the rotation pulse from the first fan and the second fan via the first connection unit.
  • the first counter measures the rotation pulse received from the first fan.
  • the second counter measures the rotation pulse received from the second fan.
  • the switching circuit receives the rotation pulse from the first fan and the second fan, and alternately switches either the rotation pulse received from the first fan or the rotation pulse received from the second fan according to the switching signal. Output to.
  • the output unit cannot measure any one of the rotation pulses of the first fan and the rotation pulses of the second fan output from the switching circuit, either the first fan or the second fan is output. Is output to the electronic device via the second connection portion.
  • connection device in one embodiment, it is possible to identify an abnormality of the added fan.
  • FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus having a fan expansion device according to the first embodiment.
  • FIG. 2 is a block diagram illustrating the configuration of the fan expansion device according to the first embodiment.
  • FIG. 3 is a diagram illustrating an example of the reset signal generation circuit.
  • FIG. 4 is a diagram illustrating an example of a reset signal generation operation.
  • FIG. 5 is a timing chart when the fan is operating normally.
  • FIG. 6 is a timing chart when the additional fan is out of order.
  • FIG. 7 is a flowchart illustrating a processing procedure performed by the fan expansion device in a normal state.
  • FIG. 8 is a flowchart showing a processing procedure performed by the fan expansion device when a fan fails.
  • FIG. 9 is a flowchart illustrating a processing procedure performed by the fan expansion device when the expansion fan fails.
  • FIG. 10 is a diagram illustrating an example of cooling of an electronic component using a fan in an electronic device.
  • connection device and the abnormality detection method disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Each embodiment can be appropriately combined within a range in which processing contents are not contradictory.
  • the first embodiment shows a fan expansion device that adds a fan to an electronic device such as an information processing device as an example of a connection device.
  • an electronic device such as an information processing device as an example of a connection device.
  • the configuration of the fan expansion device, the processing operation, the processing flow, and the like will be described with reference to FIGS.
  • FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus 10 including a fan expansion device 100 according to the first embodiment.
  • the information processing apparatus 10 includes a power source 11, an I / O device 12, a motherboard 20, a fan 31, a fan 32, a fan 33, an expansion fan 34, and a fan expansion device 100. .
  • the power supply 11 supplies power to the information processing apparatus 10.
  • the I / O device 12 is a device that stores data in a medium such as a CD (Compact Disc).
  • the motherboard 20 includes a fan connection port 21, a fan connection port 22, a fan connection port 23, a multiplexer 24, a counter 25, and a CPU (Central Processing Unit) 26.
  • the fan connection port 21 is connected to the fan 31 and outputs the rotation pulse input from the fan 31 to the multiplexer 24.
  • the fan connection port 22 is connected to the fan 32 and outputs the rotation pulse input from the fan 32 to the multiplexer 24.
  • the fan connection port 23 is connected to the fan 33 and the expansion fan 34 via the fan expansion device 100, and outputs the rotation pulse input from the fan 33 and the expansion fan 34 to the multiplexer 24.
  • the multiplexer 24 selects any one of the rotation pulses input from the fan 31, the fan 32, the fan 33, and the expansion fan 34 and outputs the selected pulse to the counter 25.
  • the CPU 26 determines whether or not an abnormality has occurred in the fan 31, the fan 32, the fan 33, and the additional fan 34 by monitoring the rotation pulse counted by the counter 25.
  • the CPU 26 may be a main CPU included in the motherboard 20 or may be a sub CPU included in the motherboard 20.
  • the fan 31, the fan 32, the fan 33, and the additional fan 34 cool the air by sucking the cooling air sucked from the outside of the information processing apparatus 10 to the electronic parts.
  • the fan 31 outputs a rotation pulse to the fan connection port 21, and the fan 32 outputs the rotation pulse to the fan connection port 22.
  • the fan 33 and the expansion fan 34 output a rotation pulse to the fan expansion device 100.
  • the fan expansion device 100 includes a fan connection port 101, a fan connection port 102, a connection port 103, and a monitoring circuit 104.
  • the fan connection port 101 is connected to the fan 33 and outputs a rotation pulse input from the fan 33 to the monitoring circuit 104.
  • the fan connection port 102 is connected to the expansion fan 34 and outputs the rotation pulse input from the expansion fan 34 to the monitoring circuit 104.
  • the connection port 103 is connected to the monitoring circuit 104 and the fan connection port 23 included in the motherboard 20, and outputs the rotation pulse input from the monitoring circuit 104 to the motherboard 20 via the fan connection port 23.
  • the monitoring circuit 104 inputs a rotation pulse from the fan 33 and the additional fan 34 via the fan connection port 101 and the fan connection port 102.
  • the monitoring circuit 104 measures a rotation pulse input from the fan 33 by a counter 401 described later, and measures a rotation pulse input from the expansion fan 34 by a counter 402 described later. If the monitoring circuit 104 cannot measure the rotation pulse of either the fan 33 or the expansion fan 34, a signal indicating that either the fan 33 or the expansion fan 34 is abnormal is sent via the connection port 103. Output to the motherboard 20.
  • FIG. 2 is a block diagram illustrating the configuration of the monitoring circuit 104 according to the first embodiment.
  • the monitoring circuit 104 according to the first embodiment includes a fan input switching circuit 200, a fan input selection circuit 300, a fan abnormality detection circuit 400, an AND circuit 500, and an OR circuit 600.
  • a three-terminal regulator for adjusting the power supply voltage may be inserted between the power supply input from the monitoring circuit 104 and the power supply to the circuit element.
  • a power-on reset circuit and a bypass capacitor of a logic IC (Integrated Circuit) are necessary, and the bypass capacitor is omitted in FIG.
  • the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34.
  • the fan input switching circuit 200 alternately outputs one of the rotation pulse input from the fan 33 or the rotation pulse input from the additional fan 34 to the fan input selection circuit 300 and the AND circuit 500 in accordance with the fan input switching signal.
  • the fan input switching circuit 200 selects the rotation pulse input from the fan 33 and outputs it to the fan input selection circuit 300 and the AND circuit 500.
  • the fan input switching circuit 200 selects the rotation pulse input from the expansion fan 34 and outputs it to the fan input selection circuit 300 and the AND circuit 500.
  • the fan input selection circuit 300 receives the rotation pulse output from the fan input switching circuit 200, measures the rotation pulse by a counter 301 described later, and outputs the measured result to the fan input switching circuit 200 as a fan input switching signal. To do. Note that the number of bits that the counter 301 has is smaller than the number of bits that the counter 401 and the counter 402 described later have.
  • the fan abnormality detection circuit 400 receives the rotation pulse from the fan 33 and measures it with the counter 401, and also inputs the rotation pulse from the additional fan 34 and measures it with the counter 402.
  • the fan abnormality detection circuit 400 includes a reset signal generation circuit 403 that receives a fan input switching signal from the fan input selection circuit 300 and generates a reset signal from the input fan input switching signal.
  • the fan abnormality detection circuit 400 determines that the rotation pulse of the fan 33 and the additional fan 34 can be measured, and the result of measurement by the counter 401 and the counter 402 To reset.
  • the fan abnormality detection circuit 400 determines that the rotation pulse of either the fan 33 or the additional fan 34 cannot be measured. Then, the fan abnormality detection circuit 400 outputs a signal indicating that either the fan 33 or the additional fan 34 is abnormal to the mother board 20 via the connection port 103.
  • the fan abnormality detection circuit 400 executes the following processing. To do. That is, the fan abnormality detection circuit 400 outputs a low potential signal “L” indicating that the fan 33 is abnormal to the OR circuit 600.
  • the fan abnormality detection circuit 400 executes the following processing when the reset signal cannot be input from the reset signal generation circuit 403 and the rotation pulse input from the fan 33 is continuously measured up to the upper limit value of the counter 401. . That is, the fan abnormality detection circuit 400 outputs a high potential signal “H” indicating that the additional fan 34 is abnormal to the OR circuit 600.
  • the AND circuit 500 outputs a signal that is a logical product of the rotation pulse input from the fan input switching circuit 200 and the signal input from the fan abnormality detection circuit 400 to the OR circuit 600. For example, when the fan 33 and the additional fan 34 are normal, the AND circuit 500 receives a rotation pulse from the fan input switching circuit 200 and a high potential signal “H” from the fan abnormality detection circuit 400. Then, the AND circuit 500 outputs the rotation pulse to the OR circuit 600.
  • the AND circuit 500 cannot input a rotation pulse from the fan input switching circuit 200 and inputs a low potential signal “L” from the fan abnormality detection circuit 400 when either the fan 33 or the expansion fan 34 fails. . Then, the AND circuit 500 outputs a low potential signal “L” to the OR circuit 600.
  • OR circuit 600 outputs, to connection port 103, a signal that is a logical sum of the signal input from AND circuit 500 and the signal input from fan abnormality detection circuit 400. For example, when the fan 33 and the additional fan 34 are normal, the OR circuit 600 receives a rotation pulse from the AND circuit 500 and a low potential signal “L” from the fan abnormality detection circuit 400. Then, the OR circuit 600 outputs a rotation pulse to the connection port 103.
  • the OR circuit 600 receives a low potential signal “L” from the AND circuit 500 and a low potential signal “L” from the fan abnormality detection circuit 400 when the fan 33 fails. Then, the OR circuit 600 outputs a low potential signal “L” to the connection port 103.
  • the OR circuit 600 receives a low potential signal “L” from the AND circuit 500 and a high potential signal “H” from the fan abnormality detection circuit 400 when the expansion fan 34 fails. Then, the OR circuit 600 outputs a high potential signal “H” to the connection port 103.
  • the fan input switching circuit 200 includes a NOT circuit 201, an AND circuit 202 and an AND circuit 203, and an EX-OR circuit 204.
  • the NOT circuit 201 inverts the fan input switching signal input from the fan input selection circuit 300 and outputs the inverted signal to the AND circuit 202.
  • the AND circuit 202 outputs a signal that is a logical product of the rotation pulse input from the fan 33 via the fan connection port 101 and the inverted fan input switching signal input from the NOT circuit 201 to the EX-OR circuit 204.
  • the AND circuit 203 outputs to the EX-OR circuit 204 a signal that is the logical product of the rotation pulse input from the additional fan 34 via the fan connection port 102 and the fan input switching signal input from the fan input selection circuit 300. .
  • the EX-OR circuit 204 outputs the exclusive OR of the signal input from the AND circuit 202 and the signal input from the AND circuit 203 to the fan input selection circuit 300 and the AND circuit 500 as a rotation pulse.
  • the fan input selection circuit 300 has a counter 301.
  • the counter 301 counts the rotation pulse input from the fan input switching circuit 200 and outputs the counted value of the most significant bit to the fan input switching circuit 200 and the fan abnormality detection circuit 400 as a fan input switching signal.
  • the fan abnormality detection circuit 400 includes a counter 401 and a counter 402, a reset signal generation circuit 403, an OR circuit 404, a NOT circuit 405, a NOT circuit 406, an AND circuit 407, and an AND circuit 408.
  • the counter 401 counts the rotation pulses input from the fan 33 via the fan connection port 101, and outputs the counted value of the most significant bit to the OR circuit 404 and the OR circuit 600. Further, the counter 401 resets the counted value when a reset signal is input from the reset signal generation circuit 403.
  • the counter 402 counts the rotation pulses input from the expansion fan 34 via the fan connection port 102 and outputs the counted value of the most significant bit to the OR circuit 404.
  • the counter 402 resets the counted value when a reset signal is input from the reset signal generation circuit 403.
  • the counter 401 and the counter 402 have a larger number of bits than the counter 301 included in the fan input selection circuit 300. Thereby, when there is a difference in the rotation speed of the fan connected to the fan abnormality detection circuit 400, the most significant bit of the counter 401 and the counter 402 is changed from “L” to “H” before the fan input switching signal is output. To prevent switching to. That is, the most significant bit of the counter 401 and the counter 402 does not become “H” when the fan 33 and the additional fan 34 are in normal operation.
  • the difference in the rotation speed of fans used in the same system is usually about 2 to 3 times, and a bit number of about twice is sufficient. Further, the difference in the rotation speed of the fan is not limited to 2 to 3 times, and can be changed according to the fan to be used.
  • the reset signal generation circuit 403 receives the fan input switching signal from the fan input selection circuit 300, generates a reset signal from the input fan input switching signal, and outputs the reset signal to the counter 401 and the counter 402. Details of the reset signal generation circuit 403 will be described later with reference to FIG.
  • OR circuit 404 outputs a signal that is a logical sum of the value of the most significant bit input from counter 401 and the value of the most significant bit input from counter 402 to NOT circuit 405 and NOT circuit 406.
  • NOT circuit 405 inverts the signal input from OR circuit 404 and outputs the result to AND circuit 500.
  • the NOT circuit 406 inverts the signal input from the OR circuit 404 and outputs the inverted signal to the AND circuit 407 and the AND circuit 408.
  • the AND circuit 407 outputs, to the counter 401, a signal that is a logical product of the rotation pulse input from the fan 33 via the fan connection port 101 and the signal input from the NOT circuit 406. For example, since the AND circuit 407 receives a high potential signal “H” from the NOT circuit 406 when the fan 33 and the additional fan 34 are normal, the rotation pulse input from the fan 33 via the fan connection port 101 is input. Output to the counter 401.
  • the AND circuit 407 inputs a low potential signal “L” from the NOT circuit 406 when either the fan 33 or the expansion fan 34 fails, and therefore cannot output a rotation pulse to the counter 401. That is, the input to the counter 401 is masked.
  • the AND circuit 408 outputs a signal, which is a logical product of the rotation pulse input from the additional fan 34 via the fan connection port 102 and the signal input from the NOT circuit 406, to the counter 402. For example, since the AND circuit 408 inputs a high potential signal “H” from the NOT circuit 406 when the fan 33 and the expansion fan 34 are normal, the rotation pulse input from the expansion fan 34 via the fan connection port 102. Is output to the counter 402.
  • the AND circuit 408 inputs a low-potential signal “L” from the NOT circuit 406 when either the fan 33 or the expansion fan 34 fails, and therefore cannot output a rotation pulse to the counter 402. That is, the input to the counter 402 is masked.
  • FIG. 3 is a diagram illustrating an example of the reset signal generation circuit.
  • the reset signal generation circuit 403 includes a resistor 403a, a capacitor 403b, and an EX-OR circuit 403c.
  • the resistor 403a and the capacitor 403b are integrating circuits, and output a voltage having a waveform equal to the time integration of the waveform of the input voltage of the fan input switching signal to the EX-OR circuit 403c.
  • the resistor 403a and the capacitor 403b output a signal obtained by multiplying the fan input switching signal by the time constant to the EX-OR circuit 403c.
  • the EX-OR circuit 403c inputs a fan input switching signal and a signal obtained by multiplying the fan input switching signal by a time constant, and outputs a reset signal generated by taking an exclusive OR.
  • FIG. 4 is a diagram illustrating an example of a reset signal generation operation.
  • the reset signal is generated by taking an exclusive OR of a fan input switching signal and a signal obtained by multiplying the fan input switching signal by a time constant. For this reason, as shown in FIG. 4, the rise of the waveform of the signal obtained by multiplying the fan input switching signal by the time constant is delayed as compared to the rise of the waveform of the fan input switching signal. The time until the rising waveform delayed by the time constant exceeds the threshold value of the logic circuit is the pulse width of the reset signal.
  • V (t) is a threshold value and “V” is a “high potential voltage”
  • t is a time to reach the threshold value from the low potential voltage.
  • FIG. 5 is a timing chart when the fan is operating normally.
  • the fan input switching circuit 200 inputs rotation pulses from the fan 33 and the expansion fan 34.
  • the AND circuit 202 outputs the rotation pulse input from the fan 33 to the EX-OR circuit 204 in the period t1.
  • the EX-OR circuit 204 outputs the rotation pulse input from the AND circuit 202 to the fan input selection circuit 300.
  • the counter 301 counts the rotation pulses input from the fan input switching circuit 200 and outputs the most significant bit of the counter 301. At t2, the most significant bit of the counter 301 is switched from “L” to “H”, and the fan input selection circuit 300 outputs a fan input switching signal “H”.
  • the AND circuit 203 outputs a rotation pulse to the EX-OR circuit 204 in the period t3. That is, the fan input switching circuit 200 switches the rotation pulse output from the rotation pulse input from the fan 33 to the rotation pulse input from the expansion fan 34.
  • the EX-OR circuit 204 outputs the rotation pulse input from the AND circuit 203 to the fan input selection circuit 300.
  • the fan abnormality detection circuit 400 generates a reset signal at t2 which is the highest switching timing of the counter 301, and resets the counter 401 and the counter 402. Thereby, the fan abnormality detection circuit 400 does not switch the most significant bit of the counter 401 and the counter 402 from “L” to “H”.
  • FIG. 6 is a timing chart when the expansion fan 34 fails.
  • the fan input switching circuit 200 inputs rotation pulses from the fan 33 and the expansion fan 34.
  • the AND circuit 202 outputs the rotation pulse input from the fan 33 to the EX-OR circuit 204 in the period t1.
  • the EX-OR circuit 204 outputs the rotation pulse input from the AND circuit 203 to the fan input selection circuit 300.
  • the counter 301 counts the rotation pulses input from the fan input switching circuit 200 and outputs the most significant bit of the counter 301. At t2, the most significant bit of the counter 301 is switched from “L” to “H”, and the fan input selection circuit 300 outputs a fan input switching signal “H”.
  • the AND circuit 203 outputs a rotation pulse during the period t3. That is, the fan input switching circuit 200 switches the rotation pulse output from the rotation pulse input from the fan 33 to the rotation pulse input from the expansion fan 34.
  • the expansion fan 34 fails after switching the rotation pulse is shown.
  • the fan input switching circuit 200 cannot input the rotation pulse from the failed expansion fan 34 and cannot output the rotation pulse. Further, since the fan input selection circuit 300 cannot input a rotation pulse from the fan input switching circuit 200, the counter 301 stops its operation. For this reason, the fan input selection circuit 300 cannot generate a fan input switching signal. That is, the fan input switching circuit 200 cannot switch the rotation pulse input from the failed additional fan 34 to the normal fan 33. For this reason, the fan expansion device 100 does not output a rotation pulse.
  • the fan abnormality detection circuit 400 cannot generate a reset signal. For this reason, the counter 401 continues to count the rotation pulses input from the fan 33.
  • the fan abnormality detection circuit 400 masks the inputs of the counter 401 and the counter 402 when the most significant bit of the counter 401 becomes “H”, and the most significant bit of the counter 401 is “H”. The state in which the most significant bit is “L” is maintained.
  • the fan abnormality signal that is the logical sum of the most significant bits of the counter 401 and the counter 402 masks the rotation pulse output from the EX-OR circuit 204.
  • the most significant bit of the counter 402 connected to the failed additional fan 34 is “L”
  • the most significant bit of the counter 401 connected to the non-failed fan 33 is “H”.
  • the OR circuit 600 synthesizes the logical sum of the most significant bit “H” of the counter 401 and the masked rotation pulse, thereby fixing the output state according to the failed fan.
  • the output of the OR circuit 600 when the output of the OR circuit 600 is “L”, it indicates a failure of the fan 33, and when the output of the OR circuit 600 is “H”, it indicates a failure of the expansion fan 34.
  • the user of the information processing apparatus 10 can detect that a failure has occurred in any of the fans connected to the fan expansion device 100.
  • FIG. 7 is a flowchart showing a processing procedure performed by the fan expansion device 100 in a normal state.
  • the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34 (step S101). Further, the fan abnormality detection circuit 400 receives a rotation pulse from the fan 33 and the additional fan 34 (step S102).
  • the fan input selection circuit 300 outputs the most significant bit of the counter 301 as a fan input switching signal (step S103).
  • the fan input switching circuit 200 receives the input switching signal from the fan input selection circuit 300 (step S104), and outputs a rotation pulse of the fan 33 (step S105).
  • the fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S106). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal “L” (step S107). The fan abnormality detection circuit 400 outputs a signal obtained by inverting the logical sum of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 to the AND circuit 500 as a fan abnormality signal “H”. (Step S108). The fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S109).
  • the fan input selection circuit 300 counts the rotation pulses of the fan 33 (step S110), and outputs the most significant bit of the counter 301 as a fan input switching signal (step S111).
  • the fan input switching circuit 200 receives the fan input switching signal from the fan input selection circuit 300 (step S112), and outputs a rotation pulse of the expansion fan 34 (step S113).
  • the fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S114). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal (step S115). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “L” of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 as a fan abnormality signal “H”, and the AND circuit 500. (Step S116). Further, the fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S117).
  • the fan input selection circuit 300 counts the rotation pulses of the expansion fan 34 (step S118), and outputs the most significant bit of the counter 301 as a fan input switching signal (step S119). If the fan 33 and the expansion fan 34 are normal after the end of step S119, the fan expansion device 100 repeatedly executes the processes from step S101 to step S119.
  • FIG. 8 is a flowchart showing a processing procedure performed by the fan expansion device 100 when the fan 33 fails.
  • the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34 (step S201). Further, the fan abnormality detection circuit 400 receives a rotation pulse from the fan 33 and the additional fan 34 (step S202).
  • the fan input selection circuit 300 outputs the most significant bit of the counter 301 as a fan input switching signal (step S203).
  • the fan input switching circuit 200 receives the input switching signal from the fan input selection circuit 300 (step S204), and outputs a rotation pulse of the fan 33 (step S205).
  • the fan input selection circuit 300 determines that the rotation pulses of the fan 33 cannot be counted (step S206).
  • the fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S207). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal (step S208). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “L” of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 as a fan abnormality signal “H”, and the AND circuit 500. (Step S209).
  • the fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S210). Then, the fan abnormality detection circuit 400 determines whether or not the most significant bit of the counter 402 is “H” (step S211). If the fan abnormality detection circuit 400 determines that the most significant bit of the counter 402 is not “H” (step S211, No), the process proceeds to step S208.
  • the fan abnormality detection circuit 400 determines that the most significant bit of the counter 402 is “H” (Yes in step S211), the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal. (Step S212). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “H” of the most significant bit “L” of the counter 401 and the most significant bit “H” of the counter 402 as the fan abnormality signal “L”. (Step S213).
  • the fan abnormality detection circuit 400 masks the rotation pulse input from the fan 33 and the additional fan 34 with the fan abnormality signal “L” (step S214). As a result, the most significant bit of the counter 401 to which the failed fan 33 is connected is “L”, and the most significant bit of the counter 402 to which the non-failed additional fan 34 is connected is “H”.
  • FIG. 9 is a flowchart showing a processing procedure performed by the fan expansion device 100 when the expansion fan 34 fails.
  • the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34 (step S301). Further, the fan abnormality detection circuit 400 receives a rotation pulse from the fan 33 and the additional fan 34 (step S302).
  • the fan input selection circuit 300 outputs the most significant bit of the counter 301 as a fan input switching signal (step S303).
  • the fan input switching circuit 200 receives the input switching signal from the fan input selection circuit 300 (step S304), and outputs a rotation pulse of the expansion fan 34 (step S305).
  • the fan input selection circuit 300 determines that the rotation pulses of the expansion fan 34 cannot be counted (step S306).
  • the fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S307). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal (step S308). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “L” of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 as a fan abnormality signal “H”, and the AND circuit 500. (Step S309).
  • the fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S310). Then, the fan abnormality detection circuit 400 determines whether or not the most significant bit of the counter 401 is “H” (step S311). If the fan abnormality detection circuit 400 determines that the most significant bit of the counter 401 is not “H” (step S311, No), the process proceeds to step S308.
  • the fan abnormality detection circuit 400 determines that the most significant bit of the counter 401 is “H” (Yes in step S311), the fan abnormality detection circuit 400 outputs the most significant bit “H” of the counter 402 to the OR circuit 600 as a failure fan signal. (Step S312). Further, the fan abnormality detection circuit 400 uses the AND circuit 500 as a fan abnormality signal “L” obtained by inverting the logical sum “H” of the most significant bit “H” of the counter 401 and the most significant bit “L” of the counter 402. (Step S313).
  • the fan abnormality detection circuit 400 masks the rotation pulse input from the fan 33 and the additional fan 34 with the fan abnormality signal “L” (step S314).
  • the most significant bit of the counter 401 to which the non-failed fan 33 is connected is “H”
  • the most significant bit of the counter 402 to which the failed additional fan 34 is connected is “L”.
  • the fan expansion device 100 can not only supply power to the added fan but also monitor the rotation of the added fan.
  • the fan expansion device 100 it is not necessary to change the design of the motherboard or the like for the fan expansion.
  • the fan expansion device 100 when it is necessary to support a new CPU or a new HDD with high power consumption, the designer can use an existing system. This saves development costs and time. Furthermore, new CPUs, new HDDs and the like can be supplied to customers at an early stage.
  • the monitoring circuit 104 can be realized in a small size, and is mounted in the middle of the cable connecting the fan 33 and the additional fan 34 and the motherboard 20 including the circuit for detecting the rotation pulse of the fan. May be.
  • the monitoring circuit 104 may be integrated with this cable. Further, the monitoring circuit 104 may be installed in the housing of the information processing apparatus as one component. Further, the monitoring circuit 104 may be realized by plugging into a fan connection port of the motherboard 20 including a circuit for detecting a rotation pulse of the fan.

Abstract

A connection device (100) receives rotation pulses from a first fan and a second fan through a first connection section connected to the first fan and the second fan. The connection device (100) also counts the rotation pulses received from the first fan with a first counter and counts the rotation pulses received from the second fan with a second counter. Then, the connection device (100) receives the rotation pulses from the first fan and the second fan, and alternately outputs one of the rotation pulses received from the first fan and the rotation pulses received from the second fan according to a switching signal. If the connection device (100) cannot count either the output rotation pulses of the first fan or the output rotation pulses of the second fan, the connection device (100) outputs a signal indicating that either the first fan or the second fan is faulty to an electronic unit through a second connection section connected to the electronic unit.

Description

接続装置及び異常検出方法Connection device and abnormality detection method
　本発明は、接続装置及び異常検出方法に関する。 The present invention relates to a connection device and an abnormality detection method.
　従来、電子機器では、電子機器内の電子部品の温度が上昇して障害が発生する場合がある。このため、電子機器は、ファンを用いて電子機器の外部から冷却風を吸入し、吸入した冷却風で発熱する電子部品を冷却する。このようにして、電子機器の設計者は、電子部品の温度が上昇することを防止して、障害を発生させないようにしている。 Conventionally, in an electronic device, the temperature of an electronic component in the electronic device rises and a failure may occur. For this reason, the electronic device sucks cooling air from the outside of the electronic device using a fan, and cools the electronic components that generate heat by the sucked cooling air. In this way, the designer of the electronic device prevents the temperature of the electronic component from rising and prevents a failure from occurring.
　図１０を用いて、電子機器におけるファンを用いた電子部品の冷却について説明する。図１０は、電子機器におけるファンを用いた電子部品の冷却の一例を示す図である。なお、図１０は、電子機器の一例として情報処理装置を示す。図１０に示すように、情報処理装置９００は、電源９０１と、電源コネクタ９０２と、Ｉ／Ｏ（Input　Output）装置９０３と、ファン９０４、ファン９０５、ファン９０６と、マザーボード９１０と、ファン９２０とを有する。 Referring to FIG. 10, the cooling of electronic components using a fan in an electronic device will be described. FIG. 10 is a diagram illustrating an example of cooling of an electronic component using a fan in an electronic device. Note that FIG. 10 illustrates an information processing apparatus as an example of an electronic device. As illustrated in FIG. 10, the information processing apparatus 900 includes a power source 901, a power connector 902, an I / O (Input Output) device 903, a fan 904, a fan 905, a fan 906, a motherboard 910, and a fan 920. Have
　電源９０１は、情報処理装置９００に電力を供給する。電源コネクタ９０２は、Ｉ／Ｏ装置９０３などの装置が増設された場合に、増設された装置に電源９０１からの電力を供給する。Ｉ／Ｏ装置９０３は、例えば、ＣＤ（Compact　Disc）などの媒体にデータを記憶させる装置である。ファン９０４、ファン９０５、ファン９０６は、情報処理装置９００の外部から吸入した冷却風を電子部品に送風して冷却する。 The power source 901 supplies power to the information processing apparatus 900. When a device such as the I / O device 903 is added, the power connector 902 supplies power from the power source 901 to the added device. The I / O device 903 is a device that stores data on a medium such as a CD (Compact Disc). The fan 904, the fan 905, and the fan 906 send cooling air sucked from the outside of the information processing apparatus 900 to the electronic components and cools them.
　マザーボード９１０は、ファン接続ポート９１１、ファン接続ポート９１２、ファン接続ポート９１３と、マルチプレクサ９１４と、カウンタ９１５と、ＣＰＵ（Central　Processing　Unit）９１６とを有する。各ファン接続ポート９１１、ファン接続ポート９１２、ファン接続ポート９１３は、ファン９０４、ファン９０５、ファン９０６と接続し、ファンから入力した回転パルスをマルチプレクサ９１４に出力する。そして、マルチプレクサ９１４は、ファン９０４、ファン９０５、ファン９０６から入力した回転パルスのうちいずれかを選択してカウンタ９１５に出力する。ＣＰＵ９１６は、カウンタ９１５によりカウントされる回転パルスを監視することで、ファン９０４、ファン９０５、ファン９０６に異常が生じたか否かを判定する。 The motherboard 910 includes a fan connection port 911, a fan connection port 912, a fan connection port 913, a multiplexer 914, a counter 915, and a CPU (Central Processing Unit) 916. Each fan connection port 911, fan connection port 912, and fan connection port 913 are connected to the fan 904, the fan 905, and the fan 906, and output a rotation pulse input from the fan to the multiplexer 914. The multiplexer 914 selects one of the rotation pulses input from the fan 904, the fan 905, and the fan 906 and outputs the selected pulse to the counter 915. The CPU 916 determines whether or not an abnormality has occurred in the fan 904, the fan 905, and the fan 906 by monitoring the rotation pulse counted by the counter 915.
　このような、情報処理装置９００には、ファンの増設を見込み予備のファン接続ポートが設けられている。例えば、図１０では、ファン接続ポート９１３が予備のファン接続ポートに該当し、この予備のファン接続ポート９１３を介してファン９０６が増設される。 Such an information processing apparatus 900 is provided with a spare fan connection port for which an additional fan is expected. For example, in FIG. 10, the fan connection port 913 corresponds to a spare fan connection port, and the fan 906 is added via the spare fan connection port 913.
　さらに、情報処理装置９００において、予備のファン接続ポート９１３を介してファン９０６が増設されたにもかかわらず、電子部品が、設計当初に想定したよりも高い熱量を発する場合がある。このような場合、情報処理装置９００には、電源コネクタ９０２を介してファン９２０が更に増設される。 Further, in the information processing apparatus 900, even though the fan 906 is added via the spare fan connection port 913, the electronic component may emit a higher amount of heat than assumed at the beginning of the design. In such a case, a fan 920 is further added to the information processing apparatus 900 via the power connector 902.
特開２００８－９１６０７号公報JP 2008-91607 A
　しかしながら、上述した従来の技術では、増設したファンの異常を特定することができない。 However, the conventional technology described above cannot identify the abnormality of the added fan.
　具体的には、電源コネクタ９０２は、増設したファン９２０から入力した回転パルスをカウントするカウンタ及びカウンタによりカウントされる回転パルスを監視するＣＰＵを有さないので、増設したファン９２０に異常が生じたか否かを判定できない。このため、増設したファン９２０が故障すると情報処理装置９００では電子部品の温度が上昇し、システムダウンが発生する。 Specifically, since the power connector 902 does not have a counter that counts the rotation pulses input from the added fan 920 and a CPU that monitors the rotation pulses counted by the counter, has an abnormality occurred in the added fan 920? Cannot determine whether or not. For this reason, when the added fan 920 fails, the temperature of the electronic component in the information processing apparatus 900 rises, causing a system down.
　また、この場合、利用者は、システムダウンがファン９２０の故障に起因するのか、情報処理装置９００の他の箇所の故障に起因するのかを特定できない。この結果、利用者がシステムダウンの原因を調査するのに時間がかかる。 In this case, the user cannot specify whether the system down is caused by a failure of the fan 920 or a failure of another part of the information processing apparatus 900. As a result, it takes time for the user to investigate the cause of the system down.
　１つの側面では、本発明は、増設したファンの異常を特定することができる接続装置及び異常検出方法を提供することを目的とする。 In one aspect, an object of the present invention is to provide a connection device and an abnormality detection method that can identify an abnormality of an added fan.
　１つの案では、接続装置は、第１のファン及び第２のファンを接続する第１の接続部と、電子機器を接続する第２の接続部と、第１のファン及び第２のファンの動作を監視する監視回路と、を有する。監視回路は、受信部と、第１のカウンタと、第２のカウンタと、切替回路と、出力部と、を有する。受信部は、第１の接続部を介して第１のファン及び第２のファンから回転パルスを受信する。第１のカウンタは、第１のファンから受信した回転パルスを計測する。第２のカウンタは、第２のファンから受信した回転パルスを計測する。切替回路は、第１のファン及び第２のファンから回転パルスを受信し、第１のファンから受信した回転パルスまたは第２のファンから受信した回転パルスのいずれか一方を切替信号に応じて交互に出力する。出力部は、切替回路から出力された第１のファンの回転パルス又は第２のファンの回転パルスのうち、いずれかの回転パルスを計測できない場合、第１のファン又は第２のファンのいずれかが異常であることを示す信号を第２の接続部を介して電子機器に出力する。 In one proposal, the connection device includes a first connection unit that connects the first fan and the second fan, a second connection unit that connects the electronic device, a first fan and a second fan. And a monitoring circuit for monitoring the operation. The monitoring circuit includes a receiving unit, a first counter, a second counter, a switching circuit, and an output unit. The receiving unit receives the rotation pulse from the first fan and the second fan via the first connection unit. The first counter measures the rotation pulse received from the first fan. The second counter measures the rotation pulse received from the second fan. The switching circuit receives the rotation pulse from the first fan and the second fan, and alternately switches either the rotation pulse received from the first fan or the rotation pulse received from the second fan according to the switching signal. Output to. When the output unit cannot measure any one of the rotation pulses of the first fan and the rotation pulses of the second fan output from the switching circuit, either the first fan or the second fan is output. Is output to the electronic device via the second connection portion.
　１実施形態における接続装置によれば、増設したファンの異常を特定することができる。 According to the connection device in one embodiment, it is possible to identify an abnormality of the added fan.
図１は、実施例１に係るファン増設装置を有する情報処理装置の構成を示すブロック図である。FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus having a fan expansion device according to the first embodiment. 図２は、実施例１に係るファン増設装置の構成を示すブロック図である。FIG. 2 is a block diagram illustrating the configuration of the fan expansion device according to the first embodiment. 図３は、リセット信号生成回路の一例を示す図である。FIG. 3 is a diagram illustrating an example of the reset signal generation circuit. 図４は、リセット信号の生成動作の一例を示す図である。FIG. 4 is a diagram illustrating an example of a reset signal generation operation. 図５は、ファンが正常動作時のタイミングチャートである。FIG. 5 is a timing chart when the fan is operating normally. 図６は、増設ファンが故障時のタイミングチャートである。FIG. 6 is a timing chart when the additional fan is out of order. 図７は、正常時のファン増設装置による処理手順を示すフローチャートである。FIG. 7 is a flowchart illustrating a processing procedure performed by the fan expansion device in a normal state. 図８は、ファン故障時のファン増設装置による処理手順を示すフローチャートである。FIG. 8 is a flowchart showing a processing procedure performed by the fan expansion device when a fan fails. 図９は、増設ファン故障時のファン増設装置による処理手順を示すフローチャートである。FIG. 9 is a flowchart illustrating a processing procedure performed by the fan expansion device when the expansion fan fails. 図１０は、電子機器におけるファンを用いた電子部品の冷却の一例を示す図である。FIG. 10 is a diagram illustrating an example of cooling of an electronic component using a fan in an electronic device.
　以下に、本願の開示する接続装置及び異常検出方法の実施例を図面に基づいて詳細に説明する。なお、この実施例によりこの発明が限定されるものではない。そして、各実施例は、処理内容を矛盾させない範囲で適宜組み合わせることが可能である。 Hereinafter, embodiments of the connection device and the abnormality detection method disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Each embodiment can be appropriately combined within a range in which processing contents are not contradictory.
　実施例１では、接続装置の一例として、情報処理装置などの電子機器にファンを増設するファン増設装置を示す。また、実施例１では、図１から図９を用いて、ファン増設装置の構成、処理の動作、処理の流れなどについて説明する。 The first embodiment shows a fan expansion device that adds a fan to an electronic device such as an information processing device as an example of a connection device. In the first embodiment, the configuration of the fan expansion device, the processing operation, the processing flow, and the like will be described with reference to FIGS.
［情報処理装置の構成］
　図１を用いて、実施例１に係るファン増設装置１００を有する情報処理装置１０の構成を説明する。図１は、実施例１に係るファン増設装置１００を有する情報処理装置１０の構成を示すブロック図である。図１に示すように、情報処理装置１０は、電源１１と、Ｉ／Ｏ装置１２と、マザーボード２０と、ファン３１、ファン３２、ファン３３と、増設ファン３４と、ファン増設装置１００とを有する。 [Configuration of information processing device]
A configuration of the information processing apparatus 10 including the fan expansion device 100 according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus 10 including a fan expansion device 100 according to the first embodiment. As illustrated in FIG. 1, the information processing apparatus 10 includes a power source 11, an I / O device 12, a motherboard 20, a fan 31, a fan 32, a fan 33, an expansion fan 34, and a fan expansion device 100. .
　電源１１は、情報処理装置１０に電力を供給する。Ｉ／Ｏ装置１２は、ＣＤ（Compact　Disc）などの媒体にデータを記憶させる装置である。 The power supply 11 supplies power to the information processing apparatus 10. The I / O device 12 is a device that stores data in a medium such as a CD (Compact Disc).
　マザーボード２０は、ファン接続ポート２１、ファン接続ポート２２、ファン接続ポート２３、マルチプレクサ２４と、カウンタ２５と、ＣＰＵ（Central　Processing　Unit）２６とを有する。ファン接続ポート２１は、ファン３１と接続し、ファン３１から入力した回転パルスをマルチプレクサ２４に出力する。また、ファン接続ポート２２は、ファン３２と接続し、ファン３２から入力した回転パルスをマルチプレクサ２４に出力する。ファン接続ポート２３は、ファン増設装置１００を介してファン３３及び増設ファン３４と接続し、ファン３３及び増設ファン３４から入力した回転パルスをマルチプレクサ２４に出力する。 The motherboard 20 includes a fan connection port 21, a fan connection port 22, a fan connection port 23, a multiplexer 24, a counter 25, and a CPU (Central Processing Unit) 26. The fan connection port 21 is connected to the fan 31 and outputs the rotation pulse input from the fan 31 to the multiplexer 24. The fan connection port 22 is connected to the fan 32 and outputs the rotation pulse input from the fan 32 to the multiplexer 24. The fan connection port 23 is connected to the fan 33 and the expansion fan 34 via the fan expansion device 100, and outputs the rotation pulse input from the fan 33 and the expansion fan 34 to the multiplexer 24.
　そして、マルチプレクサ２４は、ファン３１、ファン３２、ファン３３及び増設ファン３４から入力した回転パルスのうちいずれかを選択してカウンタ２５に出力する。ＣＰＵ２６は、カウンタ２５によりカウントされる回転パルスを監視することで、ファン３１、ファン３２、ファン３３及び増設ファン３４に異常が生じたか否かを判定する。なお、ＣＰＵ２６は、マザーボード２０が有するメインのＣＰＵであってもよく、あるいは、マザーボード２０が有するサブのＣＰＵであってもよい。 Then, the multiplexer 24 selects any one of the rotation pulses input from the fan 31, the fan 32, the fan 33, and the expansion fan 34 and outputs the selected pulse to the counter 25. The CPU 26 determines whether or not an abnormality has occurred in the fan 31, the fan 32, the fan 33, and the additional fan 34 by monitoring the rotation pulse counted by the counter 25. The CPU 26 may be a main CPU included in the motherboard 20 or may be a sub CPU included in the motherboard 20.
　ファン３１、ファン３２、ファン３３及び増設ファン３４は、情報処理装置１０の外部から吸入した冷却風を電子部品に送風して冷却する。また、ファン３１は回転パルスをファン接続ポート２１に出力し、ファン３２は回転パルスをファン接続ポート２２に出力する。ファン３３及び増設ファン３４は回転パルスをファン増設装置１００に出力する。 The fan 31, the fan 32, the fan 33, and the additional fan 34 cool the air by sucking the cooling air sucked from the outside of the information processing apparatus 10 to the electronic parts. The fan 31 outputs a rotation pulse to the fan connection port 21, and the fan 32 outputs the rotation pulse to the fan connection port 22. The fan 33 and the expansion fan 34 output a rotation pulse to the fan expansion device 100.
　ファン増設装置１００は、ファン接続ポート１０１及びファン接続ポート１０２と接続ポート１０３と監視回路１０４とを有する。ファン接続ポート１０１は、ファン３３と接続し、ファン３３から入力した回転パルスを監視回路１０４に出力する。また、ファン接続ポート１０２は、増設ファン３４と接続し、増設ファン３４から入力した回転パルスを監視回路１０４に出する。接続ポート１０３は、監視回路１０４と、マザーボード２０が有するファン接続ポート２３とに接続し、監視回路１０４から入力した回転パルスを、ファン接続ポート２３を介してマザーボード２０に出力する。 The fan expansion device 100 includes a fan connection port 101, a fan connection port 102, a connection port 103, and a monitoring circuit 104. The fan connection port 101 is connected to the fan 33 and outputs a rotation pulse input from the fan 33 to the monitoring circuit 104. The fan connection port 102 is connected to the expansion fan 34 and outputs the rotation pulse input from the expansion fan 34 to the monitoring circuit 104. The connection port 103 is connected to the monitoring circuit 104 and the fan connection port 23 included in the motherboard 20, and outputs the rotation pulse input from the monitoring circuit 104 to the motherboard 20 via the fan connection port 23.
　監視回路１０４は、ファン接続ポート１０１及びファン接続ポート１０２を介してファン３３及び増設ファン３４から回転パルスを入力する。また、監視回路１０４は、ファン３３から入力した回転パルスを後述するカウンタ４０１で計測するとともに、増設ファン３４から入力した回転パルスを後述するカウンタ４０２で計測する。そして、監視回路１０４は、ファン３３及び増設ファン３４のいずれかの回転パルスを計測できない場合には、ファン３３及び増設ファン３４のいずれかが異常であることを示す信号を、接続ポート１０３を介してマザーボード２０に出力する。 The monitoring circuit 104 inputs a rotation pulse from the fan 33 and the additional fan 34 via the fan connection port 101 and the fan connection port 102. The monitoring circuit 104 measures a rotation pulse input from the fan 33 by a counter 401 described later, and measures a rotation pulse input from the expansion fan 34 by a counter 402 described later. If the monitoring circuit 104 cannot measure the rotation pulse of either the fan 33 or the expansion fan 34, a signal indicating that either the fan 33 or the expansion fan 34 is abnormal is sent via the connection port 103. Output to the motherboard 20.
［実施例１に係る監視回路１０４の構成］
　次に、図２を用いて、実施例１に係る監視回路１０４の構成を説明する。図２は、実施例１に係る監視回路１０４の構成を示すブロック図である。実施例１に係る監視回路１０４は、ファン入力切替回路２００と、ファン入力選択回路３００と、ファン異常検出回路４００と、ＡＮＤ回路５００と、ＯＲ回路６００とを有する。なお、監視回路１０４から入力される電源と、回路素子との電源の間には、電源電圧を調整するための３端子レギュレータが入る場合もある。また、パワーオンリセット回路、論理ＩＣ（Integrated　Circuit）のバイパスコンデンサが必要な事は自明であり、図２にはバイパスコンデンサを省略している。 [Configuration of Monitoring Circuit 104 According to Embodiment 1]
Next, the configuration of the monitoring circuit 104 according to the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram illustrating the configuration of the monitoring circuit 104 according to the first embodiment. The monitoring circuit 104 according to the first embodiment includes a fan input switching circuit 200, a fan input selection circuit 300, a fan abnormality detection circuit 400, an AND circuit 500, and an OR circuit 600. Note that a three-terminal regulator for adjusting the power supply voltage may be inserted between the power supply input from the monitoring circuit 104 and the power supply to the circuit element. Further, it is obvious that a power-on reset circuit and a bypass capacitor of a logic IC (Integrated Circuit) are necessary, and the bypass capacitor is omitted in FIG.
　ファン入力切替回路２００は、ファン３３及び増設ファン３４から回転パルスを入力する。そして、ファン入力切替回路２００は、ファン３３から入力した回転パルスまたは増設ファン３４から入力した回転パルスの一方を、ファン入力切替信号に応じて交互にファン入力選択回路３００とＡＮＤ回路５００とに出力する。例えば、ファン入力切替回路２００は、ファン入力切替信号が「Ｌ」の場合、ファン３３から入力した回転パルスを選択してファン入力選択回路３００とＡＮＤ回路５００とに出力する。また、ファン入力切替回路２００は、ファン入力切替信号が「Ｈ」の場合、増設ファン３４から入力した回転パルスを選択してファン入力選択回路３００とＡＮＤ回路５００とに出力する。 The fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34. The fan input switching circuit 200 alternately outputs one of the rotation pulse input from the fan 33 or the rotation pulse input from the additional fan 34 to the fan input selection circuit 300 and the AND circuit 500 in accordance with the fan input switching signal. To do. For example, when the fan input switching signal is “L”, the fan input switching circuit 200 selects the rotation pulse input from the fan 33 and outputs it to the fan input selection circuit 300 and the AND circuit 500. Further, when the fan input switching signal is “H”, the fan input switching circuit 200 selects the rotation pulse input from the expansion fan 34 and outputs it to the fan input selection circuit 300 and the AND circuit 500.
　ファン入力選択回路３００は、ファン入力切替回路２００により出力される回転パルスを入力し、後述するカウンタ３０１で該回転パルスを計測し、計測した結果をファン入力切替信号としてファン入力切替回路２００に出力する。なお、カウンタ３０１が有するビット数は、後述するカウンタ４０１及びカウンタ４０２が有するビット数よりも少ないものとする。 The fan input selection circuit 300 receives the rotation pulse output from the fan input switching circuit 200, measures the rotation pulse by a counter 301 described later, and outputs the measured result to the fan input switching circuit 200 as a fan input switching signal. To do. Note that the number of bits that the counter 301 has is smaller than the number of bits that the counter 401 and the counter 402 described later have.
　ファン異常検出回路４００は、ファン３３から回転パルスを入力してカウンタ４０１で計測するとともに、増設ファン３４から回転パルスを入力してカウンタ４０２で計測する。また、ファン異常検出回路４００は、ファン入力選択回路３００からファン入力切替信号を入力し、入力したファン入力切替信号からリセット信号を生成するリセット信号生成回路４０３を有する。 The fan abnormality detection circuit 400 receives the rotation pulse from the fan 33 and measures it with the counter 401, and also inputs the rotation pulse from the additional fan 34 and measures it with the counter 402. The fan abnormality detection circuit 400 includes a reset signal generation circuit 403 that receives a fan input switching signal from the fan input selection circuit 300 and generates a reset signal from the input fan input switching signal.
　また、ファン異常検出回路４００は、リセット信号をリセット信号生成回路４０３から入力した場合には、ファン３３及び増設ファン３４の回転パルスを計測できると判定して、カウンタ４０１及びカウンタ４０２が計測した結果をリセットする。また、ファン異常検出回路４００は、リセット信号をリセット信号生成回路４０３から入力できない場合には、ファン３３または増設ファン３４のいずれかの回転パルスを計測できないと判定する。そして、ファン異常検出回路４００は、ファン３３または増設ファン３４のいずれかが異常であることを示す信号を、接続ポート１０３を介してマザーボード２０に出力する。 Further, when the reset signal is input from the reset signal generation circuit 403, the fan abnormality detection circuit 400 determines that the rotation pulse of the fan 33 and the additional fan 34 can be measured, and the result of measurement by the counter 401 and the counter 402 To reset. In addition, when the reset signal cannot be input from the reset signal generation circuit 403, the fan abnormality detection circuit 400 determines that the rotation pulse of either the fan 33 or the additional fan 34 cannot be measured. Then, the fan abnormality detection circuit 400 outputs a signal indicating that either the fan 33 or the additional fan 34 is abnormal to the mother board 20 via the connection port 103.
　例えば、ファン異常検出回路４００は、リセット信号をリセット信号生成回路４０３から入力できず、増設ファン３４から入力した回転パルスをカウンタ４０２の上限値まで計測し続けた場合には、以下の処理を実行する。すなわち、ファン異常検出回路４００は、ファン３３が異常であることを示す低電位の信号「Ｌ」をＯＲ回路６００に出力する。 For example, when the fan abnormality detection circuit 400 cannot input the reset signal from the reset signal generation circuit 403 and continues to measure the rotation pulse input from the expansion fan 34 up to the upper limit value of the counter 402, the fan abnormality detection circuit 400 executes the following processing. To do. That is, the fan abnormality detection circuit 400 outputs a low potential signal “L” indicating that the fan 33 is abnormal to the OR circuit 600.
　また、ファン異常検出回路４００は、リセット信号をリセット信号生成回路４０３から入力できず、ファン３３から入力した回転パルスをカウンタ４０１の上限値まで計測し続けた場合には、以下の処理を実行する。すなわち、ファン異常検出回路４００は、増設ファン３４が異常であることを示す高電位の信号「Ｈ」をＯＲ回路６００に出力する。 The fan abnormality detection circuit 400 executes the following processing when the reset signal cannot be input from the reset signal generation circuit 403 and the rotation pulse input from the fan 33 is continuously measured up to the upper limit value of the counter 401. . That is, the fan abnormality detection circuit 400 outputs a high potential signal “H” indicating that the additional fan 34 is abnormal to the OR circuit 600.
　ＡＮＤ回路５００は、ファン入力切替回路２００から入力した回転パルスと、ファン異常検出回路４００から入力した信号との論理積である信号をＯＲ回路６００に出力する。例えば、ＡＮＤ回路５００は、ファン３３及び増設ファン３４が正常である場合、ファン入力切替回路２００から回転パルスを入力し、ファン異常検出回路４００から高電位の信号「Ｈ」を入力する。そして、ＡＮＤ回路５００は、回転パルスをＯＲ回路６００に出力する。 The AND circuit 500 outputs a signal that is a logical product of the rotation pulse input from the fan input switching circuit 200 and the signal input from the fan abnormality detection circuit 400 to the OR circuit 600. For example, when the fan 33 and the additional fan 34 are normal, the AND circuit 500 receives a rotation pulse from the fan input switching circuit 200 and a high potential signal “H” from the fan abnormality detection circuit 400. Then, the AND circuit 500 outputs the rotation pulse to the OR circuit 600.
　また、ＡＮＤ回路５００は、ファン３３または増設ファン３４のいずれかが故障した場合、ファン入力切替回路２００から回転パルスを入力できず、ファン異常検出回路４００から低電位の信号「Ｌ」を入力する。そして、ＡＮＤ回路５００は、低電位の信号「Ｌ」をＯＲ回路６００に出力する。 Further, the AND circuit 500 cannot input a rotation pulse from the fan input switching circuit 200 and inputs a low potential signal “L” from the fan abnormality detection circuit 400 when either the fan 33 or the expansion fan 34 fails. . Then, the AND circuit 500 outputs a low potential signal “L” to the OR circuit 600.
　ＯＲ回路６００は、ＡＮＤ回路５００から入力した信号と、ファン異常検出回路４００から入力した信号との論理和である信号を、接続ポート１０３に出力する。例えばＯＲ回路６００は、ファン３３及び増設ファン３４が正常である場合、ＡＮＤ回路５００から回転パルスを入力し、ファン異常検出回路４００から低電位の信号「Ｌ」を入力する。そして、ＯＲ回路６００は、回転パルスを接続ポート１０３に出力する。 OR circuit 600 outputs, to connection port 103, a signal that is a logical sum of the signal input from AND circuit 500 and the signal input from fan abnormality detection circuit 400. For example, when the fan 33 and the additional fan 34 are normal, the OR circuit 600 receives a rotation pulse from the AND circuit 500 and a low potential signal “L” from the fan abnormality detection circuit 400. Then, the OR circuit 600 outputs a rotation pulse to the connection port 103.
　また、ＯＲ回路６００は、ファン３３が故障した場合、ＡＮＤ回路５００から低電位の信号「Ｌ」を入力し、ファン異常検出回路４００から低電位の信号「Ｌ」を入力する。そして、ＯＲ回路６００は、低電位の信号「Ｌ」を接続ポート１０３に出力する。また、ＯＲ回路６００は、増設ファン３４が故障した場合、ＡＮＤ回路５００から低電位の信号「Ｌ」を入力し、ファン異常検出回路４００から高電位の信号「Ｈ」を入力する。そして、ＯＲ回路６００は、高電位の信号「Ｈ」を接続ポート１０３に出力する。 The OR circuit 600 receives a low potential signal “L” from the AND circuit 500 and a low potential signal “L” from the fan abnormality detection circuit 400 when the fan 33 fails. Then, the OR circuit 600 outputs a low potential signal “L” to the connection port 103. The OR circuit 600 receives a low potential signal “L” from the AND circuit 500 and a high potential signal “H” from the fan abnormality detection circuit 400 when the expansion fan 34 fails. Then, the OR circuit 600 outputs a high potential signal “H” to the connection port 103.
（ファン入力切替回路の構成）
　ファン入力切替回路２００は、ＮＯＴ回路２０１と、ＡＮＤ回路２０２及びＡＮＤ回路２０３と、ＥＸ－ＯＲ回路２０４とを有する。ＮＯＴ回路２０１は、ファン入力選択回路３００から入力したファン入力切替信号を反転させてＡＮＤ回路２０２に出力する。 (Fan input switching circuit configuration)
The fan input switching circuit 200 includes a NOT circuit 201, an AND circuit 202 and an AND circuit 203, and an EX-OR circuit 204. The NOT circuit 201 inverts the fan input switching signal input from the fan input selection circuit 300 and outputs the inverted signal to the AND circuit 202.
　ＡＮＤ回路２０２は、ファン接続ポート１０１を介してファン３３から入力した回転パルスと、ＮＯＴ回路２０１から入力した反転させたファン入力切替信号との論理積である信号をＥＸ－ＯＲ回路２０４に出力する。ＡＮＤ回路２０３は、ファン接続ポート１０２を介して増設ファン３４から入力した回転パルスと、ファン入力選択回路３００から入力したファン入力切替信号との論理積である信号をＥＸ－ＯＲ回路２０４に出力する。 The AND circuit 202 outputs a signal that is a logical product of the rotation pulse input from the fan 33 via the fan connection port 101 and the inverted fan input switching signal input from the NOT circuit 201 to the EX-OR circuit 204. . The AND circuit 203 outputs to the EX-OR circuit 204 a signal that is the logical product of the rotation pulse input from the additional fan 34 via the fan connection port 102 and the fan input switching signal input from the fan input selection circuit 300. .
　ＥＸ－ＯＲ回路２０４は、ＡＮＤ回路２０２から入力した信号とＡＮＤ回路２０３から入力した信号との排他的論理和を回転パルスとして、ファン入力選択回路３００とＡＮＤ回路５００とに出力する。 The EX-OR circuit 204 outputs the exclusive OR of the signal input from the AND circuit 202 and the signal input from the AND circuit 203 to the fan input selection circuit 300 and the AND circuit 500 as a rotation pulse.
（ファン入力選択回路の構成）
　ファン入力選択回路３００は、カウンタ３０１を有する。カウンタ３０１は、ファン入力切替回路２００から入力した回転パルスをカウントし、カウントした最上位ビットの値をファン入力切替信号として、ファン入力切替回路２００とファン異常検出回路４００とに出力する。 (Fan input selection circuit configuration)
The fan input selection circuit 300 has a counter 301. The counter 301 counts the rotation pulse input from the fan input switching circuit 200 and outputs the counted value of the most significant bit to the fan input switching circuit 200 and the fan abnormality detection circuit 400 as a fan input switching signal.
（ファン異常検出回路の構成）
　ファン異常検出回路４００は、カウンタ４０１及びカウンタ４０２と、リセット信号生成回路４０３と、ＯＲ回路４０４と、ＮＯＴ回路４０５と、ＮＯＴ回路４０６と、ＡＮＤ回路４０７と、ＡＮＤ回路４０８とを有する。 (Configuration of fan abnormality detection circuit)
The fan abnormality detection circuit 400 includes a counter 401 and a counter 402, a reset signal generation circuit 403, an OR circuit 404, a NOT circuit 405, a NOT circuit 406, an AND circuit 407, and an AND circuit 408.
　カウンタ４０１は、ファン接続ポート１０１を介してファン３３から入力した回転パルスをカウントし、カウントした最上位ビットの値をＯＲ回路４０４とＯＲ回路６００とに出力する。また、カウンタ４０１は、リセット信号生成回路４０３からリセット信号を入力した場合、カウントした値をリセットする。 The counter 401 counts the rotation pulses input from the fan 33 via the fan connection port 101, and outputs the counted value of the most significant bit to the OR circuit 404 and the OR circuit 600. Further, the counter 401 resets the counted value when a reset signal is input from the reset signal generation circuit 403.
　また、カウンタ４０２は、ファン接続ポート１０２を介して増設ファン３４から入力した回転パルスをカウントし、カウントした最上位ビットの値をＯＲ回路４０４に出力する。また、カウンタ４０２は、リセット信号生成回路４０３からリセット信号を入力した場合、カウントした値をリセットする。 Further, the counter 402 counts the rotation pulses input from the expansion fan 34 via the fan connection port 102 and outputs the counted value of the most significant bit to the OR circuit 404. The counter 402 resets the counted value when a reset signal is input from the reset signal generation circuit 403.
　このカウンタ４０１及びカウンタ４０２は、ファン入力選択回路３００が有するカウンタ３０１よりも多いビット数を持つ。これにより、ファン異常検出回路４００に接続されたファンの回転数に差がある場合、ファン入力切替信号が出力される前に、カウンタ４０１及びカウンタ４０２の最上位ビットが「Ｌ」から「Ｈ」へ切り替わることを防止する。すなわち、カウンタ４０１及びカウンタ４０２の最上位ビットは、ファン３３及び増設ファン３４が通常動作時に、「Ｈ」にならない。 The counter 401 and the counter 402 have a larger number of bits than the counter 301 included in the fan input selection circuit 300. Thereby, when there is a difference in the rotation speed of the fan connected to the fan abnormality detection circuit 400, the most significant bit of the counter 401 and the counter 402 is changed from “L” to “H” before the fan input switching signal is output. To prevent switching to. That is, the most significant bit of the counter 401 and the counter 402 does not become “H” when the fan 33 and the additional fan 34 are in normal operation.
　なお、通常、同一システム内で使用されるファンの回転数の差は２倍～３倍程度であり、倍程度のビット数であれば十分である。また、ファンの回転数の差は２倍～３倍限定されるものではなく、使用するファンに応じて変更可能である。 It should be noted that the difference in the rotation speed of fans used in the same system is usually about 2 to 3 times, and a bit number of about twice is sufficient. Further, the difference in the rotation speed of the fan is not limited to 2 to 3 times, and can be changed according to the fan to be used.
　リセット信号生成回路４０３は、ファン入力切替信号をファン入力選択回路３００から入力し、入力したファン入力切替信号からリセット信号を生成してカウンタ４０１及びカウンタ４０２に出力する。なお、リセット信号生成回路４０３の詳細については、図３を用いて後述する。 The reset signal generation circuit 403 receives the fan input switching signal from the fan input selection circuit 300, generates a reset signal from the input fan input switching signal, and outputs the reset signal to the counter 401 and the counter 402. Details of the reset signal generation circuit 403 will be described later with reference to FIG.
　ＯＲ回路４０４は、カウンタ４０１から入力した最上位ビットの値と、カウンタ４０２から入力した最上位ビットの値との論理和である信号を、ＮＯＴ回路４０５とＮＯＴ回路４０６とに出力する。 OR circuit 404 outputs a signal that is a logical sum of the value of the most significant bit input from counter 401 and the value of the most significant bit input from counter 402 to NOT circuit 405 and NOT circuit 406.
　ＮＯＴ回路４０５は、ＯＲ回路４０４から入力した信号を反転させてＡＮＤ回路５００に出力する。ＮＯＴ回路４０６は、ＯＲ回路４０４から入力した信号を反転させてＡＮＤ回路４０７とＡＮＤ回路４０８とに出力する。 NOT circuit 405 inverts the signal input from OR circuit 404 and outputs the result to AND circuit 500. The NOT circuit 406 inverts the signal input from the OR circuit 404 and outputs the inverted signal to the AND circuit 407 and the AND circuit 408.
　ＡＮＤ回路４０７は、ファン接続ポート１０１を介してファン３３から入力した回転パルスと、ＮＯＴ回路４０６から入力した信号との論理積である信号をカウンタ４０１に出力する。例えば、ＡＮＤ回路４０７は、ファン３３及び増設ファン３４が正常である場合、ＮＯＴ回路４０６から高電位の信号「Ｈ」を入力するので、ファン接続ポート１０１を介してファン３３から入力した回転パルスをカウンタ４０１に出力する。 The AND circuit 407 outputs, to the counter 401, a signal that is a logical product of the rotation pulse input from the fan 33 via the fan connection port 101 and the signal input from the NOT circuit 406. For example, since the AND circuit 407 receives a high potential signal “H” from the NOT circuit 406 when the fan 33 and the additional fan 34 are normal, the rotation pulse input from the fan 33 via the fan connection port 101 is input. Output to the counter 401.
　また、ＡＮＤ回路４０７は、ファン３３または増設ファン３４のいずれかが故障した場合、ＮＯＴ回路４０６から低電位の信号「Ｌ」を入力するので、回転パルスをカウンタ４０１に出力できない。すなわち、カウンタ４０１への入力がマスクされる。 The AND circuit 407 inputs a low potential signal “L” from the NOT circuit 406 when either the fan 33 or the expansion fan 34 fails, and therefore cannot output a rotation pulse to the counter 401. That is, the input to the counter 401 is masked.
　ＡＮＤ回路４０８は、ファン接続ポート１０２を介して増設ファン３４から入力した回転パルスと、ＮＯＴ回路４０６から入力した信号との論理積である信号をカウンタ４０２に出力する。例えば、ＡＮＤ回路４０８は、ファン３３及び増設ファン３４が正常である場合、ＮＯＴ回路４０６から高電位の信号「Ｈ」を入力するので、ファン接続ポート１０２を介して増設ファン３４から入力した回転パルスをカウンタ４０２に出力する。 The AND circuit 408 outputs a signal, which is a logical product of the rotation pulse input from the additional fan 34 via the fan connection port 102 and the signal input from the NOT circuit 406, to the counter 402. For example, since the AND circuit 408 inputs a high potential signal “H” from the NOT circuit 406 when the fan 33 and the expansion fan 34 are normal, the rotation pulse input from the expansion fan 34 via the fan connection port 102. Is output to the counter 402.
　また、ＡＮＤ回路４０８は、ファン３３または増設ファン３４のいずれかが故障した場合、ＮＯＴ回路４０６から低電位の信号「Ｌ」を入力するので、回転パルスをカウンタ４０２に出力できない。すなわち、カウンタ４０２への入力がマスクされる。 The AND circuit 408 inputs a low-potential signal “L” from the NOT circuit 406 when either the fan 33 or the expansion fan 34 fails, and therefore cannot output a rotation pulse to the counter 402. That is, the input to the counter 402 is masked.
［リセット信号生成回路］
　次に、図３を用いて、リセット信号生成回路４０３の構成について説明する。図３は、リセット信号生成回路の一例を示す図である。図３に示すように、リセット信号生成回路４０３は、抵抗４０３ａと、コンデンサ４０３ｂと、ＥＸ－ＯＲ回路４０３ｃとを有する。 [Reset signal generation circuit]
Next, the configuration of the reset signal generation circuit 403 will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of the reset signal generation circuit. As shown in FIG. 3, the reset signal generation circuit 403 includes a resistor 403a, a capacitor 403b, and an EX-OR circuit 403c.
　抵抗４０３ａとコンデンサ４０３ｂとは、積分回路であり、ファン入力切替信号の入力電圧の波形の時間積分に等しい波形の電圧をＥＸ－ＯＲ回路４０３ｃに出力する。言い換えると、抵抗４０３ａ及びコンデンサ４０３ｂは、ファン入力切替信号に時定数を掛けた信号をＥＸ－ＯＲ回路４０３ｃに出力する。 The resistor 403a and the capacitor 403b are integrating circuits, and output a voltage having a waveform equal to the time integration of the waveform of the input voltage of the fan input switching signal to the EX-OR circuit 403c. In other words, the resistor 403a and the capacitor 403b output a signal obtained by multiplying the fan input switching signal by the time constant to the EX-OR circuit 403c.
　ＥＸ－ＯＲ回路４０３ｃは、ファン入力切替信号と、ファン入力切替信号に時定数を掛けた信号とを入力し、排他的論理和を取ることにより生成されるリセット信号を出力する。 The EX-OR circuit 403c inputs a fan input switching signal and a signal obtained by multiplying the fan input switching signal by a time constant, and outputs a reset signal generated by taking an exclusive OR.
［リセット信号生成動作］
　次に、図４を用いて、リセット信号の生成動作について説明する。図４は、リセット信号の生成動作の一例を示す図である。リセット信号は、ファン入力切替信号とファン入力切替信号に時定数を掛けた信号との排他的論理和を取ることにより生成される。このため、図４に示すように、ファン入力切替信号の波形の立ち上がりに比べて、ファン入力切替信号に時定数を掛けた信号の波形の立ち上がりは、遅延する。そして、時定数により遅延した立ち上がり波形が論理回路の閾地を超えるまでの時間が、リセット信号のパルス幅となる。 [Reset signal generation operation]
Next, the reset signal generation operation will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of a reset signal generation operation. The reset signal is generated by taking an exclusive OR of a fan input switching signal and a signal obtained by multiplying the fan input switching signal by a time constant. For this reason, as shown in FIG. 4, the rise of the waveform of the signal obtained by multiplying the fan input switching signal by the time constant is delayed as compared to the rise of the waveform of the fan input switching signal. The time until the rising waveform delayed by the time constant exceeds the threshold value of the logic circuit is the pulse width of the reset signal.
　具体的には、波形立ち上がり時における、時定数回路による電圧変化は、一般的に以下の式「Ｖ（ｔ）＝Ｖ（１－ｅ－ｔ／ＲＣ）」で表される。これを「ｔ」について解くと、「ｔ＝－ＲＣ・ｌｏｇｅ（１－Ｖ（ｔ）／Ｖ）」となる。ここで、「Ｖ（ｔ）」を閾値、「Ｖ」を「高電位の電圧とすると、「ｔ」は低電位の電圧から閾地へ達する時間となる。 Specifically, the voltage change caused by the time constant circuit at the rising edge of the waveform is generally represented by the following expression “V (t) = V (1−e −t / RC )”. Solving this for “t” yields “t = −RC · log e (1−V (t) / V)”. Here, when “V (t)” is a threshold value and “V” is a “high potential voltage”, “t” is a time to reach the threshold value from the low potential voltage.
［実施例１に係るファン増設装置による処理動作］
　次に図５及び図６を用いてファン増設装置１００による処理動作を説明する。ここでは、図５を用いて、正常時のファン増設装置１００による処理動作を説明し、図６を用いて、増設ファン３４が故障時のファン増設装置１００による処理動作を説明する。 [Processing Operation by Fan Expansion Device According to Embodiment 1]
Next, the processing operation by the fan expansion device 100 will be described with reference to FIGS. Here, the processing operation performed by the fan expansion device 100 in a normal state will be described with reference to FIG. 5, and the processing operation performed by the fan expansion device 100 when the expansion fan 34 has failed will be described with reference to FIG.
（正常時のファン増設装置による処理動作）
　図５は、ファンが正常動作時のタイミングチャートである。図５に示すように、ファン増設装置１００において、ファン入力切替回路２００は、ファン３３及び増設ファン３４から回転パルスを入力する。ファン入力切替回路２００において、期間ｔ１では、ＡＮＤ回路２０２がファン３３から入力した回転パルスをＥＸ－ＯＲ回路２０４に出力する。そして、ＥＸ－ＯＲ回路２０４は、ＡＮＤ回路２０２から入力した回転パルスをファン入力選択回路３００に出力する。 (Processing by fan expansion device in normal operation)
FIG. 5 is a timing chart when the fan is operating normally. As shown in FIG. 5, in the fan expansion device 100, the fan input switching circuit 200 inputs rotation pulses from the fan 33 and the expansion fan 34. In the fan input switching circuit 200, the AND circuit 202 outputs the rotation pulse input from the fan 33 to the EX-OR circuit 204 in the period t1. Then, the EX-OR circuit 204 outputs the rotation pulse input from the AND circuit 202 to the fan input selection circuit 300.
　また、ファン入力選択回路３００において、カウンタ３０１は、ファン入力切替回路２００から入力した回転パルスをカウントし、カウンタ３０１の最上位ビットを出力する。そして、ｔ２では、カウンタ３０１の最上位ビットが「Ｌ」から「Ｈ」に切替わり、ファン入力選択回路３００は、ファン入力切替信号「Ｈ」を出力する。 In the fan input selection circuit 300, the counter 301 counts the rotation pulses input from the fan input switching circuit 200 and outputs the most significant bit of the counter 301. At t2, the most significant bit of the counter 301 is switched from “L” to “H”, and the fan input selection circuit 300 outputs a fan input switching signal “H”.
　この結果、ファン入力切替回路２００において、期間ｔ３では、ＡＮＤ回路２０３が回転パルスをＥＸ－ＯＲ回路２０４に出力する。すなわち、ファン入力切替回路２００は、ファン３３から入力した回転パルスから増設ファン３４から入力した回転パルスに出力する回転パルスを切り替える。また、ＥＸ－ＯＲ回路２０４は、ＡＮＤ回路２０３から入力した回転パルスをファン入力選択回路３００に出力する。 As a result, in the fan input switching circuit 200, the AND circuit 203 outputs a rotation pulse to the EX-OR circuit 204 in the period t3. That is, the fan input switching circuit 200 switches the rotation pulse output from the rotation pulse input from the fan 33 to the rotation pulse input from the expansion fan 34. The EX-OR circuit 204 outputs the rotation pulse input from the AND circuit 203 to the fan input selection circuit 300.
　また、ファン異常検出回路４００は、カウンタ３０１の最上位の切替えタイミングであるｔ２でリセット信号を生成し、カウンタ４０１及びカウンタ４０２をリセットする。これにより、ファン異常検出回路４００は、カウンタ４０１及びカウンタ４０２の最上位ビットを「Ｌ」から「Ｈ」に切替えない。 Further, the fan abnormality detection circuit 400 generates a reset signal at t2 which is the highest switching timing of the counter 301, and resets the counter 401 and the counter 402. Thereby, the fan abnormality detection circuit 400 does not switch the most significant bit of the counter 401 and the counter 402 from “L” to “H”.
（増設ファン３４が故障時のファン増設装置による処理動作）
　図６は、増設ファン３４が故障時のタイミングチャートである。図６に示すように、ファン増設装置１００において、ファン入力切替回路２００は、ファン３３及び増設ファン３４から回転パルスを入力する。ファン入力切替回路２００において、期間ｔ１では、ＡＮＤ回路２０２がファン３３から入力した回転パルスをＥＸ－ＯＲ回路２０４に出力する。また、ＥＸ－ＯＲ回路２０４は、ＡＮＤ回路２０３から入力した回転パルスをファン入力選択回路３００に出力する。 (Processing by the fan expansion device when the expansion fan 34 fails)
FIG. 6 is a timing chart when the expansion fan 34 fails. As shown in FIG. 6, in the fan expansion device 100, the fan input switching circuit 200 inputs rotation pulses from the fan 33 and the expansion fan 34. In the fan input switching circuit 200, the AND circuit 202 outputs the rotation pulse input from the fan 33 to the EX-OR circuit 204 in the period t1. The EX-OR circuit 204 outputs the rotation pulse input from the AND circuit 203 to the fan input selection circuit 300.
　また、ファン入力選択回路３００において、カウンタ３０１は、ファン入力切替回路２００から入力した回転パルスをカウントし、カウンタ３０１の最上位ビットを出力する。そして、ｔ２では、カウンタ３０１の最上位ビットが「Ｌ」から「Ｈ」に切替わり、ファン入力選択回路３００は、ファン入力切替信号「Ｈ」を出力する。 In the fan input selection circuit 300, the counter 301 counts the rotation pulses input from the fan input switching circuit 200 and outputs the most significant bit of the counter 301. At t2, the most significant bit of the counter 301 is switched from “L” to “H”, and the fan input selection circuit 300 outputs a fan input switching signal “H”.
　この結果、ファン入力切替回路２００において、期間ｔ３では、ＡＮＤ回路２０３が回転パルスを出力する。すなわち、ファン入力切替回路２００は、ファン３３から入力した回転パルスから増設ファン３４から入力した回転パルスに出力する回転パルスを切り替える。なお、ここでは、回転パルスを切替えた後、増設ファン３４が故障する例を示す。 As a result, in the fan input switching circuit 200, the AND circuit 203 outputs a rotation pulse during the period t3. That is, the fan input switching circuit 200 switches the rotation pulse output from the rotation pulse input from the fan 33 to the rotation pulse input from the expansion fan 34. Here, an example in which the expansion fan 34 fails after switching the rotation pulse is shown.
　この結果、ファン入力切替回路２００は、故障した増設ファン３４から回転パルスを入力できず、回転パルスを出力できない。また、ファン入力選択回路３００は、ファン入力切替回路２００から回転パルスを入力できないので、カウンタ３０１は、動作を停止する。このため、ファン入力選択回路３００は、ファン入力切替信号を生成できない。すなわち、ファン入力切替回路２００は、故障した増設ファン３４から正常なファン３３へ回転パルスの入力を切替ることができない。このため、ファン増設装置１００は、回転パルスを出力しなくなる。 As a result, the fan input switching circuit 200 cannot input the rotation pulse from the failed expansion fan 34 and cannot output the rotation pulse. Further, since the fan input selection circuit 300 cannot input a rotation pulse from the fan input switching circuit 200, the counter 301 stops its operation. For this reason, the fan input selection circuit 300 cannot generate a fan input switching signal. That is, the fan input switching circuit 200 cannot switch the rotation pulse input from the failed additional fan 34 to the normal fan 33. For this reason, the fan expansion device 100 does not output a rotation pulse.
　また、ｔ２以後、ファン異常検出回路４００は、リセット信号を生成できない。このため、カウンタ４０１は、ファン３３から入力した回転パルスをカウントし続ける。そして、ファン異常検出回路４００は、カウンタ４０１の最上位ビットが「Ｈ」になった時点で、カウンタ４０１、カウンタ４０２の入力をマスクし、カウンタ４０１の最上位ビットが「Ｈ」、カウンタ４０２の最上位ビットが「Ｌ」の状態を維持する。 Also, after t2, the fan abnormality detection circuit 400 cannot generate a reset signal. For this reason, the counter 401 continues to count the rotation pulses input from the fan 33. The fan abnormality detection circuit 400 masks the inputs of the counter 401 and the counter 402 when the most significant bit of the counter 401 becomes “H”, and the most significant bit of the counter 401 is “H”. The state in which the most significant bit is “L” is maintained.
　また、カウンタ４０１及びカウンタ４０２の最上位ビットの論理和であるファン異状信号は、ＥＸ－ＯＲ回路２０４が出力する回転パルスをマスクする。この時点では、故障した増設ファン３４と接続するカウンタ４０２の最上位ビットは「Ｌ」であり、故障していないファン３３と接続するカウンタ４０１の最上位ビットは「Ｈ」となる。また、ＯＲ回路６００は、カウンタ４０１の最上位ビット「Ｈ」とマスクされた回転パルスとの論理和を合成することで、故障したファンに応じて出力の状態を固定する。 Further, the fan abnormality signal that is the logical sum of the most significant bits of the counter 401 and the counter 402 masks the rotation pulse output from the EX-OR circuit 204. At this time, the most significant bit of the counter 402 connected to the failed additional fan 34 is “L”, and the most significant bit of the counter 401 connected to the non-failed fan 33 is “H”. Further, the OR circuit 600 synthesizes the logical sum of the most significant bit “H” of the counter 401 and the masked rotation pulse, thereby fixing the output state according to the failed fan.
　例えば、ＯＲ回路６００の出力が「Ｌ」である場合は、ファン３３の故障を示し、ＯＲ回路６００の出力が「Ｈ」である場合は、増設ファン３４の故障を示す。このようにして、情報処理装置１０の利用者は、ファン増設装置１００と接続するいずれかのファンに故障が生じたことを検出できる。 For example, when the output of the OR circuit 600 is “L”, it indicates a failure of the fan 33, and when the output of the OR circuit 600 is “H”, it indicates a failure of the expansion fan 34. In this way, the user of the information processing apparatus 10 can detect that a failure has occurred in any of the fans connected to the fan expansion device 100.
［実施例１に係るファン増設装置による処理手順］
　次に図７から図９を用いて、実施例１に係るファン増設装置１００による処理手順を説明する。ここでは、図７を用いて正常時のファン増設装置１００による処理手順を説明し、図８を用いてファン３３故障時のファン増設装置１００による処理手順を説明し、図９を用いて増設ファン３４故障時のファン増設装置１００による処理手順を説明する。 [Processing procedure by fan expansion device according to embodiment 1]
Next, a processing procedure performed by the fan expansion device 100 according to the first embodiment will be described with reference to FIGS. 7 to 9. Here, the processing procedure by the fan expansion device 100 at normal time will be described with reference to FIG. 7, the processing procedure by the fan expansion device 100 at the time of failure of the fan 33 will be described with reference to FIG. 8, and the expansion fan will be described with reference to FIG. A processing procedure performed by the fan expansion device 100 at the time of 34 failure will be described.
（正常時のファン増設装置による処理動作）
　図７は、正常時のファン増設装置１００による処理手順を示すフローチャートである。図７に示すように、ファン入力切替回路２００は、ファン３３、増設ファン３４から回転パルスを入力する（ステップＳ１０１）。また、ファン異常検出回路４００は、ファン３３、増設ファン３４から回転パルスを入力する（ステップＳ１０２）。 (Processing by fan expansion device in normal operation)
FIG. 7 is a flowchart showing a processing procedure performed by the fan expansion device 100 in a normal state. As shown in FIG. 7, the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34 (step S101). Further, the fan abnormality detection circuit 400 receives a rotation pulse from the fan 33 and the additional fan 34 (step S102).
　ファン入力選択回路３００は、カウンタ３０１の最上位ビットをファン入力切替信号として出力する（ステップＳ１０３）。そして、ファン入力切替回路２００は、ファン入力選択回路３００から入力切替信号を受信し（ステップＳ１０４）、ファン３３の回転パルスを出力する（ステップＳ１０５）。 The fan input selection circuit 300 outputs the most significant bit of the counter 301 as a fan input switching signal (step S103). The fan input switching circuit 200 receives the input switching signal from the fan input selection circuit 300 (step S104), and outputs a rotation pulse of the fan 33 (step S105).
　また、ファン異常検出回路４００は、ファン入力選択回路３００が出力した入力切替信号からリセット信号を生成して、カウンタ４０１及びカウンタ４０２をリセットする（ステップＳ１０６）。そして、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」を故障ファン信号「Ｌ」としてＯＲ回路６００に出力する（ステップＳ１０７）。また、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」とカウンタ４０２の最上位ビット「Ｌ」の論理和を反転させた信号をファン異常信号「Ｈ」としてＡＮＤ回路５００に出力する（ステップＳ１０８）。また、ファン異常検出回路４００は、ファン３３、増設ファン３４から入力した回転パルスをカウントする（ステップＳ１０９）。 The fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S106). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal “L” (step S107). The fan abnormality detection circuit 400 outputs a signal obtained by inverting the logical sum of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 to the AND circuit 500 as a fan abnormality signal “H”. (Step S108). The fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S109).
　ファン入力選択回路３００は、ファン３３の回転パルスをカウントし（ステップＳ１１０）、カウンタ３０１の最上位ビットをファン入力切替信号として出力する（ステップＳ１１１）。そして、ファン入力切替回路２００は、ファン入力選択回路３００からファン入力切替信号を受信し（ステップＳ１１２）、増設ファン３４の回転パルスを出力する（ステップＳ１１３）。 The fan input selection circuit 300 counts the rotation pulses of the fan 33 (step S110), and outputs the most significant bit of the counter 301 as a fan input switching signal (step S111). The fan input switching circuit 200 receives the fan input switching signal from the fan input selection circuit 300 (step S112), and outputs a rotation pulse of the expansion fan 34 (step S113).
　また、ファン異常検出回路４００は、ファン入力選択回路３００が出力した入力切替信号からリセット信号を生成して、カウンタ４０１及びカウンタ４０２をリセットする（ステップＳ１１４）。そして、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」を故障ファン信号としてＯＲ回路６００に出力する（ステップＳ１１５）。また、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」とカウンタ４０２の最上位ビット「Ｌ」の論理和「Ｌ」を反転させた信号をファン異常信号「Ｈ」としてＡＮＤ回路５００に出力する（ステップＳ１１６）。また、ファン異常検出回路４００は、ファン３３、増設ファン３４から入力した回転パルスをカウントする（ステップＳ１１７）。 The fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S114). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal (step S115). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “L” of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 as a fan abnormality signal “H”, and the AND circuit 500. (Step S116). Further, the fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S117).
　ファン入力選択回路３００は、増設ファン３４の回転パルスをカウントし（ステップＳ１１８）、カウンタ３０１の最上位ビットをファン入力切替信号として出力する（ステップＳ１１９）。なお、ファン増設装置１００は、ステップＳ１１９の終了後、ファン３３及び増設ファン３４が正常であれば、ステップＳ１０１からステップＳ１１９までの処理を繰り返し実行する。 The fan input selection circuit 300 counts the rotation pulses of the expansion fan 34 (step S118), and outputs the most significant bit of the counter 301 as a fan input switching signal (step S119). If the fan 33 and the expansion fan 34 are normal after the end of step S119, the fan expansion device 100 repeatedly executes the processes from step S101 to step S119.
（ファン３３故障時のファン増設装置による処理動作）
　図８は、ファン３３故障時のファン増設装置１００による処理手順を示すフローチャートである。図８に示すように、ファン入力切替回路２００は、ファン３３、増設ファン３４から回転パルスを入力する（ステップＳ２０１）。また、ファン異常検出回路４００は、ファン３３、増設ファン３４から回転パルスを入力する（ステップＳ２０２）。 (Processing by fan expansion device when fan 33 fails)
FIG. 8 is a flowchart showing a processing procedure performed by the fan expansion device 100 when the fan 33 fails. As shown in FIG. 8, the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34 (step S201). Further, the fan abnormality detection circuit 400 receives a rotation pulse from the fan 33 and the additional fan 34 (step S202).
　ファン入力選択回路３００は、カウンタ３０１の最上位ビットをファン入力切替信号として出力する（ステップＳ２０３）。そして、ファン入力切替回路２００は、ファン入力選択回路３００から入力切替信号を受信し（ステップＳ２０４）、ファン３３の回転パルスを出力する（ステップＳ２０５）。ここで、ファン入力選択回路３００は、ファン３３の回転パルスをカウントできないと判定する（ステップＳ２０６）。 The fan input selection circuit 300 outputs the most significant bit of the counter 301 as a fan input switching signal (step S203). The fan input switching circuit 200 receives the input switching signal from the fan input selection circuit 300 (step S204), and outputs a rotation pulse of the fan 33 (step S205). Here, the fan input selection circuit 300 determines that the rotation pulses of the fan 33 cannot be counted (step S206).
　また、ファン異常検出回路４００は、ファン入力選択回路３００が出力した入力切替信号からリセット信号を生成して、カウンタ４０１及びカウンタ４０２をリセットする（ステップＳ２０７）。そして、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」を故障ファン信号としてＯＲ回路６００に出力する（ステップＳ２０８）。また、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」とカウンタ４０２の最上位ビット「Ｌ」の論理和「Ｌ」を反転させた信号をファン異常信号「Ｈ」としてＡＮＤ回路５００に出力する（ステップＳ２０９）。 The fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S207). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal (step S208). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “L” of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 as a fan abnormality signal “H”, and the AND circuit 500. (Step S209).
　ファン異常検出回路４００は、ファン３３、増設ファン３４から入力した回転パルスをカウントする（ステップＳ２１０）。そして、ファン異常検出回路４００は、カウンタ４０２の最上位ビットが「Ｈ」であるか否かを判定する（ステップＳ２１１）。ここで、ファン異常検出回路４００は、カウンタ４０２の最上位ビットが「Ｈ」ではないと判定した場合（ステップＳ２１１、Ｎｏ）、ステップＳ２０８に移行する。 The fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S210). Then, the fan abnormality detection circuit 400 determines whether or not the most significant bit of the counter 402 is “H” (step S211). If the fan abnormality detection circuit 400 determines that the most significant bit of the counter 402 is not “H” (step S211, No), the process proceeds to step S208.
　ファン異常検出回路４００は、カウンタ４０２の最上位ビットが「Ｈ」であると判定した場合（ステップＳ２１１、Ｙｅｓ）、カウンタ４０１の最上位ビット「Ｌ」を故障ファン信号としてＯＲ回路６００に出力する（ステップＳ２１２）。また、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」とカウンタ４０２の最上位ビット「Ｈ」の論理和「Ｈ」を反転させた信号をファン異常信号「Ｌ」としてＡＮＤ回路５００に出力する（ステップＳ２１３）。 If the fan abnormality detection circuit 400 determines that the most significant bit of the counter 402 is “H” (Yes in step S211), the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal. (Step S212). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “H” of the most significant bit “L” of the counter 401 and the most significant bit “H” of the counter 402 as the fan abnormality signal “L”. (Step S213).
　また、ファン異常検出回路４００は、ファン３３及び増設ファン３４から入力する回転パルスをファン異常信号「Ｌ」によりマスクする（ステップＳ２１４）。これによって、故障したファン３３が接続されたカウンタ４０１の最上位ビットは「Ｌ」であり、故障していない増設ファン３４が接続されたカウンタ４０２の最上位ビットは「Ｈ」となる。 Further, the fan abnormality detection circuit 400 masks the rotation pulse input from the fan 33 and the additional fan 34 with the fan abnormality signal “L” (step S214). As a result, the most significant bit of the counter 401 to which the failed fan 33 is connected is “L”, and the most significant bit of the counter 402 to which the non-failed additional fan 34 is connected is “H”.
（増設ファン３４故障時のファン増設装置による処理動作）
　図９は、増設ファン３４故障時のファン増設装置１００による処理手順を示すフローチャートである。図９に示すように、ファン入力切替回路２００は、ファン３３、増設ファン３４から回転パルスを入力する（ステップＳ３０１）。また、ファン異常検出回路４００は、ファン３３、増設ファン３４から回転パルスを入力する（ステップＳ３０２）。 (Processing by fan expansion device when expansion fan 34 fails)
FIG. 9 is a flowchart showing a processing procedure performed by the fan expansion device 100 when the expansion fan 34 fails. As shown in FIG. 9, the fan input switching circuit 200 inputs a rotation pulse from the fan 33 and the additional fan 34 (step S301). Further, the fan abnormality detection circuit 400 receives a rotation pulse from the fan 33 and the additional fan 34 (step S302).
　ファン入力選択回路３００は、カウンタ３０１の最上位ビットをファン入力切替信号として出力する（ステップＳ３０３）。そして、ファン入力切替回路２００は、ファン入力選択回路３００から入力切替信号を受信し（ステップＳ３０４）、増設ファン３４の回転パルスを出力する（ステップＳ３０５）。ここで、ファン入力選択回路３００は、増設ファン３４の回転パルスをカウントできないと判定する（ステップＳ３０６）。 The fan input selection circuit 300 outputs the most significant bit of the counter 301 as a fan input switching signal (step S303). The fan input switching circuit 200 receives the input switching signal from the fan input selection circuit 300 (step S304), and outputs a rotation pulse of the expansion fan 34 (step S305). Here, the fan input selection circuit 300 determines that the rotation pulses of the expansion fan 34 cannot be counted (step S306).
　また、ファン異常検出回路４００は、ファン入力選択回路３００が出力した入力切替信号からリセット信号を生成して、カウンタ４０１及びカウンタ４０２をリセットする（ステップＳ３０７）。そして、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」を故障ファン信号としてＯＲ回路６００に出力する（ステップＳ３０８）。また、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｌ」とカウンタ４０２の最上位ビット「Ｌ」の論理和「Ｌ」を反転させた信号をファン異常信号「Ｈ」としてＡＮＤ回路５００に出力する（ステップＳ３０９）。 The fan abnormality detection circuit 400 generates a reset signal from the input switching signal output from the fan input selection circuit 300, and resets the counter 401 and the counter 402 (step S307). Then, the fan abnormality detection circuit 400 outputs the most significant bit “L” of the counter 401 to the OR circuit 600 as a failure fan signal (step S308). Further, the fan abnormality detection circuit 400 uses the signal obtained by inverting the logical sum “L” of the most significant bit “L” of the counter 401 and the most significant bit “L” of the counter 402 as a fan abnormality signal “H”, and the AND circuit 500. (Step S309).
　ファン異常検出回路４００は、ファン３３、増設ファン３４から入力した回転パルスをカウントする（ステップＳ３１０）。そして、ファン異常検出回路４００は、カウンタ４０１の最上位ビットが「Ｈ」であるか否かを判定する（ステップＳ３１１）。ここで、ファン異常検出回路４００は、カウンタ４０１の最上位ビットが「Ｈ」ではないと判定した場合（ステップＳ３１１、Ｎｏ）、ステップＳ３０８に移行する。 The fan abnormality detection circuit 400 counts the rotation pulses input from the fan 33 and the additional fan 34 (step S310). Then, the fan abnormality detection circuit 400 determines whether or not the most significant bit of the counter 401 is “H” (step S311). If the fan abnormality detection circuit 400 determines that the most significant bit of the counter 401 is not “H” (step S311, No), the process proceeds to step S308.
　ファン異常検出回路４００は、カウンタ４０１の最上位ビットが「Ｈ」であると判定した場合（ステップＳ３１１、Ｙｅｓ）、カウンタ４０２の最上位ビット「Ｈ」を故障ファン信号としてＯＲ回路６００に出力する（ステップＳ３１２）。また、ファン異常検出回路４００は、カウンタ４０１の最上位ビット「Ｈ」とカウンタ４０２の最上位ビット「Ｌ」の論理和「Ｈ」を反転させた信号をファン異常信号「Ｌ」としてＡＮＤ回路５００に出力する（ステップＳ３１３）。 If the fan abnormality detection circuit 400 determines that the most significant bit of the counter 401 is “H” (Yes in step S311), the fan abnormality detection circuit 400 outputs the most significant bit “H” of the counter 402 to the OR circuit 600 as a failure fan signal. (Step S312). Further, the fan abnormality detection circuit 400 uses the AND circuit 500 as a fan abnormality signal “L” obtained by inverting the logical sum “H” of the most significant bit “H” of the counter 401 and the most significant bit “L” of the counter 402. (Step S313).
　また、ファン異常検出回路４００は、ファン３３及び増設ファン３４から入力する回転パルスをファン異常信号「Ｌ」によりマスクする（ステップＳ３１４）。これによって、故障していないファン３３が接続されたカウンタ４０１の最上位ビットは「Ｈ」であり、故障した増設ファン３４が接続されたカウンタ４０２の最上位ビットは「Ｌ」となる。 Further, the fan abnormality detection circuit 400 masks the rotation pulse input from the fan 33 and the additional fan 34 with the fan abnormality signal “L” (step S314). As a result, the most significant bit of the counter 401 to which the non-failed fan 33 is connected is “H”, and the most significant bit of the counter 402 to which the failed additional fan 34 is connected is “L”.
［実施例１の効果］
　上述してきたように、ファン増設装置１００は、予備のファン接続ポートが無いシステムへファンを増設した場合、増設したファンに電源を供給するだけでなく、増設したファンの回転を監視できる。 [Effect of Example 1]
As described above, when a fan is added to a system that does not have a spare fan connection port, the fan expansion device 100 can not only supply power to the added fan but also monitor the rotation of the added fan.
　また、これにより、ファン増設装置１００は、増設したファンの故障を検出した場合、システム管理者へ「ファン故障アラーム」を通知することができる。これにより、システム管理者は、ファン故障後に確実に故障したファンの交換が可能となり、システム全体を安定に稼働できる。 This also allows the fan expansion device 100 to notify the system administrator of a “fan failure alarm” when detecting a failure of the added fan. As a result, the system administrator can reliably replace the failed fan after the fan failure, and can stably operate the entire system.
　また、ファン増設装置１００によれば、ファン増設のためにマザーボードなどの設計を変更しなくてもよい。例えば、ファン増設装置１００において、消費電力が大きい新ＣＰＵや新ＨＤＤ等のサポートが必要となった場合、設計者は、既存のシステムを使用可能である。このため、開発コスト、期間を節約できる。さらに、早期に新ＣＰＵや新ＨＤＤ等を顧客へ供給することができる。 Further, according to the fan expansion device 100, it is not necessary to change the design of the motherboard or the like for the fan expansion. For example, in the fan expansion device 100, when it is necessary to support a new CPU or a new HDD with high power consumption, the designer can use an existing system. This saves development costs and time. Furthermore, new CPUs, new HDDs and the like can be supplied to customers at an early stage.
　なお、監視回路１０４は、小型に実現することが可能であり、ファン３３及び増設ファン３４と、ファンの回転パルスを検出する回路を含むマザーボード２０との間を接続する、ケーブルの途中に実装してもよい。また、監視回路１０４は、このケーブルと一体型としてもよい。また、監視回路１０４は、一部品として情報処理装置の筺体内に設置してもよい。また、監視回路１０４は、ファンの回転パルスを検出する回路を含むマザーボード２０のファン接続ポートへプラグインする形態で実現されてもよい。 Note that the monitoring circuit 104 can be realized in a small size, and is mounted in the middle of the cable connecting the fan 33 and the additional fan 34 and the motherboard 20 including the circuit for detecting the rotation pulse of the fan. May be. The monitoring circuit 104 may be integrated with this cable. Further, the monitoring circuit 104 may be installed in the housing of the information processing apparatus as one component. Further, the monitoring circuit 104 may be realized by plugging into a fan connection port of the motherboard 20 including a circuit for detecting a rotation pulse of the fan.
　なお、本実施例において説明した各処理のうち自動的に行われるものとして説明した処理の全部または一部を手動的に行うこともできる。あるいは、手動的に行われるものとして説明した処理の全部又は一部を公知の方法で自動的に行うこともできる。この他、上記文章中や図面中で示した処理手順、制御手順、具体的名称については、特記する場合を除いて任意に変更することができる。 It should be noted that all or part of the processes described as being automatically performed among the processes described in the present embodiment may be performed manually. Alternatively, all or part of the processing described as being performed manually can be automatically performed by a known method. In addition, the processing procedures, control procedures, and specific names shown in the text and drawings can be arbitrarily changed unless otherwise specified.
　１０　情報処理装置
　１１　電源
　１２　Ｉ／Ｏ装置
　２０　マザーボード
　２１～２３、１０１、１０２　ファン接続ポート
　２４　マルチプレクサ
　２５、３０１、４０１、４０２　カウンタ
　２６　ＣＰＵ
　３１～３３　ファン
　３４　増設ファン
　１００　ファン増設装置
　１０３　接続ポート
　１０４　監視回路
　２００　ファン入力切替回路
　３００　ファン入力選択回路
　４００　ファン異常検出回路
　４０３　リセット信号生成回路 DESCRIPTION OF SYMBOLS 10 Information processing apparatus 11 Power supply 12 I / O apparatus 20 Mother board 21-23, 101, 102 Fan connection port 24 Multiplexer 25, 301, 401, 402 Counter 26 CPU
31 to 33 Fan 34 Expansion fan 100 Fan expansion device 103 Connection port 104 Monitoring circuit 200 Fan input switching circuit 300 Fan input selection circuit 400 Fan abnormality detection circuit 403 Reset signal generation circuit

Claims (8)

  1. 　第１のファン及び第２のファンと接続された第１の接続部と、
    　電子機器と接続された第２の接続部と、
    　前記第１のファン及び前記第２のファンの動作を監視する監視回路と、を有し、
    　前記監視回路は、
    　前記第１の接続部を介して前記第１のファン及び前記第２のファンから回転パルスを受信する受信部と、
    　前記第１のファンから受信した回転パルスを計測する第１のカウンタと、
    　前記第２のファンから受信した回転パルスを計測する第２のカウンタと、
    　前記第１のファン及び前記第２のファンから回転パルスを受信し、前記第１のファンから受信した回転パルスまたは前記第２のファンから受信した回転パルスのいずれか一方を切替信号に応じて交互に出力する切替回路と、
    　前記切替回路から出力された前記第１のファンの回転パルス又は前記第２のファンの回転パルスのうち、いずれかの回転パルスを計測できない場合には、前記第１のファンまたは前記第２のファンのいずれかが異常であることを示す信号を前記第２の接続部を介して前記電子機器に出力する出力部と、
    　を有することを特徴とする接続装置。     A first connection connected to the first fan and the second fan;
    A second connection connected to the electronic device;
    A monitoring circuit that monitors the operation of the first fan and the second fan,
    The monitoring circuit is
    A receiver for receiving rotation pulses from the first fan and the second fan via the first connection;
    A first counter that measures rotational pulses received from the first fan;
    A second counter for measuring rotation pulses received from the second fan;
    A rotation pulse is received from the first fan and the second fan, and either the rotation pulse received from the first fan or the rotation pulse received from the second fan is alternately changed according to a switching signal. A switching circuit that outputs to
    If any one of the rotation pulses of the first fan and the rotation pulses of the second fan output from the switching circuit cannot be measured, the first fan or the second fan An output unit that outputs a signal indicating that any of the above is abnormal to the electronic device via the second connection unit;
    A connection device comprising:
  2. 　前記監視回路は、
    　前記切替回路により出力される回転パルスを受信し、前記第１のカウンタ及び前記第２のカウンタよりもビット数の少ない第３のカウンタで該回転パルスを計測し、計測した結果を前記切替信号として前記切替回路に出力する選択回路と、
    　前記選択回路から前記切替信号を受信し、受信した前記切替信号からリセット信号を生成する生成回路と、を更に有し、
    　前記出力部は、前記リセット信号を前記生成回路から受信した場合には、前記第１のファン及び前記第２のファンの回転パルスを計測できると判定して、前記第１のカウンタ及び前記第２のカウンタが計測した結果をリセットし、前記リセット信号を前記生成回路から受信できない場合には、前記第１のファンまたは前記第２のファンのいずれかの回転パルスを計測できないと判定し、前記第１のファンまたは前記第２のファンのいずれかが異常であることを示す信号を前記電子機器に出力する
    　ことを特徴とする請求項１に記載の接続装置。     The monitoring circuit is
    The rotation pulse output from the switching circuit is received, the rotation pulse is measured by a third counter having a smaller number of bits than the first counter and the second counter, and the measured result is used as the switching signal. A selection circuit for outputting to the switching circuit;
    A generation circuit that receives the switching signal from the selection circuit and generates a reset signal from the received switching signal;
    When the output unit receives the reset signal from the generation circuit, the output unit determines that rotation pulses of the first fan and the second fan can be measured, and the first counter and the second counter If the counter signal is reset and the reset signal cannot be received from the generation circuit, it is determined that the rotation pulse of either the first fan or the second fan cannot be measured, and the first The connection device according to claim 1, wherein a signal indicating that either one of the fans or the second fan is abnormal is output to the electronic device.
  3. 　前記出力部は、前記リセット信号を前記生成回路から受信できず、前記第２のファンから受信した回転パルスを前記第２のカウンタの上限値まで計測し続けた場合には、前記第１のファンが異常であることを示す低電位の信号を前記電子機器に出力することを特徴とする請求項２に記載の接続装置。 When the output unit cannot receive the reset signal from the generation circuit and continues to measure the rotation pulse received from the second fan up to the upper limit value of the second counter, the first fan The connection device according to claim 2, wherein a low-potential signal indicating that is abnormal is output to the electronic device.
  4. 　前記出力部は、前記リセット信号を前記生成回路から受信できず、前記第１のファンから受信した回転パルスを前記第１のカウンタの上限値まで計測し続けた場合には、前記第２のファンが異常であることを示す高電位の信号を前記電子機器に出力することを特徴とする請求項２に記載の接続装置。 When the output unit cannot receive the reset signal from the generation circuit and continues to measure the rotation pulse received from the first fan up to the upper limit value of the first counter, the second fan The connection device according to claim 2, wherein a high-potential signal indicating that is abnormal is output to the electronic device.
  5. 　接続装置によるファンの異常検出方法であって、
    　第１のファン及び第２のファンと接続された第１の接続部を介して前記第１のファン及び前記第２のファンから回転パルスを受信し、
    　前記第１のファンから受信した回転パルスを第１のカウンタで計測し、
    　前記第２のファンから受信した回転パルスを第２のカウンタで計測し、
    　前記第１のファン及び前記第２のファンから回転パルスを受信し、前記第１のファンから受信した回転パルスまたは前記第２のファンから受信した回転パルスのいずれか一方を切替信号に応じて交互に出力し、
    　出力した前記第１のファンの回転パルス又は前記第２のファンの回転パルスのうち、いずれかの回転パルスを計測できない場合には、前記第１のファンまたは前記第２のファンのいずれかが異常であることを示す信号を、電子機器と接続された第２の接続部を介して前記電子機器に出力する
    　処理を含むことを特徴とする異常検出方法。     A fan abnormality detection method by a connected device,
    Receiving a rotation pulse from the first fan and the second fan via a first connection connected to the first fan and the second fan;
    The rotation pulse received from the first fan is measured by a first counter,
    The rotation pulse received from the second fan is measured by a second counter,
    A rotation pulse is received from the first fan and the second fan, and either the rotation pulse received from the first fan or the rotation pulse received from the second fan is alternately changed according to a switching signal. Output to
    If any one of the output rotation pulses of the first fan and the rotation pulses of the second fan cannot be measured, either the first fan or the second fan is abnormal. The abnormality detection method characterized by including the process which outputs the signal which shows that it is to the said electronic device via the 2nd connection part connected with the electronic device.
  6. 　前記接続装置が、
    　切替信号に応じて出力した回転パルスを受信し、前記第１のカウンタ及び前記第２のカウンタよりもビット数の少ない第３のカウンタで該回転パルスを計測し、計測した結果を前記切替信号として出力し、
    　前記切替信号を受信し、受信した前記切替信号からリセット信号を生成する
    　各処理を更に含み、
    　前記電子機器に出力する処理は、前記リセット信号を前記生成回路から受信した場合には、前記第１のファン及び前記第２のファンの回転パルスを計測できると判定して、前記第１のカウンタ及び前記第２のカウンタが計測した結果をリセットし、前記リセット信号を前記生成回路から受信できない場合には、前記第１のファンまたは前記第２のファンのいずれかの回転パルスを計測できないと判定し、前記第１のファンまたは前記第２のファンのいずれかが異常であることを示す信号を前記電子機器に出力する
    　ことを特徴とする請求項５に記載の異常検出方法。     The connecting device is
    A rotation pulse output in response to the switching signal is received, the rotation pulse is measured by a third counter having a smaller number of bits than the first counter and the second counter, and the measured result is used as the switching signal. Output,
    Each process of receiving the switching signal and generating a reset signal from the received switching signal further includes:
    When the reset signal is received from the generation circuit, the process of outputting to the electronic device determines that the rotation pulses of the first fan and the second fan can be measured, and the first counter And when the reset signal cannot be received from the generation circuit, it is determined that the rotation pulse of either the first fan or the second fan cannot be measured. The abnormality detection method according to claim 5, wherein a signal indicating that either the first fan or the second fan is abnormal is output to the electronic device.
  7. 　前記電子機器に出力する処理は、前記リセット信号を前記生成回路から受信できず、前記第２のファンから受信した回転パルスを前記第２のカウンタの上限値まで計測し続けた場合には、前記第１のファンが異常であることを示す低電位の信号を前記電子機器に出力することを特徴とする請求項６に記載の異常検出方法。 The process of outputting to the electronic device cannot receive the reset signal from the generation circuit, and continues to measure the rotation pulse received from the second fan up to the upper limit value of the second counter. The abnormality detection method according to claim 6, wherein a low-potential signal indicating that the first fan is abnormal is output to the electronic device.
  8. 　前記電子機器に出力する処理は、前記リセット信号を前記生成回路から受信できず、前記第１のファンから受信した回転パルスを前記第１のカウンタの上限値まで計測し続けた場合には、前記第２のファンが異常であることを示す高電位の信号を前記電子機器に出力することを特徴とする請求項６に記載の異常検出方法。 The process of outputting to the electronic device cannot receive the reset signal from the generation circuit, and continues to measure the rotation pulse received from the first fan up to the upper limit value of the first counter. The abnormality detection method according to claim 6, wherein a high-potential signal indicating that the second fan is abnormal is output to the electronic device.
PCT/JP2012/058266 2012-03-28 2012-03-28 Connection device and failure detection method WO2013145196A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01197824A (en) * 1988-02-02 1989-08-09 Fujitsu Ltd Fault detector for cooling fan
JPH02230411A (en) * 1989-03-03 1990-09-12 Fujitsu Ltd Detecting system for fan abnormality
JPH03241893A (en) * 1990-02-20 1991-10-29 Fujitsu Ltd Cooling system
JPH06244577A (en) * 1993-02-18 1994-09-02 Fujitsu Ltd Cooling fan control equipment of electronic equipment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01197824A (en) * 1988-02-02 1989-08-09 Fujitsu Ltd Fault detector for cooling fan
JPH02230411A (en) * 1989-03-03 1990-09-12 Fujitsu Ltd Detecting system for fan abnormality
JPH03241893A (en) * 1990-02-20 1991-10-29 Fujitsu Ltd Cooling system
JPH06244577A (en) * 1993-02-18 1994-09-02 Fujitsu Ltd Cooling fan control equipment of electronic equipment

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