JP6149585B2 - Parallel bus device, electrical equipment and wiring control method - Google Patents

Description

  The present invention relates to a parallel bus device, an electric device, and a wiring control method, and more particularly, to a parallel bus device, an electric device, and a wiring control method for accurately detecting a connection state of a parallel bus.

  In an image processing apparatus including an image forming apparatus such as a copying apparatus, a facsimile apparatus, and a printer apparatus, and an image reading apparatus such as a scanner apparatus, and an electrical apparatus such as a computer or other electrical products, the internal substrates are connected with each other as the size is reduced. The connection using FFC (Flexible Flat Cable) is increasing. FFC has contributed greatly to the miniaturization of current miniaturized electrical devices because of its thinness and bending resistance.

  For example, in a composite apparatus, a CPU (Central Processing Unit) and devices having other functions are arranged on different substrates.

  For example, in a composite apparatus, a CPU and a ROM (Read Only Memory) for storing a program are usually mounted on the same substrate, and a device such as an ASIC (Application Specific Integrated Circuit) having other functions is mounted on another substrate. It is installed. In the composite apparatus, a CPU, a ROM, and other devices are connected by a parallel bus, and a parallel bus is connected between the boards using an FFC as a parallel bus I / F (see Patent Document 1).

  An electrical device may malfunction or cause a failure if a disconnection or a short circuit occurs in the FFC that connects the parallel buses between the boards.

  That is, generally, as shown in FIG. 7, the parallel bus device 100 includes a master device (hereinafter simply referred to as a master) 101 and a slave device (hereinafter simply referred to as a slave) 102. They are connected by a parallel bus 103. The parallel bus 103 includes an address bus 103a, a data bus 103b, and a signal line for a control signal, a signal line 103c for a chip select signal CS1_N, a signal line 103d for a read enable signal RD_N, and a signal line 103e for a write enable signal WR_N. Are wired in sequence. FIG. 7 shows a case where a CPU is used as the master 101 and an ASIC is used as the slave 102.

  In such a parallel bus device 100, the master 101 reads or writes data to the slave 102 via the parallel bus 103 when necessary. The address bus 103a and the data bus 103b are lines through which addresses ADDRESS0 to ADDRESS15 and data DATA0 to DATA15 for designating the area of the device to be connected, and there are as many wires as there are address areas and data widths of each device. The signal line 103d is a signal line for sending a read enable signal RD_N for the master to read data. The signal line 103d is asserted (L level output) at the timing when the master reads data, and the slave that has received the read enable signal RD_N Put out the data. The signal line 103e is a signal line for sending a write enable signal WR_N for the master to write data. The signal line 103e is asserted (L level output) at the timing when the master writes, and the slave that receives the write enable signal WR_N receives the data Is written inside.

  In such a parallel bus device 100, the address bus 103a, the data bus 103b, the signal line 103d for the read enable signal RD_N, and the signal line 103e for the write enable signal WR_N are connected to all devices by wired OR. Therefore, when there are a plurality of devices as slaves, it is impossible to identify which slave (device) the access is for. Therefore, in the parallel bus device 100, the master sends a chip select signal CS1_N to the control signal line 103c of the parallel bus 103 to select a slave (device) for communication, and simultaneously, two or more slaves (devices). Control to prevent communication with

  In the parallel bus device 100, as described above, the slave is a device mounted on the same substrate as the master CPU such as a ROM, and a device mounted on a different substrate such as an ASIC. There is.

  When the master and the slave are mounted on different boards, as shown in FIG. 8, the parallel bus device 100 includes a parallel bus I / F (interface) on a master side parallel bus 100a and a slave side parallel bus 100b. ) Using the FFC 100c.

  In the FFC 100c, when a slave is mounted on a substrate mounted on a movable part of an electric device, disconnection, a short circuit between adjacent wirings, and the like may occur with the operation of the electric device.

  However, as shown in FIG. 8, the conventional parallel bus device 100 generally has an address bus 103a, a data bus 103b, a signal line 103c for chip select signals CS1_N to CS3_N, and a signal line 103d for a read enable signal RD_N. The signal lines 103e for the write enable signal WR_N are wired in order. FIG. 8 shows a case where there are three slaves mounted on a board different from the board on which the master is mounted.

  In the parallel bus device 100 having such a wiring structure, for example, the wiring position indicated by C in FIG. 8 of the FFC 100c, that is, the data bus 103b and the signal lines 103c for the chip select signals CS1_N to CS3_N are adjacent to each other. If a short circuit occurs at the wiring position, for example, even if the master CPU asserts the chip select signal CSROM_N for selecting the ROM as the slave (output at L level) as shown in FIG. Sometimes, the chip select signals CS1_N to CS3_N short-circuited to the data bus 103b are affected by the data value of the data bus 103b short-circuited to the signal line 103c for the chip select signals CS1_N to CS3_N, indicating the chip select state. It may be asserted (L level output). In FIG. 9, the chip select signal CS1_N is asserted (L level output) under the influence of the data signal. Therefore, the slave connected to the shorted signal line 103c for the chip select signal CS1_N is not selected, but becomes a selected state during the period indicated by the double arrow in FIG. Two slaves are in a selected state, and a proper read / write cannot be performed. In addition, although the case where the short circuit has occurred in the wiring position C in FIG. 8 has been described above, the same applies to the case where the short circuit has occurred in the wiring position D. That is, even if a short circuit occurs between the signal line 103d for the read enable signal RD_N and the adjacent signal line 103c for the chip select signals CS1_N to CS3_N, the read enable signal RD_N remains at the L level while performing the chip select. Therefore, the short-circuited chip select signals CS1_N to CS3_N (in FIG. 8, chip select signal CS3_N) are asserted (L level output).

  Therefore, conventionally, in an electrical apparatus such as a composite device, a connection detection process for detecting the connection state of the FFC at the time of activation is performed to prevent the occurrence of malfunction or the like. Conventionally, generally, in an electric device, a program for performing connection detection processing is stored in a nonvolatile memory such as a ROM. Then, the CPU reads the program from the ROM through the parallel bus and performs connection detection processing.

  However, in the above prior art, the CPU reads the program from the ROM at the time of startup and performs connection detection processing. Therefore, for example, as shown in FIG. 8, when a problem occurs in which the L level bus and the signal line for chip select signal are short-circuited at the time of reading the program, other slaves as well as the ROM are in the selected state. It becomes. As a result, there is a problem that the CPU cannot accurately read the program and accurately perform the parallel bus connection detection process.

  In view of the above, an object of the present invention is to reliably execute connection detection processing in a parallel bus and perform accurate failure determination.

  To achieve the above object, a parallel bus device according to claim 1 is a non-volatile storage means for storing a program, and a chip select that is connected to the non-volatile storage means by a parallel bus and selects the non-volatile storage means. A control means for sending a signal to the parallel bus and reading the program from the nonvolatile storage means; a device connected to the parallel bus and selected by a chip select signal sent from the control means to the parallel bus; The control means reads the program from the nonvolatile storage means through the parallel bus at the time of startup, and then performs connection detection processing of the parallel bus based on the program. Next to the signal line through which the chip select signal for the control means to select the device flows As Route, at least, while the control means reads the program, it is characterized in that guard signal line of flow of the guard signal as a signal state indicating that the device is a non-selected state is disposed.

  According to the present invention, the connection detection process in the parallel bus can be reliably performed, and an accurate failure determination can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a main part of an image processing apparatus showing parallel bus wiring. The flowchart which shows the starting control process accompanied by a connection detection process. The sequence diagram of each signal at the time of program reading. The principal part schematic block diagram of the image processing apparatus which has another parallel bus wiring. The flowchart which shows an ASIC_WAKE signal process. The figure which shows an example of a parallel bus apparatus. The wiring block diagram of the conventional parallel bus and FFC. The figure which shows a signal state in case the chip select signal is short-circuited with the adjacent data bus.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 6 are diagrams showing an embodiment of a parallel bus device, an electric device, and a wiring control method according to the present invention. FIG. 1 is an embodiment of the parallel bus device, the electric device, and the wiring control method according to the present invention. It is a principal part schematic block diagram of the image processing apparatus 1 to which the example is applied.

  In FIG. 1, an image processing apparatus 1 as an electrical device includes a control board 10, a device board 20, and other parts necessary for performing image processing. The control board 10 and the device board 20 are connected by an FFC 30. Has been. The image processing apparatus 1 is, for example, a composite apparatus, a printer apparatus, a copying apparatus, a facsimile apparatus, a projector apparatus or the like. In the case of a composite apparatus, a composite apparatus such as an image forming unit, an image reading unit, a communication unit, and an operation display unit is further provided. Each part for executing the function is provided. In this embodiment, the case where the present invention is applied to the image processing apparatus 1 will be described as an electrical apparatus. However, the electrical apparatus is not limited to the image processing apparatus 1 and, for example, a parallel bus such as a computer is used. It can be applied to electrical equipment in general.

  The control board 10 is equipped with a CPU 11, a ROM 12, an EEPROM (Electrically Erasable and Programmable Read Only Memory) 13, and the like. A parallel bus 14 and a serial bus 15 are formed, and an FFC connector 16 is provided. .

  A ROM (nonvolatile storage means) 12 stores programs such as a basic program and connection detection program of the image processing apparatus 1 and necessary system data, and is connected to the parallel bus 14. In the present embodiment, it is assumed that the connection detection program is stored in the ROM 12 in a state where it is incorporated into a basic program, particularly a program necessary for starting up the image processing apparatus 1.

  The CPU (control means) 11 includes a plurality of modules such as a RAM (Random Access Memory), a communication control unit that performs communication control to communicate with the parallel bus 14 and the serial bus 15, and is connected to the parallel bus 14. And connected to the serial bus 15.

  The CPU 11 sends a chip select signal for selecting the ROM 12 to the parallel bus 14, reads (reads) the program in the ROM 12, and controls each part of the image processing apparatus 1 using the internal RAM, thereby controlling the image processing apparatus 1. The basic process is executed. Further, the CPU 11 sends a chip select signal for selecting the ROM 12 to the parallel bus 14 and reads the connection detection program in the ROM 12 together with the activation program. The CPU 11 performs connection detection processing for the entire parallel bus, which will be described later, based on the read connection detection program.

  That is, the image processing apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), a DVD. Connection detection for executing the connection detection method with the wiring control method of the present invention recorded on a computer-readable recording medium such as (Digital Versatile Disk), SD (Secure Digital) card, MO (Magneto-Optical Disc), etc. By loading the program and introducing it into the ROM 12, it is constructed as an image processing apparatus that accurately executes connection detection of a parallel bus, which will be described later. This connection detection program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. Can be distributed.

  The EEPROM 13 is connected to the CPU 11 via the serial bus 15, and necessary data is written and read by the CPU 11.

  The device substrate 20 is mounted with ASICs 21a, ASICs 21b, and ASICs 21c that are a plurality of devices (three in this embodiment), a parallel bus 22 is formed, and an FFC connector 23 is disposed. The device substrate 20 includes, for example, a substrate that controls I / O such as a motor and a sensor, a substrate that performs various image processing on image data, a substrate that performs image formation control for forming an image on paper P, and a document on the scanner unit. Either a substrate that performs scanner control for reading an image, or a substrate having a plurality of functions among the substrates. Therefore, the device substrate 20 is an ASIC that performs processing necessary for the ASICs 21a to 21c to be mounted to execute its functions.

  The ASICs 21 a to 21 c are connected to the parallel bus 22, and the parallel bus 22 is connected to the FFC connector 23.

  FFCs 30 serving as parallel cable means are connected to the FFC connector 16 of the control board 10 and the FFC connector 23 of the device board 20, respectively. That is, the parallel bus 14 of the control board 10 and the parallel bus 22 of the device board 20 are connected by the FFC 30. The FFC 30 is a high-density wiring cable used to reduce the size and weight when a large number of signal lines are provided.

  That is, the image processing apparatus 1 includes a parallel bus unit (parallel bus device) 40 including a parallel bus 14, an FFC connector 16, a parallel bus 22, an FFC connector 23, and an FFC 30.

  As shown in FIG. 2, the image processing apparatus 1 includes wiring lines parallel to the signal line L1 for the read enable signal line RD_N and addresses ADDRESS0 to ADDRESSn (ADDR0 in FIG. 2). To ADDRn.) Signal line (address bus) L2 for data, signal line (data bus) L3 for data DATA0 to DATAn, signal line L4 for write enable signal WR_N, and chip select signals CS1_N to CS3_N for devices The wirings of the signal line L5 and the signal line L6 for the ROM chip select signal CSROM_N are arranged in order. In FIGS. 1 and 2, the case where there are three devices ASICs 21a to 21c connected to the CPU 11 is taken as an example, and therefore the signal lines L5 for the chip select signals CS1_N to CS3_N are provided. There are three signal lines. Therefore, as the number of devices increases, the number of signal lines for chip select signals also increases by the number of devices. In FIG. 2, the signal line L4 for the write enable signal WR_N is shown by a wavy line in order to distinguish it from other bus wirings, but it is the same as other wirings, not virtual wirings. is there.

  The signal line L1 for the read enable signal RD_N is a signal line through which a read enable signal RD_N for the CPU 11 as a master to read data is sent. The read enable signal RD_N is asserted (L level output) at the timing when the CPU 11 that is the master reads data, and the ROM 12 and the ASICs 21a to 21c that are the slaves that have received the read enable signal RD_N output data. The signal line L4 for the write enable signal WR_N is a bus through which the write enable signal WR_N for the CPU 11 as a master to write data is passed. The write enable signal WR_N is asserted (L level output) at the timing of writing by the CPU 11 as a master, and the ROM 12 and the ASICs 21a to 21c as slaves having received the write enable signal WR_N write data therein. The address bus L2 is a bus through which addresses ADDRESS0 to ADDRESSn specifying addresses when data is read and written, and the data bus L3 is a bus through which data DATA0 to DATAn actually flows.

  In the image processing apparatus 1, the address bus L2, the data bus L3, the signal line L1 for the read enable signal RD_N, and the signal line L4 for the write enable signal WR_N from the CPU 11, which is the master, are the ROM 12, ASICs 21a to It is connected to 21c by wired OR. Therefore, it is necessary for the CPU 11 to identify which slave (device) of the ROM 12 and the ASICs 21a to 21c as slaves is to be accessed. Therefore, the CPU 11 serving as the master sends the chip select signals CSROM_N and CS1_N to CS3_N through the chip select signal lines L5 and L6, selects the slaves (devices) for communication, and simultaneously two or more slaves (devices). Control to prevent communication with

  Then, the parallel bus unit 40 includes a wiring adjacent to the upper side of the signal line L5 for the chip select signals CS1_N to CS3_N, that is, a wiring adjacent to the signal line L5 for the chip select signal CS1_N, as a signal for the write enable signal WR_N. This is a line (guard signal line) L4. The write enable signal WR_N flowing through the signal line L4 is an H level signal and functions as a guard signal except when data is written to the ROM 12 or the ASICs 21a to 21c. That is, the signal line L4 for the write enable signal WR_N normally causes the H level write enable signal WR_N to flow when the image processing apparatus 1 is activated. Further, the signal line L5 for the chip select signals CS1_N to CS3_N does not have a wiring adjacent to the lower side, that is, a wiring adjacent to the signal line L5 through which the chip select signal CS3_N flows, in particular, the FFC 30 and its connector 16. In 23, it does not exist. If a short circuit occurs in the signal line L5 through which the chip select signal CS3_N flows, it occurs only between the adjacent signal line L5 through which the upper chip select signal CS2_N flows. Then, while the CPU 11 at the time of starting the image processing apparatus 1 reads a program from the ROM 12, the chip select signals CS1_N to CS3_N flowing through the signal line L5 are normally at the H level.

  Next, the operation of this embodiment will be described. The image processing apparatus 1 of the present embodiment accurately performs the connection detection process in the parallel bus unit 40.

  In the image processing apparatus 1, among the CPU 11, the ROM 12, and the ASICs 21 a to 21 c that perform parallel communication using the parallel bus unit 40, the ASICs 21 a to 21 c are connected to a device board 20 that is different from the control board 10 on which the CPU 11 is mounted. ing. In the parallel bus unit 40, the parallel bus 14 on the control board 10 and the parallel bus 22 on the device board 20 are connected by an FFC 30 that connects the FFC connector 16 of the control board 10 and the FFC connector 23 of the device board 20. Yes.

  In the FFC 30, when the device substrate 20 is a substrate mounted on a movable part of the image processing apparatus 1, a disconnection or a short circuit between adjacent wirings may occur due to the operation of the image processing apparatus 1. is there.

  Therefore, when the CPU 11 is activated by reading the activation program from the ROM 12 at the time of activation such as when the power is turned on or at the time of rebooting, the CPU 11 is incorporated together with the activation program or as a part of the activation program. Read the connection detection program. The CPU 11 executes the connection detection program together with the start-up process, thereby executing the detection process of the connection state of the parallel bus unit 40, particularly the connection state of the FFC 30.

  That is, as shown in FIG. 3, the image processing apparatus 1 performs an activation control process with a connection detection process. When the power is turned on or reset, the image processing apparatus 1 starts supplying power to each of the substrates 10 and 20 (power on) as shown in FIG. 3 (step S101). Next, the image processing apparatus 1 resets each device such as the CPU 11, the ROM 112, the EEPROM 13, and the ASICs 21a to 21c (step S102).

  When the reset of each device is completed, the image processing apparatus 1 cancels the reset of the CPU 11 and the ROM 12 (step S103), and the CPU 11 reads the program from the ROM 12 (step S104).

  When reading the program from the ROM 12, the CPU 11 first asserts the chip select signal CSROM_N (L level output) flowing through the ROM chip select signal line L6 as shown in FIG. Next, the CPU 11 asserts (L level output) the read enable signal RD_N of the signal line L1. The CPU 11 negates signals (write enable signal WR_N, chip select signals CS1_N to CS3_N) of other control buses (signal line L4, signal line L5) (H level output).

  In this state, the address ADDRESS0 to ADDRESSn of the address bus L2 is designated, the program including the connection detection program is read from the ROM 12, and it is checked whether the program reading has failed (step S105).

  If the CPU 11 fails to read the program, the CPU 11 performs an error process for displaying a CPU error on the display of the operation display unit of the image processing apparatus 1, and ends the activation control process (step S106).

  When the CPU 11 succeeds in reading the program in step S105, the CPU 11 performs initial settings in the CPU 11, based on the program, for example, bus timing settings and serial communication module settings for other devices, and communication to peripheral devices. Make preparations.

  When the CPU 11 completes the initial setting, it executes the connection detection program that has been read, and performs connection detection processing for detecting the connection state of the parallel bus, in particular, the connection state of the FFC 30 (step S108), and checks whether there is a connection error. (Step S109).

  The CPU 11 executes the connection detection program to detect the presence / absence of a defect such as a disconnection or a short circuit in the parallel bus unit 40. In particular, the CPU 11 detects the presence / absence of a defect in the FFC 30.

  Now, in the image processing apparatus 1, the parallel bus unit 40 has the signal line L4 for the write enable signal WR_N as the bus wiring adjacent to the signal line L5 for the chip select signals CS1_N to CS3_N as described above. Has been placed. The write enable signal WR_N flowing through the signal line L4 is negated (H level output) while the CPU 11 reads the program from the ROM 12, as shown in FIG. Therefore, even if a short circuit occurs between the signal line L4 for the write enable signal WR_N and the signal line L5 through which the adjacent chip select signal CS1_N flows, the chip select signal CS1_N flowing through the signal line L5 is at the H level. Output. Therefore, as in the conventional case shown in FIG. 9, it is possible to prevent the chip select signals CS1_N to CS3_N from being short-circuited to the adjacent bus wiring and being output at the L level by the signal of the bus wiring. As a result, for example, even if a short circuit occurs at the wiring position of the FFC 30 indicated by A in FIG. 2, the CPU 11 has a chip select signal CSROM_N to the ROM 12 and chip select signals to the ASICs 21a to 21c as shown in FIG. CS1_N to CS3_N are never asserted (L level output) at the same time. As a result, the program including the connection detection program can be accurately read from the ROM 12. Even if a short circuit occurs between the signal lines L5 for the chip select signals CS1_N to CS3_N of the parallel bus section 40, for example, at the position indicated by B in FIG. 4, when the program is read, the chip select signals CS1_N to the ASICs 21a to 21c are read. CS3_N is negated (H level output) and never asserted (L level output). Therefore, the CPU 11 can accurately read the program from the ROM 12.

  Therefore, the CPU 11 can accurately detect whether or not a defect such as a short circuit or disconnection has occurred in the parallel bus unit 40 by executing the read connection detection program.

  The CPU 11 performs a connection detection process, and when there is no connection error in step S109, the start control process is terminated as it is.

  In step S109, when there is a connection error, the CPU 11 notifies and outputs a notification that an FFC connection error (parallel bus connection error) has occurred on the display of the image processing apparatus 1, and the startup control process. Is finished (step S110).

  Therefore, when the CPU 11 fails to read the program in step S105, the CPU 11 determines that it is not a problem in the parallel bus unit 40 but an operation problem of the CPU 11 itself, and performs CPU error processing. Yes (step S106).

  In the above description, the signal line L4 for the write enable signal WR_N is arranged as the guard signal line between the signal line L5 for the chip select signals CS1_N to CS3_N and the data bar L3. It is not limited to the signal line L5 for WR_N. That is, as a bus line adjacent to the signal line L5 for the chip select signals CS1_N to CS3_N, a signal that is a negate (H level output) flows while the CPU 11 reads a program from the ROM 12 at least at the time of startup or restart. Any signal line may be used as long as it is a bus wiring. As such a bus wiring, for example, as shown in FIG. 5, a WAKE signal line (control signal line) L7 through which an ASIC_WAKE signal (control signal) flows may be used. Note that FIG. 5 is applied to an image processing apparatus similar to the image processing apparatus 1, and the same components are denoted by the same reference numerals, and description thereof is omitted or simplified. In FIG. 5, the ASIC_WAKE signal is described as ASIC_W.

  That is, in FIG. 5, in the image processing apparatus 50, the control board 60 and the device board 70 are connected by the FFC 80. The control board 60 is mounted with a CPU 11, a ROM 12, an EEPROM 13 (not shown), and the like. A parallel bus 61 and an FFC connector 62 are formed, and a predetermined voltage is applied to the pull-up resistor Rp. The device substrate 70 is mounted with the ASIC 21a, and a parallel bus 71 and an FFC connector 72 are formed. FIG. 5 shows a case where only one ASIC 21a is mounted as a device. However, the number of devices is not limited to one. For example, as shown in FIGS. An ASIC or other device may be mounted.

  The FFC connector 62 of the control board 60 and the FFC connector 72 of the device board 70 are connected by the FFC 80. The parallel bus 61, the FFC connector 62, the parallel bus 71, the FFC connector 72, and the FFC 80 are constructed as a parallel bus unit (parallel bus device) 90 as a whole.

  In FIG. 5, the parallel bus unit 90 has a signal line L1 for a read enable signal RD_N, an address bus L2 for addresses ADDRESS0 to ADDRESSn (indicated as ADDR0 to ADDRn in FIG. 5), and data DATA0 to DATAn from above. The data bus L3, the WAKE signal line L7, the signal line L5 for the chip select signal CS1_N, the signal line L4 for the write enable signal WR_N, and the signal line L6 for the ROM chip select signal CSROM_N are arranged in order. It is arranged in a state. That is, the WAKE signal line L7 is disposed between the signal line L5 through which the chip select signal CS1_N for selecting the ASIC 21a flows and the data bus L3. In FIG. 5, the WAKE signal line L7 is indicated by a wavy line in order to clearly show the WAKE signal line L7.

  The WAKE signal line L7 is pulled up to a predetermined voltage via a pull-up resistor Rp. When the ASIC 21a is, for example, an ASIC that performs I / O (Input / Output) control, the WAKE signal line L7 is normally at the H level. An ASIC1_WAKE signal (hard reset signal) is input to the CPU 11. Then, the ASIC 21a performs ASIC1_WAKE signal processing as shown in FIG. That is, when the ASIC 21a starts the I / O control (step S201), the ASIC 21a checks whether the I / O control is normal (step S202). When the I / O control is normal, the ASIC 21a operates so that the H level ASIC1_WAKE signal is input to the CPU 11. If an abnormality occurs in the I / O control in step S202, the ASIC 21a is reset (step S203) and negates (outputs L level) the ASIC1_WAKE signal to the CPU 11 (step S204). When the CPU 11 receives the ASIC1_WAKE signal at the L level, it resets (step S205).

  Therefore, the ASIC1_WAKE signal flowing through the WAKE signal line L7 is a signal that is normally at the H level during a period in which the CPU 11 reads the program from the ROM 12 at the time of startup or restart.

  As a result, even if a short circuit occurs between the signal line L5 through which the chip select signal CS1_N flows and the WAKE signal line L7, the chip select signal CSROM_N to the ROM 12 and the chip select signal CS1_N to the ASIC 21a are simultaneously asserted (L level). Output). Therefore, the program including the connection detection program can be accurately read from the ROM 12.

  As described above, in the image processing apparatuses 1 and 50 of the present embodiment, the parallel bus units 40 and 90 are connected by the ROM (nonvolatile storage means) 12 that stores the program, the ROM 12 and the parallel buses 14 and 61, A chip select signal CSROM_N for selecting the ROM 12 is sent to the parallel buses 14 and 61, and the CPU (control means) 11 for reading the program from the ROM 12 is connected to the parallel buses 22 and 71. ASIC (devices) 21a to 21c selected by chip select signals CS1_N to CS3_N sent to 71, and the CPU 11 reads the program from the ROM 12 through the parallel buses 14 and 61 at the time of startup, and then stores the program in the program. Based on parallel buses 14, 22, FFC30 or para The parallel buses 14, 22, and FFC 30 or the parallel buses 61, 71, and FFC 80 are connected to the signal lines L5 through which the chip select signals CS1_N to CS3_N through which the CPU 11 selects the ASICs 21a to 21c. As a neighboring signal line, at least while the CPU 11 reads the program, a guard signal line through which a guard signal that is in a signal state (negate (H level output)) indicating that the ASICs 21a to 21c are in the non-selected state flows. (The signal line L5 for the write enable signal WR_N and the WAKE signal line L7 for the ASIC1_WAKE signal) are arranged.

  Therefore, even if a short circuit occurs between the signal line L4 for the write enable signal WR_N or the WAKE signal line L7 and the adjacent signal line L5 through which the chip select signals CS1_N to CS3_N flow, the chip that flows through the signal line L5. The select signals CS1_N to CS3_N are H level outputs. As a result, the program including the connection detection program can be read accurately, and the connection detection process on the parallel bus can be performed accurately.

  In addition, the image processing apparatuses 1 and 50 of the present embodiment include a CPU in which the parallel bus units 40 and 90 are connected by a ROM (nonvolatile storage means) 12 that stores a program and parallel buses 14 and 61. (Control means) 11 is connected to the parallel buses 22 and 71 and a program reading processing step for reading the program from the ROM 12 by sending a chip select signal CSROM_N for selecting the ROM 12 to the parallel buses 14 and 61 Device selection processing steps in which the ASICs (devices) 21a to 21c are sent to the CPU 11 through the chip select signals CS1_N to CS3_N for selecting the ASICs 21a to 21c through the parallel buses 14, 22, FFC30 or the parallel buses 61, 71, FFC80. When the CPU 11 starts up, A connection detection processing step for performing connection detection processing for the parallel buses 14, 22, and FFC30 or the parallel buses 61, 71, and FFC80 after the program is read from the ROM 12 by the gram reading processing; and a chip select for the CPU 11 to select the ASICs 21a to 21c. Signals indicating that the ASICs 21a to 21c are in the non-selected state on the signal line adjacent to the signal line L5 through which the signals CS1_N to CS3_N flow, at least while the program is being read in the program reading processing step. A wiring control method including a guard signal processing step for passing a guard signal in a state (negate (H level output)) is executed.

  Therefore, even if a short circuit occurs between the signal line L4 or WAKE signal line L7 for the write enable signal WR_N and the signal line L5 for the adjacent chip select signals CS1_N to CS3_N, the chip select signals CS1_N to CS3_N Becomes an H level output. As a result, the program including the connection detection program can be read accurately, and the connection detection process on the parallel bus can be performed accurately.

  Furthermore, the parallel bus units 40 and 90 included in the image processing apparatuses 1 and 50 of the present embodiment have the ROM 12 and the CPU 11 mounted on the same control boards 10 and 60, and the ASICs (devices) 21a to 21c are controlled. The control parallel buses 14 and 61 are mounted on the device boards 20 and 70 different from the boards 10 and 60, and the parallel buses are formed on the control boards 10 and 60 to connect the ROM 12 and the CPU 11; 70, device parallel buses 22 and 71 connected to the ASICs 21a to 21c, and FFCs (parallel cable means) 30 and 80 connecting the control parallel buses 14 and 61 and the device parallel buses 22 and 71 are provided. At least in the FFC 30, 80, the CPU 11 selects the ASICs 21a to 21c. As neighboring signal lines of the signal lines L5 to recto signal CS1_N~CS3_N flows, the guard signal lines are arranged.

  Therefore, even if a short circuit occurs between the signal line L4 for the write enable signal WR_N or the WAKE signal line L7 and the adjacent signal line L5 for the chip select signals CS1_N to CS3_N in the FFC 30, 80, the chip The select signals CS1_N to CS3_N are H level outputs. As a result, the program including the connection detection program can be read accurately, and the connection detection process on the parallel bus can be performed accurately.

  In the parallel bus unit 40 included in the image processing apparatuses 1 and 50 according to the present embodiment, the guard signal line is a signal line (write enable signal line) L4 through which the write enable signal WR_N flows as the guard signal. .

  Therefore, using the signal line L4 through which the write enable signal WR_N, which is an existing signal line, flows, the chip select signals CS1_N to CS3_N are negated (H level output at least while the CPU 11 reads the program from the ROM 12). ) State. As a result, the program including the connection detection program can be accurately read simply and efficiently without increasing the number of wires, and the connection detection processing in the parallel bus can be performed accurately and inexpensively.

  Further, the parallel bus unit 90 included in the image processing apparatus 50 according to the present embodiment is configured so that the CPU 11 or the ASICs 21a to 21c can read the program after the CPU 11 has read the program, with the guard signal line serving as the guard signal line. This is a WAKE signal line (control signal line) L7 through which an ASIC_WAKE signal (control signal) whose voltage level can be changed flows.

  Therefore, even if a short circuit occurs between the signal line L5 through which the chip select signal CS1_N flows and the WAKE signal line L7, the chip select signal CSROM_N to the ROM 12 and the chip select signal CS1_N to the ASIC 21a are simultaneously asserted (L level output). ). Therefore, the program including the connection detection program can be accurately read from the ROM 12.

  The parallel bus units 40 and 90 included in the image processing apparatuses 1 and 50 according to the present embodiment include a plurality of ASICs 21a to 21c as devices, and the parallel buses are chip select signals CS1_N of all the ASICs 21a to 21c. The signal line L5 for .about.CS3_N is wired adjacently, and among the plurality of signal lines L5 for the chip select signals CS1_N to CS3_N, the data bus (data signal line) L3, the address bus (address signal line) L2, or The guard signal line is disposed between the signal line L5 closest to the signal line L1 for the read enable signal RD_N.

  Therefore, even when the signal lines L5 for the chip select signals CS1_N to CS3_N for a plurality of devices are provided, all the chip select signals CS1_N to CS3_N are output at the H level at least while the CPU 11 reads the program from the ROM 12. be able to. As a result, the program including the connection detection program can be read accurately, and the connection detection process on the parallel bus can be performed accurately.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 10 Control board 11 CPU
12 ROM
13 EEPROM
14 Parallel bus 15 Serial bus 16 FFC connector 20 Device board 21a, 21b, 21c ASIC
22 Parallel bus 23 FFC connector 30 FFC
40 Parallel Bus Unit L1 to L6 Signal Line 50 Image Processing Device 60 Control Board 61 Parallel Bus 62 FFC Connector 70 Device Board 71 Parallel Bus 72 FFC Connector 80 FFC
90 Parallel bus L7 WAKE signal line

JP 2000-284624 A

Claims (8)

Non-volatile storage means for storing a program;
A control means connected to the nonvolatile memory means by a parallel bus, and for supplying a chip select signal for selecting the nonvolatile memory means to the parallel bus and reading the program from the nonvolatile memory means;
A device connected to the parallel bus and selected by a chip select signal sent from the control means to the parallel bus;
With
The control means includes
After reading the program from the non-volatile storage means through the parallel bus at the time of startup, the connection state of the parallel bus is detected based on the program,
The parallel bus is
A signal state indicating that the device is in a non-selected state as a signal line adjacent to a signal line through which a chip select signal for selecting the device by the control unit is read at least while the control unit reads the program. A parallel bus device in which a guard signal line through which a guard signal flows is arranged. The nonvolatile storage means and the control means are:
Mounted on the same control board,
The device is
It is mounted on a device board different from the control board,
The parallel bus is
A control parallel bus formed on the control board for connecting the nonvolatile storage means and the control means; a device parallel bus formed on the device board for connecting to the device; the control parallel bus; and Parallel cable means for connecting to a device parallel bus, and at least in the parallel cable means, the guard signal line is a signal line adjacent to a signal line through which a chip select signal for the control means to select the device flows. The parallel bus device according to claim 1, wherein the parallel bus device is arranged. The guard signal line is
3. The parallel bus device according to claim 1, wherein the guard signal is a write enable signal line through which a write enable signal flows. The guard signal line is
2. The signal line as claimed in claim 1, wherein the guard signal is a signal line through which a control signal capable of changing a voltage level of the control means or the device after the reading of the program by the control means is completed. 3. The parallel bus device according to 2. The device is
Multiple installed,
The parallel bus is
Chip select signal lines of all the devices are wired adjacent to each other, and among the plurality of chip select signal lines, a data signal line, an address signal line, or a chip select signal line closest to the read enable signal line The parallel bus device according to any one of claims 1 to 4, wherein the guard signal line is disposed therebetween. Non-volatile storage means for storing a program; control means for reading and controlling the program; and a device that performs processing under the control of the control means. There,
An electric apparatus comprising the parallel bus device according to claim 1 as the parallel bus unit. The electrical equipment is
The electrical apparatus according to claim 6, wherein the control unit is an image processing apparatus that performs image processing by controlling the operation of the device based on the program stored in the nonvolatile storage unit. A program for reading the program from the nonvolatile storage means by causing the control means connected to the nonvolatile storage means for storing the program by the parallel bus to flow a chip select signal for selecting the nonvolatile storage means to the parallel bus A reading process step;
A device selection processing step in which a device connected to the parallel bus is operated by passing a chip select signal through which the control means selects the device through the parallel bus;
A connection detection processing step for detecting a connection state of the parallel bus after the control means reads the program from the non-volatile storage means in the program reading process at startup;
While the program is being read at least in the program read processing step on the signal line adjacent to the signal line through which the chip select signal for selecting the device by the control means is, the device remains in the non-selected state. A guard signal processing step for passing a guard signal that is in a signal state indicating that there is,
A wiring control method characterized by comprising:

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