JP5278267B2 - END COVER, PROGRAMMABLE LOGIC CONTROLLER DEVICE EQUIPPED WITH THE SAME, END COVER INSTALLATION CHECK METHOD, AND PROGRAMMABLE LOGIC CONTROLLER FAILURE DIAGNOSIS METHOD - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLC device allowing certain and easy failure diagnosis of a bus signal and allowing confirmation of presence/absence of mounting of an end cover by equipping a bus interface (hereinafter bus I/F), a register for a bus function, and a bus failure-diagnosing register in the end cover of the PLC device. <P>SOLUTION: A CPU unit communicates with the bus I/F 61 of this end cover 6 in start-up or at prescribed time intervals, and reads end cover peculiar information 621 of the register 62 for the bus function to confirm the presence/absence of the end cover 6. The CPU unit communicates with the bus I/F 61 of the end cover 6 at prescribed time intervals, writes prescribed failure diagnostic data into the bus failure-diagnosing register 63, thereafter reads the failure diagnostic data from the bus failure-diagnosing register 63, and compares the previously stored failure diagnostic data and the read failure diagnostic data to diagnose failure of a bus. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a system using a programmable logic controller (hereinafter, PLC) device. In particular, in a PLC device that connects each unit constituting a PLC device by connecting them using a connector, a bus interface (in the end cover provided at the last stage of the bus for protecting signal terminals and terminating signals) The following relates to a PLC device provided with a bus I / F).

  In a conventional PLC device that does not have a backplane and connects each unit by connecting connectors, a bus signal termination circuit is provided on the end cover to reduce signal reflection on the bus and prevent signal waveform disturbance. ing. Furthermore, a dedicated signal line for recognizing whether or not the end cover is attached is provided, and it is determined whether or not the end cover is attached to the PLC device based on the logical value of the dedicated signal (for example, Patent Document 1). . That is, for example, when the logical value of the dedicated signal is “H”, it is determined that the end cover is removed, and when it is “L”, it is determined that the end cover is attached.

JP 2007-18503 A

  In a conventional PLC device that connects units by connecting connectors, the longest path of the bus varies as the number of connected units increases or decreases. For such a system, it is not sufficient to provide a termination circuit in the end cover as in a conventional PLC device. That is, in order to improve the reliability, operability, serviceability (RAS) function, which is a general term for the comprehensive usability of automated equipment, failure diagnosis by bus access is required. Since the bus connected to the unit connected between the CPU unit and the end cover must be accessed, and the number and type of units to be connected are not uniquely determined, it is not easy to realize. In other words, the conventional PLC system has a problem that the failure diagnosis of the bus signal cannot be surely and easily performed. Further, the conventional PLC system has a problem that the dedicated signal line as described above must be provided in order to recognize whether or not the end cover is attached.

  The end cover according to the present invention includes a connector connected to at least the CPU unit by a bus, bus interface means connected to the connector and communicating with the CPU unit via the bus, and connected to the bus interface means. A first storage means capable of storing end cover specific information and mounting position information sent from the CPU unit; and a second storage means connected to the bus interface means and capable of writing and reading failure diagnosis data sent from the CPU unit. Storage means.

  According to the present invention, by providing the bus I / F means in the end cover, it is possible to detect a bus abnormality and to stop the system safely, so that the RAS function is improved and the failure of the bus signal reliably and easily. The effect is that a diagnosis can be made. Further, it is possible to determine whether or not the end cover is attached to the PLC device without providing a dedicated signal line.

It is a block diagram which shows the structure of the PLC apparatus in Embodiment 1 of this invention. It is a block diagram which shows the structure of the end cover in Embodiment 1 of this invention. It is a flowchart which shows the end cover mounting | wearing presence / absence confirmation operation at the time of starting in Embodiment 1 of this invention. It is a flowchart which shows the end cover mounting | wearing presence / absence confirmation operation | movement in operation | movement in Embodiment 1 of this invention. It is a figure for demonstrating the failure diagnosis operation | movement in Embodiment 1 of this invention. It is a flowchart which shows the failure diagnosis operation | movement in Embodiment 1 of this invention.

Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of the PLC device 1 according to the first embodiment. The PLC device 1 does not include a backplane as shown in FIG. 1, and each unit of the power supply unit 2, the CPU unit 3, the I / O unit 4, the analog unit 5 and the end cover 6 is a connector for connecting the units. 7 are connected. Here, an arbitrary number of I / O units 4 or analog units 5 are usually connected between the I / O unit 4 and the analog unit 5 shown in FIG. 1, but these are not shown for simplicity. Description is omitted.

  The power supply unit 2 is supplied with electric power from the outside of the PLC device 1 and supplies predetermined power to each unit of the CPU unit 3, the I / O unit 4, the analog unit 5, and the end cover 6 with a predetermined voltage. The CPU unit 3 having a central processing unit (CPU) 31 as an internal unique function means performs bus access to the I / O unit 4, the analog unit 5 or the end cover 6 through the bus I / F and connector 7, The entire PLC device 1 is controlled by transmitting and receiving signals.

  The I / O unit 4 receives a predetermined signal from the CPU unit 3 via the connector 7 and receives a necessary signal from other units including the CPU unit 3 via the bus I / F. Then, control of external devices, predetermined input / output control, and the like are performed through an external I / O (not shown). Furthermore, a predetermined signal is transmitted to other units including the CPU unit 3 through the bus I / F and the connector 7 as necessary. On the other hand, the analog unit 5 receives a predetermined signal from the CPU unit 3 via the connector 7 in the same manner as the I / O unit 4, and receives necessary signals from other units including the CPU unit 3 through the bus I / F. Receive. Then, the necessary signal is converted into an analog signal by a D / A converter (not shown) of the specific function means, and external devices and predetermined input / output control are performed through an external I / O (not shown). Furthermore, the signal input from the external device through the external I / O is converted into a digital signal by an A / D converter (not shown) of the specific function means, and to other units such as the CPU unit 3 as necessary. It transmits via the bus I / F and the connector 7.

  The end cover 6 is provided at the final stage of the bus signal, and has a function of protecting the terminal of the bus signal and the like from dust and the like existing in the external environment, for example, preventing erroneous contact. The end cover 6 includes a register inside, and the register is used for bus failure diagnosis and confirmation of whether the end cover 6 is attached.

  The configuration of the end cover 6 in the first embodiment will be described. FIG. 2 is a block diagram showing the configuration of the end cover 6. As shown in FIG. 2, the end cover 6 is connected to the analog unit 5 by a connector 7 and is connected to a bus. The bus connected to the end cover 6 is connected to a bus I / F 61 which is a bus interface means. The bus I / F 61 is connected to the bus function register 62 as the first storage means and the bus failure diagnosis register 63 as the second storage means via an internal signal line. The bus function register 62 is configured to store the end cover specific information 621 at least at a predetermined address and store the mounting position information 622 at another predetermined address.

  Next, the operation of the PLC device 1 according to the first embodiment will be described with reference to the drawings. First, an operation for confirming whether or not the end cover 6 is attached will be described. FIG. 3 is a flowchart showing an operation flow for confirming whether or not the end cover 6 is attached at the time of activation. First, when the PLC device 1 is activated, the CPU unit 3 performs bus access to each connected unit. For example, the mounting position information viewed from the CPU unit 3 is transmitted to each unit and stored in a register (not shown) of the unique function means of each unit. For example, when the PLC device 1 is activated in FIG. 1, the CPU unit 3 first performs bus access to the adjacent I / O unit 4. Then, for example, “1” is stored in the register of the I / O unit 4 as the mounting position information. Next, the CPU unit 3 performs bus access to the analog unit 5 and stores “2”, for example, as mounting position information in the register of the analog unit 5.

  Similarly, the CPU unit 3 performs bus access to the end cover 6 to check whether the end cover 6 is attached. Hereinafter, an operation flow in which the CPU unit 3 confirms whether or not the end cover 6 is attached will be described with reference to FIG. In the first embodiment, when the PLC device 1 is activated (step S31) and the CPU unit 3 performs bus access to the end cover 6 (step S32), the end cover 6 is attached to the PLC device 1. In this case, the bus I / F 61 of the end cover 6 responds to the bus access from the CPU unit 3 and communicates with the CPU unit 3. Specifically, the CPU unit 3 generates, for example, “3” as the mounting position information (step S33) and transmits it to the end cover 6. Then, the bus I / F 61 of the end cover 6 receives the mounting position information, and stores “3” as the mounting position information 622 in the bus function register 62 (step S34). The CPU unit 3 reads the mounting position information stored in the bus function register 62 (step S35), and checks whether correct mounting position information is stored in the bus function register 62 (step S36). If the correct mounting position information is stored, the CPU unit 3 reads the end cover specific information 621 (step S37). Then, it is determined whether or not the end cover specific information 621 has been read (step S38). If it is read, it is determined that the end cover is attached.

  On the other hand, when the end cover 6 is not attached to the PLC device 1, the CPU unit 3 cannot read the end cover specific information 621 and the attachment position information 622. For example, if the mounting position information does not match because the correct mounting position information cannot be read after the bus access of the CPU unit 3 (step S36), the CPU unit 3 has an abnormal bus signal or the end cover 6 is mounted on the PLC device 1. The system is judged to be abnormal (step S39), and the system is safely stopped according to a predetermined sequence (step S40).

  The operation of confirming whether or not the end cover 6 is attached is performed not only when the system is activated, but also during system operation. FIG. 4 is a flowchart showing an operation flow for confirming whether or not the end cover 6 is attached during operation. Hereinafter, a confirmation operation flow during system operation will be described with reference to FIG. In this case, a mounting confirmation command for confirming whether or not the end cover 6 is mounted is generated at a predetermined time interval T1 using a timer (not shown) provided in the unique function means of the CPU unit 3. That is, it is determined whether or not a predetermined time T1 has passed by a timer or the like (step S41), and when T1 has passed, a mounting confirmation command is sent from the CPU unit 3 to the end cover 6 (step S42). The mounting confirmation command in the first embodiment is a command to read the end cover specific information 621 of the unit having the mounting position information “3”, for example.

  If the end cover 6 is attached to the PLC device 1, the bus I / F 61 responds to a bus access that is an attachment confirmation command from the CPU unit 3 and communicates with the CPU unit 3. Then, the CPU unit 3 reads the end cover specific information 621 stored in the bus function register 62. The CPU unit 3 reads the end cover specific information 621 from the end cover 6 (step S43), and collates it with the end cover specific information 621 stored in advance in an internal register (step S44). If they match, it is determined that the end cover 6 is attached to the PLC device 1 and the operation is terminated (step S45), and the timer and the like are restarted.

  On the other hand, if the end cover 6 is dropped from the PLC device 1 due to an external impact or the like, the end cover specific information 621 cannot be read in response to a bus access which is a mounting confirmation command from the CPU unit 3. . For example, after the bus access of the CPU unit 3, if there is no signal from the end cover 6 even after a predetermined time T 0 has elapsed, it is determined that reading is not possible. Since correct end cover specific information cannot be read, it does not match the end cover specific information 621 stored in the internal register in advance (step S44), the CPU unit 3 has an abnormal bus signal, or the end cover 6 has dropped from the PLC device 1. The system is safely stopped according to a predetermined sequence (step S47).

  Next, failure diagnosis of a bus signal for detecting a bus abnormality will be described with reference to the drawings. The failure diagnosis in the present embodiment will be described on the assumption that the system is safely stopped when a failure is detected, so that the failure diagnosis is periodically performed at the time interval T2 when the system is started and during operation. FIG. 5 is a diagram for explaining failure diagnosis, and is a connection diagram focusing on the connection between the CPU unit 3 and the end cover 6, and the connection with other units is not shown. FIG. 6 is a flowchart showing the operation flow of the failure diagnosis operation. In the first embodiment, as shown in FIG. 5, the failure diagnosis data stored in the memory 32 is sent from the CPU unit 3 to the end cover 6 and is written in the bus failure diagnosis register 63. The data is read again from the CPU unit 3 and collated to diagnose the presence or absence of a bus failure.

  Here, the failure diagnosis data will be described. In the first embodiment, a case where the number of bits of the bus is 16 will be described as an example. In the case of a 16-bit bus, for example, the failure diagnosis data includes the following eight data described in hexadecimal: “AAAAAh”, “5555h”, “CCCCh”, “3333h”, “F0F0h”, “0F0Fh”, “FF00h” "," 00FFh "(h indicates hexadecimal notation) can be used. By using these 8 data sequentially for writing and reading out as failure diagnosis data, even if one bit, if the bus signal is open or shorted, the collation result will not match, so failure diagnosis of all signal lines on the bus is performed. be able to.

Next, a bus signal failure diagnosis operation will be described with reference to the drawings. In FIG. 6, when the PLC device 1 is activated, the CPU 31 inside the CPU unit 3 generates a write signal that is a write request and failure diagnosis data every predetermined time interval T2. That is, it is determined whether or not a predetermined time T2 has passed by a timer or the like (step S61), and when T2 has passed, a write signal and failure diagnosis data are generated (step S62). For example, when “AAAAAh” is generated as the first failure diagnosis data, it is sent from the CPU unit 3 to the end cover 6 (step S63). The write signal and failure diagnosis data are written to the bus failure diagnosis register 63 of the end cover 6 by bus access (step S64). Specifically, the bus I / F 61 of the end cover 6 responds to bus access for sending a write signal and failure diagnosis data from the CPU unit 3 and communicates with the CPU unit 3. The bus I / F 61 sends a write signal and failure diagnosis data to the bus failure diagnosis register 63. The bus failure diagnosis register 63 receives the write signal and writes failure diagnosis data at a predetermined address.

When failure diagnosis data is written in the bus failure diagnosis register 63 of the end cover 6, the CPU 31 of the unique function means of the CPU unit 3 reads out failure diagnosis data of the end cover 6 by bus access (step S65). Specifically, a read signal as a read request is generated from the CPU unit 3 to the end cover 6 after a predetermined time T3 has elapsed since the bus access for writing the failure diagnosis data to the bus failure diagnosis register 63 is performed. Sent. The bus I / F 61 of the end cover 6 responds to bus access for sending a read signal from the CPU unit 3 and communicates with the CPU unit 3. Then, the bus I / F 61 sends a read signal to the bus failure diagnosis register 63. When receiving the read signal, the bus failure diagnosis register 63 reads the written failure diagnosis data and sends it to the bus I / F 61.

The read failure diagnosis data is read by the CPU unit 3 via the bus I / F 61. The CPU 31 in the unique function means of the CPU unit 3 collates the read failure diagnosis data received by the CPU unit 3 with the failure diagnosis data stored in the memory (step S66). If the signs of all the bits match as a result of the collation, it is determined that there is no abnormality in the bus with the first failure diagnosis data. Then, it is determined whether or not failure diagnosis has been performed using all failure diagnosis data (step S67). If all failure diagnosis data has not been performed, the CPU 31 receives second failure diagnosis data, for example, “5555h”. The same write / read operations as described above are performed. Finally, if there is no difference in sign even if all 8 fault diagnosis data are written and read, it is determined that there is no abnormality in the bus, the fault diagnosis operation is terminated, and the timer is restarted. To do.

  On the other hand, if there is even one bit with a different sign as a result of the verification of each of the eight fault diagnosis data, it is determined that some abnormality exists in the bus, and the system is secured in accordance with a predetermined sequence. (Step S68).

  As described above, in the PLC device 1 according to the first embodiment, by providing the end cover 6 with the bus I / F, bus access is made to each unit connected between the CPU unit 3 and the end cover 6. Therefore, it is possible to detect a bus abnormality without stopping the system and to stop the system safely. Therefore, it is possible to improve the RAS function and to obtain an effect that the failure diagnosis of the bus signal can be surely and easily performed. Furthermore, it is possible to obtain an effect that the CPU unit 3 can determine whether or not the end cover 6 is attached to the PLC device 1 without providing a dedicated signal line.

  In the first embodiment, the bus access for confirming whether or not the end cover 6 is attached is generated by the CPU unit 3, but it is not necessarily limited to the CPU unit 3 and may be generated by another unit. Needless to say, similar effects can be obtained.

  In the first embodiment, a system in which the I / O unit 4 and the analog unit 5 are mounted between the CPU unit 3 and the end cover 6 has been described as an example. However, the present invention is not necessarily limited to these units. For example, it is needless to say that the same effect can be obtained even in a system in which a unit for controlling an external device or a unit having a specific function such as temperature adjustment or positioning is mounted.

  In the first embodiment, the bus for performing failure detection is described as 16 bits. However, this is not necessarily limited to this, and the number of bits may be large or small. In addition, although the case where eight pieces of failure diagnosis data are used has been described, the number may be eight or more depending on the number of bits of the bus.

  In the first embodiment, it has been described that the system is safely stopped according to a predetermined sequence when it is detected that the end cover 6 is dropped or a bus failure is detected. The stopping method may take any form, such as an emergency stop if it is possible. Further, in the first embodiment, the system is described as being stopped when it is detected that the end cover 6 is dropped or a bus failure is detected, but it is not always necessary to stop the system. For example, it may be possible to notify an operator who is away from the machine tool by operating a predetermined alarm.

  The present invention can be used in a PLC device that controls equipment such as machines in the field of machine tools and the like.

DESCRIPTION OF SYMBOLS 1 PLC apparatus 2 Power supply unit 3 CPU unit 4 I / O unit 5 Analog unit 6 End cover 7 Connector 31 CPU
32 Memory 61 Bus I / F
62 Bus function register 63 Bus failure diagnosis register 621 End cover specific information 622 Mounting position information

Claims (12)

A connector connected to at least the CPU unit by a bus;
Bus interface means connected to the connector and communicating with the CPU unit via the bus;
First storage means connected to the bus interface means and capable of storing end cover specific information and mounting position information sent from the CPU unit;
An end cover comprising: second storage means connected to the bus interface means and capable of writing and reading failure diagnosis data sent from the CPU unit. The CPU unit and the bus interface means communicate with each other at the time of activation so that the end cover specific information stored in the first storage means can be read by the CPU unit, and the mounting position information sent from the CPU unit is the first information. The end cover according to claim 1, wherein the end cover is stored in one storage means. The CPU unit and the bus interface unit communicate with each other at predetermined time intervals based on the mounting position information, and the CPU unit can read the end cover specific information stored in the first storage unit. The end cover according to claim 1. The CPU unit and the bus interface unit communicate with each other at a predetermined time, and write failure diagnosis data sent from the CPU unit in accordance with a write request from the CPU unit to the second storage unit and from the CPU unit. 2. The end cover according to claim 1, wherein the CPU unit can read out the failure diagnosis data stored in the second storage unit according to the read request. A CPU unit that communicates with other units connected by a bus and sends fault diagnosis data and mounting position information; and
A connector connected to the CPU unit by the bus;
Bus interface means connected to the connector and communicating with the CPU unit via the bus;
First storage means connected to the bus interface means and capable of storing end cover specific information and mounting position information sent from the CPU unit;
And a programmable logic controller device comprising a second storage means connected to the bus interface means and capable of writing and reading failure diagnosis data sent from the CPU unit. The CPU unit communicates with the bus interface unit of the end cover at the time of activation, reads end cover specific information from the first storage unit, and stores mounting position information in the first storage unit. The programmable logic controller device according to claim 5. 6. The CPU unit according to claim 5, wherein the CPU unit communicates with the bus interface unit of the end cover based on the mounting position information and reads end cover specific information from the first storage unit at predetermined time intervals. The programmable logic controller device described. At every predetermined time, the CPU unit communicates with the bus interface means of the end cover, makes a write request, writes failure diagnosis data in the second storage means, makes a read request, and makes the second storage. 6. The programmable logic controller device according to claim 5, wherein the failure diagnosis data written in the means is read out. The CPU unit communicates with the bus interface means of the end cover at the time of activation, and stores the mounting position information in the first storage means of the end cover;
A CPU unit communicates with the bus interface means of the end cover that stores the mounting position information to request reading of the end cover specific information stored in the first storage means of the end cover;
Determining that the end cover is attached when the end cover specific information can be read by the read request, and stopping the programmable logic controller device when the end cover specific information cannot be read. A method for confirming whether or not an end cover is mounted. Based on the first pre-stored so the mounting position information in the storage means of the end cover CPU unit communicates with bus interface means of the end cover, and the CPU unit every predetermined time bus interface means of said end cover Performing communication to request reading of end cover specific information stored in the first storage means of the end cover;
Determining that the end cover is attached when the end cover specific information can be read by the read request, and stopping the programmable logic controller device when the end cover specific information cannot be read. A method for confirming whether or not an end cover is mounted. The CPU unit communicates with the bus interface means of the end cover at every predetermined time, makes a write request, and writes failure diagnosis data in the second storage means of the end cover;
The CPU unit communicates with the bus interface means of the end cover and makes a request to read the failure diagnosis data written in the second storage means;
A step of determining that the bus is normal when the failure diagnosis data can be read by the read request, and stopping the programmable logic controller device when the failure diagnosis data cannot be read. A fault diagnosis method for a programmable logic controller device. A step of comparing the failure diagnosis data stored in advance by the CPU unit with the failure diagnosis data read from the second storage means when the failure diagnosis data can be read by the read request;
As a result of the comparison, if they match, it is determined that the bus is normal, and if they do not match, stopping the programmable logic controller device;
The fault diagnosis method for a programmable logic controller device according to claim 11 , further comprising:

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