JP6144348B2 - チップソケットプロトコル上のネットワーク - Google Patents

チップソケットプロトコル上のネットワーク Download PDF

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Publication number
JP6144348B2
JP6144348B2 JP2015533265A JP2015533265A JP6144348B2 JP 6144348 B2 JP6144348 B2 JP 6144348B2 JP 2015533265 A JP2015533265 A JP 2015533265A JP 2015533265 A JP2015533265 A JP 2015533265A JP 6144348 B2 JP6144348 B2 JP 6144348B2
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Japan
Prior art keywords
transaction
interface unit
network interface
initiator
chip
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JP2015533265A
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English (en)
Japanese (ja)
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JP2015535991A (ja
JP2015535991A5 (cg-RX-API-DMAC7.html
Inventor
ブーカル、フィリップ
ルクレー、ジャン−ジャック
ブーティリエ、ボリス
Original Assignee
クゥアルコム・テクノロジーズ・インコーポレイテッド
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Priority claimed from US13/626,758 external-priority patent/US9471538B2/en
Priority claimed from US13/626,766 external-priority patent/US9225665B2/en
Application filed by クゥアルコム・テクノロジーズ・インコーポレイテッド filed Critical クゥアルコム・テクノロジーズ・インコーポレイテッド
Publication of JP2015535991A publication Critical patent/JP2015535991A/ja
Publication of JP2015535991A5 publication Critical patent/JP2015535991A5/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/1735—Network adapters, e.g. SCI, Myrinet
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP2015533265A 2012-09-25 2013-09-24 チップソケットプロトコル上のネットワーク Active JP6144348B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/626,758 US9471538B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
US13/626,758 2012-09-25
US13/626,766 US9225665B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
US13/626,766 2012-09-25
PCT/US2013/061295 WO2014052261A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Publications (3)

Publication Number Publication Date
JP2015535991A JP2015535991A (ja) 2015-12-17
JP2015535991A5 JP2015535991A5 (cg-RX-API-DMAC7.html) 2017-01-26
JP6144348B2 true JP6144348B2 (ja) 2017-06-07

Family

ID=50388890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015533265A Active JP6144348B2 (ja) 2012-09-25 2013-09-24 チップソケットプロトコル上のネットワーク

Country Status (6)

Country Link
EP (2) EP4123468A1 (cg-RX-API-DMAC7.html)
JP (1) JP6144348B2 (cg-RX-API-DMAC7.html)
KR (1) KR101690568B1 (cg-RX-API-DMAC7.html)
CN (1) CN104685480B (cg-RX-API-DMAC7.html)
IN (1) IN2015MN00441A (cg-RX-API-DMAC7.html)
WO (1) WO2014052261A1 (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2529217A (en) 2014-08-14 2016-02-17 Advanced Risc Mach Ltd Transmission control checking for interconnect circuitry
US11436185B2 (en) * 2019-11-15 2022-09-06 Arteris, Inc. System and method for transaction broadcast in a network on chip
CN116711281B (zh) * 2020-12-30 2025-08-15 华为技术有限公司 一种片上系统及相关方法
CN117389931B (zh) * 2023-12-12 2024-05-03 芯动微电子科技(武汉)有限公司 适用于总线访问gpu核内存储器的协议转换模块及方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477646B1 (en) * 1999-07-08 2002-11-05 Broadcom Corporation Security chip architecture and implementations for cryptography acceleration
US6826191B1 (en) * 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US8087064B1 (en) * 2000-08-31 2011-12-27 Verizon Communications Inc. Security extensions using at least a portion of layer 2 information or bits in the place of layer 2 information
WO2002069575A1 (en) * 2001-02-28 2002-09-06 Gotham Networks, Inc. Methods and apparatus for network routing device
US7277449B2 (en) * 2002-07-29 2007-10-02 Freescale Semiconductor, Inc. On chip network
US6996651B2 (en) * 2002-07-29 2006-02-07 Freescale Semiconductor, Inc. On chip network with memory device address decoding
US6671275B1 (en) * 2002-08-02 2003-12-30 Foundry Networks, Inc. Cross-point switch with deadlock prevention
CN1689312B (zh) * 2002-10-08 2010-04-14 皇家飞利浦电子股份有限公司 用于建立事务的集成电路和方法
US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
JP2007531101A (ja) * 2004-03-26 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 集積回路及びトランザクション中止方法
US7716409B2 (en) * 2004-04-27 2010-05-11 Intel Corporation Globally unique transaction identifiers
CN101379841A (zh) * 2005-09-13 2009-03-04 Ist国际公司 为提供异种网络之间的小包连通性和组分和小包之系统和方法
WO2007033363A2 (en) * 2005-09-13 2007-03-22 Ist International, Inc. System and method for providing packet connectivity between heterogeneous networks
US20070245033A1 (en) * 2006-04-14 2007-10-18 Microsoft Corporation Link layer discovery and diagnostics
JP2010500807A (ja) * 2006-08-08 2010-01-07 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子装置及び通信制御方法
GB2450148A (en) * 2007-06-14 2008-12-17 Advanced Risc Mach Ltd Controlling write transactions between initiators and recipients via interconnect logic
US8285912B2 (en) * 2009-08-07 2012-10-09 Arm Limited Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure
FR2951342B1 (fr) * 2009-10-13 2017-01-27 Arteris Inc Reseau sur puce a latence nulle
EP2333830B1 (en) * 2009-12-07 2014-09-03 STMicroelectronics (Research & Development) Limited a package comprising a first and a second die coupled by a multiplexed bus
EP2388707B1 (en) * 2010-05-20 2014-03-26 STMicroelectronics (Grenoble 2) SAS Interconnection method and device, for example for systems-on-chip
JPWO2011148925A1 (ja) * 2010-05-24 2013-07-25 日本電気株式会社 半導体装置とネットワークルーティング方法とシステム
FR2961048B1 (fr) * 2010-06-03 2013-04-26 Arteris Inc Reseau sur puce avec caracteristiques de qualite-de-service
EP2444903A1 (en) * 2010-09-29 2012-04-25 STMicroelectronics (Grenoble 2) SAS A transaction reordering arrangement

Also Published As

Publication number Publication date
IN2015MN00441A (cg-RX-API-DMAC7.html) 2015-09-11
EP4123468A1 (en) 2023-01-25
EP2901294A4 (en) 2016-08-10
CN104685480A (zh) 2015-06-03
KR101690568B1 (ko) 2016-12-28
EP2901294A1 (en) 2015-08-05
JP2015535991A (ja) 2015-12-17
WO2014052261A1 (en) 2014-04-03
CN104685480B (zh) 2017-07-14
KR20150063433A (ko) 2015-06-09

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