JP6143950B2 - ダイ上の積層再分配層 - Google Patents
ダイ上の積層再分配層 Download PDFInfo
- Publication number
- JP6143950B2 JP6143950B2 JP2016515942A JP2016515942A JP6143950B2 JP 6143950 B2 JP6143950 B2 JP 6143950B2 JP 2016515942 A JP2016515942 A JP 2016515942A JP 2016515942 A JP2016515942 A JP 2016515942A JP 6143950 B2 JP6143950 B2 JP 6143950B2
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- Japan
- Prior art keywords
- layer
- metal
- metal redistribution
- redistribution layer
- ubm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000010410 layer Substances 0.000 claims description 790
- 229910052751 metal Inorganic materials 0.000 claims description 393
- 239000002184 metal Substances 0.000 claims description 393
- 239000010949 copper Substances 0.000 claims description 65
- 238000001465 metallisation Methods 0.000 claims description 65
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 64
- 229910052802 copper Inorganic materials 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 58
- 239000004065 semiconductor Substances 0.000 claims description 53
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 52
- 239000012790 adhesive layer Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 37
- 229910052759 nickel Inorganic materials 0.000 claims description 26
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 claims description 22
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 17
- 238000004891 communication Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 description 38
- 230000015556 catabolic process Effects 0.000 description 30
- 238000006731 degradation reaction Methods 0.000 description 30
- 238000002161 passivation Methods 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 11
- FEBFYWHXKVOHDI-UHFFFAOYSA-N [Co].[P][W] Chemical compound [Co].[P][W] FEBFYWHXKVOHDI-UHFFFAOYSA-N 0.000 description 9
- 239000002131 composite material Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000002401 inhibitory effect Effects 0.000 description 7
- 229920002577 polybenzoxazole Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 229910016347 CuSn Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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Description
本出願は、その内容の全体が参照により本明細書に組み込まれている、2013年8月6日に米国特許商標庁に出願された非仮出願第13/960,110号の優先権および恩典を主張する。
いくつかの新規の特徴は、基板と、基板に結合されるいくつかの金属層および誘電体層と、複数の金属層のうちの1つに結合されるパッドと、パッドに結合される第1の金属再分配層と、第1の金属再分配層に結合される第2の金属再分配層とを含む半導体デバイス(たとえば、ダイ)に関連する。第2の金属再分配層は、コバルトタングステンリン材料を含む。いくつかの実装態様では、第1の金属再分配層は銅層である。いくつかの実装態様では、半導体デバイスはさらに、第1のアンダーバンプメタライゼーション(UBM)層と、第2のアンダーバンプメタライゼーション(UBM)層とを含む。
図2は、急速エレクトロマイグレーション(EM)劣化に対してより耐性があるダイの側面図の一例を示す。具体的には、図2は、基板201と、いくつかの金属層および誘電体層202と、パッド204と、パッシベーション層206と、第1の絶縁層208と、第1の金属再分配層(RDL)210と、第2の金属再分配層(RDL)211と、第2の絶縁層214とを含むダイ200の側面図を示す。また、図2は、ダイ200上のハンダボール216も示す。具体的には、ハンダボール216は第2の金属再分配層211に結合される。図2に示されるように、パッド204は、下位金属層202のうちの少なくとも1つに結合される。第1の金属再分配層210はパッド204に結合される。第2の金属再分配層211は、第1の金属再分配層210に結合される。パッド204、第1の金属再分配層210および第2の金属再分配層211は、少なくとも1つの導電性材料から形成される。たとえば、パッド204はアルミニウム材料とすることができる。
図2〜図5は、銅拡散に対してより耐性が高いように構成されるダイの概念的な例を示す。図6〜図9は、銅拡散に対してより耐性が高いように構成されるダイのより詳細な例を示す。具体的には、図6〜図9は、いくつかの再分配層および/またはいくつかのUBM層を含むダイを示しており、接着層(たとえば、接着のための手段)が図示されている。
図10A〜図10Eは、いくつかの再分配層および/またはいくつかのアンダーバンプメタライゼーション(UBM)層を含むダイを設けるための例示的なシーケンスを示す。いくつかの実装態様では、図10A〜図10Eのシーケンスを用いて、図2〜図9のダイまたは本開示において説明される他のダイを設ける/製造することができる。
図11は、積層再分配層および/または積層UBM層を含む1つまたは複数のダイを設ける/製造するための例示的な方法を示す。いくつかの実装態様では、図11の方法を用いて、図2〜図9のダイまたは本開示において説明される他のダイを設ける/製造することができる。
図12は、上記の半導体デバイス、集積回路、ダイ、インターポーザ、またはパッケージのうちのいずれかと一体に構成することができる様々の電子デバイスを示す。たとえば、モバイル電話1202、ラップトップコンピュータ1204、および定置端末1206が、本明細書において説明されるような集積回路(IC)1200を含むことができる。IC1200は、たとえば、本明細書において説明されるような集積回路、ダイ、またはパッケージのいずれかとすることができる。図12に示されるデバイス1202、1204、1206は例示にすぎない。限定はしないが、モバイルデバイス、ハンドヘルドパーソナル通信システム(PCS)ユニット、携帯情報端末などのポータブルデータユニット、GPS対応デバイス、ナビゲーションデバイス、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンタテイメントユニット、メータ読取り機器などの定置データユニット、通信デバイス、スマートフォン、タブレットコンピュータ、またはデータもしくはコンピュータ命令の記憶もしくは取り出しを行う任意の他のデバイス、またはそれらの任意の組合せを含む、他の電子デバイスが、IC1200を搭載することもできる。
101 基板
102 いくつかの金属層および誘電体層
104 パッド
106 パッシベーション層
108 第1の絶縁層
110 金属再分配層(RDL)
114 第2の絶縁層
116 ハンダボール
118 RDL/ボール領域
200 ダイ
201 基板
202 いくつかの金属層および誘電体層
204 パッド
206 パッシベーション層
208 第1の絶縁層
210 第1の金属再分配層(RDL)
211 第2の金属再分配層(RDL)
214 第2の絶縁層
216 ハンダボール
300 ダイ
301 基板
302 いくつかの金属層および誘電体層
304 パッド
306 パッシベーション層
308 第1の絶縁層
310 第1の金属再分配層(RDL)
311 第2の金属再分配層(RDL)
313 第1のアンダーバンプメタライゼーション(UBM)層
314 第2の絶縁層
315 第2のアンダーバンプメタライゼーション(UBM)層
316 ハンダボール
400 ダイ
401 基板
402 いくつかの金属層および誘電体層
404 パッド
406 パッシベーション層
408 第1の絶縁層
410 第1の金属再分配層(RDL)
411 第2の金属再分配層(RDL)
414 第2の絶縁層
416 ハンダボール
500 ダイ
501 基板
502 いくつかの金属層および誘電体層
504 パッド
506 パッシベーション層
508 第1の絶縁層
510 第1の金属再分配層(RDL)
511 第2の金属再分配層(RDL)
513 第1のアンダーバンプメタライゼーション(UBM)層
514 第2の絶縁層
515 第2のアンダーバンプメタライゼーション(UBM)層
516 ハンダボール
600 ダイ
601 基板
602 いくつかの金属層および誘電体層
604 パッド
606 パッシベーション層
608 第1の絶縁層
609 接着層
610 第1の金属再分配層(RDL)
611 第2の金属再分配層(RDL)
614 第2の絶縁層
616 ハンダボール
700 ダイ
701 基板
702 いくつかの金属層および誘電体層
704 パッド
706 パッシベーション層
708 第1の絶縁層
709 接着層
710 第1の金属再分配層(RDL)
711 第2の金属再分配層(RDL)
713 第1のアンダーバンプメタライゼーション(UBM)層
714 第2の絶縁層
715 第2のアンダーバンプメタライゼーション(UBM)層
716 ハンダボール
800 ダイ
801 基板
802 いくつかの金属層および誘電体層
804 パッド
806 パッシベーション層
808 第1の絶縁層
809 接着層
810 第1の金属再分配層(RDL)
811 第2の金属再分配層(RDL)
812 第3の金属再分配層(RDL)
814 第2の絶縁層
816 ハンダボール
900 ダイ
901 基板
902 いくつかの金属層および誘電体層
904 パッド
906 パッシベーション層
908 第1の絶縁層
909 接着層
910 第1の金属再分配層(RDL)
911 第2の金属再分配層(RDL)
912 第3の金属再分配層(RDL)
913 第1のアンダーバンプメタライゼーション(UBM)層
914 第2の絶縁層
915 第2のアンダーバンプメタライゼーション(UBM)層
1001 基板
1002 下位金属層および誘電体層
1004 パッド
1006 パッシベーション層
1008 第1の絶縁層
1009 空洞
1010 第1の金属再分配層
1011 第2の金属再分配層
1012 第2の絶縁層
1013 空洞
1014 第1のアンダーバンプメタライゼーション(UBM)層
1015 第2のアンダーバンプメタライゼーション(UBM)層
1016 ハンダボール
1200 集積回路(IC)
1202 モバイル電話
1204 ラップトップコンピュータ
1206 定置端末
Claims (26)
- 半導体デバイスであって、
基板と、
前記基板に結合された複数の金属層および複数の誘電体層と、
前記複数の金属層のうちの1つに結合されたパッドと、
前記パッドに結合された第1の金属再分配層と、
前記第1の金属再分配層に結合された第2の金属再分配層と、
第1のアンダーバンプメタライゼーション(UBM)層と、を備え、
前記第2の金属再分配層はコバルトタングステンリン材料を含み、
前記第1のUBM層はコバルトタングステンリン材料を含む、半導体デバイス。 - 前記第1の金属再分配層は銅層である、請求項1に記載の半導体デバイス。
- 第2のアンダーバンプメタライゼーション(UBM)層をさらに備え、前記第2のUBM層はコバルトタングステンリン材料を含む、請求項1に記載の半導体デバイス。
- 前記第1の金属再分配層と前記パッドとの間に接着層をさらに備え、前記接着層は前記第1の金属再分配層を前記パッドに結合するように構成された、請求項1に記載の半導体デバイス。
- 前記半導体デバイスは、少なくともダイ、ダイパッケージ、集積回路(IC)、ウェハおよび/またはインターポーザのうちの1つである、請求項1に記載の半導体デバイス。
- 前記半導体デバイスは、音楽プレーヤ、ビデオプレーヤ、エンタテイメントユニット、ナビゲーションデバイス、通信デバイス、モバイルデバイス、モバイルフォン、スマートフォン、携帯情報端末、定置端末、タブレットコンピュータ、および/またはラップトップコンピュータのうちの少なくとも1つに組み込まれる、請求項1に記載の半導体デバイス。
- 半導体デバイスであって、
基板と、
前記基板に結合された複数の金属層および複数の誘電体層と、
前記複数の金属層のうちの1つに結合されたパッドと、
前記パッドに結合された第1の金属再分配層と、
前記第1の金属再分配層に結合された第2の金属再分配層と、
前記第2の金属再分配層に結合された第3の金属再分配層と、
第1のアンダーバンプメタライゼーション(UBM)層と、を備え、
前記第1の金属再分配層、前記第2の金属再分配層または前記第3の金属再分配層のうちの少なくとも1つは、コバルトタングステンリン材料を含み、
前記第1のUBM層はコバルトタングステンリン材料を含む、半導体デバイス。 - 前記第1の金属再分配層、前記第2の金属再分配層または前記第3の金属再分配層のうちの少なくとも1つは、銅層またはニッケル層を含む、請求項7に記載の半導体デバイス。
- 第2のアンダーバンプメタライゼーション(UBM)層をさらに備え、前記第2のUBM層はコバルトタングステンリン材料を含む、請求項7に記載の半導体デバイス。
- 第2のアンダーバンプメタライゼーション(UBM)層をさらに備え、前記第2のUBM層は銅層である、請求項7に記載の半導体デバイス。
- 前記第1の金属再分配層と前記パッドとの間に接着層をさらに備え、前記接着層は前記第1の金属再分配層を前記パッドに結合するように構成された、請求項7に記載の半導体デバイス。
- 前記半導体デバイスは、少なくともダイ、ダイパッケージ、集積回路(IC)、ウェハおよび/またはインターポーザのうちの1つである、請求項7に記載の半導体デバイス。
- 前記半導体デバイスは、音楽プレーヤ、ビデオプレーヤ、エンタテイメントユニット、ナビゲーションデバイス、通信デバイス、モバイルデバイス、モバイルフォン、スマートフォン、携帯情報端末、定置端末、タブレットコンピュータ、および/またはラップトップコンピュータのうちの少なくとも1つに組み込まれる、請求項7に記載の半導体デバイス。
- 半導体デバイスを設けるための方法であって、
基板を設けるステップと、
前記基板に結合された複数の金属層および複数の誘電体層を設けるステップと、
前記複数の金属層のうちの1つに結合されたパッドを設けるステップと、
前記パッドに結合された第1の金属再分配層を設けるステップと、
前記第1の金属再分配層に結合された第2の金属再分配層を設けるステップと、
第1のアンダーバンプメタライゼーション(UBM)層を設けるステップと、
を含み、
前記第2の金属再分配層はコバルトタングステンリン材料を含み、
前記第1のUBM層はコバルトタングステンリン材料を含む、半導体デバイスを設けるための方法。 - 前記第1の金属再分配層は銅層である、請求項14に記載の方法。
- 第2のアンダーバンプメタライゼーション(UBM)層を設けるステップをさらに含み、前記第2のUBM層はコバルトタングステンリン材料を含む、請求項14に記載の方法。
- 前記第1の金属再分配層と前記パッドとの間に接着層を設けるステップをさらに含み、前記接着層は前記第1の金属再分配層を前記パッドに結合するように構成された、請求項14に記載の方法。
- 前記半導体デバイスは、少なくともダイ、ダイパッケージ、集積回路(IC)、ウェハおよび/またはインターポーザのうちの1つである、請求項14に記載の方法。
- 前記半導体デバイスは、音楽プレーヤ、ビデオプレーヤ、エンタテイメントユニット、ナビゲーションデバイス、通信デバイス、モバイルデバイス、モバイルフォン、スマートフォン、携帯情報端末、定置端末、タブレットコンピュータ、および/またはラップトップコンピュータのうちの少なくとも1つに組み込まれる、請求項14に記載の方法。
- 半導体デバイスを設けるための方法であって、
基板を設けるステップと、
前記基板に結合された複数の金属層および複数の誘電体層を設けるステップと、
前記複数の金属層のうちの1つに結合されたパッドを設けるステップと、
前記パッドに結合された第1の金属再分配層を設けるステップと、
前記第1の金属再分配層に結合された第2の金属再分配層を設けるステップと、
前記第2の金属再分配層に結合された第3の金属再分配層を設けるステップと、
第1のアンダーバンプメタライゼーション(UBM)層を設けるステップと、
を含み、
前記第1の金属再分配層、前記第2の金属再分配層または前記第3の金属再分配層のうちの少なくとも1つを設けるステップは、コバルトタングステンリン材料を設けるステップをさらに含み、
前記第1のUBM層はコバルトタングステンリン材料を含む、半導体デバイスを設けるための方法。 - 前記第1の金属再分配層、前記第2の金属再分配層または前記第3の金属再分配層のうちの少なくとも1つは、銅層またはニッケル層である、請求項20に記載の方法。
- 第2のアンダーバンプメタライゼーション(UBM)層を設けるステップをさらに含み、前記第2のUBM層はコバルトタングステンリン材料を含む、請求項20に記載の方法。
- 第2のアンダーバンプメタライゼーション(UBM)層を設けるステップをさらに含み、前記第2のUBM層は銅層である、請求項20に記載の方法。
- 前記第1の金属再分配層と前記パッドとの間に接着層を設けるステップをさらに含み、前記接着層は前記第1の金属再分配層を前記パッドに結合するように構成された、請求項20に記載の方法。
- 前記半導体デバイスは、少なくともダイ、ダイパッケージ、集積回路(IC)、ウェハおよび/またはインターポーザのうちの1つである、請求項20に記載の方法。
- 前記半導体デバイスは、音楽プレーヤ、ビデオプレーヤ、エンタテイメントユニット、ナビゲーションデバイス、通信デバイス、モバイルデバイス、モバイルフォン、スマートフォン、携帯情報端末、定置端末、タブレットコンピュータ、および/またはラップトップコンピュータのうちの少なくとも1つに組み込まれる、請求項20に記載の方法。
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Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9419156B2 (en) * | 2013-08-30 | 2016-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package and method for integration of heterogeneous integrated circuits |
US20150115442A1 (en) * | 2013-10-31 | 2015-04-30 | Infineon Technologies Ag | Redistribution layer and method of forming a redistribution layer |
US9263302B2 (en) | 2014-02-21 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via structure for packaging and a method of forming |
US9865798B2 (en) * | 2015-02-24 | 2018-01-09 | Qualcomm Incorporated | Electrode structure for resistive memory device |
CN105097726B (zh) * | 2015-06-16 | 2019-03-12 | 合肥矽迈微电子科技有限公司 | 封装结构及封装方法 |
KR20170068095A (ko) * | 2015-12-09 | 2017-06-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9935024B2 (en) | 2016-04-28 | 2018-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor structure |
TWI744498B (zh) * | 2018-03-05 | 2021-11-01 | 矽品精密工業股份有限公司 | 基板結構及其製法 |
CN109390127B (zh) | 2018-11-12 | 2024-01-30 | 矽力杰半导体技术(杭州)有限公司 | 可支撑式封装器件和封装组件 |
GB2584681B (en) * | 2019-06-11 | 2021-12-29 | Rockley Photonics Ltd | Interposer |
US11581262B2 (en) * | 2019-10-02 | 2023-02-14 | Qualcomm Incorporated | Package comprising a die and die side redistribution layers (RDL) |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100313706B1 (ko) * | 1999-09-29 | 2001-11-26 | 윤종용 | 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
JP2003045877A (ja) * | 2001-08-01 | 2003-02-14 | Sharp Corp | 半導体装置およびその製造方法 |
US6743660B2 (en) * | 2002-01-12 | 2004-06-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method of making a wafer level chip scale package |
JP3804797B2 (ja) | 2002-10-11 | 2006-08-02 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
KR100541396B1 (ko) * | 2003-10-22 | 2006-01-11 | 삼성전자주식회사 | 3차원 ubm을 포함하는 솔더 범프 구조의 형성 방법 |
US7207096B2 (en) * | 2004-01-22 | 2007-04-24 | International Business Machines Corporation | Method of manufacturing high performance copper inductors with bond pads |
US7446422B1 (en) | 2005-04-26 | 2008-11-04 | Amkor Technology, Inc. | Wafer level chip scale package and manufacturing method for the same |
US7397121B2 (en) | 2005-10-28 | 2008-07-08 | Megica Corporation | Semiconductor chip with post-passivation scheme formed over passivation layer |
US7863183B2 (en) * | 2006-01-18 | 2011-01-04 | International Business Machines Corporation | Method for fabricating last level copper-to-C4 connection with interfacial cap structure |
US8367543B2 (en) * | 2006-03-21 | 2013-02-05 | International Business Machines Corporation | Structure and method to improve current-carrying capabilities of C4 joints |
US7808105B1 (en) * | 2007-04-13 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
JP4585561B2 (ja) | 2007-09-04 | 2010-11-24 | 株式会社東芝 | 半導体装置の製造方法 |
US8232190B2 (en) * | 2007-10-01 | 2012-07-31 | International Business Machines Corporation | Three dimensional vertical E-fuse structures and methods of manufacturing the same |
US7863742B2 (en) * | 2007-11-01 | 2011-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Back end integrated WLCSP structure without aluminum pads |
US8058726B1 (en) | 2008-05-07 | 2011-11-15 | Amkor Technology, Inc. | Semiconductor device having redistribution layer |
KR101483273B1 (ko) | 2008-09-29 | 2015-01-16 | 삼성전자주식회사 | 구리 패드와 패드 장벽층을 포함하는 반도체 소자와 그의 배선 구조 및 그 제조 방법들 |
US20100099250A1 (en) * | 2008-10-21 | 2010-04-22 | Samsung Electronics Co., Ltd. | Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers |
US8659155B2 (en) * | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
US8242012B2 (en) | 2010-07-28 | 2012-08-14 | International Business Machines Corporation | Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure |
US8546254B2 (en) * | 2010-08-19 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
US8039385B1 (en) * | 2010-09-13 | 2011-10-18 | Texas Instruments Incorporated | IC devices having TSVS including protruding tips having IMC blocking tip ends |
JP2012204788A (ja) | 2011-03-28 | 2012-10-22 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US8786081B2 (en) * | 2011-07-27 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and device for circuit routing by way of under-bump metallization |
JP6144003B2 (ja) * | 2011-08-29 | 2017-06-07 | 富士通株式会社 | 配線構造及びその製造方法並びに電子装置及びその製造方法 |
JP2013073981A (ja) * | 2011-09-26 | 2013-04-22 | Toshiba Corp | 半導体装置及びその製造方法 |
US8659144B1 (en) * | 2011-12-15 | 2014-02-25 | Marvell International Ltd. | Power and ground planes in package substrate |
US9437564B2 (en) * | 2013-07-09 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of fabricating same |
US9607921B2 (en) * | 2012-01-12 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package interconnect structure |
US9082870B2 (en) * | 2013-03-13 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of packaging semiconductor devices |
US9018757B2 (en) * | 2013-07-16 | 2015-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for forming bump structures over wide metal pad |
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