JP6133580B2 - Transistor drive control circuit, transistor drive control system, and transistor drive control method - Google Patents

Description

  The present invention relates to a transistor drive control circuit, a transistor drive control system, and a transistor drive control method for driving a transistor from an off state to an on state.

  Transistors are used as switches in various circuits. For example, an ORing circuit provided at the output terminal of each power supply apparatus operating in parallel is one of the circuits using the above-described transistors.

  The ORing circuit includes a field effect transistor (FET) in the middle of a power supply path from each power supply device to the electronic device. The ORing circuit operates normally when one of the power supplies operating in parallel fails, such as when a current flows back into one of the power supplies and draws current from the other power supplies operating in parallel. The FET is controlled to be turned on / off so that the existing power supply device does not stop.

  As a technique related to on / off control of transistors in the above-described ORing circuit, Patent Document 1 discloses an ORING power supply circuit including a diode, a capacitor, a resistor, and a Zener diode.

  Further, as a related technology of elements used in the ORING control circuit, Patent Document 2 includes a resistor, a power supply capacitor, a semiconductor switch element, and a Zener diode for preventing overcharge of the power supply capacitor. The circuit is open to the public.

  Patent Document 3 discloses, as a related technology of an element used in an ORING control circuit, an FET of an amplifier circuit, a shunt regulator IC, a resistor, and a capacitor, and an output of the shunt regulator IC at the gate terminal of the FET. A bias circuit that applies a voltage to stabilize the operation of the FET has been disclosed.

  In Patent Document 4, as a related technique of an element used in an ORING control circuit, a voltage dividing resistor is connected in parallel to a backflow element diode, and the voltage at the collector terminal of the power transistor is passed through a monitoring input resistor. The circuit applied to the monitoring input signal input terminal of the microprocessor is disclosed.

JP 2010-110077 A JP 2011-172342 A Japanese Unexamined Patent Publication No. 08-213853 JP 2007-071840

  When a transistor is used as a switch, it takes time to change the transistor from off to on. Regarding this time, for example, the above-described ORing circuit has the following problems.

  When one of the power supply units operating in parallel is overvoltaged and the voltage on the drain terminal side of the FET of the ORing circuit becomes high, the ORING control IC that controls the ORing circuit turns off the FET to supply power to prevent backflow current. Block the path. Next, when the overvoltage state is released and the voltage on the drain terminal side of the ORing FET becomes low, the ORING control IC turns on the ORing FET and reconnects the power feeding path.

  At this time, if the voltage of the gate terminal necessary for driving the ORing FET is high, it takes time to turn on the ORing FET, resulting in a problem that the period of power loss of the FET becomes long. The techniques disclosed in Patent Documents 1 to 4 are not intended to solve the above-described problem of switching time of transistors.

  An object of the present invention is to provide a transistor drive control circuit, a transistor drive control system, and a transistor drive control method that solve the above problems.

  A transistor drive control circuit according to an embodiment of the present invention outputs a voltage Vl lower than a drive voltage Vd of a transistor functioning as a switch between a source terminal and a drain terminal, and a voltage within a range of a voltage Vh higher than Vl. Bias for applying a voltage to the gate terminal of the transistor by adding a positive bias voltage Vb greater than Vd−Vh and smaller than Vd−Vl to the output voltage of the control means and the control means Applying means.

  The transistor drive control method according to an embodiment of the present invention provides a control voltage within a range of a voltage Vl lower than a drive voltage Vd of a transistor functioning as a switch between a source terminal and a drain terminal, and a voltage Vh higher than Vl. On the other hand, a positive bias voltage Vb larger than Vd−Vh and smaller than Vd−Vl is added, and a voltage is applied to the gate terminal of the transistor.

  The present invention shortens the driving time until the transistor is turned on from the off state.

It is a block diagram which shows the structure of the transistor drive control system of 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the 1st Embodiment of this invention. It is a time transition of the voltage of each site | part in 1st Embodiment of this invention. It is a block diagram which shows the structure of the transistor drive control system of 2nd Embodiment of this invention. It is a block diagram which shows the structure of the transistor drive control system of 3rd Embodiment of this invention. It is a block diagram which shows the structure of the transistor drive circuit of 4th Embodiment of this invention.

  A first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a transistor drive control system 1 of the present embodiment.

  The transistor drive control system 1 of the present embodiment includes transistor drive control circuits 10 to 20, FETs 30 to 40, a power supply device 1 power supply terminal 50, a power supply device 2 power supply terminal 51, and an electronic device power reception terminal 52. ing.

  The power supply device 1 power supply terminal 50 is connected to the power supply output of the power supply device 1 (not shown), and the power supply device 2 power supply terminal 51 is connected to the power supply output of the power supply device 2 (not shown). The power supply outputs of the power supply devices 1 and 2 are connected in parallel to the electronic device power receiving terminal 52 through the transistor drive control circuits 10 to 20 and the FETs 30 to 40, respectively. The power output of the power supply devices 1 and 2 input to the electronic device power receiving terminal 52 is supplied to an electronic device (not shown).

  The FETs 30 to 40 include source terminals 300 to 400, drain terminals 301 to 401, and gate terminals 302 to 402, respectively. The FETs 30 to 40 are functionally equivalent. When the voltage applied to the gate terminal 302 becomes equal to or higher than the drive voltage Vd of the FET 30, the FET 30 electrically connects the source terminal and the drain terminal, and the voltage applied to the gate terminal 302 is less than the drive voltage Vd of the FET 30. In this case, the source terminal and the drain terminal are electrically cut off.

  The transistor drive control circuit 10 includes a bias applying unit 11 and a control unit 12. The transistor drive control circuit 20 is also functionally equivalent to the transistor drive control circuit 10.

  The bias applying unit 11 includes an electronic circuit 110 and a Zener diode 113, and applies an output voltage obtained by connecting the electronic circuit 110 and the Zener diode 113 in parallel to the gate terminal 302 of the FET 30.

  The electronic circuit 110 is a circuit in which a diode 111 and a resistor 112 are connected in series, and receives a power supply output from the power supply device 1 power supply terminal 50. The Zener diode 113 inputs the output voltage of the control unit 12.

  Since the potential of the power supply device 1 power supply terminal 50 is higher than the potential of the output of the control unit 12, the voltage applied to the gate terminal 302 is a bias corresponding to the Zener voltage applied to the Zener diode 113 with respect to the output of the control unit 12. The voltage Vb is applied.

  The controller 12 outputs a voltage between a minimum output voltage Vl having a value lower than the drive voltage Vd and a maximum output voltage Vh having a value higher than Vl. The control unit 12 monitors the potential difference between the source terminal 300 and the drain terminal 301 of the FET 30 and outputs a voltage for controlling the driving of the FET 30 based on the value of the potential difference. When the potential difference between the source terminal 300 and the drain terminal 301 is larger than 0, that is, when the potential on the source terminal side is larger, the control unit 12 outputs the maximum output voltage Vh, and the source terminal 300 and the drain terminal 301 When the potential difference between is less than 0, the voltage of the lowest output voltage Vl is output. In many cases, the value of Vl is generally set to 0 at the ground level.

The bias voltage Vb, the drive voltage Vd, the minimum output voltage Vl, and the maximum output voltage Vh are set to satisfy the following relationship.

When Vd ≧ Vh Vd−Vh <Vb <Vd−Vl
When Vd <Vh 0 <Vb <Vd-Vl

When the control unit 12 outputs the maximum output voltage Vh, a voltage of Vh + Vb to which the bias voltage Vb is added by the bias application unit 11 is applied to the gate terminal 302. In this case, since the value of Vh + Vb becomes larger than the drive voltage Vd, the FET 30 is turned on.

  When the control unit 12 outputs the minimum output voltage Vl, a voltage of Vl + Vb to which the bias voltage Vb is added by the bias application unit 11 is applied to the gate terminal 302. In this case, since the value of Vl + Vb is smaller than the drive voltage Vd, the FET 30 is turned off.

  That is, the control unit 12 turns on the FET 30 in a normal state in which the potential difference between the source terminal 300 and the drain terminal 301 is greater than 0, and conducts the power supply path from the power supply device 1 to the electronic device. In an abnormal state in which the potential difference between the drain terminal 301 and the drain terminal 301 is 0 or less, the FET 30 is controlled to be turned off so that current does not flow backward to the power supply device 1 side.

  In the present embodiment, when the voltage applied with the bias voltage Vb by the bias application unit 11 is applied to the gate terminal 302, the output voltage of the control unit 12 is directly applied to the gate terminal 302 without the bias application unit 11. FIG. 3 shows the time transition of the voltage at each part when applied.

  In the state where the potential difference between the source terminal 300 and the drain terminal 301 is 0 or less and the FET 30 is turned off by the control unit 12, the output voltage of the control unit 12 is applied to the gate terminal 302 as it is. The voltage applied to is Vl. Similarly, when the voltage applied with the bias voltage Vb from the bias applying unit 11 is applied to the gate terminal 302 in a state in which the FET 30 is turned off by the control unit 12, the voltage applied to the gate terminal 302 is Vl + Vb.

  In this case, after the state where the potential difference between the source terminal 300 and the drain terminal 301 is zero or less is eliminated, the driving time t0 of the FET 30 when the bias applying unit 11 is not provided, and the FET 30 when the bias applying unit 11 is provided. A relationship of t1 <t0 is established between the driving time t1 and the driving time t1, as shown in FIG.

  Next, the operation of this embodiment will be described in detail with reference to the flowchart of FIG.

  An overvoltage is generated at the power supply device 2 power supply terminal 51, and the potential of the drain terminal 301 of the FET 30 becomes higher than the potential of the source terminal 300 (S101). The control unit 12 reduces its own output voltage to the minimum output voltage Vl, reduces the voltage of the gate terminal 302 of the FET 30 to Vl + Vb, turns off the FET 30, and supplies power from the power supply device 1 to the electronic device. Stop (S102).

  When the overvoltage state of the power supply apparatus 2 power supply terminal 51 is not released (No in S103), the process returns to S102. When the overvoltage state of the power supply device 2 power supply terminal 51 is released (Yes in S103), the control unit 12 increases its output voltage from the minimum output voltage Vl and increases the voltage of the gate terminal 302 of the FET 30 ( S104).

  When the voltage of the gate terminal 302 does not reach the drive voltage Vd of the FET 30 (No in S105), the process returns to S104. When the voltage of the gate terminal 302 rises to the drive voltage Vd of the FET 30 (Yes in S105), the FET 30 is turned on, the power supply from the power supply device 1 to the electronic device is resumed (S106), and the entire process ends. .

  This embodiment has an effect of shortening the driving time until the transistor is turned on from the off state in the system in which the transistor is on / off controlled. The reason is that the bias application unit 11 adds the bias voltage Vb to the output voltage from the control unit 12 so that the voltage applied to the gate terminal 302 with the FET 30 turned off is equal to the bias voltage Vb. This is because the time taken for the control unit 12 to increase the voltage of the gate terminal 302 to the drive voltage Vd of the FET 30 in order to turn on the FET 30 is shortened.

  If the time until the control unit 12 turns the FET 30 from off to on is long, the amount of power loss that occurs when the FET 30 is off increases, but this embodiment can reduce the amount of power loss described above. It becomes.

In addition, the present embodiment is not limited to the system of the ORing circuit provided at the output terminal of the power supply devices connected in parallel as described above. The present embodiment can be applied to any system as long as the system performs on / off control of the transistor as a switch circuit.
<Second Embodiment>
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 4 is a block diagram showing the configuration of the transistor drive control system according to the second embodiment of the present invention.

The configuration of this embodiment is the same as that of the first embodiment except that the Zener diode 113 in the first embodiment is replaced with a shunt regulator 114. The operation and effect of this embodiment are almost the same as those of the first embodiment. However, by using the shunt regulator 114, the bias voltage applied by the bias applying unit 11 is compared with that of the first embodiment. Since the variation is reduced, the on / off operation of the FET 30 is more stable.
<Third Embodiment>
Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 5 is a block diagram showing a configuration of a transistor drive control system according to the third embodiment of the present invention.

The configuration of this embodiment is the same as that of the first embodiment except that the Zener diode 113 in the first embodiment is replaced with an electronic circuit 115 in which a resistor 116 and a capacitor 117 are connected in parallel. . The operation and effects of this embodiment are also substantially the same as those of the first embodiment. In the present embodiment, the bias voltage applied by the bias application unit 11 is a voltage applied to the resistor 116 when the output voltage of the power supply device 1 is divided by the resistor 112 and the resistor 116. Therefore, the bias voltage value can be set in detail by adjusting the resistance value of the resistor 116.
<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a block diagram showing a configuration of a transistor drive control circuit according to the fourth embodiment of the present invention.

  The transistor drive control circuit 10 of the present embodiment includes a bias application unit 11 and a control unit 12.

  The control unit 12 outputs a voltage Vl lower than the drive voltage Vd of the transistor 30 functioning as a switch between the source terminal 300 and the drain terminal 301 and a voltage within a range of the voltage Vh higher than the Vl.

  The bias applying unit 11 adds a positive bias voltage Vb that is larger than Vd−Vh and smaller than Vd−Vl to the output voltage of the control unit 12, and applies a voltage to the gate terminal 302 of the transistor 30. Apply.

  As in the first to third embodiments, this embodiment has an effect of shortening the driving time until the transistor is turned on from the off state in the system in which the transistor is on / off controlled. The reason is that the bias application unit 11 adds the bias voltage Vd to the output voltage from the control unit 12 so that the voltage applied to the gate terminal 302 when the FET 30 is off is equal to the bias voltage Vd. This is because the time taken for the control unit 12 to increase the voltage of the gate terminal 302 to the drive voltage Vd of the FET 30 to turn on the FET 30 is shortened.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Transistor drive control system 10 thru | or 20 Transistor drive control circuit 11 Bias application part 110 Electronic circuit 111 Diode 112 Resistor 113 Zener diode 114 Shunt regulator 115 Electronic circuit 116 Resistor 117 Capacitor 30 to 40 FET
300 to 400 Source terminal 301 to 401 Drain terminal 302 to 402 Gate terminal 50 Power supply device 1 power supply terminal 51 Power supply device 2 power supply terminal 52 Electronic device power reception terminal

Claims (8)

Control means for outputting a voltage Vl lower than the drive voltage Vd of the transistor functioning as a switch between the source terminal and the drain terminal, and a voltage within a range of the voltage Vh higher than the Vl;
The output voltage of the control means, greater than Vd-Vh, and a voltage is always added to the bias voltage Vb Vd-Vl positive value less than the bias application means for indicia pressurized to a gate terminal of said transistor When,
A transistor drive control circuit. The control means measures a potential difference between the source terminal and the drain terminal in the transistor in which the source terminal is connected to a power supply terminal of a power supply device and the drain terminal is connected to a power reception terminal of an electronic device, and the source The Vl voltage is output when the terminal side is lower, the Vh voltage is output when the source terminal side is higher, and the source terminal side changes from a lower state to a higher state. When the output voltage is detected, the output voltage is increased from Vl to Vh.
The transistor drive control circuit according to claim 1. The bias applying means includes a first circuit in which a diode and a first resistor are connected in series, and a Zener diode, and the first circuit and the Zener diode are connected in parallel to the gate terminal. One circuit inputs an output voltage of the power supply device, and the Zener diode inputs an output voltage of the control means lower than the output voltage of the power supply device.
The transistor drive control circuit according to claim 2. The bias applying means includes a first circuit in which a diode and a first resistor are connected in series, and a shunt regulator, the first circuit and the shunt regulator are connected in parallel to the gate terminal, One circuit inputs an output voltage of the power supply device, and the shunt regulator inputs an output voltage of the control means lower than the output voltage of the power supply device.
The transistor drive control circuit according to claim 2. The bias applying means includes a first circuit in which a diode and a first resistor are connected in series, and a second circuit in which a second resistor and a capacitor are connected in parallel, the first circuit and the A second circuit is connected in parallel to the gate terminal, the first circuit receives an output voltage of the power supply device, and the second circuit is lower than the output voltage of the power supply device. Input the output of
The transistor drive control circuit according to claim 2. A transistor drive control system comprising the transistor drive control circuit according to claim 2 , the power supply device, and the electronic device. A voltage Vl lower than the drive voltage Vd of the transistor functioning as a switch between the source terminal and the drain terminal, and a control voltage within the range of the voltage Vh higher than Vl is greater than Vd−Vh and Vd− the Vl is less than positive voltage constantly adding a bias voltage Vb values, indicia pressurized to a gate terminal of said transistor,
Transistor drive control method. In the transistor in which the source terminal is connected to a power supply terminal of a power supply device and the drain terminal is connected to a power reception terminal of an electronic device, a potential difference between the source terminal and the drain terminal is measured, and the source terminal side is more When it is low, it outputs the voltage Vl, when it is higher on the source terminal side, it outputs the voltage Vh, and when it is detected that the source terminal side has changed from a lower state to a higher state. Increasing the control voltage from Vl to Vh;
8. The transistor drive control method according to claim 7.

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