JP6098259B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a semiconductor device (semiconductor device, semiconductor element), a gallium nitride (GaN) -based semiconductor device including a P-type semiconductor layer is known. The P-type semiconductor layer in the GaN-based semiconductor device is mainly made of GaN and contains an acceptor (dopant, impurity). Magnesium (Mg) is known as an acceptor for the P-type semiconductor layer.

  The semiconductor layer in the GaN-based semiconductor device is formed by metal organic chemical vapor deposition (MOCVD). Since hydrogen atoms (H) derived from the MOCVD source gas remain in the P-type semiconductor layer formed by MOCVD, the function of the acceptor in the P-type semiconductor layer is suppressed. Therefore, a heat treatment (activation annealing treatment) is performed in which the acceptors in the P-type semiconductor layer are activated by releasing hydrogen atoms from the P-type semiconductor layer. As a result, the hole concentration of the P-type semiconductor layer is improved, and the specific resistance of the P-type semiconductor layer is lowered accordingly.

Patent Document 1 describes heat treatment for heating a GaN-based P-type semiconductor layer in an inert gas (for example, nitrogen (N ₂ )) at 400 to 1000 ° C. Patent Document 2 describes a heat treatment for heating a GaN-based P-type semiconductor layer for 20 minutes in a gas at 400 to 700 ° C. containing oxygen (O ₂ ). Non-Patent Document 1 describes that when GaN is heated for several hours in a gas containing oxygen, gallium oxide (Ga ₂ O ₃ ) is formed on the surface of GaN.

Japanese Patent No. 2540791 Japanese Patent No. 3344257

Yoshitaka Nakano, Takashi Jimbo, “Applied Physics Letters Vol. 82 No. 2”, American Institute of Physics, published January 13, 2003, pages 218-220.

  In the heat treatment of Patent Documents 1 and 2, when the dry etching region, which is a region where the thickness of the P-type semiconductor layer is reduced by dry etching, is formed in the P-type semiconductor layer, the hole concentration in the dry etching region is sufficiently improved. There was a problem that it could not be made. If the inert gas is heated to a temperature higher than 1000 ° C. in the heat treatment of Patent Document 1, the hole concentration in the dry etching region can be sufficiently improved, but the P-type semiconductor layer can be used until it cannot be used as a semiconductor device. There was a problem that the surface of the surface would be rough. If the heat treatment of Patent Document 2 is performed for several hours, the hole concentration in the dry etching region can be sufficiently improved, but the gallium oxide formed on the surface of the P-type semiconductor layer needs to be removed. For this reason, there is a problem of increase in time and cost required for production.

  Therefore, there has been a demand for a technique capable of improving the electrical characteristics of a P-type semiconductor layer subjected to dry etching in a GaN-based semiconductor device. In addition, for semiconductor devices, miniaturization, cost reduction, resource saving, easy manufacturing, improved usability, and improved durability have been desired.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
The first aspect of the present invention is a method for manufacturing a semiconductor device. This method
A semiconductor device manufacturing method for manufacturing a semiconductor device including a P-type semiconductor layer mainly made of gallium nitride (GaN),
A dry etching step of reducing the thickness of the P-type semiconductor layer by dry etching;
A heating step of heating the P-type semiconductor layer in a gas containing oxygen (O ₂ ) after performing the dry etching step , wherein the temperature of the gas is 800 to 1000 ° C .;
With
The gas is mainly composed of oxygen (O ₂ ) and nitrogen (N ₂ ),
The ratio of the flow rate of oxygen (O ₂ ) to the flow rate of nitrogen (N ₂ ) in the gas is 2% or more.
The present invention can also be realized as the following forms.

(1) According to one aspect of the present invention, there is provided a semiconductor device manufacturing method for manufacturing a semiconductor device including a P-type semiconductor layer mainly made of gallium nitride (GaN). This manufacturing method includes a dry etching step of reducing the thickness of the P-type semiconductor layer by dry etching; and after performing the dry etching step, the P-type semiconductor layer is formed in a gas containing oxygen (O ₂ ). It is a heating process to heat, Comprising: The temperature of the said gas is provided with the heating process which is 700-1000 degreeC. According to this embodiment, the hole concentration of the P-type semiconductor layer can be sufficiently improved without roughening the surface of the P-type semiconductor layer. As a result, in the GaN-based semiconductor device, the electrical characteristics of the P-type semiconductor layer subjected to dry etching can be improved.

(2) In the method for manufacturing a semiconductor device according to the above aspect, the temperature of the gas may be 800 to 900 ° C. According to this embodiment, it is possible to sufficiently improve the hole concentration of the P-type semiconductor layer while suppressing the manufacturing cost.

(3) In the method of manufacturing a semiconductor device according to the above aspect, the gas mainly includes oxygen (O ₂ ) and nitrogen (N ₂ ), and oxygen (O ₂ ) with respect to the flow rate of nitrogen (N ₂ ) in the gas. The flow rate ratio may be 1% or more. According to this embodiment, the hole concentration of the P-type semiconductor layer can be sufficiently improved.

(4) In the method for manufacturing a semiconductor device according to the above aspect, the time for heating the P-type semiconductor layer in the heating step may be 5 minutes or more. According to this embodiment, the hole concentration of the P-type semiconductor layer can be sufficiently improved.

(5) In the method for manufacturing a semiconductor device according to the above aspect, the dry etching may be a process for processing the P-type semiconductor layer in a gas containing at least one of chlorine and chloride. According to this embodiment, the hole concentration of the P-type semiconductor layer subjected to dry etching using a chlorine-based gas can be sufficiently improved.

(6) According to one aspect of the present invention, a semiconductor device is provided. This semiconductor device includes a P-type semiconductor layer that is a P-type semiconductor layer mainly made of gallium nitride (GaN) and has a dry etching region that is a region where the thickness of the P-type semiconductor layer is reduced by dry etching. The ratio of the average concentration of hydrogen atoms (H) to the average concentration of magnesium (Mg) in the dry etching region is 40% or less. According to this embodiment, the electrical characteristics of the P-type semiconductor layer having a dry etching region can be improved.

(7) In the semiconductor device of the above aspect, the ratio of the average concentration of hydrogen atoms (H) to the average concentration of magnesium (Mg) in the dry etching region may be 20% or less. According to this embodiment, the electrical characteristics of the P-type semiconductor layer having a dry etching region can be further improved.

  The present invention can be realized in various forms other than the semiconductor device and the manufacturing method thereof. For example, the present invention can be realized in the form of an electrical apparatus in which the semiconductor device of the above form is incorporated, a manufacturing apparatus for manufacturing the semiconductor device of the above form, and the like.

  According to the present invention, the hole concentration of the P-type semiconductor layer can be sufficiently improved without roughening the surface of the P-type semiconductor layer. As a result, in the GaN-based semiconductor device, the electrical characteristics of the P-type semiconductor layer subjected to dry etching can be improved.

It is sectional drawing which shows typically the structure of the semiconductor device in 1st Embodiment. It is process drawing which shows the manufacturing method of a semiconductor device. It is sectional drawing which shows typically the structure of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 3rd Embodiment. It is sectional drawing which shows typically the structure of the sample used for the evaluation test. It is a graph which shows the relationship between the activation annealing temperature in a 1st evaluation test, and the specific resistance of a P-type semiconductor layer. It is a graph which shows the relationship between the activation annealing temperature and the hole density | concentration of a P-type semiconductor layer in a 1st evaluation test. It is a graph which shows the relationship between the activation annealing temperature and the hole mobility of a P-type semiconductor layer in a 1st evaluation test. It is a graph showing the relationship between the specific resistance of the O ₂ / N ₂ flow rate ratio and the P-type semiconductor layer in the first evaluation test. Is a graph showing the relationship between the hole concentration of O ₂ / N ₂ flow rate ratio and the P-type semiconductor layer in the first evaluation test. Is a graph showing the relationship between the hole mobility of the O ₂ / N ₂ flow rate ratio and the P-type semiconductor layer in the first evaluation test. It is a graph which shows the relationship between the activation annealing time in a 2nd evaluation test, and the specific resistance of a P-type semiconductor layer. It is a graph which shows the relationship between the activation annealing time and the hole density | concentration of a P-type semiconductor layer in a 2nd evaluation test. It is a graph which shows the relationship between the activation annealing time in a 2nd evaluation test, and the hole mobility of a P-type semiconductor layer. It is a graph which shows the relationship between the activation annealing temperature in a 3rd evaluation test, and the specific resistance of a P-type semiconductor layer. It is a graph which shows the relationship between the activation annealing temperature and the hole density | concentration of a P-type semiconductor layer in a 3rd evaluation test. It is a graph which shows the relationship between the activation annealing temperature and the hole mobility of a P-type semiconductor layer in a 3rd evaluation test. It is a graph which shows the relationship between the activation annealing temperature in a 3rd evaluation test, and the specific resistance of a P-type semiconductor layer. It is a graph which shows the relationship between the activation annealing temperature and the hole density | concentration of a P-type semiconductor layer in a 3rd evaluation test. It is a graph which shows the relationship between the activation annealing temperature and the hole mobility of a P-type semiconductor layer in a 3rd evaluation test. It is a graph which shows the relationship between the activation annealing time in a 4th evaluation test, and the specific resistance of a P-type semiconductor layer. It is a graph which shows the relationship between the activation annealing time and the hole density | concentration of a P-type semiconductor layer in a 4th evaluation test. It is a graph which shows the relationship between the activation annealing time in the 4th evaluation test, and the hole mobility of a P-type semiconductor layer. It is a graph which shows the relationship between Mg density | concentration of a P-type semiconductor layer and H / Mg ratio in a 5th evaluation test. It is a graph which shows the relationship between the hole density | concentration of a P-type semiconductor layer in a 5th evaluation test, and H / Mg ratio.

A. First Embodiment FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device 10 according to a first embodiment. The semiconductor device 10 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 10 is used for power control and is also called a power device or a high-frequency device.

  The semiconductor device 10 includes a substrate 110, an N-type semiconductor layer 120, a P-type semiconductor layer 130, an N-type semiconductor layer 140, electrodes 210, 230, 240, 250, and an insulating film 340. The semiconductor device 10 is an NPN-type semiconductor device, and has a structure in which an N-type semiconductor layer 120, a P-type semiconductor layer 130, and an N-type semiconductor layer 140 are joined in order.

  The N-type semiconductor layer 120, the P-type semiconductor layer 130, and the N-type semiconductor layer 140 of the semiconductor device 10 are semiconductor layers formed by crystal growth by metal organic chemical vapor deposition (MOCVD). In the semiconductor device 10, a recess 182, a recess 184, and a recess 186 are formed by dry etching.

  FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis along the stacking direction in which the N-type semiconductor layer 120 is stacked on the substrate 110. Among the X-axis directions along the X-axis, the + X-axis direction is a direction from the substrate 110 toward the N-type semiconductor layer 120, and the −X-axis direction is a direction facing the + X-axis direction. Of the XYZ axes in FIG. 1, the Y axis and the Z axis are axes that are orthogonal to the Z axis and orthogonal to each other. Among the Y-axis directions along the Y-axis, the + Y-axis direction is a direction from the left side to the right side in FIG. 1, and the −Y-axis direction is a direction facing the + Y-axis direction. Among the Z-axis directions along the Z-axis, the + Z-axis direction is a direction from the front side of the paper in FIG. 1 toward the back of the paper surface, and the −Z-axis direction is a direction facing the + Z-axis direction.

  The substrate 110 of the semiconductor device 10 is a semiconductor layer extending along the Y axis and the Z axis. In the present embodiment, the substrate 110 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor at a higher concentration than the N-type semiconductor layer 120.

The N-type semiconductor layer 120 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X axis direction side of the substrate 110 and extends along the Y axis and the Z axis. The N-type semiconductor layer 120 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor at a lower concentration than the N-type semiconductor layer 140. The N-type semiconductor layer 120 is also called “n ⁻ -GaN”.

  The P-type semiconductor layer 130 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X-axis direction side of the N-type semiconductor layer 120 and extends along the Y-axis and the Z-axis. The P-type semiconductor layer 130 is mainly made of gallium nitride (GaN) and contains magnesium (Mg) as an acceptor. The P-type semiconductor layer 130 is also called “p-GaN”.

The P-type semiconductor layer 130 has a dry etching region 135 that is a region where the thickness (the length in the X-axis direction) of the P-type semiconductor layer 130 is reduced by dry etching. The dry etching region 135 is a region where the composition of the P-type semiconductor layer 130 is changed by dry etching. The dry etching region 135 includes a surface of the P-type semiconductor layer 130 formed by dry etching and a part of the P-type semiconductor layer 130 directly below the surface (−X-axis direction side). In the present embodiment, the dry etching region 135 is formed by removing the X-axis direction side of the P-type semiconductor layer 130 when the recess 182 is formed by dry etching. After the dry etching region 135 is formed by dry etching, the P-type semiconductor layer 130 is subjected to heat treatment (activation annealing treatment) in a gas at 700 to 1000 ° C. containing oxygen (O ₂ ). As a result, the H / Mg ratio in the entire dry etching region 135 is 40% or less required for realizing the electrical characteristics as the P-type semiconductor layer. The H / Mg ratio is the ratio of the average concentration of hydrogen atoms (H) to the average concentration of magnesium (Mg) in the P-type semiconductor layer 130.

The N-type semiconductor layer 140 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X-axis direction side of the P-type semiconductor layer 130 and extends along the Y-axis and the Z-axis. The N-type semiconductor layer 140 is mainly made of gallium nitride (GaN), and contains silicon (Si) as a donor at a higher concentration than the N-type semiconductor layer 120. The N-type semiconductor layer 140 is also referred to as “n ⁺ -GaN”.

  The recess 182 of the semiconductor device 10 is a portion formed by dry etching and recessed from the + X-axis direction side of the N-type semiconductor layer 140 to the P-type semiconductor layer 130. The recess 182 is also referred to as a recess. A dry etching region 135 of the P-type semiconductor layer 130 exists on the −X axis direction side of the recess 182.

  The recess 184 of the semiconductor device 10 is a portion that is formed by dry etching and is recessed from the + X-axis direction side of the N-type semiconductor layer 140 through the P-type semiconductor layer 130 to the N-type semiconductor layer 120. The recess 184 is also called a trench. In the present embodiment, the recess 184 is located on the + Y axis direction side of the recess 182.

An insulating film 340 is formed on the surface of the recess 184 so as to reach the + X-axis direction side of the N-type semiconductor layer 140. In the present embodiment, the insulating film 340 is made of silicon dioxide (SiO ₂ ).

  The recess 186 of the semiconductor device 10 is a portion that is formed by dry etching and is recessed from the + X-axis direction side of the N-type semiconductor layer 140 through the P-type semiconductor layer 130 to the N-type semiconductor layer 120. The recess 186 is also called a trench. In the present embodiment, the recess 186 is located on the −Y axis direction side of the recess 184.

  The electrode 210 of the semiconductor device 10 is a drain electrode formed on the −X axis direction side of the substrate 110. In this embodiment, the electrode 210 is formed by laminating a layer made of aluminum (Al) on a layer made of titanium (Ti) and then firing.

  The electrode 230 of the semiconductor device 10 is a body electrode formed on the P-type semiconductor layer 130 exposed inside the recess 182. In this embodiment, the electrode 230 is formed by laminating a layer made of gold (Au) on a layer made of nickel (Ni) and then firing.

  The electrode 240 of the semiconductor device 10 is a source electrode formed on the + X-axis direction side of the N-type semiconductor 140 between the recess 182 and the recess 184. In this embodiment, the electrode 240 is formed by laminating a layer made of aluminum (Al) on a layer made of titanium (Ti) and then firing.

  The electrode 250 of the semiconductor device 10 is a gate electrode formed on the insulating film 340 in the recess 184. In the present embodiment, the electrode 250 is made of aluminum (Al).

  FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, the manufacturer first forms the N-type semiconductor layer 120, the P-type semiconductor layer 130, and the N-type semiconductor layer 140 in this order on the substrate 110 (process P 120). As a result, the manufacturer obtains an intermediate product of the semiconductor device 10 in which each semiconductor layer is formed on the substrate 110. In this embodiment, the manufacturer forms each semiconductor layer on the substrate 110 using an MOCVD apparatus that realizes metal organic chemical vapor deposition (MOCVD).

  After forming each semiconductor layer (process P120), the manufacturer performs a dry etching process (process P140). In the dry etching process (process P140), the manufacturer forms the recess 182 by performing dry etching on the intermediate product of the semiconductor device 10. In this embodiment, the manufacturer forms the recess 184 and the recess 186 in addition to the recess 182 by dry etching.

In the present embodiment, the dry etching performed in the dry etching process (process P140) contains at least one of chlorine (Cl ₂ ) and chloride (for example, boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ )). In the gas to be processed, the intermediate product of the semiconductor device 10 is processed. In the present embodiment, the dry etching performed in the dry etching process (process P140) is inductively coupled plasma (ICP) dry etching.

After performing the dry etching process (process P140), the manufacturer performs a heating (activation annealing) process (process P160). In the heating process (process P160), the manufacturer heats the intermediate product of the semiconductor device 10 (activation annealing process) in a gas containing oxygen (O ₂ ). As a result, hydrogen atoms (H) are released from the P-type semiconductor layer 130, and Mg, which is an acceptor of the P-type semiconductor layer 130, is activated.

  The gas temperature (activation annealing temperature) used in the heating process (process P160) is preferably 700 to 1000 ° C, and more preferably 800 to 900 ° C. The evaluation of the activation annealing temperature will be described later.

In this embodiment, the gas used for the heating process (process P160) is mainly composed of oxygen (O ₂ ) and nitrogen (N ₂ ). The ratio of the flow rate of oxygen (O ₂ ) to the flow rate of nitrogen (N ₂ ) in the gas used in the heating step (step P160) (O ₂ / N ₂ flow rate ratio) is preferably 1% or more, preferably 2% More preferably, it is more preferably 5% or more. The evaluation of the O ₂ / N ₂ flow rate ratio will be described later.

  In the present embodiment, the time for heating the intermediate product of the semiconductor device 10 (activation annealing time) in the heating step (step P160) is 5 minutes or more, and is preferably limited to about 60 minutes. The evaluation of the activation annealing time will be described later.

  After the heating process (process P160), the manufacturer forms the electrode 230 in the recess 182 in the intermediate product of the semiconductor device 10 (process P180). In this embodiment, the manufacturer forms the electrodes 210, 240, 250 and the insulating film 340 in addition to the electrode 230. Through these steps, the semiconductor device 10 is completed.

  According to the first embodiment described above, the hole concentration of the P-type semiconductor layer 130 can be sufficiently improved without roughening the surface of the P-type semiconductor layer 130. As a result, in the GaN-based semiconductor device 10, the electrical characteristics of the P-type semiconductor layer 130 that has been dry-etched can be improved.

B. Second Embodiment FIG. 3 is a cross-sectional view schematically showing a configuration of a semiconductor device 50 according to a second embodiment. FIG. 3 shows the XYZ axes as in FIG. The semiconductor device 50 is a GaN-based semiconductor device. In the present embodiment, the semiconductor device 50 is a PIN diode (P-Intrinsic-N Diode).

  The semiconductor device 50 includes an N-type semiconductor layer 520, a P-type semiconductor layer 530, and an electrode 593. The semiconductor device 50 has a structure in which an N-type semiconductor layer 520 and a P-type semiconductor layer 530 are joined. The N-type semiconductor layer 520 and the P-type semiconductor layer 530 of the semiconductor device 50 are semiconductor layers formed by crystal growth by MOCVD. In the semiconductor device 50, a recess 582 and a recess 583 are formed by dry etching.

  The N-type semiconductor layer 520 of the semiconductor device 50 is a semiconductor layer that extends along the Y axis and the Z axis. The N-type semiconductor layer 520 is mainly made of GaN and contains Si as a donor.

  The P-type semiconductor layer 530 of the semiconductor device 50 is a semiconductor layer that is stacked on the + X-axis direction side of the N-type semiconductor layer 520 and extends along the Y-axis and the Z-axis. The P-type semiconductor layer 530 is mainly made of GaN and contains Mg as an acceptor.

  The P-type semiconductor layer 530 has a dry etching region 535 that is a region where the thickness (length in the X-axis direction) of the P-type semiconductor layer 530 is reduced by dry etching. In the present embodiment, the dry etching region 535 is formed by removing the X-axis direction side of the P-type semiconductor layer 530 when the recess 583 is formed by dry etching. After the dry etching region 535 is formed by dry etching, the P-type semiconductor layer 530 is subjected to heat treatment (activation annealing treatment) in a 700 to 1000 ° C. gas containing oxygen. As a result, the H / Mg ratio in the entire dry etching region 535 is 40% or less required for realizing electrical characteristics as a P-type semiconductor layer.

  The recess 582 of the semiconductor device 50 is a portion formed by dry etching and recessed from the + X-axis direction side of the P-type semiconductor layer 530 to the N-type semiconductor layer 520. The recess 582 has a shape surrounding the P-type semiconductor layer 530.

  The recess 583 of the semiconductor device 50 is a recessed portion that is formed by dry etching and is located at the center on the + X-axis direction side of the P-type semiconductor layer 530 surrounded by the recess 582. The recess 583 is also called a recess. A dry etching region 535 of the P-type semiconductor layer 530 exists on the −X-axis direction side of the recess 583.

  The electrode 593 of the semiconductor device 50 is an ohmic electrode formed on the P-type semiconductor layer 530 exposed inside the recess 583. In the present embodiment, the electrode 593 is formed by laminating a layer made of Au on a layer made of Ni and then firing.

  The manufacturing method of the semiconductor device 50 in the second embodiment is the same as the manufacturing method of the semiconductor device 10 in the first embodiment, except that the structure formed in each step is different.

  According to the second embodiment described above, the hole concentration of the P-type semiconductor layer 530 can be sufficiently improved without roughening the surface of the P-type semiconductor layer 530. As a result, in the GaN-based semiconductor device 50, the electrical characteristics of the P-type semiconductor layer 530 subjected to dry etching can be improved.

C. Third Embodiment FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor device 60 in a third embodiment. FIG. 4 shows the XYZ axes as in FIG. The semiconductor device 60 is a GaN-based semiconductor device. In the present embodiment, the semiconductor device 60 is a light emitting element and is also called a light emitting diode (LED).

  The semiconductor device 60 includes an N-type semiconductor layer 610, a light emitting layer 620, a P-type semiconductor layer 630, and electrodes 691 and 693. The semiconductor device 60 has a structure in which a light emitting layer 620 and a P-type semiconductor layer 630 are sequentially joined to an N-type semiconductor layer 610. The N-type semiconductor layer 610, the light emitting layer 620, and the P-type semiconductor layer 630 of the semiconductor device 60 are semiconductor layers formed by crystal growth by MOCVD. A recess 681 is formed in the semiconductor device 60 by dry etching.

  The N-type semiconductor layer 610 of the semiconductor device 60 is a semiconductor layer that extends along the Y axis and the Z axis. The N-type semiconductor layer 520 is mainly made of GaN and contains Si as a donor.

  The light emitting layer 620 of the semiconductor device 60 is a semiconductor layer that is stacked on the + X axis direction side of the N-type semiconductor layer 610 and extends along the Y axis and the Z axis. The light emitting layer 620 is a semiconductor layer configured to be capable of emitting light, and is mainly composed of indium gallium nitride (InGaN) in the present embodiment.

  The P-type semiconductor layer 630 of the semiconductor device 60 is a semiconductor layer that is stacked on the + X axis direction side of the light emitting layer 620 and extends along the Y axis and the Z axis. The P-type semiconductor layer 630 is mainly made of GaN and contains Mg as an acceptor.

  The entire surface on the + X-axis direction side in the P-type semiconductor layer 630 is a surface formed by dry etching. Therefore, the entire region of the P-type semiconductor layer 630 becomes a dry etching region in which the thickness (the length in the X-axis direction) of the P-type semiconductor layer 630 is reduced by dry etching. After dry etching is performed on the P-type semiconductor layer 630, the P-type semiconductor layer 630 is subjected to heat treatment (activation annealing treatment) in a gas containing 700 to 1000 ° C. containing oxygen. As a result, the H / Mg ratio in the entire region of the P-type semiconductor layer 630 becomes 40% or less required for realizing electrical characteristics as the P-type semiconductor layer.

  The recess 681 of the semiconductor device 60 is a portion formed by dry etching and recessed from the + X-axis direction side of the P-type semiconductor layer 630 to the N-type semiconductor layer 610.

  The electrode 691 of the semiconductor device 60 is an ohmic electrode formed on the N-type semiconductor layer 610 exposed by the recess 681. In this embodiment, the electrode 691 is formed by laminating a layer made of Al on a layer made of Ti and then firing.

  The electrode 693 of the semiconductor device 60 is an ohmic electrode formed on the + X-axis direction side of the P-type semiconductor layer 630. In this embodiment, the electrode 693 is formed by laminating a layer made of Au on a layer made of Ni and then firing.

  The manufacturing method of the semiconductor device 60 in the third embodiment is the same as the manufacturing method of the semiconductor device 10 in the first embodiment, except that the structure formed in each step is different.

  According to the third embodiment described above, the hole concentration of the P-type semiconductor layer 630 can be sufficiently improved without roughening the surface of the P-type semiconductor layer 630. As a result, in the GaN-based semiconductor device 60, the electrical characteristics of the P-type semiconductor layer 630 subjected to dry etching can be improved.

D. Evaluation Test FIG. 5 is a cross-sectional view schematically showing the configuration of the sample 90 used in the evaluation test. FIG. 5 shows the XYZ axes as in FIG. The sample 90 includes a substrate 910, a buffer layer 920, an undoped semiconductor layer 930, a P-type semiconductor layer 940, and electrodes 992 and 994.

  The sample 90 has a structure in which a buffer layer 920, an undoped semiconductor layer 930, and a P-type semiconductor layer 940 are sequentially joined on a substrate 910. The buffer layer 920, the undoped semiconductor layer 930, and the P-type semiconductor layer 940 of the sample 90 are semiconductor layers formed by crystal growth by MOCVD.

  The substrate 910 of the sample 90 is a semiconductor layer extending along the Y axis and the Z axis. The substrate 910 is made of single crystal sapphire.

  The buffer layer 920 of the sample 90 is a semiconductor layer that is stacked on the + X axis direction side of the substrate 910 and extends along the Y axis and the Z axis. The buffer layer 920 is made of aluminum nitride (AlN).

  The undoped semiconductor layer 930 of the sample 90 is a semiconductor layer that is stacked on the + X axis direction side of the buffer layer 920 and extends along the Y axis and the Z axis. The undoped semiconductor layer 930 is an intrinsic semiconductor layer mainly made of GaN.

  The P-type semiconductor layer 940 of the sample 90 is a semiconductor layer that is stacked on the + X-axis direction side of the undoped semiconductor layer 930 and extends along the Y-axis and the Z-axis. The P-type semiconductor layer 940 is mainly made of GaN and contains Mg as an acceptor.

  When the sample 90 in which dry etching is performed on the P-type semiconductor layer 940 is created, the entire surface on the + X-axis direction side of the P-type semiconductor layer 940 is a surface formed by dry etching. In this case, the entire region of the P-type semiconductor layer 940 becomes a dry etching region in which the thickness (the length in the X-axis direction) of the P-type semiconductor layer 940 is reduced by dry etching.

  Electrodes 992 and 994 of the sample 90 are electrodes formed on the + X-axis direction side of the P-type semiconductor layer 940 in order to measure the characteristics of the P-type semiconductor layer 940. In the present embodiment, the electrodes 992, 994 are electrodes made of Ni. When the sample 90 in which the heat treatment (activation annealing treatment) is performed on the P-type semiconductor layer 940 is manufactured, the electrodes 992 and 994 are formed after the heat treatment on the P-type semiconductor layer 940.

  FIG. 6A is a graph showing the relationship between the activation annealing temperature and the specific resistance of the P-type semiconductor layer 940 in the first evaluation test. FIG. 6B is a graph showing the relationship between the activation annealing temperature and the hole concentration of the P-type semiconductor layer 940 in the first evaluation test. FIG. 6C is a graph showing the relationship between the activation annealing temperature and the hole mobility of the P-type semiconductor layer 940 in the first evaluation test.

FIG. 7A is a graph showing the relationship between the O ₂ / N ₂ flow rate ratio and the specific resistance of the P-type semiconductor layer 940 in the first evaluation test. FIG. 7B is a graph showing the relationship between the O ₂ / N ₂ flow rate ratio and the hole concentration of the P-type semiconductor layer 940 in the first evaluation test. FIG. 7C is a graph showing the relationship between the O ₂ / N ₂ flow rate ratio and the hole mobility of the P-type semiconductor layer 940 in the first evaluation test.

In the first evaluation test, the tester activates the sample 90 in which the dry etching and activation annealing treatment is not performed on the P-type semiconductor layer 940 and the P-type semiconductor layer 940 that is not dry-etched under the following conditions. A plurality of samples 90 subjected to the annealing treatment were prepared, and the specific resistance, hole concentration, and hole mobility of the P-type semiconductor layer 940 were measured for these samples. In the first evaluation test, the average Mg concentration in the entire P-type semiconductor layer 940 is 1.0 × 10 ¹⁹ cm ⁻³ .

<Conditions for activation annealing treatment in the first evaluation test>
Activation annealing temperature: 600-1200 ° C
・ O ₂ / N ₂ flow ratio: 0%, 1%, 2%, 5%
・ Activation annealing time: 5 minutes

As shown in FIGS. 6A and 6B, when the O ₂ / N ₂ flow rate ratio is 1% or more, the specific resistance and the hole concentration of the P-type semiconductor layer 940 are saturated if the activation annealing temperature is 700 ° C. or more. To do. On the other hand, when the O ₂ / N ₂ flow ratio is 0%, the specific resistance and hole concentration of the P-type semiconductor layer 940 are not saturated unless the activation annealing temperature is set to 900 ° C. or higher. When the activation annealing temperature is higher than 1000 ° C., the surface of the P-type semiconductor layer 940 becomes rough before it can no longer be used as a semiconductor device.

As shown in FIG. 7A and FIG. 7B, the O ₂ / N ₂ flow rate ratio is larger than 0%, that is, the fact that the gas used for the activation annealing treatment contains oxygen is a ratio in the P-type semiconductor layer 940. It is effective in reducing resistance and increasing hole concentration.

As shown in FIG. 6C, if the activation annealing temperature does not exceed 1100 ° C., the hole mobility of the P-type semiconductor layer 940 does not change significantly. As shown in FIG. 7C, there is no significant change in the hole mobility of the P-type semiconductor layer 940 at any O ₂ / N ₂ flow rate ratio.

Therefore, according to the result of the first evaluation test, the gas used for the activation annealing treatment preferably contains oxygen. For example, the O ₂ / N ₂ flow rate ratio is 0.1 to 99.9%. There may be. According to the result of the first evaluation test, the activation annealing temperature is preferably 700 to 1000 ° C.

  FIG. 8A is a graph showing the relationship between the activation annealing time and the specific resistance of the P-type semiconductor layer 940 in the second evaluation test. FIG. 8B is a graph showing the relationship between the activation annealing time and the hole concentration of the P-type semiconductor layer 940 in the second evaluation test. FIG. 8C is a graph showing the relationship between the activation annealing time and the hole mobility of the P-type semiconductor layer 940 in the second evaluation test.

In the second evaluation test, the tester creates a plurality of samples 90 in which activation annealing treatment is performed on the P-type semiconductor layer 940 that has not been dry-etched under the following conditions, and the P-type semiconductor layer 940 is used for these samples. Specific resistance, hole concentration, and hole mobility were measured. In the second evaluation test, the average concentration of Mg in the entire region of the P-type semiconductor layer 940 is 1.0 × 10 ¹⁹ cm ⁻³ .

<Conditions for activation annealing in the second evaluation test>
Activation annealing temperature: 650 ° C
・ O ₂ / N ₂ flow ratio: 1%
Activation annealing time: 5 minutes, 10 minutes, 30 minutes

  As shown in FIG. 8A, as the activation annealing time becomes longer, the specific resistance of the P-type semiconductor layer 940 decreases, and the degree to which the specific resistance decreases decreases. As shown in FIG. 8B, as the activation annealing time increases, the hole concentration of the P-type semiconductor layer 940 increases, and the degree to which the hole concentration decreases decreases. As shown in FIG. 8C, the hole mobility of the P-type semiconductor layer 940 decreases as the activation annealing time increases.

  Therefore, according to the result of the second evaluation test, it is sufficient that the activation annealing time is about 5 to 10 minutes from the viewpoint of improving the electrical characteristics of the P-type semiconductor layer 940.

  FIG. 9A is a graph showing the relationship between the activation annealing temperature and the specific resistance of the P-type semiconductor layer 940 in the third evaluation test. FIG. 9B is a graph showing the relationship between the activation annealing temperature and the hole concentration of the P-type semiconductor layer 940 in the third evaluation test. FIG. 9C is a graph showing the relationship between the activation annealing temperature and the hole mobility of the P-type semiconductor layer 940 in the third evaluation test.

  FIG. 10A is a graph showing the relationship between the activation annealing temperature and the specific resistance of the P-type semiconductor layer 940 in the third evaluation test. FIG. 10B is a graph showing the relationship between the activation annealing temperature and the hole concentration of the P-type semiconductor layer 940 in the third evaluation test. FIG. 10C is a graph showing the relationship between the activation annealing temperature and the hole mobility of the P-type semiconductor layer 940 in the third evaluation test.

In the third evaluation test, the tester produced a plurality of samples 90 under the following conditions, and measured the specific resistance, hole concentration, and hole mobility of the P-type semiconductor layer 940 for these samples. In the third evaluation test, the average Mg concentration in the entire P-type semiconductor layer 940 is 2.0 × 10 ¹⁹ cm ⁻³ .

<Condition 1>
ICP dry etching (processing gas: Cl ₂ + BCl ₃ , bias power: 45 W)
Activation annealing treatment (activation annealing time: 5 minutes, O ₂ / N ₂ flow ratio: 5%, activation annealing temperature: 650 to 900 ° C.)

<Condition 2>
ICP dry etching (processing gas: Cl ₂ + BCl ₃ , bias power: 20 W)
Activation annealing treatment (activation annealing time: 5 minutes, O ₂ / N ₂ flow ratio: 5%, activation annealing temperature: 650 to 900 ° C.)

<Condition 3>
ICP dry etching (processing gas: Cl ₂ + SiCl ₄ , bias power: 45 W)
Activation annealing treatment (activation annealing time: 5 minutes, O ₂ / N ₂ flow ratio: 5%, activation annealing temperature: 650 to 900 ° C.)

<Condition 4>
ICP dry etching (processing gas: Cl ₂ + SiCl ₄ , bias power: 20 W)
Activation annealing treatment (activation annealing time: 5 minutes, O ₂ / N ₂ flow ratio: 5%, activation annealing temperature: 650 to 900 ° C.)

<Condition 5>
ICP dry etching (processing gas: Cl ₂ + BCl ₃ , bias power: 45 W)
Activation annealing treatment (activation annealing time: 5 minutes, O ₂ / N ₂ flow ratio: 1%, activation annealing temperature: 650 to 900 ° C.)

<Condition 6>
・ No ICP dry etching ・ Activation annealing treatment (activation annealing time: 5 minutes, O ₂ / N ₂ flow ratio: 5%, activation annealing temperature: 650 to 900 ° C.)

<Condition 7>
・ No ICP dry etching ・ No activation annealing treatment

  As shown in FIGS. 9A, 9B, 10A, and 10B, the specific resistance and the hole concentration of the P-type semiconductor layer 940 in the sample 90 under dry etching conditions 1 to 5 are set under the condition 6 under dry etching. In order to obtain a value equivalent to that of the sample 90, the activation annealing temperature needs to be 800 ° C. or higher. As shown in FIGS. 9C and 10C, the hole mobility of the P-type semiconductor layer 940 does not change greatly under any conditions as long as the activation annealing temperature is 650 to 900 ° C.

Therefore, according to the result of the third evaluation test, the activation annealing temperature is more preferably 800 to 900 ° C. from the viewpoint of sufficiently improving the hole concentration of the P-type semiconductor layer while suppressing the manufacturing cost.

  FIG. 11A is a graph showing the relationship between the activation annealing time and the specific resistance of the P-type semiconductor layer 940 in the fourth evaluation test. FIG. 11B is a graph showing the relationship between the activation annealing time and the hole concentration of the P-type semiconductor layer 940 in the fourth evaluation test. FIG. 11C is a graph showing the relationship between the activation annealing time and the hole mobility of the P-type semiconductor layer 940 in the fourth evaluation test.

In the fourth evaluation test, the tester produced a plurality of samples 90 under the following conditions, and measured the specific resistance, hole concentration, and hole mobility of the P-type semiconductor layer 940 for these samples. In the fourth evaluation test, the average concentration of Mg in the entire region of the P-type semiconductor layer 940 is 2.0 × 10 ¹⁹ cm ⁻³ .

<Conditions for Fourth Evaluation Test>
ICP dry etching (processing gas: Cl ₂ + BCl ₃ , bias power: 45 W)
Activation annealing treatment (O ₂ / N ₂ flow ratio: 5%, activation annealing temperature: 800 ° C., activation annealing time: 5 minutes, 10 minutes, 30 minutes)

  As shown in FIG. 11A, as the activation annealing time increases, the specific resistance of the P-type semiconductor layer 940 decreases, and the degree of decrease in specific resistance decreases. As shown in FIG. 11B, as the activation annealing time increases, the hole concentration of the P-type semiconductor layer 940 increases, and the degree to which the hole concentration decreases decreases. As shown in FIG. 11C, the hole mobility of the P-type semiconductor layer 940 decreases as the activation annealing time increases.

  Therefore, according to the result of the fourth evaluation test, it is sufficient that the activation annealing time is about 5 to 10 minutes. If the activation annealing time becomes longer than necessary, the manufacturing cost increases and defects such as oxides formed on the surface of the P-type semiconductor layer 940 become remarkable. Therefore, the activation annealing time is preferably limited to about 60 minutes.

  FIG. 12A is a graph showing the relationship between the Mg concentration of the P-type semiconductor layer 940 and the H / Mg ratio in the fifth evaluation test. FIG. 12B is a graph showing the relationship between the hole concentration of the P-type semiconductor layer 940 and the H / Mg ratio in the fifth evaluation test.

  In the fifth evaluation test, the tester produced a plurality of samples 90 under the following conditions, and measured the Mg concentration, hole concentration, and H / Mg ratio of the P-type semiconductor layer 940 for these samples.

<Conditions for the fifth evaluation test>
ICP dry etching (processing gas: Cl ₂ + BCl ₃ , bias power: 45 W)
Activation annealing treatment (O ₂ / N ₂ flow ratio: 1%, activation annealing temperature: 650 ° C. or 750 ° C., activation annealing time: 5 minutes or 30 minutes)

As shown in FIGS. 12A and 12B, after dry etching is performed on the P-type semiconductor layer 940 having an Mg concentration of 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ²⁰ cm ⁻³ or less, A sufficient hole concentration can be obtained by performing the activation annealing process in a gas at 750 ° C. containing oxygen. In this case, the H / Mg ratio of the P-type semiconductor layer 940 is 40% or less. Is guessed. As shown in FIG. 12B, the hole concentration of the P-type semiconductor layer 940 increases as the H / Mg ratio of the P-type semiconductor layer 940 decreases.

  Therefore, according to the result of the fifth evaluation test, the H / Mg ratio of the P-type semiconductor layer 940 is preferably 40% or less, more preferably 30% or less, and preferably 20% or less. Even more preferable.

E. Other embodiments:
The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

  In the above-described embodiment, an intrinsic semiconductor layer may be formed between the substrate and the N-type semiconductor layer, or an intrinsic semiconductor layer may be formed between the N-type semiconductor layer and the P-type semiconductor layer.

In the above-described embodiment, the material of the substrate is not limited to gallium nitride (GaN), but may be silicon (Si), sapphire (Al ₂ O ₃ ), silicon carbide (SiC), or the like.

  In the above-described embodiment, the donor contained in at least one of the substrate and the N-type semiconductor layer is not limited to silicon (Si), but may be germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, the acceptor included in the P-type semiconductor layer is not limited to magnesium (Mg) but may be zinc (Zn), carbon (C), or the like.

In the above embodiment, the insulating film is made of silicon nitride (SiN), silicon nitride oxide (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum nitride oxide (AlON), zirconium dioxide (ZrO ₂ ), titanium oxide (TiO ₂ ). ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), niobium pentoxide (Nb ₂ O ₅ ), hafnium dioxide (HfO ₂ ), aluminum nitride (AlN), or the like.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 50 ... Semiconductor device 60 ... Semiconductor device 90 ... Sample 110 ... Substrate 120 ... N-type semiconductor layer 130 ... P-type semiconductor layer 135 ... Dry etching region 140 ... N-type semiconductor layer 182 ... Recess 184 ... Recess 186 ... Recess 210 ... Electrode 230 ... Electrode 240 ... Electrode 250 ... Electrode 340 ... Insulating film 520 ... N-type semiconductor layer 530 ... P-type semiconductor layer 535 ... Dry etching region 582 ... Recess 583 ... Recess 593 ... Electrode 610 ... N-type semiconductor layer 620 ... Light emitting layer 630 ... P-type semiconductor layer 681 ... Recess 691 ... Electrode 693 ... Electrode 910 ... Substrate 920 ... Buffer layer 930 ... Undoped semiconductor layer 940 ... P-type semiconductor layer 992, 994 ... Electrode

Claims (5)

A semiconductor device manufacturing method for manufacturing a semiconductor device including a P-type semiconductor layer mainly made of gallium nitride (GaN),
A dry etching step of reducing the thickness of the P-type semiconductor layer by dry etching;
A heating step of heating the P-type semiconductor layer in a gas containing oxygen (O ₂ ) after performing the dry etching step, wherein the temperature of the gas is 800 to 1000 ° C .; With
The gas is mainly composed of oxygen (O ₂ ) and nitrogen (N ₂ ),
The method for manufacturing a semiconductor device , wherein a ratio of a flow rate of oxygen (O ₂ ) to a flow rate of nitrogen (N ₂ ) in the gas is 2% or more .   The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the gas is 800 to 900 ° C. A method of manufacturing a semiconductor device according to claim 1 or 2,
Time is 5 minutes or more, a manufacturing method of a semi-conductor device for heating the P-type semiconductor layer in the heating step. It said dry etching is a process of processing the P-type semiconductor layer in a gas containing at least one of chlorine and chloride, of the semiconductor device according to any one of claims 1 to 3 Production method.   In the dry etching process, with respect to the structure in which the N-type semiconductor layer is stacked on the P-type semiconductor layer, a part of the P-type semiconductor layer is removed from the upper surface side of the N-type semiconductor layer. The process of reducing the thickness of the P-type semiconductor layer by forming a recess recessed from the upper surface side of the N-type semiconductor layer to the P-type semiconductor layer by the dry etching. The manufacturing method of the semiconductor device as described in any one of these.

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