JP6090763B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a Schottky barrier diode made of a wide band gap semiconductor.

2. Description of the Related Art Conventionally, semiconductor devices (semiconductor power devices) mainly used in systems in various power electronics fields such as motor control systems and power conversion systems have attracted attention.
For example, Patent Document 1 discloses a Schottky barrier diode employing SiC. The Schottky barrier diode includes an n-type 4H—SiC bulk substrate, an n-type epitaxial layer grown on the bulk substrate, an oxide film formed on the surface of the epitaxial layer, and partially exposing the surface of the epitaxial layer. And a Schottky electrode formed in the opening of the oxide film and having a Schottky junction with the epitaxial layer.

  Patent Document 1 discloses a vertical MIS field effect transistor employing SiC. The vertical MIS field effect transistor includes an n-type 4H—SiC bulk substrate, an n-type epitaxial layer grown on the bulk substrate, an n-type impurity region (source region) formed in a surface layer portion of the epitaxial layer, A p-type well region formed adjacent to both sides of the n-type impurity region, a gate oxide film formed on the surface of the epitaxial layer, and a gate electrode facing the p-type well region via the gate oxide film; It has.

JP 2005-79339 A JP 2011-9797 A

The semiconductor device of the present invention includes a semiconductor layer made of wide band gap semiconductor of a first conductivity type having a surface and a back surface, a front Symbol Schottky electrode formed in contact with the surface of the semiconductor layer, the semiconductor The layers are arranged at intervals in the direction along the surface, and each of the layers has a columnar shape extending in the thickness direction of the semiconductor layer from the front surface toward the back surface, and the first conductivity type of the semiconductor layer A plurality of second conductivity type pillar layers that form a super junction structure in the semiconductor layer in cooperation with other portions, and formed at the upper end portions of the plurality of pillar layers, for relaxing the electric field strength at the surface. the second contains a conductivity type of impurities, and are the electric field relaxation portion of compartment forming part of said semiconductor layer as a unit cell of the unit cells, the when a reverse bias voltage applying 1 A peripheral portion to which a field is applied, and a central portion to which a second electric field that is relatively higher than the first electric field is applied when the reverse voltage is applied, and the Schottky electrode includes a metal material, and Between the first electrode forming a first Schottky barrier between the peripheral portion of the unit cell and a metal material different from the first electrode, and between the central portion of the unit cell, And a second electrode forming a second Schottky barrier that is relatively higher than the first Schottky barrier .

According to the semiconductor device of the present invention, it is possible to achieve a reduction in reverse leakage current and forward voltage (VF) while ensuring a high breakdown voltage.
The breakdown voltage of the semiconductor device is related to the impurity concentration and thickness of the semiconductor layer, and tends to improve when the impurity concentration of the semiconductor layer is lowered or the thickness is increased.
On the other hand, the forward voltage of a semiconductor device reduces the on-resistance by increasing the impurity concentration or thickness of the semiconductor layer or increasing the Schottky barrier between the Schottky electrode and the semiconductor layer. When the thickness (barrier height) is lowered, there is a tendency to decrease. That is, with respect to the impurity concentration and thickness of the semiconductor layer, there is a tradeoff between improving the breakdown voltage and reducing the forward voltage.

  Therefore, according to the semiconductor device of the present invention, the second conductivity type pillar layer extending in the thickness direction of the semiconductor layer and the other portion of the first conductivity type of the semiconductor layer cooperate to form the semiconductor layer. A super junction structure is formed. With this super junction structure, the depletion layer can be spread over the entire interface in the direction along the interface with the pillar layer in the semiconductor layer (that is, in the thickness direction of the semiconductor layer). Thereby, the electric field strength in the semiconductor layer can be made uniform. As a result, when the impurity concentration and thickness of the semiconductor layer are the same, the breakdown voltage can be improved compared to a semiconductor device in which the super junction structure is not formed. Therefore, since a sufficient breakdown voltage can be ensured even in a semiconductor layer having a high impurity concentration and a small thickness as compared with the conventional case, by appropriately designing the impurity concentration and thickness of the semiconductor layer, while ensuring a high breakdown voltage, The forward voltage can be reduced.

  Furthermore, according to the semiconductor device of the present invention, the electric field relaxation portion is formed in the vicinity of the surface of the semiconductor layer, and the electric field strength at the surface of the semiconductor layer can be relaxed. Therefore, the reverse leakage current can be reduced even if the barrier height between the Schottky electrode and the semiconductor layer is lowered. As a result, while the reverse leakage current can be reduced, the barrier height can be lowered and the forward voltage can be reduced.

  In the present invention, the Schottky electrode is a metal electrode that forms a Schottky barrier between the semiconductor layer and a heterogeneous semiconductor having a band gap different from the band gap of the semiconductor layer. It is a concept that includes any semiconductor electrode (junction that forms a potential barrier with a semiconductor layer using a band gap difference). Hereinafter, in this section, the Schottky junction and the heterojunction are collectively referred to as “Schottky junction”, and the potential barrier (heterobarrier) formed by the Schottky barrier and the heterojunction is collectively referred to as “Schottky barrier”. The metal electrode and the semiconductor electrode are collectively referred to as “Schottky electrode”.

Also, in the semiconductor device of the present invention, the electric field absorbing portion, said formed by utilizing a part of the semiconductor layer and the semiconductor layer on the surface of the second conductivity type having an impurity concentration higher than that of the pillar layer The electric field relaxation layer shown may be included.

The electric field relaxation layer may include a high resistance layer having a higher resistance than other portions of the first conductivity type of the semiconductor layer forming the super junction structure . In that case, it is preferable that the high resistance layer is formed by performing an annealing process below 1500 ° C. after implanting impurity ions from the surface of the semiconductor layer.
According to this configuration, the amount of sublimation of the wide band gap semiconductor during the annealing process can be reduced. As a result, the flatness of the surface of the semiconductor layer can be maintained satisfactorily.

The annealing process below 1500 ° C. recovers defects generated in the crystal structure of the wide bandgap semiconductor due to collision of the implanted impurity ions (crystallinity recovery), but does not activate the implanted impurity ions. This means a degree of annealing treatment.
In the semiconductor device of the present invention, it is preferable that the activation rate of impurities in the high resistance layer is less than 5%. The sheet resistance of the high resistance layer is preferably 1 MΩ / □ or more.

In the semiconductor device of the present invention, a trench dug from the surface of the semiconductor layer may be formed at a position where the electric field relaxation portion is formed .
In that case, it is preferable that an edge portion of the trench formed by intersecting the side surface and the bottom surface of the trench has a curvature radius R satisfying the following formula (1).
0.01L <R <10L (1)
(However, in Formula (1), L has shown the linear distance between the edge parts which oppose along the width direction of a trench.)
According to this configuration, it is possible to relax the electric field concentrated on the edge portion of the trench and improve the breakdown voltage.

In the semiconductor device of the present invention, the electric field relaxation portion over there including the bottom surface and the second conductive type bottom relaxation layer of said formed by utilizing a part of the semiconductor layer on the edge portion of the trench and preferably, the a bottom relieving layer integrally with, said semiconductor layer side relief layer of a second conductivity type formed by utilizing a part of said side surface of said trench containing Mukoto more preferred. In this case, it is particularly preferable that the side relaxation layer is formed so as to reach the opening end of the trench along the side surface of the trench.

In the semiconductor device of the present invention, it is preferable that the trench includes a tapered trench having a planar bottom surface and a side surface inclined at an angle exceeding 90 ° with respect to the planar bottom surface.
With the tapered trench, the breakdown voltage of the semiconductor device can be further improved as compared with the case where the side surface stands at a right angle of 90 ° with respect to the bottom surface.

  Further, in the tapered trench, not only the bottom surface but also all or part of the side surface is opposed to the open end of the trench. Therefore, for example, when the second conductivity type impurity is implanted into the semiconductor layer through the trench, the impurity incident into the trench from the open end of the trench can be reliably applied to the side surface of the trench. As a result, the above-mentioned side part relaxation part can be formed easily.

Note that a taper trench is a trench in which all of the side surfaces are inclined at an angle exceeding 90 ° with respect to the bottom surface, and a part of the side surfaces (for example, a portion forming the edge portion of the trench) is 90 ° with respect to the bottom surface. It is a concept including any of the trenches inclined at an angle exceeding.
In the semiconductor device of the present invention, the Schottky electrode is formed so as to be embedded in the trench, and the shot embedded in the trench is formed in a portion of the semiconductor layer forming the bottom surface of the trench. It is preferable that a contact layer of a second conductivity type that forms an ohmic junction with the key electrode is further formed.

  With this configuration, the Schottky electrode can be ohmic-bonded to a pn diode having a pn junction between the contact layer (second conductivity type) and the semiconductor layer (first conductivity type). This pn diode is provided in parallel to a Schottky barrier diode (heterodiode) having a Schottky junction between a Schottky electrode and a semiconductor layer. Thereby, even if a surge current flows through the semiconductor device, a part of the surge current can be passed through the built-in pn diode. As a result, since the surge current flowing through the Schottky barrier diode can be reduced, thermal destruction of the Schottky barrier diode due to the surge current can be prevented.

In the present invention, there may be a portion where the electric field strength is relatively high and a portion where the electric field strength is relatively low, as in the relationship between the first portion and the second portion of the semiconductor layer.
Therefore, as described above, if the Schottky electrode is appropriately selected according to the electric field distribution of the semiconductor layer when the reverse voltage is applied, the second portion where the relatively high second electric field is applied when the reverse voltage is applied. The reverse leakage current can be suppressed by the relatively high second Schottky barrier. On the other hand, since the reverse leakage current is less likely to exceed the Schottky barrier even if the Schottky barrier height is lowered, the first Schottky barrier with a relatively low first electric field is applied. By using the barrier, a current can be preferentially passed at a low voltage when a forward voltage is applied. Therefore, with this configuration, it is possible to efficiently reduce the reverse leakage current and the forward voltage.

In the semiconductor device of the present invention, the semiconductor layer is formed on the base drift layer having the first impurity concentration and the second impurity concentration relatively higher than the first impurity concentration. The electric field relaxation portion is preferably formed such that the deepest portion reaches the low resistance drift layer.

  In the unit cell partitioned by the electric field relaxation part, the region (current path) through which current can flow is restricted, so that the resistance value of the unit cell increases when the impurity concentration in the part of the semiconductor layer forming the unit cell is low. There is a risk. Therefore, as described above, by forming the electric field relaxation portion so that the deepest portion reaches the low resistance drift layer, all or part of the unit cells can be formed of the low resistance drift layer. Therefore, in the portion where the low resistance drift layer is formed, even if the current path is narrowed, an increase in resistance value can be suppressed by the low resistance drift layer having a relatively high second impurity concentration. As a result, the resistance of the unit cell can be reduced.

  The first impurity concentration of the base drift layer may decrease from the back surface to the front surface of the semiconductor layer. The second impurity concentration of the low-resistance drift layer may be constant from the back surface to the front surface of the semiconductor layer, or may decrease as the semiconductor layer moves from the back surface to the front surface. You may do it.

In the semiconductor device of the present invention, the semiconductor layer further includes a surface drift layer formed on the low resistance drift layer and having a third impurity concentration relatively lower than the second impurity concentration. preferable.
With this configuration, since the impurity concentration near the surface of the semiconductor layer can be reduced, the electric field strength applied to the surface of the semiconductor layer when a reverse voltage is applied can be reduced. As a result, the reverse leakage current can be further reduced.

Further, when the semiconductor device of the present invention further includes a substrate made of a wide band gap semiconductor of the first conductivity type that supports the semiconductor layer, the semiconductor layer is formed on the substrate and has the first impurity concentration. In contrast, a buffer layer having a relatively high fourth impurity concentration may be further included.
In the semiconductor device of the present invention, the lower end portion of the pillar layer may be in contact with the buffer layer or may be positioned so as to be spaced from the buffer layer.

  In the semiconductor device of the present invention, the wide band gap semiconductor (with a band gap of 2 eV or more) is a semiconductor having a dielectric breakdown electric field larger than 1 MV / cm, for example, specifically SiC (for example, 4H-SiC The breakdown electric field is about 2.8 MV / cm, the band gap width is about 3.26 eV), GaN (the breakdown electric field is about 3 MV / cm, the band gap width is about 3.42 eV), diamond ( The breakdown electric field is about 8 MV / cm, and the band gap width is about 5.47 eV).

1 is a schematic plan view of a Schottky barrier diode according to a first embodiment of the present invention. It is sectional drawing of the Schottky barrier diode of FIG. 1, Comprising: The cut surface in the cutting line II-II of FIG. 1 is shown. It is a figure which shows an example of the shape of the electric field relaxation layer of FIG. 2A. It is a figure which shows the other example of the shape of the electric field relaxation layer of FIG. 2A. It is a schematic block diagram of the Schottky barrier diode used for the simulation experiment for proving the introduction effect of a super junction structure. It is a graph which shows the relationship between the thickness of an epitaxial layer, and electric field strength. It is a schematic block diagram of the Schottky barrier diode used for the simulation experiment for proving the introduction effect of a high resistance layer. It is a graph which shows the relationship between the thickness of an epitaxial layer, and electric field strength. It is the schematic diagram showing the unit cell of the crystal structure of 4H-SiC. It is a figure which shows the stripe direction of a p-type pillar layer. It is a graph which shows the relationship between each part of the surface of a unit cell, and electric field strength. It is a figure for demonstrating the impurity concentration of a board | substrate and an epitaxial layer. It is a figure which shows a part of manufacturing process of the Schottky barrier diode of FIG. 2A. It is a figure which shows the next | following process of FIG. 11A. It is a figure which shows the next | following process of FIG. 11B. It is a figure which shows the next process of FIG. 11C. FIG. 11D is a diagram showing a step subsequent to FIG. 11D. It is a figure which shows the next process of FIG. 11E. It is a figure which shows the next process of FIG. 11F. It is sectional drawing of the Schottky barrier diode which concerns on 2nd Embodiment of this invention. It is an enlarged view of the trench of FIG. It is a distribution map (simulation data) of the electric field intensity at the time of reverse voltage application, and shows a case without a trench structure. It is a distribution map (simulation data) of electric field intensity at the time of applying a reverse voltage, and shows a case with a rectangular trench structure. It is a distribution figure (simulation data) of the electric field strength at the time of reverse direction voltage application, Comprising: The case with a U-shaped trench structure is shown. It is a distribution map (simulation data) of the electric field intensity at the time of reverse voltage application, and shows a case with a trapezoidal trench structure. It is a distribution map (simulation data) of the electric field intensity at the time of reverse voltage application, and shows the case where there is a trapezoidal trench structure + bottom surface p-type layer. It is a distribution map (simulation data) of the electric field intensity at the time of reverse direction voltage application, Comprising: The case where there exists a trapezoidal trench structure + side p-type layer is shown. It is a graph which shows the current-voltage (IV) curve of a Schottky barrier diode. FIG. 13 is a diagram illustrating a part of the manufacturing process of the Schottky barrier diode of FIG. 12. It is a figure which shows the next process of FIG. 21A. It is a figure which shows the next | following process of FIG. 21B. It is a figure which shows the next | following process of FIG. 21C. FIG. 21D is a diagram showing a step subsequent to that in FIG. 21D. It is a figure which shows the next process of FIG. 21E. It is a figure which shows the next process of FIG. 21F. It is a figure which shows the next | following process of FIG. 21G. FIG. 21B is a diagram showing a step subsequent to that in FIG. 21H. FIG. 21D is a diagram showing a step subsequent to that in FIG. 21I. 22 (a), (b), (c), (d), (e), and (f) are diagrams showing modifications of the cross-sectional shape of the trench, and FIG. 22 (a) is a first modification, and FIG. b) is a second modification, FIG. 22 (c) is a third modification, FIG. 22 (d) is a fourth modification, FIG. 22 (e) is a fifth modification, and FIG. 22 (f) is a sixth modification. Each example is shown. It is a figure which shows the 1st modification of the Schottky barrier diode of FIG. 2A. It is a figure which shows the 2nd modification of the Schottky barrier diode of FIG. 2A. It is a figure which shows the 3rd modification of the Schottky barrier diode of FIG. 2A.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Overall Configuration of Schottky Barrier Diode According to First Embodiment>
FIG. 1 is a schematic plan view of a Schottky barrier diode 1 according to the first embodiment of the present invention. 2A is a cross-sectional view of the Schottky barrier diode 1 of FIG. 1 and shows a cut surface taken along the section line II-II of FIG.

  A Schottky barrier diode 1 as a semiconductor device employs a 4H-SiC (a wide band gap semiconductor having a dielectric breakdown electric field of about 2.8 MV / cm and a band gap of about 3.26 eV). The diode is, for example, a chip having a square shape in plan view. The chip-like Schottky barrier diode 1 has a length of about several millimeters in the vertical and horizontal directions on the paper surface of FIG.

The Schottky barrier diode 1 includes a substrate 2 (substrate having an off angle of 4 °) made of n ⁺ type SiC. The thickness of the substrate 2 is, for example, 50 μm to 600 μm. As the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), or the like can be used.
A cathode electrode 4 as an ohmic electrode is formed on the back surface 3 ((000-1) C surface) of the substrate 2 so as to cover the entire region. The cathode electrode 4 is made of a metal (for example, Ti / Ni / Ag, Ti / Ni / Au / Ag) that is in ohmic contact with n-type SiC.

An n-type epitaxial layer 6 as an example of a semiconductor layer is formed on the surface 5 ((0001) Si surface) of the substrate 2.
The epitaxial layer 6 has a structure in which a buffer layer 7 and a drift layer having a three-layer structure including a base drift layer 8, a low resistance drift layer 9, and a surface drift layer 10 are laminated in this order from the surface 5 of the substrate 2. Have. The buffer layer 7 forms the back surface 11 ((000-1) C surface) of the epitaxial layer 6 and is in contact with the surface 5 of the substrate 2. On the other hand, the surface drift layer 10 forms the surface 12 ((0001) Si surface) of the epitaxial layer 6.

The total thickness T of the epitaxial layer 6 is, for example, 3 μm to 100 μm. Further, the thickness t ₁ of the buffer layer 7 is, for example, 0.1 μm to ₁ μm. The thickness t2 of the base drift layer 8 is, for example, ₂ μm to 100 μm. The thickness t ₃ of the low resistance drift layer 9 is, for example, 1 μm to ₃ μm. The thickness t ₄ of the surface drift layer 10 is, for example, 0.2 μm to 0.5 μm.

On the surface 12 of the epitaxial layer 6, a field insulating film 16 having a contact hole 14 exposing a part of the epitaxial layer 6 as an active region 13 and covering a field region 15 surrounding the active region 13 is formed. The field insulating film 16 is made of, for example, SiO ₂ (silicon oxide). Further, the thickness of the field insulating film 16 is, for example, 0.5 μm to 3 μm.

In the epitaxial layer 6, a stripe-shaped p-type pillar layer 17 is formed so as to penetrate the drift layers 8 to 10 from the surface 12 and have the deepest portion located at the interface between the buffer layer 7 and the base drift layer 8. .
The striped p-type pillar layer 17 includes a plurality of p-type pillar layers 17 extending linearly along the opposing direction of a pair of opposite sides of the Schottky barrier diode 1 so that the active region 13 and the field It is formed by being arranged in parallel over the region 15. The distance W _SJ between the p-type pillar layers 17 adjacent to each other is, for example, 2 μm to 20 μm. The width _{W P} perpendicular to the longitudinal direction of the p-type pillar layer 17 is, for example, 0.1 m to 10 m. The depth _{D SJ} of each p-type pillar layer 17 is, for example, 3Myuemu～25myuemu. In addition, as an impurity for forming the p-type pillar layer 17, B (boron), Al (aluminum), etc. can be used, for example.

By forming the p-type pillar layer 17, the epitaxial layer 6 is sandwiched between the striped p-type pillar layer 17 and the adjacent p-type pillar layers 17 to maintain the conductivity type of the epitaxial layer 6. The n-type pillar layers 18 are alternately arranged in the direction along the surface 12 of the epitaxial layer 6 to form a super junction structure.
In the active region 13, the uppermost portion of each p-type pillar layer 17 (near the surface 12 of the epitaxial layer 6) penetrates the surface drift layer 10 from the surface 12, and the deepest portion is located in the middle of the low resistance drift layer 9. An electric field relaxation layer 19 is formed. The depth D _R (the distance from the surface 12 of the epitaxial layer 6 to the deepest portion of the electric field relaxation layer 19) of the electric field relaxation layer 19 is, for example, 1000 to 10,000 mm.

Thereby, in the epitaxial layer 6, unit cells 20 (line cells) partitioned by being sandwiched between adjacent electric field relaxation layers 19 are formed in a stripe shape. In each unit cell 20, a base portion occupying most of the region is formed by the low resistance drift layer 9, and a surface layer portion on the surface 12 side with respect to the base portion is formed by the surface drift layer 10.
The electric field relaxation layer 19 partitioning the unit cell 20 is a layer having an impurity concentration higher than that of the p-type pillar layer 17 and a resistance higher than that of each of the drift layers 8 to 10. For example, the sheet resistance of the electric field relaxation layer 19 is 1 MΩ / □ or more.

The electric field relaxation layer 19 may have a higher impurity concentration than that of the p-type pillar layer 17 but may be a p-type layer that does not have a high resistance.
When the electric field relaxation layer 19 is a high resistance layer, for example, the activation rate of impurities of the electric field relaxation layer 19 contained at a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ is less than 5%, Preferably, the sheet resistance in the above range is achieved by setting the content to 0% to 0.1%. The impurity activation rate indicates the ratio of the number of activated impurity ions to the total number of impurity ions implanted into the epitaxial layer 6 in the manufacturing process of the Schottky barrier diode 1.

  Further, for example, as shown in FIG. 2B, the electric field relaxation layer 19 is formed from the p-type pillar layer 17 so as to be inside the p-type pillar layer 17 with respect to the interface between the p-type pillar layer 17 and the epitaxial layer 6. The p-type pillar layer may be formed so as to protrude outside the p-type pillar layer 17 with respect to the interface between the p-type pillar layer 17 and the epitaxial layer 6 as shown in FIG. 2C. It may be formed wider than 17. When the electric field relaxation layer 19 is a p-type layer that is not high resistance, the narrow shape of FIG. 2B is preferable, and when the electric field relaxation layer 19 is a high resistance layer, the wide shape of FIG. 2C is preferable.

An anode electrode 21 is formed on the field insulating film 16. The anode electrode 21 includes a Schottky metal 22 as an example of a Schottky electrode bonded to the epitaxial layer 6 in the contact hole 14 of the field insulating film 16, and a contact metal 23 stacked on the Schottky metal 22. It has a two-layer structure.
The Schottky metal 22 straddles between the first metal 24 as an example of the first electrode formed on the surface 12 of each unit cell 20 and the electric field relaxation layer 19 adjacent to each other, and is sandwiched between the electric field relaxation layers 19. And a second metal 25 as an example of a second electrode formed so as to cover the first metal 24 on the surface 12 of the unit cell 20.

The first metal 24 is linearly formed along the longitudinal direction of the electric field relaxation layer 19 at the central portion 27 sandwiched between the peripheral edge portions 26 of the unit cells 20 adjacent to the electric field relaxation layer 19.
The second metal 25 is formed so as to cover the entire active region 13 and is buried in the contact hole 14 of the field insulating film 16. The second metal 25 is in contact with the peripheral edge 26 of the surface 12 of each unit cell 20. Further, the second metal 25 protrudes outward from the contact hole 14 in a flange shape so as to cover the peripheral portion of the contact hole 14 in the field insulating film 16 from above. That is, the peripheral edge portion of the field insulating film 16 is sandwiched by the epitaxial layer 6 (surface drift layer 10) and the second metal 25 from the upper and lower sides over the entire circumference. Therefore, the outer peripheral region of the Schottky junction in epitaxial layer 6 (that is, the inner edge portion of field region 15) is covered with the peripheral portion of field insulating film 16 made of SiC.

  The contact metal 23 is a portion of the anode electrode 21 that is exposed on the outermost surface of the Schottky barrier diode 1 and to which a bonding wire or the like is bonded. The contact metal 23 is made of, for example, Al (aluminum). Further, like the Schottky metal 22 (second metal 25), the contact metal 23 is flanged outwardly from the contact hole 14 so as to cover the periphery of the contact hole 14 in the field insulating film 16 from above. It is overhanging.

In the field region 15, the upper end portion of each p-type pillar layer 17 (near the surface 12 of the epitaxial layer 6) penetrates the surface drift layer 10 from the surface 12 of the epitaxial layer 6, and the deepest portion is the low resistance drift layer 9. A high resistance guard ring 28 is formed in the middle. The guard ring 28 is formed in an annular shape along the contour of the contact hole 14 so as to straddle the contact hole 14 of the field insulating film 16 in the plan view (so as to straddle the active region 13 and the field region 15). Has been. The depth _{D G} from the surface 12 of the epitaxial layer 6 of the guard ring 28, for example, the same depth as the electric field relaxation layer 19 (e.g., 1000Å~10000Å).

The guard ring 28 is a layer that exhibits the same characteristics as the electric field relaxation layer 19. For example, when the electric field relaxation layer 19 is a high resistance layer, the guard ring 28 is a layer having a higher resistance than the drift layers 8 to 10 and has a sheet resistance of 1 MΩ / □, similarly to the high resistance layer. The activation rate of impurities is less than 5% (preferably 0% to 0.1%).
A surface protection film 29 made of, for example, silicon nitride (SiN) is formed on the outermost surface of the Schottky barrier diode 1. An opening 30 for exposing the anode electrode 21 (contact metal 23) is formed at the center of the surface protective film 29. A bonding wire or the like is bonded to the contact metal 23 through the opening 30.

In this Schottky barrier diode 1, an active region of the epitaxial layer 6 is transferred from the cathode electrode 4 to the anode electrode 21 by being in a forward bias state in which a positive voltage is applied to the anode electrode 21 and a negative voltage is applied to the cathode electrode 4. Electrons (carriers) move through 13 and current flows. <Introduction effect of super junction structure>
Next, with reference to FIG. 3 and FIG. 4, the effect of improving the breakdown voltage by forming the super junction structure in the epitaxial layer 6 will be described.

The super junction structure was designed as shown in FIG. In FIG. 3, parts corresponding to the parts shown in FIG. 2A are denoted by the same reference numerals as those given to the respective parts. Incidentally, (the width of the n-type pillar layer 18) the distance of the p-type pillar layer 17 _{W SJ} is 5 [mu] m, a width _{W P} is 3.5μm of p-type pillar layer 17, the barrier height SB of the Schottky metal 22 and the epitaxial layer 6 It was set to 1.4 eV. The depth D _SJ of the p-type pillar layer 17 is made variable value.

Then, how the electric field intensity distribution in the epitaxial layer 6 when a reverse voltage (1200 V) is applied between the anode and the cathode in FIG. 3 changes depending on the presence or absence of the super junction structure and the depth _DSJ. Simulated. As a simulator, TCAD (product name) manufactured by Synopsys was used. The results are shown in FIG.
As shown in FIG. 4, in the Schottky barrier diode (conventional) in which the super junction structure is not formed, the electric field strength increases proportionally from the back surface 11 to the front surface 12 of the epitaxial layer 6. It became the maximum (about 1.15 × 10 ⁶ V / cm) on the surface 12.

On the other hand, in the Schottky barrier diode 1 in which the super junction structure is formed, the electric field strength can be made uniform from the back surface 11 to the front surface 12 as compared with the case where there is no super junction structure. Especially, the depth _{D SJ} is 5μm of p-type pillar layer 17, 10 [mu] m, 15 [mu] m, more deeper and 20 [mu] m, the effect is large. For example, when D _SJ = 20 μm, the electric field strength is approximately constant at about 6.0 × 10 ⁵ V / cm.

As a result, it was confirmed that the breakdown voltage can be improved as compared with the conventional structure in which the super junction structure is not formed under the same conditions of the impurity concentration and the thickness of the epitaxial layer 6. Therefore, according to the Schottky barrier diode 1 of the present embodiment, a sufficient breakdown voltage can be ensured even with the epitaxial layer 6 having a higher impurity concentration and a smaller thickness than in the conventional case, so that the impurity concentration and thickness of the epitaxial layer 6 can be ensured. It was confirmed that the forward voltage can be reduced while ensuring a high breakdown voltage by properly designing.
<Effect of introducing electric field relaxation layer 19>
With reference to FIGS. 5 and 6, the effect of reducing the reverse leakage current and the forward voltage by forming the electric field relaxation layer 19 in the epitaxial layer 6 will be described.

As the Schottky barrier diode having the electric field relaxation layer 19, aluminum is formed on the surface 12 of the epitaxial layer 6 of the Schottky barrier diode 1 (W _SJ = 5 μm, W _P = 3.5 μm, D _SJ = 20 μm) having the structure of FIG. The electric field relaxation layer 19 (Al layer) containing (Al) as an impurity was formed. The depth D _R of the electric field relaxation layer (Al layer) 19 is set to 1 [mu] m, the impurity concentration of the electric field relaxation layer 19 is a variable value.

Then, how the electric field intensity distribution in the epitaxial layer 6 when a reverse voltage (1200 V) is applied between the anode and the cathode in FIG. 5 depends on the presence / absence of the electric field relaxation layer 19 and the impurity concentration of the electric field relaxation layer 19. We simulated how it changed. As a simulator, TCAD (product name) manufactured by Synopsys was used. The results are shown in FIG.
As shown in FIG. 6, in the Schottky barrier diode 1 in which the electric field relaxation layer 19 is formed, the electric field strength on the surface 12 of the epitaxial layer 6 can be reduced as compared with the case where the electric field relaxation layer 19 is not provided. . In particular, the higher the concentration of the electric field relaxation layer 19 was 1 × 10 ¹⁶ cm ⁻³ , 3 × 10 ¹⁶ cm ⁻³ , and 1 × 10 ¹⁷ cm ⁻³ , the greater the effect. For example, in the case of concentration = 1 × 10 ¹⁶ cm ⁻³ , the electric field strength at the surface 12 of the epitaxial layer 6 was about 6.3 × 10 ⁵ V / cm, whereas the concentration = 1 × 10 ^17. In the case of cm ⁻³ , the electric field strength could be reduced to about 5.5 × 10 ⁵ V / cm.

As a result, in the Schottky barrier diode 1 of the present embodiment, the barrier height between the anode electrode 21 (Schottky metal 22) in contact with the surface 12 of the epitaxial layer 6 (the surface of the unit cell 20) and the epitaxial layer 6 is lowered. However, it was confirmed that the reverse leakage current exceeding the barrier height can be reduced because the electric field strength at the surface 12 is weak when a reverse voltage close to the breakdown voltage is applied. That is, it was confirmed that the forward voltage can be reduced by lowering the barrier height while reducing the reverse leakage current.
<Relationship between stripe direction of p-type pillar layer 17 and SiC crystal structure>
Next, the relationship between the stripe direction of the p-type pillar layer 17 and the SiC crystal structure will be described with reference to FIGS.

  FIG. 7 is a schematic diagram illustrating a unit cell having a crystal structure of 4H—SiC. FIG. 8 is a diagram showing the stripe direction of the p-type pillar layer 17. In the perspective view of the SiC crystal structure shown in the lower part of FIG. 7, only two layers are extracted from the four layers of the SiC laminated structure shown on the side. Also, the diagram shown on the left side of FIG. 8 is a diagram of the unit cell of FIG. 7 viewed from directly above the (0001) plane.

The SiC used for the Schottky barrier diode 1 of the present embodiment includes 3C-SiC, 4H-SiC, 6H-SiC, and the like depending on the crystal structure.
Among these, the crystal structure of 4H—SiC can be approximated in a hexagonal system as shown in FIGS. 7 and 8, and four carbon atoms are bonded to one silicon atom. Four carbon atoms are located at four vertices of a regular tetrahedron having a silicon atom arranged at the center. Of these four carbon atoms, one silicon atom is located in the [0001] axis direction with respect to the carbon atom, and the other three carbon atoms are located on the [000-1] axis side with respect to the silicon atom. Yes.

The [0001] axis and the [000-1] axis are along the axial direction of the hexagonal column, and the plane (the top surface of the hexagonal column) having the [0001] axis as a normal line is the (0001) plane (Si plane). On the other hand, the surface (the lower surface of the hexagonal column) whose normal is the [000-1] axis is the (000-1) surface (C surface).
Further, the directions passing through the apexes that are not adjacent to each other of the hexagonal note when viewed from directly above the (0001) plane and the [0001] axis are respectively a ₁ axis [2-1-10], a _Two axes [-12-10] and a _three axes [-1-120].

As shown in FIG. 8, the direction passing through the apex between the a ₁ axis and the a ₂ axis is the [11-20] axis, and the direction passing through the apex between the a ₂ axis and the a ₃ axis is [- 2110] an axial direction passing through the vertex between _{a 3} axis and _{a 1-axis} is [1-210] axis.
Between each of the six axes passing through the vertices of the hexagonal note, the axis that is inclined at an angle of 30 ° with respect to the respective axes on both sides thereof, and the axis that is the normal line on each side of the hexagonal note is a [10-10] axis, [1-100] axis, [0-110] axis, [-1010] axis, [-1100] axis in order clockwise from between the ₁ axis and the [11-20] axis. And the [01-10] axis. Each plane (side surface of the hexagonal column) having these axes as normals is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

In this embodiment, the substrate 2 having the (0001) plane as the main surface (surface 5) is used, and the epitaxial layer 6 is grown thereon so that the (0001) plane becomes the main surface. Examples of the stripe direction of the p-type pillar layer 17 include, for example, parallel to the [1-100] axis (0 °), perpendicular to the [1-100] axis (90 °), and to the [1-100] axis. On the other hand, there are various patterns such as 45 ° inclination. Note that the stripe pattern shown in FIG. 8 is merely an example, and various stripe patterns can be adopted as necessary.
<Two Schottky electrodes (first metal 24 and second metal 25)>
Next, with reference to FIG. 9, the efficiency of reducing the reverse leakage current and the forward voltage due to the provision of the two Schottky electrodes (the first metal 24 and the second metal 25) will be described.

FIG. 9 is a graph showing the relationship between each part of the surface 12 of the unit cell 20 and the electric field strength.
In the Schottky barrier diode 1 of the present embodiment, as a result of the simulation shown in <Effect of introduction of the electric field relaxation layer 19> as described above, as shown in FIG. It has been found that there are a high portion (the central portion 27 of the unit cell 20) and a low portion (the peripheral portion 26 of the unit cell 20).

Specifically, as shown in FIG. 9, the peripheral portion 26 of the unit cell 20 as an example of the first portion of the semiconductor layer is 1.0 × 10 ⁵ V / cm to 1.3 × 10 ⁶ V / cm. The electric field strength of about 1.5 × 10 ⁶ V / cm is distributed in the central portion 27 of the unit cell 20 as an example of the second portion of the semiconductor layer. In the electric field strength distribution when a reverse voltage is applied, the electric field strength (second electric field) of the central portion 27 of the unit cell 20 is higher than the electric field strength (first electric field) of the peripheral portion 26 of the unit cell 20. .

  Accordingly, a p-type polysilicon or the like that forms a relatively high potential barrier (for example, 1.4 eV) is formed as a first metal 24 at the central portion 27 of the unit cell 20 to which a relatively high electric field is applied. When the electrode is a semiconductor electrode such as polysilicon, it may be a heterojunction between semiconductors having different band gaps instead of a Schottky junction.

On the other hand, aluminum (Al) or the like that forms a relatively low potential barrier (for example, 0.7 eV) is Schottky bonded as the second metal 25 to the peripheral portion 26 of the unit cell 20 to which a relatively low electric field is applied.
As a result, in the central portion 27 of the unit cell 20 where a relatively high electric field is applied when a reverse voltage is applied, a high Schottky barrier (second Schottky barrier between the first metal 24 (polysilicon) and the epitaxial layer 6 is provided. ) Can suppress reverse leakage current.

  On the other hand, in the peripheral portion 26 of the unit cell 20 to which a relatively low electric field is applied, the reverse leakage current is not affected even if the Schottky barrier height between the second metal 25 (aluminum) and the epitaxial layer 6 is lowered. Less likely to cross the Schottky barrier. Therefore, by using a low Schottky barrier (first Schottky barrier), a current can be preferentially passed at a low voltage when a forward voltage is applied. The second metal 25 can also serve as the contact metal 23 by omitting the contact metal 23.

Thus, by appropriately selecting the anode electrode 21 (Schottky electrode) according to the electric field intensity distribution of the unit cell 20 when the reverse voltage is applied, the reverse leakage current and the forward voltage can be efficiently reduced. I was able to confirm that I could do it.
<Impurity concentration of epitaxial layer 6>
Next, with reference to FIG. 10, the magnitude | size of the impurity concentration of the board | substrate 2 and the epitaxial layer 6 is demonstrated.

FIG. 10 is a diagram for explaining the impurity concentrations of the substrate 2 and the epitaxial layer 6.
As shown in FIG. 10, both the substrate 2 and the epitaxial layer 6 are made of n-type SiC containing an n-type impurity. The relationship between the impurity concentrations is: substrate 2> buffer layer 7> drift layers 8-10.
The density | concentration of the board | substrate 2 is substantially constant at 5 * 10 < ¹⁸ > -5 * 10 < ¹⁹ > cm < ^-3 > along the thickness direction, for example. The concentration of the buffer layer 7 is, for example, constant at 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ along the thickness direction or low along the surface 5.

The concentration of the drift layers 8 to 10 changes stepwise with respect to the interfaces of the base drift layer 8, the low resistance drift layer 9 and the surface drift layer 10. That is, there is a difference in density between the layer on the front surface 12 side and the layer on the back surface 11 side with respect to each interface.
The concentration of the base drift layer 8 is constant, for example, 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ along the thickness direction. Note that the concentration of the base drift layer 8 is about 3 × 10 ¹⁶ cm ⁻³ to about 5 × 10 ¹⁵ cm ^{−3 as it} goes from the back surface 11 to the front surface 12 of the epitaxial layer 6 as indicated by a broken line in FIG. It may be decreased continuously.

The concentration of the low resistance drift layer 9 is higher than the concentration of the base drift layer 8 and is constant, for example, 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ along the thickness direction thereof. Note that the concentration of the low-resistance drift layer 9 is about 3 × 10 ¹⁷ cm ⁻³ to about 1 × 10 ¹⁶ cm ^{− as it} goes from the back surface 11 to the front surface 12 of the epitaxial layer 6 as shown by a broken line in FIG. ^It may be decreased continuously to ³ .

The concentration of the surface drift layer 10 is lower than the concentration of the base drift layer 8 and the low resistance drift layer 9, and is constant, for example, 5 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻³ along the thickness direction thereof. .
As shown in FIG. 2A, in the unit cell 20 (line cell) partitioned by the stripe-shaped electric field relaxation layer 19, a region (current path) through which a current can flow is a distance between adjacent electric field relaxation layers 19 (that is, Since the distance W _SJ of the p-type pillar layer 17 is limited, if the impurity concentration of the portion of the epitaxial layer 6 where the unit cell 20 is formed is low, the resistance value of the unit cell 20 may increase.

Therefore, as shown in FIG. 10, by making the concentration of the low resistance drift layer 9 forming the base portion of the unit cell 20 higher than that of the base drift layer 8, the current path is restricted by the distance _WSJ of the electric field relaxation layer 19. Even so, an increase in the resistance value of the unit cell 20 can be suppressed by the low resistance drift layer 9 having a relatively high concentration. As a result, the resistance of the unit cell 20 can be reduced.

On the other hand, the surface layer portion of the unit cell 20 in contact with the Schottky metal 22 is provided with the surface drift layer 10 having a relatively low concentration, thereby reducing the electric field strength applied to the surface 12 of the epitaxial layer 6 when a reverse voltage is applied. be able to. As a result, the reverse leakage current can be further reduced.
<Method for Manufacturing Schottky Barrier Diode 1 (First Embodiment)>
Next, a method for manufacturing the Schottky barrier diode 1 of FIG. 2A will be described with reference to FIGS. 11A to 11G.

First, as shown in FIG. 11A, the buffer layer 7, the base drift layer 8, the low resistance drift layer 9, and the surface drift layer 10 are epitaxially grown on the substrate 2 in this order.
Next, as shown in FIG. 11B, a hard mask 31 made of SiO ₂ is formed on the surface 12 of the epitaxial layer 6 by, eg, CVD. The thickness of the hard mask 31 is preferably 1.5 μm to 10 μm. Next, after patterning the hard mask 31, the epitaxial layer 6 is dry-etched through the hard mask 31. As a result, a stripe-shaped trench 32 reaching the buffer layer 7 is formed. The depth of the trench 32 is set as appropriate in accordance with the depth D _SJ of the p-type pillar layer 17. The trench 32 is formed by repeating a step of forming a hard mask, a step of dry etching using the hard mask, and a step of removing the hard mask after dry etching in accordance with the depth _DSJ. May be.

Next, after removing the hard mask 31, as shown in FIG. 11C, a p-type SiC layer 33 is epitaxially grown from the inside of the trench 32 until the surface 12 of the epitaxial layer 6 is covered.
Next, as shown in FIG. 11D, the SiC layer 33 outside the trench 32 covering the surface 12 of the epitaxial layer 6 is removed by, for example, etch back. Thereby, the p-type pillar layer 17 embedded in the trench 32 is formed, and at the same time, the n-type pillar layer 18 is formed between the p-type pillar layers 17 adjacent to each other.

Next, as shown in FIG. 11E, a hard mask 34 made of SiO ₂ is formed on the surface 12 of the epitaxial layer 6 by, eg, CVD. The thickness of the hard mask 34 is preferably 1.5 μm to 3 μm. Next, after patterning the hard mask 34, p-type impurities (boron ions) are implanted toward the surface 12 of the epitaxial layer 6 through the hard mask 34 (one-stage implantation). As a result, a high concentration impurity layer 35 in which boron ions are implanted at a high concentration is formed in the surface layer portion of the epitaxial layer 6. Note that a photoresist may be used instead of the hard mask 34 as a mask for covering the surface 12 during ion implantation.

Next, as shown in FIG. 11F, the hard mask 34 is removed, and the epitaxial layer 6 is annealed at a temperature lower than 1500 ° C., preferably 1100 ° C. to 1400 ° C. As a result, the high-concentration impurity layer 35 is transformed into the electric field relaxation layer 19 (high resistance layer) and the guard ring 28, and the electric field relaxation layer 19 is formed at the upper end of each p-type pillar layer 17. It is formed. In such an ion implantation method of boron ions, since boron ions are relatively light ions, they can be easily implanted from the surface 12 to a deep position. Therefore, the depth D _R of the electric field relaxation layer 19, can be easily controlled over a wide range up to a deep position from the shallow position with respect to the surface 12 of the epitaxial layer 6.

  11E and 11F show a method of forming the electric field relaxation layer 19 as a high resistance layer. To form the electric field relaxation layer 19 as a p-type layer that is not a high resistance layer, for example, FIG. In the step 11E, p-type impurities (aluminum ions) are implanted toward the surface 12 of the epitaxial layer 6 through the hard mask 34. Next, in the step of FIG. 11F, the hard mask 34 is peeled off, and the epitaxial layer 6 is annealed at a temperature of 1500 ° C. to 1800 ° C. Thereby, the p-type layer can be formed.

Thereafter, as shown in FIG. 11G, the field insulating film 16, the anode electrode 21, the surface protective film 29, the cathode electrode 4 and the like are formed.
Through the above steps, the Schottky barrier diode 1 of FIG. 2A is obtained.
<Overall Configuration of Schottky Barrier Diode According to Second Embodiment>
FIG. 12 is a cross-sectional view of a Schottky barrier diode 41 according to the second embodiment of the present invention. FIG. 13 is an enlarged view of the trench 42 of FIG. In FIG. 12, parts corresponding to those shown in FIG. 2A are given the same reference numerals as those assigned to those parts, and the description thereof is omitted.

  In the active region 13 of the Schottky barrier diode 41 of the second embodiment, the upper end of each p-type pillar layer 17 (near the surface 12 of the epitaxial layer 6) penetrates the surface drift layer 10 from the surface 12, A trench 42 in which the deepest part reaches the middle part of the low resistance drift layer 9 is formed. The trench 42 is a trench having an inverted trapezoidal shape when cut along the width direction orthogonal to the longitudinal direction, and extends linearly along the upper end portion of the p-type pillar layer 17.

Thereby, in the epitaxial layer 6, unit cells 20 (line cells) partitioned by being sandwiched between adjacent trapezoidal trenches 42 are formed in a stripe shape.
Each trapezoidal trench 42 is defined by a bottom surface 43 parallel to the surface 12 of the epitaxial layer 6 and a side surface 44 inclined with respect to the bottom surface 43. Inclination angle theta ₁ side 44, for example, 45 ° to 85 °. The depth of each trapezoidal trench 42 (distance from the surface 12 of the epitaxial layer 6 to the bottom surface 43 of the trapezoidal trench 42) is, for example, 0.3 to 15000 mm. Further, the width W _T (width of the deepest part) orthogonal to the longitudinal direction of each trapezoidal trench 42 is 0.3 μm to 10 μm.

Further, as shown in FIG. 13, the edge portion 45 formed by intersecting the side surface 44 and the bottom surface 43 of each trapezoidal trench 42 is formed in a shape that curves outwardly of the trapezoidal trench 42, The bottom of the trapezoidal trench 42 is formed in a U shape in cross section. The radius of curvature R of the inner surface (curved surface) of the edge portion 45 having such a shape satisfies the following formula (1).
0.01L <R <10L (1)
In Expression (1), L indicates a linear distance between the edge portions 45 facing each other along the width direction of the trench 42 (the unit is not particularly limited as long as the unit is a length unit such as μm, nm, m, etc.). ). Specifically, a width of the parallel bottom 43 to the surface 12 of the epitaxial layer 6, which is a value obtained by subtracting the width of the edge portion 45 from the width W _T of the trench 42.

Moreover, it is preferable that the curvature radius R of the edge part 45 satisfy | fills 0.02L <R <1L ... (2).
The radius of curvature R can be obtained, for example, by photographing the cross section of the trapezoidal trench 42 with a SEM (Scanning Electron Microscope) and measuring the curvature of the edge portion 45 of the obtained SEM image.

  On the bottom surface 43 and the side surface 44 of the trapezoidal trench 42, a p-type layer 46 is formed as an electric field relaxation portion along the inner surface of the trapezoidal trench 42. The p-type layer 46 is formed from the bottom surface 43 of the trapezoidal trench 42 through the edge 45 to the opening end of the trapezoidal trench 42. Further, for example, as shown in FIG. 13, the p-type layer 46 is formed from the p-type pillar layer 17 so as to be contained inside the p-type pillar layer 17 with respect to the interface between the p-type pillar layer 17 and the epitaxial layer 6. Is also formed narrow. The p-type layer 46 forms a pn junction with the n-type epitaxial layer 6. As a result, the Schottky barrier diode 41 incorporates a pn diode 47 constituted by the p-type layer 46 and the n-type epitaxial layer 6 (low resistance drift layer 9).

The thickness of p-type layer 46 (depth from the inner surface of trapezoidal trench 42) is measured along the depth direction of trapezoidal trench 42 (direction perpendicular to surface 12 of epitaxial layer 6), as shown in FIG. The first thickness t ₅ from the bottom surface 43 of the trapezoidal trench 42 is measured from the side surface 44 of the trapezoidal trench 42 measured along the width direction of the trapezoidal trench 42 (direction parallel to the surface 12 of the epitaxial layer 6). greater than the second thickness _{t 6.} Specifically, first the thickness _{t 5} is, for example, a 0.3Myuemu～0.7Myuemu, second thickness _{t 6} is, for example, 0.1 .mu.m to 0.5 .mu.m.

Further, in the p-type layer 46, a p ⁺ -type contact layer 48 into which impurities are implanted at a higher concentration than other parts of the p-type layer 46 is formed on a part of the bottom surface 43 of the trapezoidal trench 42. . For example, the impurity concentration of the contact layer 48 is 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of the other part of the p-type layer 46 excluding the contact layer 48 is 1 × 10 ^{17 to} 5 ×. 10 ¹⁸ cm ⁻³ .

The contact layer 48 is formed linearly along the longitudinal direction of the trapezoidal trench 42 and has a depth (for example, 0.05 μm to 0 μm) from the bottom surface 43 of the trapezoidal trench 42 to the middle of the p-type layer 46 in the depth direction. .2 μm).
Further, in the field region 15 of the Schottky barrier diode 41, the deepest portion penetrates the surface drift layer 10 from the surface 12 to the upper end portion (near the surface 12 of the epitaxial layer 6) of each p-type pillar layer 17. An annular trench 69 reaching the middle part of the low resistance drift layer 9 is formed. The annular trench 69 is formed so as to surround the active region 13.

A guard ring 72 is formed on the bottom surface 70 and the side surface 71 of the annular trench 69 so as to be exposed on the inner surface of the annular trench 69. The guard ring 72 is formed in the same process as the p-type layer 46 and has the same impurity concentration (for example, 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ ) and thickness as the p-type layer 46. Have.
The guard ring 72 may have a portion having an impurity concentration lower than that of the p-type layer 46 (the remaining portion of the guard ring 72) and higher than that of the p-type pillar layer 17 on the outer periphery thereof.
<Effect of introducing the trench 42 structure>
Next, the effect of reducing the reverse leakage current and the forward voltage by forming the trapezoidal trench 42 and the p-type layer 46 in the epitaxial layer 6 will be described with reference to FIGS. The trench in FIG. 15 is a rectangular trench 42 ′, and the trench in FIG. 16 is a U-shaped trench 42 ″.

FIGS. 14 to 19 are electric field intensity distribution diagrams (simulation data) when a reverse voltage is applied. FIG. 14 shows a case without a trench structure, FIG. 15 shows a rectangular trench structure, and FIG. When there is a trench structure (θ ₁ = 90 °, R = 0.125L or 1 / (1 × 10 ⁷ ) (m)), FIG. 17 shows a trapezoidal trench structure (θ ₁ = 115 °> 90 °, R = 0 .125L or 1 / (1 × 10 ⁷ ) (m)), FIG. 18 shows a trapezoidal trench structure (θ ₁ = 115 °> 90 °, R = 0.125L or 1 / (1 × 10 ⁷ ) ( m)) + with bottom p-type layer, FIG. 19 shows a trapezoidal trench structure (θ ₁ = 115 °> 90 °, R = 0.125L or 1 / (1 × 10 ⁷ ) (m)) + side p-type Each case with layers is shown. 14 to 19, portions corresponding to the respective portions illustrated in FIGS. 12 and 13 are denoted by the same reference numerals as those denoted for the respective portions.

First, the structures of FIGS. 14 to 19 were designed as follows.
N ⁺ type substrate 2: concentration is 1 × 10 ¹⁹ cm ⁻³ thickness is 1 μm
N ⁻ type epitaxial layer 6: concentration is 1 × 10 ¹⁶ cm ⁻³ thickness is 5 μm
・ Trench 42, 42 ', 42'': depth is 1.05 μm
The curvature radius R of the edge portion 45 of the trenches 42, 42 ′, 42 ″:
P-type layer 46: concentration is 1 × 10 ¹⁸ cm ⁻³
Then, the electric field strength distribution in the epitaxial layer 6 was simulated when a reverse voltage (600 V) was applied between the anode and the cathode of the Schottky barrier diode 41 having the structure of each of FIGS. As a simulator, TCAD (product name) manufactured by Synopsys was used.

As shown in FIG. 14, in a Schottky barrier diode in which no trench structure is formed and the surface 12 of the epitaxial layer 6 is flat, the electric field strength increases from the back surface 11 to the surface 12 of the epitaxial layer 6. It became strong and was the maximum (about 1.5 × 10 ⁶ V / cm) on the surface 12 of the epitaxial layer 6.
Further, as shown in FIG. 15, in a Schottky barrier diode in which a rectangular trench 42 'structure having a sharp edge 45 is formed, the rectangular trench 42' is formed so as to be sandwiched between adjacent rectangular trenches 42 '. It was possible to weaken the electric field strength in the portion (unit cell 20). For example, the electric field strength at the central portion 27 of the unit cell 20 could be reduced to about 9 × 10 ⁵ V / cm.

Further, as shown in FIGS. 16 and 17, a Schottky barrier in which a U-shaped trench 42 ″ and a trapezoidal trench 42 structure are formed, and a p-type layer 46 is not formed on the inner surfaces of these trenches 42, 42 ″. In the diode, due to the formation of the trench 42, 42 ″ structure, the electric field strength at the portion (unit cell 20) sandwiched between the trapezoidal trenches 42 adjacent to each other is weakened, and the portion where the electric field strength is maximum is trapezoidal. The entire bottom surface 43 of the trench 42 has been shifted. Specifically, the electric field strength of the central portion 27 of the unit cell 20 is weakened to about 9 × 10 ⁵ V / cm, and the electric field strength of the peripheral portion 26 of the unit cell 20 is weakened to about 3 × 10 ⁵ V / cm. The electric field strength of the entire bottom surface 43 of the trapezoidal trench 42 was maximum at about 1.5 × 10 ⁶ V / cm.

Further, as shown in FIG. 18, in the Schottky barrier diode in which the p-type layer 46 is formed on the bottom surface 43 and the edge portion 45 of the trapezoidal trench 42, the electric field strength at the bottom surface 43 of the trapezoidal trench 42 is weakened. The portion where the electric field strength was maximum was shifted to the side surface 44 of the trapezoidal trench 42. Specifically, the electric field strength at the bottom surface 43 of the trapezoidal trench 42 is weakened to 3 × 10 ⁵ V / cm or less, and the electric field strength at the lower portion of the side surface 44 of the trapezoidal trench 42 is 1.5 × 10 ⁶ V / cm. It was the maximum at cm.

Further, in the Schottky barrier diode of FIG. 19 having the same configuration as that of FIG. 12, the p-type layer 46 is also formed on the side surface 44 of the trapezoidal trench 42, so that the electric field strength at the side surface 44 of the trapezoidal trench 42 is increased. It was weakened, and it was confirmed that the electric field concentration portion was kept away from the inner surface of the trapezoidal trench 42. Specifically, the electric field strength of the side surface 44 of the trapezoidal trench 42 is weakened to 3 × 10 ⁵ V / cm or less, and the electric field strength is 1.5 × 10 ⁶ V around the inner surface of the trapezoidal trench 42. There was no area to be / cm.

  As a result, it was confirmed that the reverse leakage current of the Schottky barrier diode 41 as a whole can be reliably reduced particularly in the Schottky barrier diode 41 of FIG. That is, in the Schottky barrier diode 41 having the structure of FIG. 12, the reverse leakage current can be reliably reduced even when a reverse voltage close to the breakdown voltage is applied, so that the breakdown voltage performance of the wide band gap semiconductor can be fully utilized. Can do.

In addition, when the trapezoidal trench 42 is formed by dry etching as in the process of FIG. 21F described later, the side surface 44 of the trapezoidal trench 42 is damaged during etching, and a Schottky barrier is formed between the side surface 44 and the anode electrode 21. May not be formed as designed. Therefore, in the Schottky barrier diode 41 of this embodiment, the surface 12 of the epitaxial layer 6 that is covered and protected by a hard mask 52 (described later) during etching (step of FIG. 21E described later) is mainly used as a Schottky interface, and damage is caused. A p-type layer 46 is formed on the received side surface 44. Thereby, the side surface 44 of the trapezoidal trench 42 can be used effectively. In addition, a pn junction with a high barrier can be formed in a portion of the side surface 44 of the trapezoidal trench 42 where the electric field strength is high, and the leakage current can be reduced.
<Effect of incorporating SiC-pn diode 47>
Next, with reference to FIG. 20, the effect when the contact layer 48 is formed in the p-type layer 46 and the pn diode 47 is built in the epitaxial layer 6 will be described.

FIG. 20 is a graph showing a current-voltage (IV) curve of the Schottky barrier diode 41.
An energization test was performed by applying the forward voltage while changing the forward voltage from 1V to 7V to the Schottky barrier diode 41 having the structure of FIG. Then, the amount of change in the current flowing through the pn junction of the Schottky barrier diode 41 when the applied voltage was changed from 1 V to 7 V was evaluated.

On the other hand, with the exception that the contact layer 48 of the p-type layer 46 is not formed, a current test similar to the above is performed on the same Schottky barrier diode 41 as in the structure of FIG. The amount of change was evaluated.
As shown in FIG. 20, in the pn junction where the contact layer 48 is not formed in the p-type layer 46, the current hardly increased from the time when the applied voltage exceeded 4V and was almost constant.

On the other hand, in the Schottky barrier diode 41 in which the contact layer 48 is formed in the p-type layer 46 and the pn diode 47 is built in, the rate of increase in current from when the applied voltage exceeds 4 V increases to 4 V or less. It increased rapidly compared to the proportion.
Thus, in FIG. 12, if the anode electrode 21 (Schottky electrode) is ohmically connected to the pn diode 47 provided in parallel with the Schottky barrier diode 41, a large surge current flows through the Schottky barrier diode 41. In addition, it was confirmed that the built-in pn diode 47 was turned on to allow a part of the surge current to flow through the built-in pn diode 47. As a result, since the surge current flowing through the Schottky barrier diode 41 can be reduced, it was confirmed that the thermal destruction of the Schottky barrier diode 41 due to the surge current can be prevented.
<Method for Manufacturing Schottky Barrier Diode 41 (Second Embodiment)>
Next, a method for manufacturing the Schottky barrier diode 41 of FIG. 12 will be described with reference to FIGS. 21A to 21J.

First, as shown in FIG. 21A, the buffer layer 7, the base drift layer 8, the low resistance drift layer 9, and the surface drift layer 10 are epitaxially grown on the substrate 2 in this order.
Next, as shown in FIG. 21B, a hard mask 49 made of SiO ₂ is formed on the surface 12 of the epitaxial layer 6 by, eg, CVD. The thickness of the hard mask 49 is preferably 1.5 μm to 10 μm. Next, after patterning the hard mask 49, the epitaxial layer 6 is dry-etched through the hard mask 49. As a result, a stripe-shaped trench 50 reaching the buffer layer 7 is formed. The depth of the trench 50 is set as appropriate in accordance with the depth D _SJ of the p-type pillar layer 17. The trench 50 is formed by repeating a process of forming a hard mask, a process of dry etching using the hard mask, and a process of removing the hard mask after the dry etching a plurality of times according to the depth _DSJ. May be.

Next, after removing the hard mask 49, as shown in FIG. 21C, the p-type SiC layer 51 is epitaxially grown from the inside of the trench 50 until the surface 12 of the epitaxial layer 6 is covered.
Next, as shown in FIG. 21D, the SiC layer 51 outside the trench 50 covering the surface 12 of the epitaxial layer 6 is removed by, for example, etch back. Thereby, the p-type pillar layer 17 embedded in the trench 50 is formed, and at the same time, the n-type pillar layer 18 is formed between the p-type pillar layers 17 adjacent to each other.

Next, as shown in FIG. 21E, a hard mask 52 made of SiO ₂ is formed on the surface 12 of the epitaxial layer 6 by, eg, CVD. The thickness of the hard mask 52 is preferably 1 μm to 3 μm. Next, the hard mask 52 is patterned. At this time, the etching conditions are set so that the etching amount (thickness) is 1 to 1.5 times the thickness of the hard mask 52. Specifically, when the thickness of the hard mask 52 is 1 μm to 3 μm, the etching conditions (gas type and etching temperature) are set so that the etching amount is 1 μm to 4.5 μm. Thereby, since the amount of overetching with respect to the epitaxial layer 6 can be made smaller than a general amount, the angle θ _{1 with} respect to the surface 12 of the epitaxial layer 6 is formed on the lower side surface of the opening 53 of the hard mask 52 after etching. The edge part 54 inclined at (100 ° to 170 °> 90 °) can be formed.

Next, as shown in FIG. 21F, the epitaxial layer 6 is dry-etched through the hard mask 52 to a depth at which the deepest part reaches the middle part of the low resistance drift layer 9 from the surface 12. A trapezoidal trench 42 and an annular trench 69 are simultaneously formed at the upper end of 46. Etching conditions at this time are gas type: O ₂ + SF ₆ + HBr, bias: 20 W to 100 W, and apparatus pressure: 1 Pa to 10 Pa. Thereby, the edge part 45 of the trapezoidal trench 42 can be formed in a curved shape. Further, since the edge portion 54 having the predetermined angle θ ₁ is formed at the lower side of the side surface of the opening 53 of the hard mask 52, the side surface 44 of the trapezoidal trench 42 is inclined with respect to the bottom surface 43 of the trapezoidal trench 42 at an angle θ ₁ . be able to.

  Next, as shown in FIG. 21G, a resist 73 is formed to cover a portion of the annular trench 69 other than the portion where the guard ring 72 is to be formed, with the hard mask 52 used for forming the trapezoidal trench 42 remaining. Then, a p-type impurity (for example, aluminum (Al)) is implanted into the trapezoidal trench 42 through the resist 73 and the hard mask 52. For example, p-type impurity doping is performed in a plurality of stages so that the implantation energy decreases stepwise and the dose increases stepwise in order from a deep position with respect to the surface 12 of the epitaxial layer 6. This is achieved by the multistage injection method of injection.

In this embodiment, for example, injection is performed over five stages. The implantation energy (keV) and dose (cm ⁻² ) at each stage are as follows: first stage: 380 keV 2.0 × 10 ¹³ cm ⁻² , second stage: 260 keV 1.5 × 10 ¹³ cm ⁻² , third stage Eye: 160 keV 1.0 × 10 ¹³ cm ⁻² , 4th stage: 60 keV 2.0 × 10 ¹⁵ cm ⁻² , 5th stage: 30 keV 1.0 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 21H, a hard mask 55 having a predetermined pattern is formed, and a p-type impurity (for example, aluminum (Al)) is implanted into the trapezoidal trench 42 through the hard mask 55. As in the step of FIG. 21G, the p-type impurity is doped in such a manner that the implantation energy decreases stepwise and the dose increases stepwise in order from the deeper position with respect to the surface 12 of the epitaxial layer 6. This is achieved by a multi-stage implantation method in which impurity ions are implanted in a plurality of stages. In the present embodiment, a five-step injection under the same conditions as described above is employed. By adopting a multi-stage implantation method in which p-type impurity ions are implanted in a plurality of stages so that the implantation energy decreases stepwise and the dose increases stepwise, ohmic contact with the p-type layer 46 and the contact layer 48 is achieved. A contact can be easily formed.

After the impurity doping, as shown in FIG. 21I, the p-type layer 46, the contact layer 48, and the guard ring 72 are simultaneously formed by annealing at 1700 ° C., for example.
Thereafter, as shown in FIG. 21J, the field insulating film 16, the anode electrode 21, the surface protective film 29, the cathode electrode 4 and the like are formed.

Through the above steps, the Schottky barrier diode 41 of FIG. 12 is obtained.
According to such a forming method, since ion implantation is performed using the hard mask 52 used when forming the trapezoidal trench 42, it is not necessary to increase the number of mask forming steps when forming the p-type layer 46.
In addition, by appropriately adjusting the thickness of the hard mask 52, the trapezoidal trench 42 as designed can be precisely formed, and at the time of ion implantation, a portion other than the trapezoidal trench 42 (for example, the top of the unit cell 20). ) Can be prevented from being implanted with impurities. Therefore, an n-type region for the Schottky junction with the anode electrode 21 can be secured.

In addition, in the trapezoidal trench 42, not only the bottom surface 43 but also all of the side surfaces 44 face the open end of the trapezoidal trench 42. Therefore, when the p-type impurity is implanted into the epitaxial layer 6 through the trapezoidal trench 42, the impurity incident into the trapezoidal trench 42 from the open end of the trapezoidal trench 42 can be reliably applied to the side surface 44 of the trapezoidal trench 42. it can. As a result, the p-type layer 46 can be easily formed.
<Modification of cross-sectional shape of trench>
Next, a modification of the cross-sectional shape of the trapezoidal trench 42 will be described with reference to FIGS.

22 (a) to 22 (f) are diagrams showing modifications of the cross-sectional shape of the trench, in which FIG. 22 (a) is a first modification, FIG. 22 (b) is a second modification, and FIG. 22 (c) shows a third modification, FIG. 22 (d) shows a fourth modification, FIG. 22 (e) shows a fifth modification, and FIG. 22 (f) shows a sixth modification.
In the trapezoidal trench 42, for example, as shown in FIG. 22A, the contact layer 48 extends from the bottom surface 43 through the edge portion 45 to the opening end of the trapezoidal trench 42 as in the p-type layer 46. It may be formed over the entire inner surface of 42.

In the description of FIGS. 12 and 13, as the cross-sectional shape of the trapezoidal trench 42, only the case where the side surface 44 of each trapezoidal trench 42 is inclined with respect to the bottom surface 43 at an angle θ ₁ (> 90 °) is taken as an example. However, the cross-sectional shape of the trench is not limited to this.
For example, the trapezoidal trench 42 does not need to have the entire side surface 44 inclined, and a part of the side surface 57 (the lower portion 58 of the side surface), for example, like the selective trapezoidal trench 56 of FIGS. ) Is selectively trapezoidal (tapered), and the other part of the side surface 57 (upper portion 59 of the side surface) may form an angle of 90 ° with respect to the bottom surface 60. In this case, the p-type layer 46 is formed only from the bottom surface 60 of the selective trapezoidal trench 56 through the edge portion 61 to the lower portion 58 (trapezoidal portion) on the side surface. The contact layer 48 may be formed only on the bottom surface 60 of the selective trapezoidal trench 56 as shown in FIG. 22B, or the p-type layer 46 and the contact layer 48 as shown in FIG. Similarly, it may be formed from the bottom surface 60 of the selective trapezoidal trench 56 to the upper end of the lower portion 58 of the side surface through the edge portion 61.

22B and 22C, the lower portion 58 of the side surface faces the open end of the selective trapezoidal trench 56, so that the p-type layer 46 can be easily formed. .
Further, the side surface of the trench does not need to be inclined. For example, the side surface 64 is 90 ° (perpendicular) with respect to the bottom surface 63 as in the U-shaped trench 62 in FIGS. It may be. In this case, the p-type layer 46 may be formed from the bottom surface 63 of the U-shaped trench 62 through the edge portion 65 to the open end of the U-shaped trench 62 as shown in FIGS. Alternatively, as shown in FIG. 22 (f), it may be formed only on the bottom surface 63 and the edge portion 65 of the U-shaped trench 62. Further, the contact layer 48 may be formed only on the bottom surface 63 of the U-shaped trench 62 as shown in FIGS. 22 (d) and 22 (f), or as shown in FIG. 22 (e). Similarly to 46, it may be formed from the bottom surface 63 of the U-shaped trench 62 through the edge portion 65 to the opening end of the U-shaped trench 62.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the Schottky barrier diode 1 of FIG. 2A, the deepest portion of the p-type pillar layer 17 may be located in the middle of the buffer layer 7 in the thickness direction, as shown in FIG. As shown, it may be positioned so as to be spaced from the buffer layer 7.
In addition, as shown in FIG. 25, the epitaxial layer 6 may further include an n-type intermediate layer 66 in a direction crossing the p-type pillar layer 17 along the surface 12 thereof. Accordingly, the p-type pillar layer 17 may be divided into an upper portion 67 on the surface 12 side of the epitaxial layer 6 and a lower portion 68 on the back surface 11 side of the epitaxial layer 6 with respect to the intermediate layer 66. 23 to 25 can be applied to the Schottky barrier diode 41 in FIG.

Moreover, the structure which reversed the conductivity type of each semiconductor part of the above-mentioned Schottky barrier diodes 1 and 41 may be employ | adopted. For example, in Schottky barrier diodes 1 and 41, the p-type portion may be n-type and the n-type portion may be p-type.
The epitaxial layer 6 is not limited to an epitaxial layer made of SiC, and is a wide band gap semiconductor other than SiC, for example, a semiconductor having a breakdown electric field larger than 2 MV / cm. May be about 3 MV / cm and the band gap width is about 3.42 eV), diamond (the breakdown electric field is about 8 MV / cm and the band gap width is about 5.47 eV), and the like.

  Further, the planar shape of the p-type pillar layer 17 does not need to be a stripe shape, and may be a matrix shape or a staggered shape, for example. However, in the case of the striped p-type pillar layer 17, the surface orientation of the side surface of the trench 32 when the p-type pillar layer 17 is formed is smaller than that in the case of a matrix shape and a staggered shape (four surfaces → two surfaces). This is preferable because the concentration of the p-type impurity to be implanted can be easily controlled.

Further, as the anode electrode 21, for example, molybdenum (Mo), titanium (Ti), or the like other than the above-described aluminum and polysilicon is used, so that a Schottky junction (heterojunction) with respect to the epitaxial layer 6 is used. Can be made.
Moreover, as a p-type impurity for forming the electric field relaxation layer 19, for example, Al (aluminum) can be used.

  The semiconductor device (semiconductor power device) of the present invention is an inverter circuit that constitutes a drive circuit for driving an electric motor used as a power source for, for example, an electric vehicle (including a hybrid vehicle), a train, an industrial robot, etc. It can be incorporated in the power module used in It can also be incorporated into a power module used in an inverter circuit that converts electric power generated by a solar cell, wind power generator, or other power generation device (especially an in-house power generation device) to match the power of a commercial power source.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 Schottky barrier diode 2 Substrate 3 Back surface of substrate 4 Cathode electrode 5 Front surface of substrate 6 Epitaxial layer 7 Buffer layer 8 Base drift layer 9 Low resistance drift layer 10 Surface drift layer 11 Back surface of epitaxial layer 12 (Epitaxial layer) (Surface of epitaxial layer) 13 active region 14 contact hole 15 field region 16 field insulating film 17 p-type pillar layer 18 n-type pillar layer 19 electric field relaxation layer 20 unit cell 21 anode electrode 22 Schottky metal 23 contact metal 24 first metal 25 Second metal 26 Peripheral portion (unit cell) 27 Central portion (unit cell) 28 Guard ring 29 Surface protective film 30 Opening 31 Hard mask 32 Trench 33 SiC layer 34 Hard mask 35 High-concentration impurity layer 41 Schottky key Adiode 42 Trapezoidal trench 43 Bottom surface of the trench 44 Side surface of the trench 45 Edge portion of the trench 46 P-type layer 47 pn diode 48 Contact layer 49 Hard mask 50 Trench 51 SiC layer 52 Hard mask 53 ) Opening 54 Edge of hard mask 55 Hard mask 56 Selective trapezoidal trench 57 Side surface of selective trapezoidal trench 58 Lower side of side of selective trapezoidal trench 59 Upper side of side of selective trapezoidal trench 60 Bottom 61 (of selective trapezoidal trench) Edge portion (of selective trapezoidal trench) 62 U-shaped trench 63 Bottom surface of (U-shaped trench) 64 Side surface (of U-shaped trench) 65 Edge portion of (U-shaped trench) 66 Intermediate layer 67 Upper part (of p-type pillar layer) 68 Bottom (of p-type pillar layer) Side portion 69 Annular trench 70 Bottom surface of annular trench 71 Side surface of annular trench 72 Guard ring 73 Resist

Claims (22)

A semiconductor layer made of a wide band gap semiconductor of the first conductivity type having a front surface and a back surface;
Before SL and a formed Schottky electrode in contact with said surface of the semiconductor layer,
In the semiconductor layer,
Each of which is arranged in the direction along the surface with a space between each other, and each columnar shape extends in the thickness direction of the semiconductor layer from the front surface toward the back surface, and another portion of the first conductivity type of the semiconductor layer A plurality of pillar layers of a second conductivity type that cooperate to form a super junction structure in the semiconductor layer;
An electric field relaxation portion formed at an upper end portion of the plurality of pillar layers, containing an impurity of a second conductivity type for relaxing electric field strength on the surface , and dividing a part of the semiconductor layer as a unit cell; Formed ,
The unit cell has a peripheral part to which a first electric field is applied when a reverse voltage is applied, and a central part to which a second electric field that is relatively higher than the first electric field is applied when the reverse voltage is applied.
The Schottky electrode is
A first electrode including a metal material and forming a first Schottky barrier between the peripheral edge of the unit cell;
A second electrode including a metal material different from that of the first electrode and forming a second Schottky barrier relatively higher than the first Schottky barrier between the unit cell and the central portion; Including a semiconductor device.   The electric field relaxation part includes an electric field relaxation layer that is formed on the surface of the semiconductor layer using a part of the semiconductor layer and exhibits a second conductivity type having an impurity concentration higher than that of the pillar layer. 2. The semiconductor device according to 1.   The semiconductor device according to claim 2, wherein the electric field relaxation layer includes a high resistance layer having a higher resistance than other portions of the first conductivity type of the semiconductor layer forming the super junction structure.   The semiconductor device according to claim 3, wherein an activation rate of impurities in the high-resistance layer is less than 5%.   The semiconductor device according to claim 3 or 4, wherein the sheet resistance of the high resistance layer is 1 MΩ / □ or more.   The semiconductor device according to claim 1, wherein a trench dug from the surface of the semiconductor layer is formed at a position where the electric field relaxation portion is formed. The semiconductor device according to claim 6, wherein an edge portion of the trench formed by intersecting a side surface and a bottom surface of the trench has a curvature radius R that satisfies the following formula (1).
0.01L <R <10L (1)
(However, in Formula (1), L has shown the linear distance between the edge parts which oppose along the width direction of a trench.)   The semiconductor device according to claim 7, wherein the electric field relaxation portion includes a second conductivity type bottom relaxation layer formed on the bottom surface and the edge portion of the trench by using a part of the semiconductor layer.   The said electric field relaxation part is integral with the said bottom part relaxation layer, and contains the 2nd conductivity type side part relaxation layer formed in the said side surface of the said trench using a part of said semiconductor layer. A semiconductor device according to 1.   The semiconductor device according to claim 9, wherein the side relaxation layer is formed so as to reach the opening end of the trench along the side surface of the trench.   The semiconductor device according to claim 6, wherein the trench includes a tapered trench having a planar bottom surface and a side surface inclined at an angle exceeding 90 ° with respect to the planar bottom surface. The Schottky electrode is formed to be embedded in the trench,
2. The second conductivity type contact layer that forms an ohmic junction with the Schottky electrode embedded in the trench is further formed in a portion of the semiconductor layer forming the bottom surface of the trench. The semiconductor device according to any one of 6 to 11. The semiconductor layer includes a base drift layer having a first impurity concentration and a low resistance drift layer formed on the base drift layer and having a second impurity concentration relatively higher than the first impurity concentration. ,
The electric field absorbing portion has its deepest portion is formed so as to reach the low resistance drift layer, the semiconductor device according to any one of claims 1 to 12. The semiconductor device according to claim 13 , wherein the first impurity concentration of the base drift layer decreases from the back surface of the semiconductor layer toward the front surface. Wherein said second impurity concentration of the low-resistance drift layer, said constant according to from the back surface of the semiconductor layer toward the surface, the semiconductor device according to claim 13 or 14. Wherein said second impurity concentration of the low-resistance drift layer is reduced in accordance with the said back surface of said semiconductor layer toward said surface, the semiconductor device according to claim 13 or 14. The semiconductor layer, wherein are formed in the low resistance drift layer, further comprising a surface drift layer having a relatively low third impurity concentration to the second impurity concentration, any one of claims 13 to 16 A semiconductor device according to 1. A substrate made of a wide band gap semiconductor of the first conductivity type that supports the semiconductor layer;
The semiconductor layer is formed on the substrate, further comprising a buffer layer having a relatively high fourth impurity concentration with respect to the first impurity concentration, a semiconductor according to any one of claims 13-17 apparatus. The semiconductor device according to claim 18 , wherein a lower end portion of the pillar layer is in contact with the buffer layer. The semiconductor device according to claim 18 , wherein a lower end portion of the pillar layer is positioned so as to be spaced from the buffer layer. The dielectric breakdown field of the wide band gap semiconductor is greater than 1 MV / cm, the semiconductor device according to any one of claims 1 to 20. FIG. The semiconductor device according to any one of claims 1 to 21 , wherein the wide band gap semiconductor is SiC, GaN, or diamond.

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