JP6090447B2 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  Dynamic voltage and frequency scaling (DVFS: Dynamic Voltage and Frequency Scaling) that dynamically controls the operating frequency (frequency of the operating clock) and power supply voltage according to the processing load, etc. ) For example, in DVFS, if the operating frequency is high, the power supply voltage is set high, and if the operating frequency is low, the power supply voltage is set low.

In order to determine a plurality of operating frequencies and power supply voltage values used in DVFS control, there are the following methods <1> to <3>.
<1> Estimate by simulation.
<2> Some operating frequencies and power supply voltage values used in DVFS control are measured by actually performing tests, and the remainder is interpolated by calculating from the measurement results.
<3> All operating frequencies and power supply voltage values used in DVFS control are measured by actually performing tests.

  In addition, for example, a technique has been proposed in which a change in operating speed due to process variation in a semiconductor integrated circuit is measured using a process monitor circuit, and a power supply voltage is corrected according to the process variation based on the measurement result (for example, , See Patent Document 1). Further, a technique has been proposed in which, when determining the operating frequency and power supply voltage of an arithmetic processing unit, a test is dynamically executed, information obtained by the test is manipulated, and stored in a nonvolatile memory (for example, a patent) Reference 2).

  However, in a technique for measuring a change in operation speed due to process variation by a process monitor circuit and correcting a power supply voltage as described in Patent Document 1, for example, means for correcting the process monitor circuit and the actual circuit operation is provided. Absent. Therefore, when the circuit characteristics of the process monitor circuit do not match the characteristics of the circuit that actually operates due to process variations, an optimum power supply voltage value cannot be obtained. Further, for example, a technique for obtaining information by executing a test dynamically as described in Patent Document 2 requires a lot of time to obtain the optimum values of the operating frequency and the power supply voltage.

  Here, a case where the operating frequency and the power supply voltage value used in the DVFS control in the arithmetic processing device are determined in advance by simulation will be described with reference to FIGS. 13A and 13B. 13A and 13B are diagrams illustrating setting examples of the power supply voltage value with respect to the operating frequency based on the simulation result. In each of FIG. 13A and FIG. 13B, a horizontal axis is an operating frequency and a vertical axis | shaft is a voltage value.

  In FIG. 13A, V101 shows the power supply voltage value with respect to the operating frequency obtained by simulation. Further, V102 indicates a power supply voltage value when the process variation is fast at the time of manufacturing, and V103 indicates a power supply voltage value when the process variation is at the slow side during manufacturing. In order to avoid the malfunction of the arithmetic processing unit even if the process variation varies at the time of manufacturing, the power supply voltage value with respect to the operating frequency is V103. Furthermore, in addition to process variations, considering the margin for fluctuations in the power supply voltage supplied to the processing unit, which is caused by voltage drop due to the power supply circuit and circuit operation, noise due to power supply voltage transition in DVFS, etc. The power supply voltage value for V is V104.

That is, the initial setting values of the operating frequency and the power supply voltage value used in the DVFS control in the arithmetic processing device are (F ₀ , V ₀ ) to (F ₅ , V ₅ ) shown in FIG. This may include an unnecessarily large margin for the actual performance of the arithmetic processing unit. For example, it is set with respect to the power supply voltage value V102 with respect to the operating frequency when the process variation varies at the time of manufacturing. The supplied power supply voltage value is the most excessive. As described above, when the operating frequency and power supply voltage value used in the DVFS control are determined by simulation, an appropriate power supply voltage value corresponding to the process variation of each arithmetic processing device cannot be obtained, and wasteful power is consumed. .

  14A and 14B, refer to FIGS. 14A and 14B for a case where a part of the operating frequency and power supply voltage value used in the DVFS control in the arithmetic processing unit is actually tested and measured, and the rest is obtained by calculation based on the measurement result. To explain. 14A and 14B are diagrams illustrating setting examples of the power supply voltage value with respect to the operating frequency based on actual measurement. In each of FIG. 14A and FIG. 14B, a horizontal axis is an operating frequency and a vertical axis | shaft is a voltage value.

  14A and 14B, the marks indicated by triangles indicate the actual performance (power supply voltage value that operates normally with respect to the operating frequency) of the arithmetic processing unit. 14A and 14B, the filled triangles indicate the power supply voltage values with respect to the operating frequencies actually measured by the test, and the broken triangles indicate the power supply voltage values with respect to the unmeasured operating frequencies. 14A and 14B, power supply voltage values V102 and V104 with respect to the operating frequency correspond to power supply voltage values V102 and V104 with respect to the operating frequency shown in FIGS. 13A and 13B.

  As shown in FIG. 14A, for example, when a power supply voltage value for an unmeasured operating frequency is interpolated with a straight line using a power supply voltage value for the measured operating frequency, the power supply voltage value for the operating frequency becomes V201. Here, since the critical path in the arithmetic processing device is determined from all the paths of the arithmetic processing device, the characteristics of the operating frequency and power supply voltage of the critical path are generally not linear. Therefore, when the power supply voltage value for the unmeasured operating frequency is interpolated with a straight line using the power supply voltage value for the measured operating frequency, the power supply voltage value to be set shows the actual performance, for example, 1401 shown in FIG. 14A. It may be lower than the power supply voltage value required for obtaining. In order to avoid the malfunction of the arithmetic processing unit due to this, as shown as V202, a margin is set for the power supply voltage with respect to the measured operating frequency, and the power supply voltage value for the unmeasured operating frequency can be obtained by using a margin. Conceivable. However, the arithmetic processing unit consumes wasted power due to this margin.

  As shown in FIG. 14B, for example, if the power supply voltage value measured at the higher operating frequency is used as the power supply voltage value for the unmeasured operating frequency, the operation of the arithmetic processing unit is guaranteed. However, for example, 1402 and 1403 shown in FIG. 14B, the power supply voltage value to be set is excessive with respect to the power supply voltage value required for obtaining the actual performance, and wasteful power is consumed. .

  In addition, it is possible to obtain an appropriate power supply voltage value with respect to the operating frequency for each arithmetic processing unit by actually testing each arithmetic processing unit and measuring all the operating frequencies and power source voltage values used in the DVFS control. Is possible. However, if all the operating frequencies and power supply voltage values used in DVFS control are actually tested and measured, a great amount of test time (cost) is required.

JP 2005-322860 A Special table 2009-526336

  An object of the present invention is to provide an arithmetic processing device and a control method for the arithmetic processing device capable of performing DVFS control in consideration of process variation while suppressing an increase in test time.

One aspect of the arithmetic processing apparatus includes a table that sets a plurality of operating frequencies and power supply voltage values used in DVFS control, a critical path monitor circuit that detects a delay change according to a change in the power supply voltage, and a control circuit. The control circuit performs calibration processing of the critical path monitor circuit for the measured operating frequency and power supply voltage value obtained in the table, with reference to the calibration value according to the power supply voltage value obtained by the calibration process Then , adjustment of the power supply voltage value for the operating frequency not measured in the table is performed using the critical path monitor circuit, and the adjusted power supply voltage value is set in the table.

By measuring some of the multiple operating frequencies and power supply voltage values used in DVFS control, the increase in test time can be suppressed. Refer to the calibration values at the measured operating frequencies and power supply voltage values. By using the critical path monitor circuit to adjust the power supply voltage value for the operating frequency that is not measured, it is possible to set the power supply voltage value in consideration of process variations.

FIG. 1 is a diagram illustrating a configuration example of an arithmetic processing device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration example related to DVFS table setting in the present embodiment. FIG. 3 is a diagram illustrating a configuration example of a DVFS table in the present embodiment. FIG. 4 is a diagram illustrating a configuration example of the CPM circuit in the present embodiment. FIG. 5 is a diagram illustrating a configuration example of the control circuit in the present embodiment. FIG. 6 is a flowchart showing an operation example of setting the DVFS table in the present embodiment. FIG. 7 is a flowchart showing an operation example in step S101 shown in FIG. FIG. 8 is a flowchart showing an operation example in steps S102 and S103 shown in FIG. FIG. 9 is a diagram for explaining timing margin confirmation in the present embodiment. FIG. 10A is a diagram illustrating a data setting example of a DVFS table in the present embodiment. FIG. 10B is a diagram illustrating a data setting example of the DVFS table in the present embodiment. FIG. 10C is a diagram illustrating a data setting example of the DVFS table in the present embodiment. FIG. 10D is a diagram illustrating a data setting example of the DVFS table in the present embodiment. FIG. 10E is a diagram illustrating a data setting example of the DVFS table in the present embodiment. FIG. 11 is a diagram illustrating another configuration example of the arithmetic processing device according to the present embodiment. FIG. 12 is a diagram illustrating another configuration example of the arithmetic processing device according to the present embodiment. FIG. 13A is a diagram illustrating an example of setting a voltage value with respect to an operating frequency based on a simulation result. FIG. 13B is a diagram illustrating an example of voltage value setting with respect to an operating frequency based on a simulation result. FIG. 14A is a diagram illustrating an example of voltage value setting with respect to an operating frequency based on actual measurement. FIG. 14B is a diagram illustrating an example of voltage value setting with respect to the operating frequency based on actual measurement. FIG. 15 is a diagram illustrating an example of voltage value setting with respect to the operating frequency in DVFS according to the present embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a CPU (Central Processing Unit) as an arithmetic processing unit according to an embodiment of the present invention.
It is a figure which shows the structural example of Processing Unit. The CPU 10 includes a CPU core 11, a DVFS table 12, a control circuit 14, a frequency control unit 15, a scan control unit 17, and a memory 18.

  The CPU core 11 is supplied with the power supply voltage vdd-c from the voltage control unit 19, operates using the clock signal clk-c supplied from the frequency control unit 15 as an operation clock, and reads a program stored in the memory 18 or the like. And execute. The CPU core 11 includes a critical path monitor (CPM) circuit 13 that detects a delay change (delay change) in accordance with a change in the power supply voltage vdd-c.

  The DVFS table 12 is a table for setting an operating frequency and a power supply voltage value used in dynamic voltage and frequency control (DVFS) for the CPU core 11. The DVFS table 12 stores information on a set of a plurality of operating frequencies and power supply voltage values used in DVFS control. Each set of information includes an operating frequency used in DVFS control, a power supply voltage value for the operating frequency, information indicating the state of the power supply voltage value, a calibration group of the CPM circuit 13, and a calibration value.

  The control circuit 14 performs various controls related to DVFS control for the CPU core 11. The control circuit 14 performs, for example, control of the DVFS table 12, control of the CPM circuit 13, and setting control of the clock signal clk-c and the power supply voltage vdd-c supplied to the CPU core 11.

  The frequency control unit 15 receives the clock signal CPU CLK and the frequency setting signal fset from the control circuit 14. The frequency control unit 15 controls the multiplication rate (or division ratio) according to the frequency setting signal fset, and generates the clock signal clk-c having the frequency according to the frequency setting signal fset based on the clock signal CPU CLK. And output. The frequency control unit 15 is, for example, a PLL (Phase Locked Loop) circuit.

  The scan control unit 17 controls a scan operation in the CPU 10. For example, data (scan dat / ctr) read from the memory 18 can be written into the DVFS table 12 by a scan shift operation under the control of the scan control unit 17. The memory 18 is, for example, a nonvolatile memory, and stores a program executed by the CPU 11 and initial setting values of the DVFS table 12.

  The voltage control unit 19 generates and outputs a power supply voltage vdd-c having a voltage value corresponding to the voltage setting signal vset from the control circuit 14 based on the supplied power. The voltage control unit 19 is, for example, a VRM (Voltage Regulator Module) or a DC-DC converter that performs voltage control. In FIG. 1, the voltage control unit 19 is provided outside the CPU 10, but may be provided inside the CPU 10.

  In FIG. 1, a signal tb_wt is a write control signal related to the DVFS table 12, and a signal tb_sel is a control signal for selecting a set of data (information) in the DVFS table 12. The signal tb_rd is a read control signal related to the DVFS table 12, and the signal tb_scan is a scan signal for the DVFS table 12.

  The signal req is a request signal for performing the setting operation of the DVFS table 12, the frequency setting and the voltage setting according to the data value in the DVFS table 12, and the reference of the DVFS table 12. The signal info is a response signal to the setting request to the DVFS table 12 (setting status, data in the DVFS table 12, etc.). The signal ctr is a control signal for the control circuit 14. The signal cpm_ctr is a control signal for starting and calibrating the CPM circuit 13, and the signal cpm_dly is a timing margin information signal obtained by the operation of the CPM circuit 13. The signal scan is a signal related to data setting by the scan shift operation.

  FIG. 2 is a diagram showing a configuration example relating to the DVFS table setting in the CPU 10 shown in FIG. In FIG. 2, components having the same functions as those shown in FIG. In this embodiment, in the DVFS table 12, a set of the operating frequency and the power supply voltage value measured by actually performing a test is set as an initial value at the time of startup, and the rest is obtained by simulation. A set of the operating frequency and the power supply voltage value is set. When the CPU 10 is activated, the control circuit 14 sets the operating frequency and the power supply voltage value obtained by the measurement and performs the calibration process for the CPM circuit 13. The control circuit 14 diverts the calibration value obtained by the calibration process as a calibration value of a set of the operating frequency and the power supply voltage value obtained by simulation (not measured) and uses the CPM circuit 13. Obtain an appropriate power supply voltage value for the operating frequency that is not being measured.

  The DVFS table 12 is a table for setting an operating frequency and a power supply voltage value used in DVFS control, and includes a plurality of register arrays including a selection decoder 21 and registers 22 to 26 as shown in FIG. FIG. 3 is a diagram showing a configuration example of the DVFS table 12 in the present embodiment. 3, components having the same functions as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  The register 22 is a register that stores an operating frequency used in DVFS control, and the register 23 is a register that stores a power supply voltage value corresponding to the operating frequency stored in the register 22. The register 24 is a flag register indicating the state of the power supply voltage value stored in the register 23. Examples of the state of the power supply voltage value include a simulation value, an actual measurement value, and a correction value. The register 25 is a register indicating a calibration group of the CPM circuit 13, and the register 26 is a register for storing a calibration value of the CPM circuit 13.

  Each register 22 to 26 is combined into one set of register group. Each register group includes an operating frequency, a power supply voltage value, a state of the power supply voltage value used in the DVFS control, a calibration group of the CPM circuit 13 and a calibration. Stores the value. The register group (a set of registers 22 to 26) can be arbitrarily selected by selection according to the control signal tb_sel by the selection decoder 21.

  Further, the registers 22 to 26 in the DVFS table 12 include a signal tb_wt related to write data / control, a signal tb_sel related to selection / control of a register set, and a signal tb_rd related to read data / control from the control circuit 14. Thus, data can be written and read. Further, the registers 22 to 26 in the DVFS table 12 can write and read data by a scan shift operation according to the scan signal / control signal tb_scan from the control circuit 14.

  The CPM circuit 13 is a circuit that detects a delay change (delay change) in accordance with a change in the power supply voltage vdd-c. As shown in FIG. 4, the pulse generator 31, the offset unit 32, the critical path unit 33, the logic It has a product (AND) operation unit 35, a conversion unit 36, and a margin information signal output unit 39. FIG. 4 is a diagram illustrating a configuration example of the CPM circuit 13 in the present embodiment. 4, components having the same functions as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  The pulse generator 31 generates and outputs a pulse signal for timing margin observation in the CPM circuit 13 based on the enable signal enable included in the signal cpm_ctr from the control circuit 14. The offset unit 32 adds a time offset (delay) to the pulse signal generated by the pulse generation unit 31 based on the calibration signal calib included in the signal cpm_ctr from the control circuit 14. The devices included in the plurality of replica paths 34-1, 34-2,..., 34-n of the critical path unit 33 are affected by process variations including the devices in the CPU 10, but an offset is added by the offset unit 32. Thus, the timing margin index can be adjusted.

  The critical path unit 33 has a plurality of replica paths 34-1, 34-2,..., 34-n (n is an integer of 2 or more), and an input pulse signal is input to each replica path 34-1, 34. -2, ..., 34-n to propagate and output. The replica paths 34-1, 34-2,..., 34-n have different circuit configurations, but the delays in each path are matched.

  The AND operation unit 35 performs an AND operation on outputs from the plurality of replica paths 34-1, 34-2,..., 34-n of the critical path unit 33, and outputs an operation result. That is, when the AND operation unit 35 detects that the propagated pulse signal is output from all of the replica paths 34-1, 34-2,..., 34-n, the AND operation unit 35 asserts the output. That is, the AND operation unit 35 detects a delay in the worst path among the plurality of replica paths 34-1, 34-2, ..., 34-n.

  The conversion unit 36 includes a plurality of delay circuits 37-1, 37-2, ..., and a plurality of flip-flops 38-1, 38-2, ... 38-m (m is an integer of 2 or more). The delay circuits 37-1, 37-2,... Are connected in cascade (cascade connection). The output of the AND operation unit 35 is input to the delay circuit 37-1 and the flip-flop 38-1 in the first stage. The output of the delay circuit 37- (i-1) (i = 2 to m) is input to the delay circuit 37-i and the flip-flop 38-i. Each of the flip-flops 38-1, 38-2,..., 38-m takes the input in synchronization and outputs it. Therefore, the timing margin can be observed by detecting the edges where the output values of the flip-flops 38-1, 38-2,. The margin information signal output unit 39 generates and outputs a margin information signal cpm_dly based on the plurality of flip-flops 38-1, 38-2,.

  The control circuit 14 is a circuit that performs various controls related to the DVFS control, and includes a DVFS table setting operation control unit 41, a DVFS table control unit 42, and a CPM control unit 43, as shown in FIG. FIG. 5 is a diagram illustrating a configuration example of the control circuit 14 in the present embodiment. In FIG. 5, components having the same functions as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  The DVFS table setting operation control unit 41 controls an operation related to the setting of the DVFS table 12. The DVFS table setting operation control unit 41 includes a sequence control unit 44, a frequency setting register 45, a voltage value setting register 46, a margin confirmation unit 47, a voltage value increase / decrease control unit 48, and a table update data generation unit 49. The sequence control unit 44 controls the calibration operation of the CPM circuit 13 in the setting of the DVFS table 12 and the setting operation of the power supply voltage value using the CPM circuit 13.

  The frequency setting register 45 is a register that indicates a setting value of the operating frequency of the apparatus under DVFS control. The frequency setting register 45 is set with the operating frequency setting value read from the DVFS table 12 via the DVFS table control unit 42 and outputs a frequency setting signal fset corresponding to the setting value.

  The voltage value setting register 46 is a register that indicates a set value of the power supply voltage of the apparatus under DVFS control. The voltage value setting register 46 sets a power supply voltage setting value read from the DVFS table 12 via the DVFS table control unit 42 or a power supply voltage setting value determined by the timing margin information signal cpm_dly from the CPM circuit 13. Then, a voltage setting signal vset corresponding to the set value is output.

  The margin confirmation unit 47 determines a margin at the time of DVFS control based on the timing margin information signal cpm_dly from the CPM circuit 13. The margin confirmation unit 47 determines whether to calibrate the CPM circuit 13 based on the timing margin information signal cpm_dly during the calibration operation of the CPM circuit 13. Further, the margin confirmation unit 47 determines the margin of the voltage value from the timing margin information signal cpm_dly and the allowable value when adjusting the power supply voltage value using the CPM circuit 13.

  The voltage value increase / decrease control unit 48 performs increase / decrease control on the set value of the power supply voltage based on the determination result of the margin confirmation unit 47 when adjusting the power supply voltage value using the CPM circuit 13. The table update data generation unit 49 generates update data to be written to the DVFS table 12 in the calibration operation of the CPM circuit 13 or the power supply voltage value setting operation using the CPM circuit 13. The table update data generation unit 49 generates, for example, a power supply voltage value, a state of the power supply voltage value, and a calibration value.

  The DVFS table control unit 42 controls writing and reading of data with respect to the DVFS table 12. The DVFS table control unit 42 includes a write / read control unit 50 and registers 51 and 52. Based on the signal from the DVFS table setting operation control unit 41, the write / read control unit 50 generates and outputs a signal tb_sel for selecting a data set of the DVFS table 12 for writing and reading data. . The register 51 is a register that holds write data to the DVFS table 12, and the register 52 is a register that holds read data from the DVFS table 12.

  The CPM control unit 43 controls the operation of the CPM circuit 13. The CPM control unit 43 includes a circuit operation control unit 54 and a calibration control unit 55. The circuit operation control unit 54 controls the activation of the CPM circuit 13 according to the activation signal cpm_enb from the DVFS table setting operation control unit 41. The calibration control unit 55 generates and outputs a calibration value of the CPM circuit 13 in accordance with the output of the margin confirmation unit 47 of the DVFS table setting operation control unit 41.

  Next, an operation related to the setting of the DVFS table in the present embodiment will be described. FIG. 6 is a flowchart showing an operation example of setting the DVFS table in the present embodiment. In addition, each process shown in FIG. 6 performs the process of step S101 at the time of a test, and performs the process of step S102 and S103 at the time of starting of an apparatus after that.

  First, a test that is actually operated by the test apparatus is performed by the CPU 10 as an arithmetic processing apparatus, and a power supply voltage value that operates normally is obtained by measurement with respect to the operating frequency in the DVFS control (S101). The actual measurement of the power supply voltage value by the test in step S101 is performed not for all the operating frequencies that can be controlled in the DVFS control but for some operating frequencies. In this way, it is possible to suppress an increase in test time by performing tests for some operating frequencies instead of performing tests for all operating frequencies. Here, the power supply voltage value with respect to the operating frequency measured by performing the test is stored in an arbitrary storage device or the like in association with the CPU 10 to be measured.

  Next, when the CPU 10 is activated, the control circuit 14 sets the operating frequency and power supply voltage value (actual measurement value) measured in step S101, and performs calibration processing of the CPM circuit 13 (S102). By the calibration process of the CPM circuit 13 in step S102, the calibration value of the CPM circuit 13 for the set of the measured operating frequency and power supply voltage value is obtained. The control circuit 14 writes the obtained calibration value of the CPM circuit 13 in the DVFS table 12. In addition, since the calibration value of the CPM circuit 13 is also used for a set of operating frequencies and power supply voltage values that are not measured in the same calibration group, the control circuit 14 can be used for the same group in the DVFS table 12. A calibration value is also written to a set of operating frequency and power supply voltage value that has not been measured.

  Next, the control circuit 14 sets an operating frequency and a power supply voltage value (simulation value) that are not measured, and uses the CPM circuit 13 to obtain a power supply voltage value that operates normally with respect to the operating frequency ( S103). The control circuit 14 optimizes the power supply voltage value with respect to the operating frequency based on the timing margin information from the CPM circuit 13 calibrated with the calibration value obtained in step S102. In this way, by obtaining the power supply voltage value with respect to the operating frequency using the CPM circuit 13 calibrated with the actually measured values, it is possible to obtain the power supply voltage value in consideration of process variations in the target CPU 10. Then, the control circuit 14 writes the obtained power supply voltage value and the like in the DVFS table 12. As described above, the power supply voltage value with respect to the operating frequency in the DVFS control is set.

Hereinafter, the operation in steps S101 to S103 described above will be described in detail.
FIG. 7 is a flowchart showing an operation example in step S101 shown in FIG. Using the test apparatus, a test of the CPU 10 as the arithmetic processing apparatus is started at a part of the operation frequency used in the DVFS control with the operation frequency and the power supply voltage estimated by the simulation (S201). Then, by performing a test while changing the power supply voltage value with the test apparatus, the power supply voltage value that operates normally with respect to the operating frequency is measured including the margin (S202). Next, in order to use it as setting data in the DVFS table 12, the power supply voltage value for the operating frequency measured in the test is stored in an arbitrary storage device or the like in association with the CPU 10 as the measurement target (S203). . As a result, the power supply voltage value including the margin can be obtained by measurement for a part of the operating frequency used in the DVFS control.

  FIG. 8 is a flowchart showing an operation example in steps S102 and S103 shown in FIG. 8, steps S301 to S307 correspond to the operation in step S102 shown in FIG. 6, and steps S308 to S314 correspond to the operation in step S103 shown in FIG.

  First, when the CPU 10 is activated, the DVFS table setting operation control unit 41 of the control circuit 14 performs a scan shift operation according to the signals scan and ctr, and sets data in the DVFS table 12 via the signal tb_scan (S301). ). The data set in the DVFS table 12 includes the operating frequency used in DVFS control, the power supply voltage value (simulation value, actual measurement value), the state of the power supply voltage value, the calibration group of the CPM circuit 13, and the calibration value (initial value). Is undefined).

  Next, the sequence control unit 44 of the DVFS table setting operation control unit 41 reads the data of the DVFS table 12 via the DVFS table control unit 42 and confirms the information in the table 12 (S302). As a result of checking the flag indicating the state of the power supply voltage value of the read data, if the power supply voltage value is an actual measurement value, the sequence control unit 44 determines the operating frequency and the power supply voltage value (actual measurement) of the data read from the DVFS table 12. Value) is set in the frequency setting register 45 and the voltage value setting register 46 (S303). The DVFS table setting operation control unit 41 uses the signal ctr to set the clock signal clk-c and the power supply voltage vdd-c supplied to the CPU core 11 and confirm that they are set correctly.

  Then, the CPM control unit 43 performs calibration of the CPM circuit 13 via the signal cpm_ctr. For example, as shown in FIG. 9, the CPM control unit 43 changes the calibration value of the CPM circuit 13 so that the edge where the output value of the conversion unit 36 of the CPM circuit 13 is changing becomes the center (S304).

  When the calibration of the CPM circuit 13 is completed, the DVFS table setting operation control unit 41 writes the obtained calibration value into the DVFS table 12 via the DVFS table control unit 42 (S305). At this time, the DVFS table setting operation control unit 41 performs the same calibration for the set of the operating frequency and the power supply voltage value of the same calibration group in addition to the set of the operating frequency and the power supply voltage value of the actual measurement value to be processed. Write the action value. Further, the DVFS table setting operation control unit 41 sets a flag indicating the state of the power supply voltage value in the set of the operation frequency and the power supply voltage value of the actually measured value to be processed to be calibrated (S306).

  Subsequently, the sequence control unit 44 determines whether or not the set of the operating frequency and the power supply voltage value of the actual measurement values that require calibration of the CPM circuit 13 is in the DVFS table 12 (S307). The sequence control unit 44 does not calibrate the CPM circuit 13 based on the data read from the DVFS table 12, that is, the operation of the actual measurement value in which the flag indicating the state of the power supply voltage value is not calibrated. It is determined whether there is a set of frequency and power supply voltage value.

  As a result of the determination, when there is a set of the actual operation frequency and the power supply voltage value that require calibration of the CPM circuit 13, the process returns to step S303 to perform the above-described operation. On the other hand, if there is no set of the measured operating frequency and power supply voltage value that require calibration of the CPM circuit 13, the process proceeds to step S308. In this way, the calibration of the CPM circuit 13 is performed while confirming the flag indicating the state of the power supply voltage value for each set of the operating frequency and the power supply voltage value in the DVFS table 12, so that the operation of the DVFS table 12 is performed. It is possible to set the calibration value of the CPM circuit 13 for all sets of frequency and power supply voltage value.

  Next, the sequence control unit 44 reads the data of the DVFS table 12 via the DVFS table control unit 42 and checks a flag indicating the state of the power supply voltage value of the read data (S308). Then, the sequence control unit 44 determines whether or not the DVFS table 12 includes a combination of the operating frequency and the power supply voltage value of the simulation value in which the flag indicating the state of the power supply voltage value has not been calibrated ( S309).

  If the flag indicating the state of the power supply voltage value of the read data is a simulation value that has not been calibrated, the sequence control unit 44 sets the operating frequency and power supply voltage value (simulation value) to the frequency setting register 45 and the voltage value setting. It is set in the register 46 (S310). The DVFS table setting operation control unit 41 uses the signal ctr to set the clock signal clk-c and the power supply voltage vdd-c supplied to the CPU core 11 and confirm that they are set correctly.

  Then, the CPM control unit 43 operates the CPM circuit 13 via the signal cpm_ctr. At this time, the calibration value of the CPM circuit 13 that has been set in the DVFS table 12 is applied. The margin confirmation unit 47 of the DVFS table setting operation control unit 41 confirms the timing margin for the operation frequency set by the signal cpm_dly (S311).

  Next, the DVFS table setting operation control unit 41 determines whether or not calibration of the power supply voltage value is necessary (S312). The DVFS table setting operation control unit 41 determines that the power supply voltage value needs to be calibrated when the confirmed timing margin exceeds a predetermined allowable value, and if not, the power supply voltage value need not be calibrated. Judge.

  If the power supply voltage value needs to be calibrated as a result of the determination, the voltage value increase / decrease control unit 48 of the DVFS table setting operation control unit 41 reduces the power supply voltage value if the timing margin is greater than or equal to an allowable value. If the timing margin is less than the allowable value, the power supply voltage value is increased and set in the voltage value setting register 46. Then, by checking the timing margin again, the DVFS table setting operation control unit 41 adjusts the power supply voltage value with respect to the set operating frequency (S313). For example, as shown in FIG. 9, the power supply voltage value is changed so that the edge where the output value of the conversion unit 36 of the CPM circuit 13 is changing becomes the center.

  When the timing margin falls within the allowable value, the DVFS table setting operation control unit 41 writes the power supply voltage value set in the voltage value setting register 46 to the DVFS table 12 via the DVFS table control unit 42. At the same time, a flag indicating the state of the power supply voltage value is set to have been calibrated (S314).

  In this manner, the power supply voltage value is adjusted repeatedly until there is no longer the combination of the operating frequency and the power supply voltage value of the simulation value for which the flag indicating the state of the power supply voltage value has not been calibrated, and the DVFS table 12 The operating frequency and power supply voltage value are set for all of the sets. When the setting is completed, the DVFS table setting operation control unit 41 notifies the CPU core 11 that the data of the DVFS table 12 has been determined by the signal info.

  When adjusting the power supply voltage value, if the timing margin does not fall within the allowable value even if the power supply voltage value is changed, the DVFS table setting operation control unit 41 sets the operation of setting the DVFS table 12 using the signal info. The CPU core 11 may be notified that a problem has occurred. Further, by holding the data of the set DVFS table 12 in a nonvolatile storage device or the like, the calibration of the CPM circuit 13 or the power supply voltage value using the CPM circuit 13 at the time of starting again is obtained. It is possible to omit the operation related to the adjustment.

  FIG. 10A to FIG. 10E are diagrams showing examples of data changes in the DVFS table 12 due to operations related to the setting of the DVFS table described above. In the DVFS table 12, the operating frequency Find, for each tap of the index ind (ind is 0, 1, 2, ..., Mid-x, ..., Mid, ..., Max-2, Max-1, Max). The power supply voltage value Vind_sim, Vind_tst, or Vind_cpm, the state of the power supply voltage value, the calibration group of the CPM circuit 13, and the calibration value are stored.

  10A to 10E, the power supply voltage value is indicated by Vind_sim, a simulation value is indicated by Vind_tst, and a correction value obtained by using the CPM circuit 13 is indicated by Vind_cpm. In the example shown in FIGS. 10A to 10E, the calibration group of the CPM circuit 13 belongs to the 0th group when the index ind is 0 to 2, and the setting value where the index ind is Mid-x to Mid is It is assumed that the setting values belonging to the second group and the index ind Max-2 to Mid belong to the third group.

  Before actually measuring and measuring the actual value, as shown in FIG. 10A, all the power supply voltage values for the operating frequency Find are Vind_sim, which is a simulation value, and the flag indicating the state of the power supply voltage value is “00” indicating the simulation value. When actually measured and measured values are measured, as shown in FIG. 10B, power supply voltage values for the measured operating frequencies F0, Fmid, and Fmax are measured values V0_tst, Vmid_tst, and Vmax_tst, respectively. As shown in FIG. 10C, the flag indicating the state of the power supply voltage value is “10” indicating the actual measurement value.

  Subsequently, when the CPM circuit 13 is calibrated at the time of starting the apparatus using the actually measured operating frequency and the power supply voltage value, as shown in FIG. 10D, a flag indicating the state of the calibrated power supply voltage value Becomes “11” indicating that calibration has been completed. Also, the same calibration value is written to the same calibration group. For example, the calibration value “zzzzzzz” obtained by the calibration of the CPM circuit 13 performed by setting the measured operating frequency F0 and the power supply voltage value V0_tst is set as the zeroth group calibration value. The calibration value “yyyyyyy” obtained by setting the measured operating frequency Fmid and the power supply voltage value Vmid_tst is set as the calibration value of the second group, and set to the measured operating frequency Fmax and the power supply voltage value Vmax_tst. The obtained calibration value “xxxxxxxx” is set as the third group calibration value.

  Then, when the power supply voltage value is adjusted using the CPM circuit 13 with respect to the set of the operating frequency and the power supply voltage value of the simulation value which is not measured, the power supply voltage value is adjusted as shown in FIG. 10E. The power supply voltage values for the operating frequencies F1, F2, Fmid-x, Fmax-2, Fmax-1, etc. become the correction values V1_cpm, V2_cpm, Vmid-x_cpm, Vmax-2_cpm, Vmax-1_cpm, and the power supply voltage value The flag indicating the state is “01” indicating the correction value (calibrated).

  According to the present embodiment, information indicating the state of the power supply voltage value and information related to calibration of the CPM circuit 13 are set in the DVFS table 12. Then, for some of the plurality of operating frequencies and power supply voltage values used in the DVFS control, an actual test is performed to measure the power supply voltage values for the operating frequencies, and the power supply voltage values for the operating frequencies that are not measured are processed at the time of startup. This makes it possible to suppress an increase in test time. Further, as shown in FIG. 15, the power supply voltage value with respect to the unmeasured operating frequency is adjusted by using the CPM circuit 13 calibrated by the measured operating frequency and the power supply voltage value. Accordingly, an optimized power supply voltage value can be set, and the power performance can be improved.

  FIG. 15 is a diagram illustrating a setting example of the power supply voltage value with respect to the operating frequency in the present embodiment. In FIG. 15, the horizontal axis is the operating frequency, and the vertical axis is the voltage value. In FIG. 15, power supply voltage values V102 and V104 with respect to the operating frequency correspond to power supply voltage values V102 and V104 with respect to the operating frequency shown in FIGS. 13A and 13B. In FIG. 15, Cal0, Cal3, and Cal5 are calibration values obtained by calibrating the CPM circuit 13 with the power supply voltage values for the operating frequencies F0, F3, and F5 actually measured in the test. Further, a mark indicated by a square indicates a power supply voltage value at which the edge of the output of the CPM circuit 13 before the calibration of the CPM circuit 13 is centered.

  In the above description, the operation related to the setting of the DVFS table 12 is controlled by the control circuit 14, but is not limited to this. A register for holding a value may be arranged in the control circuit 14, and the operation related to the setting may be controlled by executing a program read from the memory 18 or the like by the CPU core 11.

  In the above-described embodiment, an example in which one CPM circuit 13 is arranged in the CPU 10 as the arithmetic processing apparatus has been described. However, a plurality of CPM circuits 13 may be arranged as shown in FIG. For example, a case where a plurality of CPU cores 11 are mounted and DVFS control is performed in common with the plurality of CPU cores 11 can be considered. FIG. 11 is a diagram illustrating another configuration example of the arithmetic processing device according to the present embodiment. FIG. 11 shows a configuration example related to the DVFS table setting. 11, components having the same functions as those shown in FIGS. 1 to 5 are denoted by the same reference numerals.

  In the example shown in FIG. 11, a plurality of CPM circuits 13-1, 13-2, 13-3,. Therefore, the worst path detection unit 56 is provided in the CPM control unit 43, and the worst path detection unit 56 has the lowest timing margin among the plurality of CPM circuits 13-1, 13-2, 13-3,. That is, the worst path timing margin information is detected and output to the margin confirmation unit 47. Thereby, it is possible to set the DVFS table 12 as in the above-described embodiment.

  Further, as shown in FIG. 12, a plurality of sets of the DVFS table 12, the CPM circuit 13, and the control circuit 14 may be arranged. For example, a case where a plurality of CPU cores 11 are mounted and DVFS control is performed for each CPU core 11 can be considered. FIG. 12 is a diagram illustrating another configuration example of the arithmetic processing device according to the present embodiment. FIG. 12 illustrates a configuration example related to the DVFS table setting. 12, components having the same functions as those shown in FIGS. 1 to 5 are given the same reference numerals.

  In the example shown in FIG. 12, the DVFS table 12-1, the CPM circuit 13-1, and the control circuit 14-1 are paired, and the DVFS table 12-2, the CPM circuit 13-2, and the control circuit 14-2 are combined. The DVFS table 12-3, the CPM circuit 13-3, and the control circuit 14-3 may be used as a set, and the DVFS table setting operation described above may be performed independently for each set.

  Note that this embodiment can be realized by, for example, an arithmetic processing device having a CPU (or MPU) and a memory executing a program stored in the memory or the like, and the program is included in the embodiment of the present invention. A recording medium on which the program is recorded is included in an embodiment of the present invention. As a recording medium for recording the program, for example, a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used.

  In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  In an arithmetic processing unit that performs DVFS control, it is possible to suppress an increase in test time for measuring the operating frequency and power supply voltage value used in DVFS control, and an optimum power supply voltage value corresponding to process variations can be set. This makes it possible to perform DVFS control.

Claims (9)

A table for setting a plurality of operating frequencies used in dynamic voltage / frequency control and power supply voltage values for the operating frequencies;
A critical path monitor circuit that detects a delay change according to a change in the power supply voltage;
Referring to the performed calibration processing of the critical path monitor circuit, a calibration value according to the power supply voltage value obtained by the calibration process in the measurement above the operating frequency and the power supply voltage value obtained in said table And adjusting the power supply voltage value with respect to the operating frequency not measured in the table using the critical path monitor circuit, and a control circuit for setting the adjusted power supply voltage value in the table. Arithmetic processing device characterized. A plurality of groups including both the power supply voltage value for the operating frequency obtained by measuring the operating frequency and the power supply voltage value in the table, respectively, and the power supply voltage value for the operating frequency not measured; Divided into
The control circuit adjusts the power supply voltage value with respect to the operating frequency that has not been measured, the power supply voltage obtained by the calibration processing at the operating frequency and the power supply voltage value obtained by measuring within the group The arithmetic processing device according to claim 1, wherein the calculation processing device is performed with reference to a calibration value related to the value . The control circuit includes:
A timing margin for the operating frequency exceeds an allowable value based on margin information corresponding to a delay in the critical path monitor circuit when the operating frequency obtained by measurement in the table and the power supply voltage value are set. A determination unit for determining whether or not
The arithmetic processing apparatus according to claim 1, further comprising: a calibration control unit that performs calibration processing of the critical path monitor circuit based on a determination result in the determination unit. The control circuit includes:
Whether the timing margin for the operating frequency exceeds an allowable value based on margin information corresponding to a delay in the critical path monitor circuit when the operating frequency and the power supply voltage value not measured in the table are set A determination unit for determining whether or not ,
The arithmetic processing apparatus according to claim 1, further comprising: an increase / decrease control unit that controls increase / decrease of the power supply voltage value with respect to the operating frequency based on a determination result of the determination unit. The control circuit includes:
A determination unit that determines whether a timing margin for the operating frequency exceeds an allowable value based on margin information according to a delay in the critical path monitor circuit;
A calibration control unit that performs calibration processing of the critical path monitor circuit based on a determination result in the determination unit when the operating frequency and the power supply voltage value obtained by measurement in the table are set;
An increase / decrease control unit that controls increase / decrease of the power supply voltage value with respect to the operating frequency based on a determination result of the determination unit when the operating frequency and the power supply voltage value that are not measured in the table are set. The arithmetic processing apparatus according to claim 1. A plurality of critical path monitor circuits;
2. The calculation according to claim 1, wherein the control circuit performs the calibration process and the adjustment of the power supply voltage value by using one critical path monitor circuit among the plurality of critical path monitor circuits. Processing equipment.   The arithmetic processing apparatus according to claim 1, comprising a plurality of sets of the table, the critical path monitor circuit, and the control circuit. Control of an arithmetic processing unit having a table for setting a plurality of operating frequencies used in dynamic voltage / frequency control and a power supply voltage value for the operating frequency, and a critical path monitor circuit for detecting a delay change according to the change of the power supply voltage A method,
Performing calibration processing of the critical path monitor circuit at the operating frequency and the power supply voltage value obtained by measurement in the table,
To adjust the power supply voltage for the measured non the operating frequency in the calibration the table refers to the calibration value according to the power supply voltage value obtained by processing using the critical path monitor circuit,
A control method for an arithmetic processing unit, wherein the adjusted power supply voltage value is set in the table. In a processing unit having a table for setting a plurality of operating frequencies used in dynamic voltage / frequency control and a power supply voltage value for the operating frequency, and a critical path monitor circuit for detecting a delay change according to a change in the power supply voltage,
Calibration is performed on the power supply voltage value based on the output of the critical path monitor circuit by executing calibration processing of the critical path monitor circuit at the operating frequency and the power supply voltage value obtained by measurement in the table . Processing to find a value ;
Wherein by applying a calibration value according to the power supply voltage value obtained by the calibration process is operated the critical path monitor circuit in measured non wherein the operating frequency and the power supply voltage value in the table, the critical path monitor a process for adjusting the power supply voltage value for the operating frequency based on the output of the circuit,
A program for executing the process of setting the adjusted power supply voltage value in the table.

Images