TWI352996B - Tester for testing semiconductor device - Google Patents

Description

1352996 IX. Description of the Invention: [Technical Field] The present invention relates to a tester for testing a semiconductor device, in particular for a test in which a plurality of clocks are used according to a time delay A tester for a semiconductor device that produces various timings to improve test efficiency and reduce manufacturing costs. [Prior Art] A tester for testing a semiconductor device tests whether the semiconductor device is defective. The tester for testing the semiconductor device is designed and developed according to the development state of a memory device. Specifically, the memory device is a DRAM, which occupies most of the memory device because it is used for testing the semiconductor device. The tester is primarily used to test memory devices. The development of DRAM is from EDO (Extended Data Output) dram, SDRAM (Synchronous DRAM), Rambus DRAM to DDR (Double Data Rate) DRAM. To test DRAM' the tester requires high speed and high precision to correspond to the directional DRAM. In addition, as the capacity of the memory increases, the time required to test the DRAM is also increased. Therefore, it is also necessary to increase the test speed. In addition, the cost of testing memory should be reduced by embodying a small and economical test. In testers for testing semiconductor devices, a particular memory tester is typically used to test and validate a memory component or a memory module in the form of a SIMM or DIMM. The tester detects functional defects of the memory module or the memory component and then installs it in an actual computer system 122876-I000318.doc 1352996. Li, έ 古 古 古 器 、 、 、 、 、 、 、 、 、 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬 硬In the middle, the software diagnostic program diagnoses the state of the 6-memory body. Therefore, the hardware semiconductor device tester is mainly used during the semiconductor memory system. α classifies the Sx test <4 device into an ATE (automatic test equipment) The high-end tester is the intermediate tester and the low-end memory tester. The ATE of the system tester used in Fig. 4 is used to carry out the test procedure of the memory device. Test, which is used to test whether the DC parameters are suitable for digital operation of the circuit, the delay time of the signal transmission, and the AC margin associated with the set time and hold time. ATE also generates a test pattern and a timing for testing. However, ΑΤΕ is more expensive to manufacture because it uses special equipment (such as a host computer with large size and high price) to manufacture ATE. Figure 1 is a diagram for testing semiconductors. Block diagram of the conventional tester shown in FIG. 1 'The conventional tester includes a pattern generator 11 〇, a timing generator #120, a format controller 130, a driver 140, a comparator 150, And a test result storage device 16. In addition to the components, the conventional test s can also include a power supply controller for DC testing, a component for generating a clock signal, and for the DUT (to be A component of the operational power supply, a component for relaying a test pattern data to the DUT 1 80 and receiving a test result from the DUT 180, for use from 122876-1000318.doc 1352996 Receiving a component of a test pattern program and a component for transmitting the test result to the outside. However, the description thereof is omitted. The pattern generator 110 generates a required test for the test 180 according to the test pattern program. Test pattern data. For example, the test pattern program is written to include an instruction to perform various operations for performing the test. The pattern generator 110 receives and interprets the test pattern from, for example, an external memory. The test pattern data is generated by the program. The test pattern data includes data such as an instruction, an address, and a data input to the DUT 18 。. In addition, an expected data is generated, which corresponds to the generated test type. The timing generator 120 generates a timing edge for converting the test pattern data generated in the pattern generator 110 into a reference of various waveforms. The plurality of clocks are used to generate the timing edge to Smooth conversion is performed. The format controller 1 3 0 converts the test pattern data into a desired waveform according to the timing edge. The conversion of the test pattern data is described in detail below. Figure 2 illustrates the tradition for testing a semiconductor device. A diagram of an example of converting a s-waveform in a tester. Referring to Figure 2, the pattern generator 1 generates the test pattern data. The other timing generator I20 generates a plurality of timing edges using a plurality of clocks ACLK, BCLK, and CCLK as shown. Because the format controller 1 30 requires a timing reference to convert the test pattern data to the desired test waveform at the desired time, the timing generator 12 uses the plurality of clocks to generate the plurality of timing edges to configure the Timing reference. The plurality of clock systems are specifically used to generate the type 122876-1000318.doc 1352996 for testing a non-synchronous semiconductor device. The format controller 130 converts the test pattern data into a desired test waveform based on each of the timing edges. For example, when the clock ACLK is used, the format controller 130 can convert the test pattern data into a test waveform of nrza or /NRZA. "NRZ" indicates a conversion in which no "0" is returned in the period of the test type data "1", and a character "A" indicates that the test pattern data is converted by the clock ACLK. Moreover, the character indicates that the test pattern data is reversed. When the clock BCLK is used, the format controller 13 can convert the test pattern data into a test waveform of NRZB or /NRZB. When using the clock CCLK, the format controller The test pattern data can be converted into a test waveform of NRZC or /NRZC. When the clocks bCLk and CCLK are used simultaneously, the format controller 13 can convert the test pattern data into test waveforms of NRZBC or /NRZBC. As described above, the plurality of clocks are used and the test pattern data can be converted to a test waveform by the format controller 130. The driver 140 transmits the converted test waveform to the dut 1 80. The comparator 150 is used in the following manner Test 180 τ 180 : The test output data output from the DUT 18 之后 after the DUT 18 〇 operation is completed by the test waveform applied to the DUT 180 is compared with the expected data generated in the pattern generator 11 。. The storage i 60 stores a test result based on the result of the comparison of the comparator i 5 . For example, storing information about the defective τ. As explained above, the conventional ATE is a very expensive device. Manufacturers efficiently design high-priced ATEs by minimizing their system 122876-1000318.doc 1352996

Caused by the original increase in competitiveness. In order to design ATE efficiently, the test pattern and timing should be optimized. Specifically, in order to embody the timing generation function of the timing generator 12, expensive components are required. Further, even when a high-priced component is used, it is difficult to be a function of generating accurate timing for testing of a semiconductor device operating at a high speed. The function of generating timing using the plurality of clocks can be used for testing of non-synchronous devices. However, the function of using the plurality of clocks to generate timing is not optimal for the synchronization device. Further, when the converted test waveform is transmitted to the DUT 180, the test waveform can be delayed by a predetermined period. The expected data can also be delayed by the comparator i 5 to perform a comparison with the data output from the DUT 180. Since the delay is implemented by the format controller 13 after the conversion, the driver j 4 or the comparator 150 can again convert an actual test waveform or the expected data by considering each of the delays. In addition, the test pattern data generated in the pattern generator 应该 should be converted in accordance with each of the channels of the DUT 180 (for example, the pins of the DUT 180). The conversion of the pins is performed, and then the test pattern data is applied to the format controller 130. In such cases, multiplexing of the test pattern data to be applied to each of the pins is performed. However, because multiplexing is performed to correspond to each of the pins, resources are wasted. SUMMARY OF THE INVENTION One object of the present invention is to provide a tester for testing a semiconductor device in which various timings are generated in accordance with a time delay instead of using a plurality of clocks to improve test efficiency and reduce manufacturing costs. 122876-1000810.doc 1352996 Patent application No. 096128074 丨一------------ Chinese manual replacement page (100 years 8' month) j1〇|· | ·#正正

To achieve the above object of the present invention, a tester for testing a DUT is provided, the tester comprising: a pattern generator for generating a test for the DU according to a test pattern program a logic test pattern data; a data selector for converting the logic test pattern data sent from the pattern generator into a physical test pattern data and converting into a expected data; a format controller, Converting the physical test pattern data into a test waveform according to a set of time delay values for testing; a Φ actuator for applying the test waveform to the DUT; and an output comparator for using the DUT Receiving an output corresponding to the test waveform to output a test output data; a test comparator for comparing the test output data with the expected data to determine the DUT is a defective DUT; For multiplexing the test waveform to conform to one of the operating speeds of the DUT, a demultiplexer for demultiplexing the test output data to conform to the hypometric test output data and the expected resource Comparing one of the operating speeds; the one-time sequence controller' is used to supersample one of the test waveforms before applying the test waveform to the multi-device; and the one-bit shifter uses The test waveform is shifted by one unit of the unit after the oversampling is performed to be applied to the multiplexer. Preferably, the tester according to the present invention further comprises a delay control for applying the physical test pattern data and the expected data to the format controller and the test comparator, respectively, by controlling the delay. Preferably, the tester according to the present invention further comprises a plurality of anti-skews. Patent application 122876-1000810.doc 1352993⁄4 096128074 Patent application replacement page (August 100)

a controller for respectively transmitting a test waveform to the DUT through the driver and compensating for each of the channels in the channel after receiving the test output data from the dummy through the output comparator Skew 0 Preferably, the anti-skew controller compensates for timing skew by setting a timing skew for each of the channels. Preferably, the tester according to the present invention further includes a plurality of anti-skew control 1 § for respectively transmitting a test waveform multiplexed by the multiplexer to the request through the driver and before Compensating for a timing skew generated in each of the channels of the Du Ding after receiving the test output data from the DUT through the output comparator, and wherein each of the anti-skew controllers is The mode is associated with the bit shifter: the timing skew is partially compensated by the bit shifter when the timing skew is greater than a predetermined value. Preferably, the anti-skew controller compensates for timing skew by setting a timing skew for each of the channels. Preferably, the driver applies a test waveform to the DUT in such a way that the test waveform has one of three levels "high", low " and "terminate". Preferably, the output comparator will The output corresponding to the test waveform form received from the DUT is compared to a threshold value to output the test output data. Preferably, the threshold value is variable. 122876-1000810.doc 1352996 100. C: . Preferably, The output comparator configures a window based on the threshold and determines an output level of a signal for use outside the window. Preferably, the test comparator includes: a resynchronizer for considering the test Performing resynchronization of the test output data with a round trip delay between the device and the DUT; and a round trip delay compensator for delaying the expected data according to the round trip delay. Preferably, the test pattern generator Generating a control flag for converting logical test pattern data into physical test pattern data according to each of the channels of the DUT for transmission to the data selector, and wherein the data selector is Testing a plurality of pre-designated data selection forms to convert logical test pattern data into physical test pattern data for transmission according to the control flag and through each of the channels of the DUT. Preferably, in accordance with the present invention The tester further includes a test result transmitter for transmitting the test result to an external device. [Embodiment] The present invention will now be described in detail with reference to the accompanying drawings. Fig. 3 is an illustration for testing one of the present invention. A block diagram of a tester for a semiconductor device. Referring to FIG. 3', the tester includes a pattern generator 21A, a data selector 220, a format controller 23A, a driver 24A, and an output comparator 250. And a test comparator 260. In addition, the tester may further include a delay controller 270, a multiplexer 280, a demultiplexer 29A, a timing controller 300, a bit shifter 310, and the like. The skew controllers 32A, 320b and a test result transmitter 33. 122876-1000810.doc 12 1352996 ί c^o 彡, π --- for testing the semiconductor device according to the present invention The feature is that it is used to implement the generation of test-type data or to optimize the conversion of a format for its efficient configuration. Therefore, the tester package 3 is used for components of the following purposes. : The formatted converted test waveform is applied to the DUT (device to be tested) 380; and by comparing a data received from the DUT 380 with an expected data, it is determined whether the DUT 38 is defective. Further, the tester includes A component for use in the following applications: a test waveform from the drive benefit 240 is distributed to a plurality of 〇1; D; the result of the test is received from the plurality of. However, the detailed description thereof is omitted. The pattern generator 210 generates logic test pattern data for testing a semiconductor device to be tested (i.e., DUT 38A) according to a test pattern program. For example, pattern generator 210 compiles a test pattern program written by a programmer and generates logical test pattern data by executing the test pattern program. The logic test type data contains a command signal 'A bit signal X and a material L number. The pattern generator 210 can also generate a control flag for each of the channels of the DUTs 3 8 (i.e., each of the pins of the DUT 380) to be transmitted to the data selector 22A. The data selector 220 converts the logical test pattern lean material sent from the pattern generator 21 to a physical test pattern data to be sent to the DUT 38 and converted into a desired data. That is, the logic test pattern data generated by the pattern generator 21 is not sent to all the channels of the DUT 380 as it is. The logical test pattern data is converted for each of the channels and sent to each of the channels. To achieve this, the data selector 22 converts the logical test pattern data into physical test pattern data for transmission to each of the channels of dut 122876-10003] 8.doc 13 1352996 380. In addition, the pattern generator 210 can generate a control flag that is transmitted to the tribute selector 22A. When the control flag is used, the data selector 220 can convert the logical test pattern data into physical test pattern data using a predetermined conversion procedure and based on the control flag. Therefore, the conversion speed is improved. That is, the data selector 220 can convert the logical test pattern data into the physical test pattern data by referring to a plurality of pre-specified data selection forms to be sent according to the control flag and through each of the channels of the DUT. . In such cases, a dut interface with a multiplexed structure or a contracted structure can be used. The format controller 230 converts the physical test pattern data into a test waveform based on a set of time delay values for performing the test. That is, the desired test waveform is generated based on the physical test pattern data. The time delay value can be set by the programmer when writing the test pattern program.

The driver 240 applies a test waveform output from the format controller 230 to the DUT 380. For example, the driver 24 applies the test waveform to the DUT 380 in a manner that the test waveform has three levels, low " and "terminate", when the test waveform is applied to the DUT 38 When removing a reflective component, select Level |, Terminate ". In another case, choose Level "High" or •, Low". The output comparator 250 receives from the DUT 380 a _35 message & corresponding to the test waveform generated by the profile applied to the DUT 380 to output the __ test output data. Output comparator 250 can perform the comparison based on a predetermined threshold. In addition to the characteristics of the test environment, the characteristics of the channel, or the characteristics of the dut 38〇, the threshold value can be efficiently generated to produce test output data. Furthermore, when the output comparator 250 converts the output signal corresponding to the test waveform into test output data based on the threshold, the conversion of a signal for the threshold may not be accurate. In such cases, a window is configured for the threshold to determine the output level of the signal for use outside the window to generate test output data.

The test comparator 260 compares the test output data output from the output comparator 25 to the expected data in the data selector 220 to determine that the bribe has a defective DUT. Fig. 4 is a view showing an example of one of conversion test waveforms in a tester for testing a semiconductor device according to the present invention. Patterns A and B represent an example of obtaining physical test pattern data by converting the logical test pattern data generated in the pattern generator 210 by the data selector 22.

"clock" denotes a reference clock for testing the conversion of the waveform, and the time delay value" table is not used for the set of values of the conversion of the test waveform by the programmer. The format controller 230 uses the reference The clock and the delay value convert the physical test type into a test waveform. For example, nrz, nrzi, rz〇, and RZOI are not examples of test waveforms converted according to the type, and dnrz and DNRZI indicate according to the pattern. An example of a converted test waveform. A tester according to the present invention is characterized in that the tester does not include a timing generator used in conventional test benefits. That is, although the tester shown in Figure 2 is 122876-1000318.doc • 15 - 1352996 uses the plurality of clocks to generate timing to generate a test waveform, but the tester according to the present invention shown in FIG. 4 uses only the reference clock instead of the plurality of clocks and performs conversion according to the time delay value. No need for a high-priced timing generator. The tester according to the present invention may further comprise an assembly for efficient use of one of the testers other than the components described above. The delay controller 270 applies the physical test pattern data and the expected data to the format controller 23 and the test comparator 26 respectively by controlling the delay. The entity test type data and The expected data is delayed by a predetermined period to control the delay. Although the physical test pattern data and the expected data are delayed by the predetermined period after generating the test waveform according to the conventional test benefit, according to the present invention, only the reference clock may be used according to the present invention. And the time delay value is used to convert the test waveform. Therefore, the physical test pattern data and the expected data are delayed by the predetermined period, and then the test waveform is converted according to the present invention. In addition, when the FIFO (first in first out) device is used, the automatic The configuration is based on the delay of writing to DUT 3 8〇 or reading from DUT 3 80. Therefore, the programmer can easily embody the program without special configuration. The operating speed of the semiconductor device becomes higher and requires south speed operation, but the test waveform is mainly generated for low speed operation. Therefore, the test waveform To be multiplexed to correspond to the operating speed of the semiconductor device or to be demultiplexed to perform a comparison of the test output data with the expected data. The multiplexer 280 multiplexes the test waveform to match the operating speed of the dut 380, and The multiplexer 290 de-multiplexes the test output data to a value of 122876-1000318.doc 1352996 σ. The operating speed of the comparison of the output metrics and the expected data is measured before the multiplexer 280 performs the multiplex. 'Extraction of test waveforms can be implemented. That is, the tester can include a timing controller that performs oversampling to apply low frequency test waveforms to 280 ° oversampling at high speeds. The frequency data is converted into high frequency data. Therefore, oversampling of the test waveform can be applied to the multiplexer 280 designed to operate only at a high frequency. The Hai tester may include a bit shifter 3, which is used to shift the test waveform by one bit unit after the oversampling is performed to be applied to the multiplexer 280. That is, the bit shifter 31 移位 shifts the test waveform by the unit of the bit to additionally generate a desired waveform or set a time delay. On the other hand, the timing skew occurring in the channel of the DUT 380 may be the same for each of the channels. p, because the signal transmission environment is not the same for each of the channels, so that timing skew is generated. Therefore, after transmitting the test waveform to the DUT 38 through the driver 24 or after receiving the test wheel data from the DUT 380 through the output comparator 250, a function for compensating for the timing skew for each of the channels is required. . To compensate for timing skew, the tester in accordance with the present invention can include anti-skew controllers 320a and 320b. Preferably, the anti-skew controllers 320a and 320b configure a timing skew for each of the channels of the DUT 380 using a programmable timing delay device. 122876-1000318.doc 17 1352996 The anti-skew controller 320a compensates for timing skew before transmitting the test waveform to the DUT 380 through the driver 240. However, when the timing skew has a large proportion, the anti-skew controller 320a may not be able to compensate for the timing skew. That is, the range of the timing skew compensated by the anti-slant controller 320a can be different depending on the programmable timing delay means. Programmable timing delay devices capable of compensating for a wide range of timing skews are expensive and have poor compensation characteristics. Thus, when the anti-skew controller 320a compensates for a timing skew greater than a predetermined value, the anti-skew controller 320 can be configured to be associated with the bit shifter 3ι to compensate for the timing skew. The 卩 bit shifter 3 1 0 primarily compensates for timing skew outside of the range that can be compensated by the anti-skew controller 32 〇 a. After the bit shifter 31 〇 performs the initial j compensation, the anti-skew controller 320a can again compensate for the timing skew within the range that can be compensated by the anti-skew controller 320a. Therefore, a large proportion of timing skew can be compensated. In addition, when the test waveform is transmitted between the tester according to the present invention and the 〇17丁38〇, the test input (four) material is received according to the test waveform, and by testing the comparator 260 to compare the expected data with the test output data, the test comparator 260 considers the round trip delay. That is, the test comparator 26 considers the delay that will change during the process of transmitting signals through different paths. Therefore, compensation for round trip delay is efficiently implemented.

Show), which is used to perform resynchronization of the test output data by considering the tester and the DUT repeater (the round trip delay between the JT 380 is not shown in the figure 122876-I000318.doc • 18-; A delay compensator (not shown) is configured to delay the expected data according to the round trip delay. The resynchronizer and the round trip delay compensator may respectively include a FIFO device. In such cases, the program may be The designer can easily create a test pattern program without special configuration. As explained above, the test pattern data generated in the pattern generator 210 contains commands, addresses, and data signals. In such cases, according to the present invention The tester can further include a test result store (not shown) for storing information about the defective DUT determined by test comparison 1 § 260 or information about the test type program. The information may be identification information of the location of the defective DUT and may include the unit address of the defective unit. Further, information about the test type program may be detected. Corresponding command, address and data when the defect is Dut. The information stored in the test result storage (not shown) can be used to remove the defective DUT or the debugging of the test pattern program. The device may further include a test result transmitter 33A for transmitting the test result of the test comparator 260 (ie, information about the defective DUT) and a data message to an external device so that the user can easily view the test result. Figure 5 is a diagram illustrating a practical embodiment of a tester for testing a semiconductor device in accordance with the present invention. 122876-1000318.doc 19 1352996 "ALPG" represents a pattern generator 210. The pattern generator 210 includes: "Instruction Memory" for storing binary data obtained by compiling the test pattern program; "Sequence Controller" for sequentially reading data stored in "Command Memory"; And "command generator", "address generator" and "data generator", the commands, addresses, or resources needed to generate the DUT test The pattern generator 210 also generates a "control flag" "PDS" to indicate the data selector 220. As shown, the data selector 220 converts commands, addresses and data according to "control flags." Latency" represents the delay controller 270. The delay controller uses the FIFO to adjust the delay. In the case of commands and address addresses, the DR (drive) FIFO is used because the command and address need to be transmitted to the DUT. In the case of data, because The data should be sent to the DUT and the data and expected data are also compared, so the DRE (Drive Enable) FIFO and the CPE (Comparative Enable) FIFO are used. "FC/TC" represents format controller 230, multiplexer 280, demultiplexer 290, timing controller 300, and bit shifter 310. "FCn" indicates the format controller 230, "TC" indicates the timing controller 300 and the bit shifter 310. Further, "MUX" and "DEMUX" correspond to the multiplexer 280 and the demultiplexer 290, respectively. "Deskew" corresponds to the anti-skew controller 320, "Drive" corresponds to the driver 240, "Comparator" corresponds to the output comparator 250 and "DCP (Digital Comparator)" corresponds to the test comparator 260. "; DFM (Data Failure Memory) " and "AFM (Address Fault Memory)" corresponds to the test result storage. Each of the "DCP" and "AFM" includes a resynchronizer 122876-10003J8.doc -20- 1352996

Resync FIFO and "rtd FIFO" corresponding to the round trip delay compensator. In addition, "DCP" compares the information and stores the information on the defective DUT in "DFM (data failure memory, and transmits the corresponding address and stores it in "AFM". Although the present invention has referenced it The present invention has been shown and described with reference to the preferred embodiments of the present invention The tester of the semiconductor device of the invention generates various timings according to time delay instead of using a plurality of clocks to improve test efficiency and reduce manufacturing cost. [Schematic Description] FIG. 1 is a diagram illustrating a conventional tester for testing a semiconductor device. Figure 2 is a diagram illustrating an example of converting a test waveform in a conventional tester for testing a semiconductor device. Figure 3 is a diagram illustrating testing of a tester for testing a semiconductor device in accordance with the present invention. Figure 4 is a block diagram showing one of the conversion test waveforms in a tester for testing a semiconductor device in accordance with the present invention. Figure 5 is a diagram illustrating a practical embodiment of a tester for testing a semiconductor device in accordance with the present invention. [Main component symbol description] 110 pattern generator 120 timing generator 122876-1000318. Doc -21- 1352996

130 format controller 140 driver 150 comparator 160 test result storage Is 180 DUT 210 pattern generator 220 data selector 230 format controller 240 driver 250 output comparator 260 test comparator 270 delay controller 280 multiplexer 290 solution The tool 300 timing controller 310 bit shifter 320a anti-skew controller 320b anti-skew controller 330 test result transmitter 380 DUT 122876-1000318.doc -22-

Claims (1)

Patent Application No. 096128074 (Replacement of Chinese Patent Application Scope (August 1st)) X. Application Patent Range: - A tester for testing -DUT, the tester includes: - a type generator Generating a test type data for the test of the DUT according to the test pattern program; and a data selector for converting the logical type 4 poor material sent from the pattern generator into an entity Testing the pattern data and converting it into a expected data; a format controller for converting the physical test pattern data into a test waveform according to a set of time delay values for the test; the driver 'used to apply the test waveform The Dut; an output comparator for receiving an output corresponding to the test wave opening from the DUT to output a test output data; a test comparator for comparing the test output data with the expected = a material to determine the DIJT system is a defective DUT; a multiplexer 'which is used to multiplex the test waveform to match one of the Du operating speeds; a solution multiplexer' which is used to solve the multiplex Testing the output data to match the operating speed of the comparison of the measured D-type output data with the expected data; a timing controller for performing one of the test waveforms before applying the test waveform to the multiplexer Sampling; and a one-bit shifter for shifting the test waveform into units of bits after the oversampling is performed to be applied to the multiplexer. 2. The tester of claim 1, further comprising a delay controller for controlling the physical test pattern data by controlling the delay thereof and the expected 122876-1000810.doc 1352996 day α Zhengling Factory iiL — the hot data is applied to the format controller and the test comparator respectively. 3. The tester of claim 1, further comprising a plurality of anti-skew control benefits, wherein the anti-skew controllers are respectively used to transmit The driver compensates for a timing skew generated in each of the channels before transmitting the test waveform to the DUT and after receiving the test output data from the DUT through the output comparator. 4. The tester of claim 3 wherein the anti-skew controller compensates for the timing skew by setting the timing skew for each of the channels. 5. The tester of claim 1, further comprising a plurality of anti-skew controllers for respectively transmitting the test waveform multiplexed by the multiplexer through the driver to the Compensating for a timing skew generated in each of the channels of the DUT before and after receiving the test output data from the DUT through the output comparator, and wherein the anti-skew controllers Each is associated with the bit shifter by partially compensating for the timing skew due to the timing skew when the timing skew is greater than a predetermined value. 6. The tester of claim 5, wherein the anti-skew controller compensates for the timing skew by setting the timing skew for each of the channels. 7. The tester of claim 1, wherein the driver applies the test waveform to the DUT in a manner that the test waveform has two levels of "shang" "low" and "terminate" 122876-I000810.doc The tester of item 1 of the present month, wherein the output comparator compares the output corresponding to the test waveform received from ο T with a threshold value to output the test round-out data. The tester of item 8, wherein the threshold value is variable. The tester of claim 8, wherein the turn-out comparator configures the window according to the threshold value and determines the output of the signal outside the f-output Position The tester of claim 1 wherein the test comparator comprises: resynchronization, which is used to perform resynchronization of one of the test output data by considering a round trip delay between the tester and the DUT; A round trip delay compensator' is used to delay the expected data based on the round trip delay. 12. The tester of claim 1, wherein the test pattern generator generates the logic test pattern data to the entity test type according to each of the channels of the DUT to be sent to the data selector a control flag for converting the sample data; and contending for the feed selector to convert the logical test pattern poem to be transmitted through the DUT by referring to a plurality of pre-specified data selection forms The physical test pattern data sent by each of the equal channels. 13. The tester of claim 1 wherein the step further comprises a test result transmitter for transmitting the result of the test to an external device. 122876-1000810.doc