JP6085592B2 - Method for forming ultra shallow doping region by solid phase diffusion - Google Patents

Description

  The present invention relates generally to semiconductor devices and methods of manufacturing the same, and more specifically to the formation of ultra shallow dopant regions by solid phase diffusion from a dopant layer to a substrate layer.

  The semiconductor industry is characterized by a trend towards producing increasingly larger and more complex circuits on a given chip. Such large and complex circuits are achieved by reducing the size of individual devices in the circuit and bringing them closer together. As the dimensions of individual components, such as metal oxide semiconductor (MOS) transistors or bipolar transistors, in the device are reduced and the device components are brought closer together, improved electrical performance can be obtained. However, care must be taken to form the doped regions in the substrate to ensure that no harmful field conditions occur.

  For example, when the size of a device component such as a transistor gate of a MOS device or an emitter region of a bipolar device is reduced, the junction depth of the doped region formed in the semiconductor substrate must also be reduced. Formation of shallow junctions with a uniform doping profile and high surface concentration has proven very difficult. A commonly used technique is to implant dopant atoms into the substrate using an ion implanter. When ion implantation is used, high-energy dopant atoms collide with the substrate surface at a high speed and penetrate into the substrate. Although this method has been found to be effective in forming doped regions having moderately deep junctions, it is extremely difficult to form ultra shallow junctions using ion implantation. At the low energy required to form a shallow implant junction, both the path of energized dopant atoms in the substrate and the uniformity of the implant are difficult to control. The implantation of energized dopant atoms damages the crystal lattice in the substrate, which is difficult to repair. Dislocations resulting from lattice damage can easily spike across shallow junctions and cause current leakage across the junction. Also, ion implantation of p-type dopants, such as boron, that diffuse quickly through silicon results in excessive dispersion of dopant atoms after they are introduced into the substrate. Thus, it becomes difficult to form highly confined populations of p-type dopant atoms within a particular region within the substrate, particularly at the surface of the substrate.

  In addition, new device structures for transistors and memory devices that utilize doped three-dimensional structures are being implemented. Examples of such devices include, but are not limited to, FinFETs, tri-gate FETs, recess channel transistors (RCAT), and embedded dynamic random access memory (EDRAM) trenches. In order to uniformly dope these structures, it is desirable to have a conformal doping method. The ion implantation process is effectively line of sight and therefore requires a special substrate orientation to uniformly dope the fin and trench structures. Also, at high device density, the shadowing effect makes uniform doping of the fin structure by ion implantation techniques extremely difficult or even impossible. Conventional plasma doping and atomic layer doping are demonstrated conformal doping techniques for three-dimensional semiconductor structures, each limited to a range of dopant densities and depths that can be made available under ideal conditions. Is. Embodiments of the present invention provide a method for forming a very shallow doped region that overcomes some of these difficulties.

  Several embodiments are disclosed for forming ultra shallow boron dopant regions by solid phase diffusion from a boron dopant layer into a substrate layer. The dopant region may be formed in a planar substrate, in a raised feature on the substrate (a raised feature), or in a recessed feature in the substrate (a concave feature).

  According to one embodiment, a method is provided for forming a very shallow boron (B) dopant region in a substrate. The method includes depositing a boron dopant layer by atomic layer deposition (ALD) in direct contact with the substrate, the boron dopant layer reacting with a gas exposure of a boron amide precursor or an organic boron precursor and reacting. It has an oxide, nitride or oxynitride formed by alternating gas exposure to gas. The method further includes patterning the boron dopant layer and diffusing boron from the patterned boron dopant layer into the substrate by a heat treatment to form an ultra shallow boron dopant region in the substrate. including.

  According to some embodiments, a method is provided for forming a very shallow boron (B) dopant region in a raised feature or in a concave feature in a substrate.

  According to another embodiment, a method is provided for forming a very shallow boron (B) dopant region in a substrate. The method includes, by atomic layer deposition (ALD), depositing a boron dopant layer in direct contact with the substrate and depositing a cap layer over the boron dopant layer, the boron dopant layer Has a thickness of 4 nm or less, and the boron dopant layer is formed by alternately performing a gas exposure of a boron amide precursor or an organic boron precursor and a gas exposure of a reactive gas. Or oxynitride. The method further includes patterning the boron dopant layer and the cap layer, and diffusing boron from the patterned boron dopant layer into the substrate by a heat treatment, thereby forming an ultra-shallow boron dopant region in the substrate. Forming and removing the patterned boron dopant layer and the patterned cap layer from the substrate.

  According to one embodiment, a method is provided for forming a very shallow dopant region in a substrate. The method deposits a dopant layer in direct contact with the substrate, the dopant layer comprising an oxide, nitride or oxynitride, the dopant layer comprising aluminum (Al), gallium (Ga). And a dopant selected from indium (In), thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi), and patterning the dopant layer And forming a very shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a heat treatment. According to some embodiments, a method is provided for forming a very shallow dopant region in a raised feature or in a concave feature in a substrate.

  According to another embodiment, a method for forming a very shallow dopant region in a substrate is provided. The method includes depositing a first dopant layer containing a first dopant by atomic layer deposition (ALD) in direct contact with the substrate and patterning the first dopant layer. The method further includes depositing a second dopant layer containing a second dopant by ALD in direct contact with the substrate adjacent to the patterned first dopant layer; The first and second dopant layers include oxide, nitride, or oxynitride, and the first and second dopant layers contain an n-type dopant or a p-type dopant, provided that the first The dopant layer and the second dopant layer do not contain the same dopant, and the n-type dopant and the p-type dopant are boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium. (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi). The method further includes diffusing the first dopant from the first dopant layer into the substrate by heat treatment to form a first ultra-shallow dopant region in the substrate, and by the heat treatment, Diffusing the second dopant into the substrate from a second dopant layer to form a second ultra-shallow dopant region in the substrate.

  According to yet another embodiment, a method for forming a very shallow dopant region in a substrate is provided. The method includes a patterned layer on the substrate, a patterned cap layer on the patterned layer, and adjacent to the substrate, the patterned cap layer, and the patterned layer. A first spacer layer containing a first dopant is deposited by atomic layer growth (ALD) in direct contact with the substrate adjacent to the sidewall spacer; Depositing a first cap layer over the one dopant layer and planarizing the first cap layer and the first dopant layer. The method further includes removing the patterned cap layer and the patterned layer and directly contacting the substrate adjacent to the sidewall spacer to form a second dopant layer containing a second dopant. Depositing and depositing a second cap layer on the second dopant layer, wherein the first and second dopant layers comprise oxide, nitride or oxynitride, The first and second dopant layers contain an n-type dopant or a p-type dopant, provided that the first dopant layer and the second dopant layer do not contain the same dopant, the n-type dopant and the second dopant layer The p-type dopant is boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As It is selected from antimony (Sb) and bismuth (Bi). The method further includes diffusing the first dopant from the first dopant layer into the substrate by heat treatment to form a first ultra-shallow dopant region in the substrate, and by the heat treatment, Diffusing the second dopant into the substrate from a second dopant layer to form a second ultra-shallow dopant region in the substrate.

FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a process flow for forming an ultra-shallow dopant region in a substrate according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a process flow for forming an ultra-shallow dopant region in a substrate according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing raised features to which embodiments of the present invention can be applied. FIG. 6B is a schematic cross-sectional view illustrating a conformal dopant layer deposited on the raised feature of FIG. 6A. It is a typical sectional view showing a concave feature to which an embodiment of the present invention may be applied. FIG. 7B is a schematic cross-sectional view illustrating a conformal dopant layer deposited in the concave feature of FIG. 7A.

  Various embodiments disclose a method for forming ultra shallow dopant regions in a semiconductor device by solid phase diffusion from a dopant layer into a substrate layer. The dopant region may include a very shallow source-drain extension, for example, a planar transistor, FinFET, or tri-gate FET. Other applications of ultra-shallow dopant region formation may include channel doping in substitution gate process flows and in FinFET or extremely thin silicon-on-insulator (ET-SOI) devices. Devices with other ultra-thin semiconductor channels such as germanium-on-insulator (GeOI) devices or Ge FinFETs and III-V channel devices such as GaAs, InGaAs or InGaSb FinFETs also use the disclosed methods. Can be doped. Devices formed in an amorphous Si layer or a polycrystalline Si layer, such as an EDRAM device, for example, can also utilize the disclosed method to adjust the Si doping level.

  As those skilled in the art will appreciate, various embodiments may be practiced without one or more of the specific details, with other substitutions, and / or additional methods, materials, or components. May be used. In other instances, well-known structures, materials, or operations are not shown or described in detail so as to obscure the usefulness of the various embodiments of the present invention. Similarly, specific numbers, materials and configurations are set forth for illustrative purposes in order to provide a thorough understanding of the present invention. It should also be understood that the various embodiments shown in the drawings are drawn for purposes of illustration and are not necessarily drawn to scale.

  Reference to “one embodiment” throughout this specification means that a particular function, structure, material, or feature described with respect to that embodiment is included in at least one embodiment of the invention. And do not represent that they are present in all embodiments. Thus, the appearance of the phrase “in one embodiment” in various places throughout this specification is not necessarily referring to the same embodiment of the invention.

1A-1E show schematic cross-sectional views of a process flow for forming ultra shallow dopant regions in a substrate according to one embodiment of the present invention. FIG. 1A shows a schematic cross-sectional view of the substrate 100. The substrate 100 may be of any size, for example, a 200 mm substrate, a 300 mm substrate, or a larger substrate. According to one embodiment, the substrate 100 may contain Si, such as crystalline Si, polycrystalline Si, or amorphous Si. In one example, the substrate 100 can be a tensile strained Si layer. According to another embodiment, the substrate 100 may contain Ge or a Si _x Ge _1-x compound. However, x is an atomic fraction of Si, 1-x is an atomic fraction of Ge, and 0 <x <1. Typical Si _x Ge _1-x compounds are Si _0.1 Ge _0.9 , Si _0.2 Ge _0.8 , Si _0.3 Ge _0.7 , Si _0.4 Ge _0.6 , Si _{0. .5 Ge 0.5, Si 0.6 Ge 0.4} , Si 0.7 Ge 0.3, containing Si 0.8 _{Ge 0.2,} and _Si 0.9 _{Ge 0.1.} In one example, the substrate 100 can be a compressively strained Ge layer or a tensile strained Si _x Ge _1-x (x> 0.5) deposited on a relaxed Si _0.5 Ge _0.5 buffer layer. According to some embodiments, the substrate 100 can include silicon-on-insulator (SOI).

FIG. 1B shows a dopant layer 102 that can be deposited in direct contact with the substrate 100 by atomic layer deposition (ALD), after which a cap layer 104 can be deposited on the dopant layer 102. In some examples, the cap layer 104 may be omitted from the film structure of FIGS. 1B-1D. The dopant layer 102 may be an oxide (eg, SiO ₂ ), nitride (nitride) layer (eg, SiN), or oxynitride (oxynitride) layer (eg, SiON), or these Combinations of two or more of them may be included. The dopant layer 102 includes groups IIIA of the periodic table of elements: boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl); and group VA: nitrogen (N), phosphorus (P ), One or more dopants from arsenic (As), antimony (Sb), and bismuth (Bi). According to some embodiments, the dopant layer 102 may contain a dopant with a low dopant concentration, such as between about 0.5 atomic percent and about 5 atomic percent. According to other embodiments, the dopant layer 102 may contain a medium dopant concentration, such as between about 5 atomic percent and about 20 atomic percent. According to yet other embodiments, the dopant layer may contain a high dopant concentration of, for example, greater than 20 atomic percent. In some examples, the thickness of the dopant layer 102 may be 4 nanometers (nm) or less, such as between 1 nm and 4 nm, between 2 nm and 4 nm, or between 3 nm and 4 nm. However, other thicknesses may be used.

According to other embodiments, the dopant layer 102 can contain or consist of a doped high-k dielectric material in the form of an oxide layer, a nitride layer, or an oxynitride layer. Can do. The dopant in the high-k dielectric material can be selected from the list of dopants described above. The high-k dielectric material can contain one or more metal elements selected from alkaline earth elements, rare earth elements, Group IIIA, Group IVA and Group IVB elements of the Periodic Table of Elements. Alkaline earth metal elements include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba). Exemplary oxides include magnesium oxide, calcium oxide, and barium oxide, and combinations thereof. The rare earth metal elements are scandium (Sc), yttrium (Y), lutetium (Lu), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), It may be selected from the group consisting of gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb). Group IVB elements include titanium (Ti), hafnium (Hf), and zirconium (Zr). According to some embodiments of the present invention, the high-k dielectric material comprises HfO ₂ , HfON, HfSiON, ZrO ₂ , ZrON, ZrSiON, TiO ₂ , TiON, Al ₂ O ₃ , La ₂ O ₃ , W ₂ O ₃ , CeO ₂ , Y ₂ O ₃ , or Ta ₂ O ₅ , or a combination of two or more thereof. However, other dielectric materials are contemplated and can be used. Precursor gases that can be used in ALD of high-k dielectric materials are described in US Pat. No. 7,777,73, the entire contents of which are incorporated herein.

  The cap layer 104 can be an oxide layer, a nitride layer, or an oxynitride layer, and can include Si and / or one or more of the high-k dielectric materials described above. The cap layer 104 can be deposited, for example, by chemical vapor deposition (CVD) or ALD. In some examples, the thickness of the cap layer 104 can be between 1 nm and 100 nm, between 2 nm and 50 nm, or between 2 nm and 20 nm.

  According to embodiments of the present invention, the film structure shown in FIG. 1B can be patterned to form the patterned film structure schematically shown in FIG. 1C. For example, the patterned dopant layer 106 and the patterned cap layer 108 may be formed using conventional photolithography patterning and etching methods.

Thereafter, the patterned film structure of FIG. 1C has a dopant 110 (eg, B, Al, Ga, In, Tl, N, P, As, Sb, or Bi) from the patterned dopant layer 106 into the substrate 100. It can be diffused and heat treated to form a very shallow dopant region 112 in the substrate 100 under the patterned dopant layer 106 (FIG. 1D). In this heat treatment, the substrate 100 is heated to 100 ° C. and 1000 ° C. in an inert atmosphere (for example, argon (Ar) or nitrogen (N ₂ )) or in an oxidizing atmosphere (for example, oxygen (O ₂ ) or water vapor (H ₂ O)). Heating to a temperature between 10 ° C. for a time between 10 seconds and 10 minutes may be included. Some heat treatment examples include substrate temperatures between 100 ° C. and 500 ° C., substrate temperatures between 200 ° C. and 500 ° C., substrate temperatures between 300 ° C. and 500 ° C., and 400 ° C. and 500 ° C. Including the substrate temperature between. Other examples are substrate temperatures between 500 ° C and 1000 ° C, substrate temperatures between 600 ° C and 1000 ° C, substrate temperatures between 700 ° C and 1000 ° C, and between 800 ° C and 1000 ° C. Includes substrate temperature and substrate temperature between 900 ° C and 1000 ° C. In some examples, the heat treatment may include rapid thermal annealing (RTA), spike annealing, or laser spike annealing.

  In some examples, the thickness of the ultra-shallow dopant region 112 can be between 1 nm and 10 nm, or between 2 nm and 5 nm. However, as one skilled in the art will readily recognize, the lower boundary of the ultra-shallow dopant region 112 in the substrate 100 may be characterized by a gradual decrease rather than a sharp decrease in dopant concentration.

  After the heat treatment and formation of the ultra-shallow dopant region 112, the patterned dopant layer 106 and the patterned cap layer 108 may be removed using a dry etch process or a wet etch process. The resulting structure is shown in FIG. 1E. Further, following the heat treatment, a dry or wet cleaning process may be performed to remove etching residues from the substrate 100.

  According to another embodiment of the invention, following deposition of the dopant layer 102 on the substrate 100, the dopant layer 102 is patterned to form a patterned dopant layer, after which the cap layer is patterned. The deposited dopant layer 106 may be conformally deposited. Thereafter, the film structure may be further processed as shown in FIGS. 1D-1E to form a very shallow dopant region 112 in the substrate 100.

  FIG. 6A shows a schematic cross-sectional view of a raised feature (bump feature) 602 to which an embodiment of the present invention can be applied. This exemplary raised feature 601 is formed on a substrate 600. The material of the substrate 600 and raised features 601 can include one or more of the materials described above with respect to the substrate 100 of FIG. 1A. In one example, the substrate 600 and raised features 601 can contain or consist of the same material (eg, Si). As those skilled in the art will readily recognize, embodiments of the present invention may be applied to other simple or complex raised features on the substrate.

  FIG. 6B shows a schematic cross-sectional view of a conformal dopant layer 602 deposited on the raised features 601 of FIG. 6A. The material of the conformal dopant layer 602 can include one or more of the materials described above with respect to the dopant layer 102 of FIG. 1B. The membrane structure of FIG. 6B can then be processed in the same manner as described in FIGS. 1C-1E. The treatment includes, for example, depositing a cap layer (not shown) on the dopant layer 602, patterning the dopant layer 602 and the cap layer (not shown) as necessary, and patterning the dopant layer (not shown). ) Is heat-treated to diffuse the dopant from the patterned dopant layer (not shown) into the substrate 600 and / or into the raised features 601, and the patterned dopant layer (not shown) and the patterned cap Removing a layer (not shown).

  FIG. 7A shows a schematic cross-sectional view of a recessed shaped part (concave feature) 701 to which an embodiment of the present invention can be applied. This exemplary concave feature 701 is formed in the substrate 700. The material of the substrate 700 may include one or more of the materials described above with respect to the substrate 100 of FIG. 1A. In one example, the substrate 700 can contain Si or consist of Si. As those skilled in the art will readily recognize, embodiments of the present invention may be applied to other simple or complex concave features on the substrate.

  FIG. 7B shows a schematic cross-sectional view of a conformal dopant layer 702 deposited in the concave feature 701 of FIG. 7A. The material of the conformal dopant layer 702 can include one or more of the materials described above with respect to the dopant layer 102 of FIG. 1B. The membrane structure of FIG. 7B can then be processed in the same manner as described in FIGS. 1C-1E. The treatment includes, for example, depositing a cap layer (not shown) on the dopant layer 702, patterning the dopant layer 702 and the cap layer (not shown) as necessary, and patterning the dopant layer (not shown). ) Is heat treated to diffuse the dopant from the patterned dopant layer (not shown) into the substrate 700 of the concave feature 701 part, and the patterned dopant layer (not shown) and the patterned cap layer (not shown). Removing (not shown).

  2A-2E show schematic cross-sectional views of a process flow for forming ultra shallow dopant regions in a substrate according to another embodiment of the present invention. The embodiments schematically shown in FIGS. 2A-2E include materials (eg, composition of substrate, dopant layer, dopant, and cap layer) described above with reference to FIGS. 1A-1E, processing conditions (eg, deposition methods). , And heat treatment conditions), and one or more of the layer thicknesses can be readily used.

  FIG. 2A shows a schematic cross-sectional view of the substrate 200. FIG. 2B shows a patterned mask layer 202 formed on the substrate 200, where a dopant window 203 is defined in the patterned mask layer 202 on the substrate 200. The patterned mask layer 202 can be, for example, a nitride hard mask (eg, a SiN hard mask) that can be formed using conventional photolithography patterning and etching methods.

  FIG. 2C shows a dopant layer 204 deposited by ALD on the patterned mask layer 202 and a cap layer 206 deposited on the dopant layer 204 in direct contact with the substrate 200 in the dopant window 203. Show. The dopant layer 204 can contain an n-type dopant or a p-type dopant. In some examples, the cap layer 206 may be omitted from the film structure of FIGS. 2C-2D.

  Thereafter, the film structure of FIG. 2C is annealed to diffuse the dopant 208 from the dopant layer 204 into the substrate 200 to form a very shallow dopant region 210 in the substrate 200 under the dopant layer 204 in the dopant window 203. Can be done (FIG. 2D). In some examples, the thickness of the ultra-shallow dopant region 210 can be between 1 nm and 10 nm, or between 2 nm and 5 nm. However, as one skilled in the art will readily recognize, the lower boundary of the ultra-shallow dopant region 210 in the substrate 200 may be characterized by a gradual decrease rather than a sharp decrease in dopant concentration.

  After the heat treatment and formation of the ultra-shallow dopant region 210, the patterned mask layer 202, dopant layer 204, and cap layer 206 can be removed using a dry or wet etch process (FIG. 2E). Further, subsequent to the heat treatment, a dry or wet cleaning process may be performed to remove etching residues from the substrate 200.

  3A-3D show schematic cross-sectional views of a process flow for forming ultra shallow dopant regions in a substrate according to yet another embodiment of the present invention. The process flow shown in FIGS. 3A-3D can include channel doping in, for example, planar SOI, FinFET, or ET SOI. This process flow can also be utilized to form self-aligned ultra-shallow source / drain extensions. The embodiments schematically illustrated in FIGS. 3A-3D include materials (eg, substrate, dopant layer, dopant, and cap layer composition) described above with reference to FIGS. 1A-1E, processing conditions (eg, deposition methods). , And heat treatment conditions), and one or more of the layer thicknesses can be readily used.

  FIG. 3A shows a schematic cross-sectional view of a film structure similar to the film structure of FIG. 1C, which is patterned with a patterned first dopant layer 302 in direct contact with the substrate 300. And a patterned cap layer 304 overlying the first dopant layer 302. The patterned first dopant layer 302 can contain an n-type dopant or a p-type dopant.

  FIG. 3B illustrates a second dopant layer 306 that can be conformally deposited directly on the substrate 300 adjacent to the patterned first dopant layer 302 and over the patterned cap layer 304; A second cap layer 308 is shown deposited on the dopant layer 306. In some examples, the second cap layer 308 may be omitted from the film structure of FIGS. 3B-3C. The second dopant layer 306 can contain an n-type dopant or a p-type dopant, provided that the second dopant layer 306 does not contain the same dopant as the patterned first dopant layer 302; Only one of the patterned first dopant layer 302 and second dopant layer 306 contains a p-type dopant, and of the patterned first dopant layer 302 and second dopant layer 306. Only one of these contains an n-type dopant.

  Thereafter, the film structure of FIG. 3B diffuses the first dopant 310 from the patterned first dopant layer 302 into the substrate 300, and the first structure in the substrate 300 under the patterned first dopant layer 302. One ultra-shallow dopant region 312 may be heat treated. This heat treatment also diffuses the second dopant 314 from the second dopant layer 306 into the substrate 300 to form a second ultra-shallow dopant region 316 in the substrate 300 below the second dopant layer 306. (FIG. 3C).

  After this heat treatment, the patterned first dopant layer 302, the patterned cap layer 304, the second dopant layer 306, and the second cap layer 308 may be removed using a dry etching process or a wet etching process. (FIG. 3D). Further, following the heat treatment, a cleaning process may be performed to remove etching residues from the substrate 300.

  4A-4F show schematic cross-sectional views of a process flow for forming ultra-shallow dopant regions in a substrate according to yet another embodiment of the present invention. The process flow shown in FIGS. 4A to 4F can be used, for example, in a process of forming a gate-last type dummy transistor having a self-aligned source / drain extension. The embodiments schematically illustrated in FIGS. 4A-4F include materials (eg, substrate, dopant layer, dopant, and cap layer composition) described above with reference to FIGS. 1A-1E, processing conditions (eg, deposition methods). , And heat treatment conditions), and one or more of the layer thicknesses can be readily used.

  FIG. 4A illustrates a patterned first dopant layer 402 on the substrate 400, a patterned cap layer 404 on the patterned first dopant layer 402, and a patterned dummy on the patterned cap layer 404. A schematic sectional view of a film structure including a gate electrode layer 406 (for example, poly-Si) is shown. The patterned first dopant layer 402 can contain an n-type dopant or a p-type dopant. In some examples, the patterned cap layer 404 may be omitted from the film structure of FIGS. 4A-4F.

FIG. 4B schematically illustrates a first sidewall spacer layer 408 adjacent to the patterned dummy gate electrode layer 406, the patterned cap layer 404, and the patterned first dopant layer 402. FIG. . The first sidewall spacer layer 408 can contain an oxide (eg, SiO ₂ ) or nitride (eg, SiN), deposits a conformal layer covering the film structure of FIG. 4A and the conformal. It can be formed by anisotropically etching the layer.

  FIG. 4C shows a second dopant layer 410 that can be conformally deposited over the film structure shown in FIG. 4B, including in direct contact with the substrate 400 adjacent to the first sidewall spacer layer 408. Show. A second cap layer 420 is conformally deposited on the second dopant layer 410. The second dopant layer 410 can contain an n-type dopant or a p-type dopant, provided that the second dopant layer 410 does not contain the same dopant as the patterned first dopant layer 402; Only one of the patterned first dopant layer 402 and second dopant layer 410 contains a p-type dopant, and of the patterned first dopant layer 402 and second dopant layer 410. Only one of these contains an n-type dopant. In some examples, the second cap layer 420 may be omitted from the film structure of FIGS. 4C-4D.

  Thereafter, the film structure of FIG. 4C diffuses the first dopant 412 from the patterned first dopant layer 402 into the substrate 400, so that the first dopant 412 is diffused into the substrate 400 under the patterned first dopant layer 402. One ultra-shallow dopant region 414 may be heat treated. This heat treatment also diffuses the second dopant 416 from the second dopant layer 410 into the substrate 400 and causes the second dopant 416 to be in direct contact with the substrate 400 and into the substrate 400 under the second dopant layer 410. Ultra shallow dopant regions 418 are formed (FIG. 4D).

  After this heat treatment, the film structure schematically shown in FIG. 4E can be formed by removing the second dopant layer 410 and the second cap layer 420 by using a dry etching process or a wet etching process. Further, following the heat treatment, a cleaning process may be performed to remove etching residues from the substrate 400.

Next, a second sidewall spacer layer 422 may be formed adjacent to the first sidewall spacer layer 408. This is schematically shown in FIG. 4F. The second sidewall spacer layer 422 can contain an oxide (eg, SiO ₂ ) or nitride (eg, SiN), deposits a conformal layer that covers the film structure, and makes the conformal layer different. It can be formed by isotropic etching.

  Thereafter, the membrane structure shown in FIG. 4F can be further processed. Further processing may include forming additional source / drain extensions or performing a replacement gate process including ion implantation and liner deposition.

  5A-5E show schematic cross-sectional views of a process flow for forming a very shallow dopant region in a substrate according to another embodiment of the present invention. The process flow shown in FIGS. 5A-5E can be utilized, for example, in the process of forming a spacer-defined PiN junction (junction) for a band-to-band tunnel transistor. The embodiments schematically illustrated in FIGS. 5A-5E include materials (eg, substrate, dopant layer, dopant, and cap layer composition) described above with reference to FIGS. 1A-1E, processing conditions (eg, deposition methods). , And heat treatment conditions), and one or more of the layer thicknesses can be readily used.

FIG. 5A is a schematic of a film structure that includes a patterned layer 502 (eg, oxide, nitride, or oxynitride) on the substrate 500 and a patterned cap layer 504 on the patterned layer 502. A cross-sectional view is shown. FIG. 5A further shows a sidewall spacer layer 506 adjacent to the substrate 500, patterned cap layer 504, and patterned layer 502. The sidewall spacer layer 506 can contain an oxide (eg, SiO ₂ ) or nitride (eg, SiN) and is formed by depositing a conformal layer and anisotropically etching the conformal layer. Can be done.

  FIG. 5B shows a first dopant layer 508 containing a first dopant deposited by ALD in direct contact with the substrate 500 adjacent to the sidewall spacer layer 506 and deposited on the first dopant layer 508. Further, a schematic cross-sectional view with the first cap layer 510 (for example, an oxide layer) is shown. By planarizing the obtained film structure (for example, by chemical mechanical polishing CMP), the film structure shown in FIG. 5B can be formed.

  Thereafter, the patterned layer 502 and the patterned cap layer 504 may be removed using a dry or wet etch process. A second dopant layer 512 containing a second dopant is then deposited in direct contact with the substrate 500 and a second cap layer 514 (eg, an oxide layer) is deposited on the second dopant layer 512. Can be deposited. By planarizing (for example, by CMP) the obtained film structure, the planarized film structure shown in FIG. 5C can be formed. The first dopant layer 508 and the second dopant layer 512 can contain an n-type dopant or a p-type dopant, provided that the first dopant layer 508 and the second dopant layer 512 have the same dopant. No one, only one of the first dopant layer 508 and the second dopant layer 512 contains a p-type dopant, and one of the first dopant layer 508 and the second dopant layer 512 Only contain an n-type dopant.

  Thereafter, the film structure of FIG. 5C diffuses the first dopant 516 from the first dopant layer 508 into the substrate 500 to provide a first ultra-shallow dopant region in the substrate 500 under the first dopant layer 508. Heat treatment can be performed to form 518. This heat treatment also diffuses the second dopant 520 from the second dopant layer 512 into the substrate 500 to form a second ultra-shallow dopant region 522 in the substrate 500 under the second dopant layer 512. (FIG. 5D). FIG. 5E shows first and second ultra-shallow dopant regions 518 and 522 in the substrate 500 according to spacer definitions.

  An exemplary method for depositing a dopant layer on a substrate is then described in accordance with various embodiments of the present invention.

According to one embodiment, the boron dopant layer may include boron oxide, boron nitride, or boron oxynitride. According to other embodiments, the boron dopant layer can contain or consist of a boron-doped high-k material in the form of an oxide layer, a nitride layer, or an oxynitride layer. . In one example, a) supplying a substrate into a processing chamber configured to perform an ALD process, b) exposing the substrate to a gaseous boronamide or organoborane precursor, c) purging / evacuating the processing chamber, d) exposing the substrate to a reactive gas containing H ₂ O, O ₂ , O ₃ or combinations thereof, e) purging / evacuating the processing chamber, and f) so that the boron oxide dopant layer has the desired thickness. By repeating steps b) -e) several times until the boron oxide dopant layer can be deposited by ALD. According to other embodiments, a boron nitride dopant layer is deposited using a reaction gas containing NH ₃ in step d), or 1) H ₂ O, O ₂ or O ₃ in step d). A boron oxynitride dopant layer may be deposited using NH ₃ or 2) NO, NO ₂ or N ₂ O and optionally one or more of H ₂ O, O ₂ , O ₃ and NH _3. .

According to an embodiment of the present invention, the boron amide may comprise a boron compound in the form of L _n B (NR ¹ R ² ) ₃ . However, L is a neutral Lewis base, n is 0 or 1, and each of R ¹ and R ² is an alkyl group, an aryl group, a fluoroalkyl group, a fluoroaryl group, an alkoxyalkyl group, and an aminoalkyl group. Can be selected. Examples of boron amides include B (NMe ₂ ) ₃ , (Me ₃ ) B (NMe ₂ ) ₃ , and B [N (CF ₃ ) ₂ ] ₃ . According to an embodiment of the present invention, organoborane _may include a boron compound in the form of ^{L n BR 1 R 2 R 3} . Where L is a neutral Lewis base, n is 0 or 1, and each of R ¹ , R ² and R ³ is an alkyl group, an aryl group, a fluoroalkyl group, a fluoroaryl group, an alkoxyalkyl group, and It can be selected from aminoalkyl groups. Examples of boron amide include BMe ₃ , (Me ₃ N) BMe ₃ , B (CF ₃ ) ₃ , and (Me ₃ N) B (C ₆ F ₃ ).

According to one embodiment, the arsenic dopant layer may comprise arsenic oxide, arsenic nitride, or arsenic oxynitride. According to other embodiments, the arsenic dopant layer can comprise or consist of an arsenic doped high-k material in the form of an oxide layer, a nitride layer, or an oxynitride layer. it can. In one example, a) a substrate is supplied into a processing chamber configured to perform an ALD process, b) the substrate is exposed to a gas phase precursor containing arsenic, c) the processing chamber is purged / evacuated, d B) —exposing the substrate to H ₂ O, O ₂ , O ₃ or a combination thereof, e) purging / evacuating the processing chamber, and f) the arsenic oxide dopant layer to have the desired thickness. By repeating e) several times, an arsenic oxide dopant layer can be deposited by ALD. According to another embodiment, an arsenic nitride dopant layer is deposited using NH ₃ in step d), or 1) H ₂ O, O ₂ or O ₃ and NH ₃ or 2 in step d). ) An arsenic oxynitride dopant layer may be deposited using NO, NO ₂ or N ₂ O and optionally one or more of H ₂ O, O ₂ , O ₃ and NH ₃ . According to some embodiments of the invention, the gas phase precursor containing arsenic can comprise an arsenic halide, such as AsCl ₃ , AsBr _3, or AsI ₃ .

According to one embodiment, the phosphorus dopant layer may include phosphorus oxide, phosphorus nitride, or phosphorus oxynitride. According to other embodiments, the phosphorus dopant layer may contain or consist of a phosphorus-doped high-k material in the form of an oxide layer, a nitride layer, or an oxynitride layer. . In one example, a) supplying a substrate into a processing chamber configured to perform an ALD process, b) exposing the substrate to a vapor phase precursor containing phosphorus, c) purging / evacuating the processing chamber, d ) Exposing the substrate to a reactive gas containing H ₂ O, O ₂ , O _3, or combinations thereof, e) purging / evacuating the processing chamber, and f) the phosphorous oxide dopant layer has the desired thickness. By repeating steps b) -e) until several times, a phosphorous oxide dopant layer can be deposited by ALD. According to another embodiment, a phosphorous nitride dopant layer is deposited using a reaction gas containing NH ₃ in step d), or 1) H ₂ O, O ₂ or O ₃ in step d). A phosphorous oxynitride dopant layer may be deposited using NH ₃ or 2) NO, NO ₂ or N ₂ O and optionally one or more of H ₂ O, O ₂ , O ₃ and NH ₃ . According to some embodiments of the invention, the gas phase precursor containing phosphorus is [(CH ₃ ) ₂ N] ₃ PO, P (CH ₃ ) ₃ , PH ₃ , OP (C ₆ H ₅ ). _{3, OPCl 3, PCl 3,} PBr 3, may include _{[(CH 3) 2 N]} 3 P, P (C 4 H 9) 3.

  A number of embodiments of ultra-shallow dopant region formation by solid phase diffusion from the dopant layer to the substrate layer have been described. The foregoing descriptions of the embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. The specification and claims include terms that are used for descriptive purposes only and should not be construed as limiting. For example, the term “on” herein (including the claims) does not require that the film on the substrate “on” be directly on and in direct contact with the substrate; A second film or other structure may be present between the substrate and the substrate.

  Many modifications and variations are possible under the above teachings, as will be appreciated by those skilled in the art. Various equivalent combinations and substitutions of the various components shown will be recognized by those skilled in the art. Accordingly, the scope of the invention is not limited by this detailed description, but only by the appended claims.

  This application claims the priority of US Patent Application No. 13/077721 and US Patent Application No. 13/077678, the entire contents of which are hereby incorporated by reference.

Claims (25)

A method of forming a very shallow boron (B) dopant region in a substrate, comprising:
A boron dopant layer is deposited by direct contact with the substrate by atomic layer deposition (ALD), and the boron dopant layer is formed by alternately exposing the boron amide precursor to gas and reacting with the reactant gas. Having an oxide, nitride or oxynitride,
Patterning the boron dopant layer and diffusing boron from the patterned boron dopant layer into the substrate by a heat treatment to form the ultra-shallow boron dopant region in the substrate;
A method that has that. Removing the patterned boron dopant layer from the substrate;
The method of claim 1 further comprising: Depositing a cap layer over the boron dopant layer or over the patterned boron dopant layer;
The method of claim 1 further comprising: The method of claim 1, wherein the boron dopant layer comprises an oxide and the reactive gas comprises H ₂ O, O _2, or O ₃ , or a combination of two or more thereof. The method of claim 1, wherein the boron dopant layer comprises nitride and the reaction gas comprises NH ₃ . The boron dopant layer has an oxynitride, and the reaction gas includes a) H ₂ O, O ₂ or O ₃ and NH ₃ , or b) NO, NO ₂ or N ₂ O and as required. The method of claim 1, comprising one or more of all H ₂ O, O ₂ , O ₃ and NH ₃ .   The method of claim 1, wherein the boron dopant layer has a thickness of 4 nm or less.   2. The substrate of claim 1, wherein the substrate includes a patterned mask layer defining a dopant window on the substrate, the boron dopant layer being deposited in direct contact with the substrate in the dopant window. The method described. The method of claim 1, wherein the substrate comprises Si, Ge, In, Ga, As, Sb, GaAs, InGaAs, InGaSb, or Si _x Ge _1-x , where 0 <x <1. A method of forming a very shallow boron (B) dopant region in a substrate, comprising:
Atomic layer deposition (ALD) deposits a boron dopant layer in direct contact with the substrate , wherein the boron dopant layer alternates between gas exposure of the boron amide precursor or organoboron precursor and gas exposure of the reactant gas. a nitride compound or an oxynitride which is formed by performing a,
Patterning the previous SL boron dopant layer, and by diffusing boron by heat treatment in the substrate from the patterned boron dopant layer to form the ultra-shallow boron dopant region in said substrate,
A method that has that. The method of claim 10, wherein the boron dopant layer comprises nitride and the reaction gas comprises NH ₃ . The boron dopant layer has an oxynitride, and the reaction gas includes a) H ₂ O, O ₂ or O ₃ and NH ₃ , or b) NO, NO ₂ or N ₂ O and as required. of _H 2 _{O Te,} and a O 2, _{O 3} and one or more of the NH _3, the method of claim 10.   11. The substrate of claim 10, wherein the substrate includes a patterned mask layer that defines a dopant window on the substrate, the boron dopant layer being deposited in direct contact with the substrate in the dopant window. The method described. A method of forming a very shallow boron (B) dopant region, comprising:
Providing a substrate including raised or recessed features;
A boron dopant layer is conformally deposited in direct contact with the raised feature or the inner surface of the concave feature, the boron dopant layer comprising a gas exposure of a boron amide precursor or an organic boron precursor and a gas exposure of a reactive gas. Having oxides, nitrides or oxynitrides deposited by atomic layer deposition (ALD) using alternating and
In the raised features by patterning the boron dopant layer and diffusing boron by heat treatment from the patterned boron dopant layer into the raised features or into the substrate in the recessed features, Or forming the ultra-shallow boron dopant region in the concave feature;
A method that has that. Removing the patterned boron dopant layer from the substrate;
15. The method of claim 14 , further comprising: The method of claim 14 , wherein the boron dopant layer comprises an oxide and the reactive gas comprises H ₂ O, O _2, or O ₃ , or a combination of two or more thereof. The method of claim 14 , wherein the boron dopant layer comprises nitride and the reaction gas comprises NH ₃ . The boron dopant layer has an oxynitride, and the reaction gas includes a) H ₂ O, O ₂ or O ₃ and NH ₃ , or b) NO, NO ₂ or N ₂ O and as required. of _H 2 _{O Te,} and a O 2, _{O 3} and one or more of the NH _3, the method of claim 14. A method of forming a very shallow dopant region in a substrate,
Depositing a first dopant layer containing a first dopant by atomic layer deposition (ALD) in direct contact with the substrate;
Patterning the first dopant layer;
A second dopant layer containing a second dopant is deposited by ALD in direct contact with the substrate adjacent to the patterned first dopant layer, the first and second dopant layers being , Oxide, nitride or oxynitride, and the first and second dopant layers contain an n-type dopant or a p-type dopant, provided that the first dopant layer and the second dopant The n-type dopant and the p-type dopant are boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), and nitrogen (N). , Phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and by heat treatment, the first dopant is introduced into the substrate from the first dopant layer. Diffusing the punt to form a first ultra-shallow dopant region in the substrate, and by the heat treatment, diffusing the second dopant from the second dopant layer into the substrate; Forming a second ultra-shallow dopant region;
A method that has that. Removing the patterned first dopant layer and the second dopant layer from the substrate;
20. The method of claim 19 , further comprising: Forming a cap layer on the patterned first dopant layer;
20. The method of claim 19 , further comprising: A patterned cap layer over the patterned first dopant layer, a patterned dummy gate electrode layer over the patterned cap layer, and the patterned dummy gate electrode layer; Forming a first sidewall spacer adjacent to the cap layer and the patterned first dopant layer;
20. The method of claim 19 , further comprising: After the diffusion, removing the second dopant layer and forming a second sidewall spacer adjacent to the first sidewall spacer and the second ultra-shallow dopant region;
23. The method of claim 22 , further comprising: A method of forming a very shallow dopant region in a substrate,
A patterned layer on the substrate, a patterned cap layer on the patterned layer, and a sidewall spacer adjacent to the substrate, the patterned cap layer, and the patterned layer Form the
Depositing a first dopant layer containing a first dopant by atomic layer growth (ALD) in direct contact with the substrate adjacent to the sidewall spacer;
Depositing a first cap layer on the first dopant layer;
Planarizing the first cap layer and the first dopant layer;
Removing the patterned cap layer and the patterned layer;
Depositing a second dopant layer containing a second dopant in direct contact with the substrate adjacent to the sidewall spacer;
A second cap layer is deposited on the second dopant layer, and the first and second dopant layers comprise oxide, nitride, or oxynitride, and the first and second dopants The layer contains an n-type dopant or a p-type dopant, provided that the first dopant layer and the second dopant layer do not contain the same dopant, and the n-type dopant and the p-type dopant are boron. Selected from (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi) And heat-treating the first dopant from the first dopant layer into the substrate to form a first ultra-shallow dopant region in the substrate; and Diffusing the second dopant into the substrate from the second dopant layer to form a second ultra-shallow dopant region in the substrate;
A method that has that. Planarizing the second cap layer and the second dopant layer;
25. The method of claim 24 , further comprising:

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