JP2010123660A - Insulated gate-type semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly and selectively control a work function of a tantalum carbide film in an insulated gate-type semiconductor device, related to a method of manufacturing the insulated gate-type semiconductor device. <P>SOLUTION: The method of manufacturing the insulated gate-type semiconductor device has steps of: forming a gate insulating film on a semiconductor substrate; carrying out the film formation of the tantalum carbide film on the gate insulating film; and performing hydrogen plasma treatment after forming a mask pattern having an aperture for exposing a part of the tantalum carbide film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device and a manufacturing method thereof, and more particularly, an insulated gate field effect type such as a MISFET using a high dielectric constant film as a gate insulating film and a tantalum carbide film as a gate electrode. The present invention relates to a configuration for appropriately setting a threshold voltage of a transistor.

Since a conventional MIS type semiconductor device employs a structure using complementary transistors, it is necessary to form an n channel MISFET and a p channel MISFET on the same semiconductor substrate. Further, in order for each of the n-channel MISFET and the p-channel MISFET to have an appropriate threshold voltage _Vth , it is necessary that each gate electrode has an appropriate work function.

  Therefore, conventionally, polysilicon is used for the gate electrode, and arsenic or the like is implanted into the n-channel MISFET gate electrode and boron or the like is implanted into the gate electrode of the p-channel MISFET by a doping technique by ion implantation. Controlled.

  However, as miniaturization progresses in order to improve the performance of semiconductor devices, there are the following problems due to the use of polysilicon for the gate electrode. First, a depletion layer is generated at the interface of polysilicon gate insulation film during the operation of the MIS type semiconductor device. There is a problem that the capacity during operation cannot be obtained sufficiently.

  Second, a high dielectric material such as hafnium oxide or hafnium silicate is used for the gate insulating film in order to suppress the gate leakage current while increasing the electric capacity of the gate insulating film due to miniaturization. However, in the combination of this material and the polysilicon gate electrode, there is a problem that the threshold value becomes large due to a phenomenon called Fermi level pinning and the occurrence of a dipole at the interface, and good operating characteristics cannot be obtained.

  In order to solve these problems, research and development are underway to use a metal material for the gate electrode. When a metal material is used for the gate electrode, a metal film for controlling a work function is formed on the gate insulating film. Since materials having different work functions are required in the n-type region and the p-type region, after forming one metal material, the metal material in an unnecessary region is removed by etching using a patterning technique, and the other metal It is necessary to deposit a material (for example, refer to Patent Document 1).

  FIG. 11 is an explanatory diagram of a manufacturing process of a conventional metal gate CMOSFET. As shown in FIG. 11A, after an element isolation region 82 having an STI (Shallow Trench Isolation) structure is formed on a silicon substrate 81, an n-type well region 83 and a p-type well region 84 are formed.

  Next, after forming a gate insulating film 85 made of a high dielectric constant film, a (111) -rich TaC film 86 is formed by alternately supplying a Ta source and a C source. The work function of the (111) -rich TaC film 86 is larger than that of the (200) -rich TaC film described later.

  Next, as shown in FIG. 11B, after depositing the SiN film, the SiN film on the p-type well region 84 is removed, and the remaining SiN film pattern 87 is used as a mask for TaC on the p-type well region 84. The film 86 is selectively removed.

  Next, as shown in FIG. 11C, a (200) -rich TaC film 88 is formed by simultaneously supplying a Ta source and a C source. The work function of the (200) -rich TaC film 88 is, for example, about 4.18 eV, which is smaller than the work function of 4.8 eV of the (111) -rich TaC film 86 described above.

  Next, as shown in FIG. 11 (d), the TaC film 88 deposited on the SiN film pattern 87 is lifted off by removing the SiN film pattern 87. As a result, the (200) -rich TaC film 88 having a work function of, for example, about 4.18 eV is selectively formed only on the p-type well region 84.

  Thereafter, an n-channel formed in the p-type well region 84 through a normal gate structure patterning step, impurity introduction step, contact electrode formation step, interlayer insulating film formation step, and extraction electrode formation step. A CMOSFET comprising a type MOSFET and a p-channel type MOSFET formed in the n-type well region 83 is formed.

  FIG. 12 is an explanatory diagram of another conventional metal gate CMOSFET manufacturing process. As shown in FIG. 11A, after an element isolation region 82 having an STI structure is formed on a silicon substrate 81, an n-type well region 83 and a p-type well region 84 are formed. Next, after forming a gate insulating film 85 made of a high dielectric constant film, an SiN film is deposited, and the SiN film on the n-type well region 83 is removed to form a mask made of the SiN film pattern 89.

  Next, as shown in FIG. 12B, a (111) -rich TaC film 90 is formed by alternately supplying a Ta source and a C source.

  Next, as shown in FIG. 12C, the TaC film 90 deposited on the SiN film pattern 89 is lifted off by removing the SiN film pattern 89. As a result, the (111) -rich TaC film 90 is selectively formed only on the n-type well region 83.

Then, as shown in FIG. 12D, a (200) -rich TaC film 91 is formed on the entire surface by simultaneously supplying a Ta source and a C source. Thereafter, an n-channel formed in the p-type well region 84 through a normal gate structure patterning step, impurity introduction step, contact electrode formation step, interlayer insulating film formation step, and extraction electrode formation step. A CMOSFET composed of a p-channel MOSFET formed in the n-type well and the n-type well region 83 is formed.
JP 2007-165414 A

  However, in the above-described manufacturing process of the metal gate CMOSFET, since the etching action is exerted on the gate insulating film in the TaC film removing process or the SiN film pattern forming process and removing process, the reliability of the gate insulating film is adversely affected. there is a possibility.

  In addition, since the work function is controlled by controlling the crystal orientation in the TaC film forming process, the work function becomes a specific value depending on the crystal structure and cannot be set to an arbitrary value. is there. In this case, in order to accurately control the ratio of the (111) phase to the (200) phase to an arbitrary value even though the work function can be controlled by the ratio of the (111) phase to the (200) phase. However, there is a problem that it is necessary to manage the film forming process with high accuracy and the reproducibility is poor.

Furthermore, in any case, it is only possible to obtain a configuration in which one is a p-channel type and the other is an n-channel type, and MOSFETs of the same conductivity type having different _Vths with gate electrodes having different work functions are obtained. There is also a problem that it cannot be formed selectively.

  In order to solve such a problem, it is conceivable to control the work function by ion-implanting carbon into tantalum. However, in this case, the implanted carbon has a distribution with a spread in the depth direction. Therefore, if sufficient carbon is implanted near the interface with the gate insulating film, the carbon is not even introduced into the gate insulating film. As a result, it is difficult to keep carbon only in the gate electrode. Further, there is a problem that the gate insulating film is damaged by the ion implantation.

  Therefore, an object of the present invention is to appropriately set the work function of a tantalum carbide film without damaging the gate insulating film.

  From one aspect of the present invention, a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, and a first tantalum carbide having a first carbon concentration formed on the first gate insulating film A first insulated gate field effect transistor having a first gate electrode including a film, a second gate insulating film formed on the semiconductor substrate, and formed on the second gate insulating film, There is provided a semiconductor device having a second insulated gate field effect transistor having a second gate electrode including a second tantalum carbide film having a second carbon concentration different from the first carbon concentration.

  From another viewpoint of the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of forming a tantalum carbide film on the gate insulating film, and a portion of the tantalum carbide film are exposed. A method for manufacturing a semiconductor device is provided, which includes a step of performing a hydrogen plasma treatment after forming a mask pattern having an opening.

According to the disclosed insulated gate semiconductor device and its manufacturing method, by using hydrogen plasma treatment, the work function is appropriately controlled using a conductive material called tantalum carbide in a simple process without damaging the gate insulating film. The gate electrode can be formed. Accordingly, it is possible to improve the reliability of the complementary semiconductor device and the insulated gate semiconductor device that constitutes the multi-value logic circuit including the transistors having high _Vth .

  Here, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is an explanatory diagram of the manufacturing process of the metal gate MISFET according to the embodiment of the present invention. As shown in FIG. 1A, first, for example, an element isolation region 12 having an STI structure is formed on a silicon substrate 11, and then an n-type first well region 13 and a second well region 14 are formed.

Next, after forming a gate insulating film 15 made of a high dielectric constant film such as HfO ₂ or HfSiON, a TaC film 16 is formed with a work function of about 4.8 eV, for example. The TaC film 16 may be, for example, a (111) -rich TaC film by alternately supplying a Ta source and a C source. The film thickness of the TaC film 16 is set to 3 to 15 nm, for example, 5 nm so that C can be easily separated in the next hydrogen plasma processing step.

Next, as shown in FIG. 1B, after the SiN film is deposited, the SiN film pattern 17 remaining after removing the SiN film on the second well region 14 is used as a mask. Next, by performing a heat treatment in the hydrogen plasma 18, C in the TaC film 16 is released and converted into a C-poor TaC film 19. By exposing the TaC film 16 to the hydrogen plasma 18, H ⁺ enters the TaC film 16 and combines with carbon, desorbs from the TaC film 16 as hydrocarbon (C _x H _y ), and reduces carbon in the film. As a result, the film is converted into a C-poor TaC film 19. For example, C is reduced so that it becomes 1/3 or less of Ta.

  TaC has a work function of about 4.8 eV and is suitable as a gate electrode material for a p-channel semiconductor device. On the other hand, by reducing C from TaC, the work function approaches 4.0 eV possessed by Ta, which is suitable as a gate electrode material for an n-channel semiconductor device. The degree of reduction of C depends on processing conditions such as processing time. When the processing is performed at a high temperature for a long time, in the case of a thin TaC film of about 5 nm, C is almost detached and the Ta is very low. Close to.

As conditions for the hydrogen plasma treatment step in this case, the substrate temperature may be 20 to 200 ° C. under a plasma atmosphere pressure of 3 Pa, and the treatment may be performed for about 5 seconds to 2 minutes depending on the film thickness of the TaC film 16. The applied power depends on the configuration of the plasma processing apparatus. For example, in the case of a parallel plate type plasma processing apparatus in which parallel plate electrodes having an area of 800 cm ² are opposed to each other at an interval of 5 cm, power of about 1000 W is applied. .

  Next, as shown in FIG. 1C, by removing the SiN film pattern 17, a TaC film 19 having a low C concentration and a low work function is formed on the second well region 14, and an n-type film is formed. A TaC film 16 having a high C concentration and a high work function is selectively formed on the first well region 13.

  Next, as shown in FIG. 1D, a conductive film 20 to be an upper gate electrode such as polycrystalline silicon or W is formed on the entire surface, and then patterned to form a gate structure. Thereafter, a p-channel MISFET is formed in the n-type first well region 13 through a normal impurity introduction step, a contact electrode formation step, an interlayer insulating film formation step, and an extraction electrode formation step. It is formed.

On the other hand, when the second well region 14 is p-type, an n-channel type MISFET is formed and constitutes a complementary transistor together with the p-type MISFET. When the second well region 14 is n-type, a p-type channel MISFET having a _Vth higher than that of the p-channel MISFET formed in the first well region 13 is formed.

  As described above, in the embodiment of the present invention, the work function of the TaC film is controlled by a simple process in which the hydrogen plasma treatment is performed on the TaC film formed in a single film forming process without performing the etching process. is doing. Therefore, since the etching action does not reach the gate insulating film, the reliability is not deteriorated.

In the case of forming the n-channel type MISFET of mutually different V _th on the same semiconductor substrate, the first well region and the second well region and n-type both the first hydrogen plasma treatment step After that, the second hydrogen plasma treatment may be performed by removing the mask made of the SiN film.

  Alternatively, in the first film formation step, a Ta source and a C source are simultaneously supplied to form a (200) -rich TaC film having a small work function suitable for an n-channel MISFET, and this TaC film is selectively hydrogenated. Plasma treatment may be performed. In this case, the work function is reduced by reducing the C concentration of the TaC film in the portion subjected to the hydrogen plasma treatment.

Based on the above, the manufacturing process of the complementary semiconductor device according to the first embodiment of the present invention will be described next with reference to FIGS. First, as shown in FIG. 2A, for example, by performing HCl oxidation at 850 ° C., a SiO ₂ film 22 having a thickness of, eg, 10 nm is formed on the surface of the p-type silicon substrate 21, and then the pressure is reduced. A SiN film 23 having a thickness of, for example, 100 nm is deposited by chemical vapor deposition (LPCVD).

  Next, as shown in FIG. 2B, a resist pattern (not shown) that leaves the SiN film 23 only in the element formation region is provided. The SiN film pattern 24 is formed by performing dry etching using this resist pattern as a mask.

  Next, as shown in FIG. 2C, after removing the resist pattern, by performing dry etching using the SiN film pattern 24 as a mask, an element isolation groove 25 having a depth of, for example, 200 nm is formed.

Next, as shown in FIG. 2D, by performing HCl oxidation again at 850 ° C., a liner oxide film (not shown) having a thickness of, for example, 10 nm is formed on the surface of the element isolation trench 25. For example, an HDP-SiO ₂ film having a thickness of, for example, 500 nm is deposited using a high-density plasma CVD method (HDP-CVD method).

Then, by removing the HDP-SiO ₂ film up to the SiN film pattern 24 and the SiN film pattern 24 as a stopper is exposed by using CMP (Chemical Mechanical Polishing) method, fill the device isolation trench 25 by HDP-SiO ₂ film . The buried HDP-SiO ₂ film and liner oxide film become the buried oxide film 26.

Then, as shown in FIG. 3 (e), after the SiN film pattern 24 was removed using hot phosphoric acid to remove the SiO ₂ film 22 by HF. In the removal process of the SiO ₂ film 22, the surface of the buried oxide film 26 is also etched, so that the surface becomes flat.

  Next, as shown in FIG. 3F, a sacrificial oxide film for ion implantation having a thickness of, for example, 10 nm is formed on the surface of the p-type silicon substrate 21. Next, after providing a resist mask so as to cover one element formation region, P ions are ion-implanted with high acceleration energy to form an ion implantation region for well formation at a deep position, and As ions with low acceleration energy. Then, an ion implantation region for forming a channel dope region (both not shown) is formed on the surface side.

  Next, after removing the resist mask, a resist mask is provided so as to cover the other element formation region, and then B ions are implanted with high acceleration energy to form an ion implantation region for forming a well at a deep position. , B ions are implanted at a low acceleration energy to form an ion implantation region (not shown) for forming a channel dope region on the surface side.

  Next, after removing the resist pattern, a heat treatment for activating the implanted ions is performed to form an n-type well region 27 in one element formation region, and a channel dope region (not shown) is formed on the surface. . At the same time, a p-type well region 28 is formed in the other element formation region, and a channel doped region (not shown) is formed on the surface, and then the sacrificial oxide film is removed.

Next, as shown in FIG. 3 (g), after performing the SC2 cleaning process using HCl + H ₂ O ₂ , the thickness is increased over the entire surface using the ALCVD method in which HfCl ₄ and H ₂ O are alternately supplied. For example, a 3 nm HfO ₂ film 29 is formed. Next, a TaC film 30 having a thickness of, for example, 5 nm is formed by performing sputtering by alternately supplying a Ta source and a C source.

Next, as shown in FIG. 3H, a SiN film having a thickness of, for example, 20 nm is deposited by CVD, and then a resist pattern 31 is provided so as to cover the n-type well region 27. . Next, the SiN film exposed by using the resist pattern 31 as a mask is removed by RIE (reactive ion etching) in an atmosphere containing CHF ₃ and Ar to form a SiN film pattern 32.

  Next, as shown in FIG. 4I, after removing the resist pattern 31, hydrogen plasma treatment is performed using the SiN film pattern 32 as a mask. By this hydrogen plasma treatment, C is released from the TaC film on the p-type well region 28 to form a TaC film 33 having a low carbon concentration and a low work function. In this hydrogen plasma treatment, the substrate temperature is set to 20 ° C., for example, and the treatment is performed for 30 seconds under a plasma pressure of 3 Pa.

  Next, as shown in FIG. 4J, after removing the resist pattern 31, a polycrystalline silicon film 34 having a thickness of, for example, 100 nm is deposited on the entire surface by CVD.

Next, as shown in FIG. 4K, the polycrystalline silicon film 34, the TaC films 30, 33, and the HfO ₂ film 29 are patterned to form a gate structure.

  Next, as shown in FIG. 4L, after covering the n-type well region 27 side with a resist pattern 35, As ions are implanted with low acceleration energy using the gate structure on the p-type well region 28 side as a mask. An n-type extension region 36 is formed.

  Next, as shown in FIG. 5M, after removing the resist pattern 35, the p-type well region 28 side is newly covered with the resist pattern 37, and the gate structure on the n-type well region 27 side is used as a mask. B ions are implanted with low acceleration energy to form the p-type extension region 38.

Next, as shown in FIG. 5 (n), after removing the resist pattern 37, a thick SiO ₂ film is deposited on the entire surface by LPCVD, and then anisotropic etching is performed to form the sidewalls 39, 40. Form.

  Next, as shown in FIG. 5 (o), the p-type well region 28 side is covered with a resist pattern 41, and then B ions are formed with high acceleration energy using the gate structure and sidewalls 40 on the n-type well region 27 side as a mask. A p-type source / drain region 42 is formed by ion implantation. At this time, the polycrystalline silicon film 34 constituting the gate structure on the n-type well region 27 side is doped with B to become a p-type polycrystalline silicon film 43.

  Next, as shown in FIG. 5 (p), after removing the resist pattern 41, the n-type well region 27 side is newly covered with the resist pattern 44, and then the As ions are increased using the gate structure and the sidewall 39 as a mask. N-type source / drain regions 45 are formed by ion implantation with acceleration energy. At this time, the polycrystalline silicon film 34 constituting the gate structure on the p-type well region 28 side is doped with As to form an n-type polycrystalline silicon film 46.

  Next, as shown in FIG. 6 (q), after removing the resist pattern 44, heat treatment for activating the implanted ions is performed. Next, a Co film 47 having a thickness of, for example, 10 nm is deposited on the entire surface by sputtering.

  Next, as shown in FIG. 6 (r), heat treatment is performed to react the Co film 47 with the n-type polycrystalline silicon film 46 and the p-type polycrystalline silicon film 43 to form Co silicide layers 48 and 49. To do. At the same time, the Co film 47 is reacted with the n-type source / drain region 45 and the p-type source / drain region 42 to form Co silicide layers 50 and 51 to be source / drain electrodes.

The heat treatment conditions at this time are, for example, rapid thermal annealing (RTA) in a N ₂ atmosphere at a temperature of 400 to 600 ° C., for example, 500 ° C., for 10 to 900 seconds, for example, 30 seconds. To do.

Next, as shown in FIG. 6 (s), the unreacted Co film 47 is removed by etching with a mixed solution of H ₂ SO ₄ : H ₂ O ₂ = 3: 1 for 20 minutes, and then the entire surface is made of BPSG. An interlayer insulating film 52 is formed by depositing a film and polishing and planarizing by a CMP method. Thereafter, in order to form a necessary wiring structure, a complementary semiconductor device is completed by repeating a via forming process, a wiring forming process, and an interlayer insulating film forming process.

As described above, in Example 1 of the present invention, a TaC film having a high work function is formed, and then selectively exposed to a hydrogen plasma atmosphere, whereby the C concentration in the TaC film is suitable for an n-channel MISFET. Reduced to work function. Accordingly, the _Vth of each MISFET can be controlled with high accuracy, and the gate insulating film is not damaged due to etching damage or ion implantation, so that the reliability of the semiconductor device is not lowered.

  Next, with reference to FIGS. 7 to 8, the manufacturing process of the p-channel MISFET according to the second embodiment of the present invention will be described. First, as shown in FIG. 7A, n-type well regions 27 and 53 that are separated from each other by a buried oxide film 26 are formed on a p-type silicon substrate 21 through substantially the same steps as in the first embodiment.

Next, after performing an SC2 cleaning process using HCl + H ₂ O ₂ , an HfO ₂ film 29 having a thickness of, for example, 3 nm is formed on the entire surface by using an ALCVD method in which HfCl ₄ and H ₂ O are alternately supplied. To do. Next, a TaC film 30 having a thickness of, for example, 5 nm is formed by performing sputtering by alternately supplying a Ta source and a C source.

Next, as shown in FIG. 7B, after a SiN film having a thickness of, for example, 20 nm is deposited by using the CVD method, a resist pattern 31 is provided so as to cover the n-type well region 27. . Next, the SiN film exposed by using the resist pattern 31 as a mask is removed by etching by RIE in an atmosphere InAlAs containing CHF ₃ and Ar to form a SiN film pattern 32.

  Next, as shown in FIG. 7C, after removing the resist pattern 31, hydrogen plasma treatment is performed using the SiN film pattern 32 as a mask. By this hydrogen plasma treatment, C is released from the TaC film on the n-type well region 51, and a TaC film 54 having a relatively low carbon concentration and a low work function is obtained.

  Next, as shown in FIG. 7D, after the SiN film pattern 32 is removed, a polycrystalline silicon film 34 having a thickness of, for example, 100 nm is deposited on the entire surface by CVD.

Next, as shown in FIG. 8E, the polycrystalline silicon film 34, the TaC films 30, 52, and the HfO ₂ film 29 are patterned to form a gate structure. Next, p-type extension regions 38 and 55 are formed by implanting B ions with low acceleration energy using the gate structure as a mask.

Next, as shown in FIG. 8F, after depositing a thick SiO ₂ film on the entire surface by LPCVD, anisotropic etching is performed to form sidewalls 40 and 56. Next, p-type source / drain regions 42 and 57 are formed by implanting B ions with high acceleration energy using the gate structure and sidewalls 40 and 56 as a mask. At this time, the polycrystalline silicon film 34 constituting the gate structure is doped with B to become p-type polycrystalline silicon films 43 and 58.

  Next, the implanted ions are activated, and then, as shown in FIG. 8G, a Co film having a thickness of, for example, 10 nm is deposited on the entire surface by sputtering, and then heat treatment is performed. As a result, Co silicide layers 49, 51, 59, 60 are formed.

Next, as shown in FIG. 8 (h), the unreacted Co film is removed by etching for 20 minutes with a mixed solution of H ₂ SO ₄ : H ₂ O ₂ = 3: 1, and then the BPSG film is formed on the entire surface. Then, the interlayer insulating film 52 is formed by polishing and planarizing by CMP. Thereafter, in order to form a wiring structure in need, the formation process of the via, the formation process of the wiring, and comprising a plurality of p-channel type MISFET having different V _th one another by repeating the step of forming the interlayer insulating film A semiconductor device is completed.

As described above, in Example 2 of the present invention, a TaC film having a high work function is formed, and then selectively exposed to a hydrogen plasma atmosphere, whereby the C concentration in the TaC film is suitable for a p-channel MISFET. It is reduced within the work function range. Accordingly, the _Vth of each MISFET can be controlled with high accuracy, and the gate insulating film is not damaged due to etching damage or ion implantation, so that the reliability of the semiconductor device is not lowered.

  Next, with reference to FIGS. 9 to 10, a manufacturing process of the n-channel MISFET according to the third embodiment of the present invention will be described. First, as shown in FIG. 9A, p-type well regions 28 and 61 separated by a buried oxide film 26 are formed in a p-type silicon substrate 21 through substantially the same steps as in the first embodiment.

Next, after performing an SC2 cleaning process using HCl + H ₂ O ₂ , an HfO ₂ film 29 having a thickness of, for example, 3 nm is formed on the entire surface by using an ALCVD method in which HfCl ₄ and H ₂ O are alternately supplied. To do. Next, a TaC film 30 having a thickness of, for example, 5 nm is formed by performing sputtering by alternately supplying a Ta source and a C source.

Next, as illustrated in FIG. 9B, a SiN film having a thickness of, for example, 20 nm is deposited by CVD, and then a resist pattern 31 is provided so as to cover the p-type well region 61. . Next, the SiN film exposed by using the resist pattern 31 as a mask is removed by etching by RIE under an atmosphere containing CHF ₃ and Ar to form a SiN film pattern 32.

  Next, as shown in FIG. 9C, after removing the resist pattern 31, hydrogen plasma treatment is performed using the SiN film pattern 32 as a mask. By this hydrogen plasma treatment, C is released from the TaC film on the p-type well region 28 to form a TaC film 62 having a relatively low carbon concentration and a low work function.

  Next, as shown in FIG. 9D, after removing the SiN film pattern 32, hydrogen plasma treatment is performed again. By this hydrogen plasma treatment, C further desorbs from the TaC film 62 on the p-type well region 28 to form a TaC film 63 having a low carbon concentration and a low work function. On the other hand, C is detached from the TaC film 30 on the p-type well region 61, so that a TaC film 64 having a relatively low carbon concentration and a slightly reduced work function is obtained.

Next, as shown in FIG. 10E, a polycrystalline silicon film 34 having a thickness of, for example, 100 nm is deposited on the entire surface by using the CVD method, and then the polycrystalline silicon film 34, TaC films 63 and 64, Then, the gate structure is formed by patterning the HfO ₂ film 29.
Next, n-type extension regions 65 and 66 are formed by implanting As ions with low acceleration energy using the gate structure as a mask.

Next, as shown in FIG. 10F, a thick SiO ₂ film is deposited on the entire surface by LPCVD, and then sidewalls 67 and 68 are formed by performing anisotropic etching. Next, n-type source / drain regions 69 and 70 are formed by implanting As ions with high acceleration energy using the gate structure and sidewalls 67 and 68 as a mask. At this time, the polycrystalline silicon film 34 constituting the gate structure is doped with As to form n-type polycrystalline silicon films 71 and 72.

  Next, a heat treatment for activating the implanted ions is performed. Next, as shown in FIG. 10G, a Co film having a thickness of, for example, 10 nm is deposited on the entire surface by sputtering, and then heat treatment is performed to form Co silicide layers 73 to 76. To do.

Next, as shown in FIG. 10 (h), the unreacted Co film is removed by etching for 20 minutes with a mixed solution of H ₂ SO ₄ : H ₂ O ₂ = 3: 1, and then the BPSG film is formed on the entire surface. Then, the interlayer insulating film 52 is formed by polishing and planarizing by CMP. Thereafter, in order to form a wiring structure in need, the formation process of the via, the formation process of the wiring, and comprising a plurality of n-channel type MISFET having different V _th one another by repeating the step of forming the interlayer insulating film A semiconductor device is completed.

Thus, in Example 3 of the present invention, after a TaC film having a high work function is formed, it is selectively exposed twice to a hydrogen plasma atmosphere, whereby the C concentration in the TaC film is changed to an n-channel MISFET. Reduced within a suitable work function. Accordingly, the _Vth of each MISFET can be controlled with high accuracy, and the gate insulating film is not damaged due to etching damage or ion implantation, so that the reliability of the semiconductor device is not lowered.

  The embodiments and embodiments of the present invention have been described above. However, the present invention is not limited to the configurations described in the embodiments and embodiments, and various modifications can be made. For example, in the description of each of the above examples and embodiments, a silicon substrate is used as a substrate, but the present invention is not limited to a silicon substrate. For example, an SiGe substrate or an epitaxial substrate obtained by growing a SiGe layer on a silicon substrate or the like may be used.

In each of the above embodiments, HfO ₂ is used as the high dielectric constant film. However, it is not limited to HfO ₂ , but a film having a dielectric constant of 10 to 40, for example, zirconium oxide (ZrO ₂ ), oxidation Yttrium (Y ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ) and its silicates and aluminates, aluminum oxide (Al ₂ O ₃ ), or tantalum pentoxide (Ta ₂ O ₅ ) may be used. is there.

  In the method of manufacturing a semiconductor device shown in each of the above examples and embodiments, for example, the order of extension formation in the first well region and extension formation in the second well region, The order of forming the source / drain in the well region and forming the source / drain in the second well region is arbitrarily changed as appropriate.

  In each of the above embodiments, a Co silicide layer using Co is formed for each of the gate, source, and drain electrodes. However, the present invention is not limited to Co. For example, Ni silicide using Ni or the like is used. A layer may be used.

Here, the following additional notes are disclosed regarding the embodiment of the present invention including Examples 1 to 3.
(Appendix 1) a semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate; and a first gate electrode including a first tantalum carbide film having a first carbon concentration formed on the first gate insulating film. An insulated gate field effect transistor of
A second gate insulating film formed on the semiconductor substrate; and a second tantalum carbide film having a second carbon concentration different from the first carbon concentration formed on the second gate insulating film. A semiconductor device comprising: a second insulated gate field effect transistor having a second gate electrode.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the first insulated gate field effect transistor and the second insulated gate field effect transistor constitute a complementary transistor.
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the first insulated gate field effect transistor and the second insulated gate field effect transistor constitute transistors of the same conductivity type having different threshold voltages.
(Supplementary Note 4) The first gate insulating film and the second insulating film are made of the same high dielectric constant film, and the high dielectric constant film is composed of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, and silicates thereof. 4. The semiconductor device according to any one of appendix 1 to appendix 3, comprising at least one of aluminate, aluminum oxide, or tantalum pentoxide.
(Additional remark 5) The process of forming a gate insulating film on a semiconductor substrate,
Forming a tantalum carbide film on the gate insulating film;
Forming a mask pattern having an opening exposing a portion of the tantalum carbide film, and then performing a hydrogen plasma treatment.
(Supplementary Note 6) A step of forming a p-channel field effect transistor using the tantalum carbide film as a gate electrode not subjected to hydrogen plasma treatment in a region other than the region corresponding to the opening, and hydrogen plasma in the region corresponding to the opening The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming an n-channel field effect transistor using the treated tantalum carbide film as a gate electrode.
(Supplementary Note 7) A step of forming a first p-channel field effect transistor using the tantalum carbide film that is not subjected to hydrogen plasma treatment as a gate electrode in a region other than a region corresponding to the opening, and a region corresponding to the opening A second p-channel field effect transistor having a threshold voltage smaller than that of the first p-channel field effect transistor is formed using the tantalum carbide film subjected to hydrogen plasma treatment as a gate electrode. The manufacturing method of the semiconductor device of appendix 5 which has a process to do.
(Additional remark 8) The manufacturing method of the semiconductor device of Additional remark 5 which has the process of performing a 2nd hydrogen plasma process after removing the said mask pattern.
(Supplementary Note 9) A step of forming a first n-channel field effect transistor using the tantalum carbide film that has undergone only the second hydrogen plasma treatment as a gate electrode in a region other than a region corresponding to the opening; And a second n having a threshold voltage larger in absolute value than the first n-channel field-effect transistor, with the tantalum carbide film subjected to at least twice hydrogen plasma treatment in a region corresponding to The method for manufacturing a semiconductor device according to appendix 8, further comprising a step of forming a channel type field effect transistor.
(Appendix 10) The appendix 5 to appendix 9, wherein the gate insulating film is made of at least one of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, silicate, aluminate, aluminum oxide, or tantalum pentoxide. The manufacturing method of the semiconductor device of any one.

It is explanatory drawing of the manufacturing process of the metal gate MISFET of embodiment of this invention. It is explanatory drawing of the manufacturing process to the middle of the complementary semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 2 after the complementary semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the complementary semiconductor device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 4 of the complementary semiconductor device of Example 1 of this invention. FIG. 6 is an explanatory diagram of the manufacturing process of FIG. 5 and subsequent drawings of the complementary semiconductor device of Example 1 of the present invention. It is explanatory drawing of the manufacturing process to the middle of p channel type MISFET of Example 2 of this invention. It is explanatory drawing of the manufacturing process after FIG. 7 of p channel type MISFET of Example 2 of this invention. It is explanatory drawing of the manufacturing process to the middle of n channel type MISFET of Example 3 of this invention. FIG. 10 is an explanatory diagram of the manufacturing process of FIG. It is explanatory drawing of the manufacturing process of the conventional metal gate CMOSFET. It is explanatory drawing of the manufacturing process of other conventional metal gate CMOSFET.

Explanation of symbols

11 silicon substrate 12 element isolation region 13 first well region 14 second well region 15 gate insulating film 16, 19 TaC film 17 SiN film pattern 18 hydrogen plasma 20 conductive film 21 p-type silicon substrate 22 SiO ₂ film 23 SiN film 24, 32 SiN film pattern 25 Element isolation trench 26 Embedded oxide film 27, 53 n-type well region 28, 61 p-type well region 29 HfO ₂ film 30, 33, 54, 62-64 TaC film 31, 35, 37, 41, 44 Resist pattern 34 Polycrystalline silicon films 36, 65, 66 n-type extension regions 38, 55 p-type extension regions 39, 40, 56, 67, 68 Side walls 42, 57 p-type source / drain regions 43, 58 p-type polycrystalline silicon films 45, 69, 70 n-type source / drain regions 46, 71, 2 n-type polycrystalline silicon film 47 Co films 48 to 51, 59, 60, 73 to 76 Co silicide layer 52 Interlayer insulating film 81 Silicon substrate 82 Element isolation region 83 n-type well region 84 p-type well region 85 Gate insulating film 86 , 88, 90 TaC film 87, 89 SiN film pattern

Claims (5)

A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate; and a first gate electrode including a first tantalum carbide film having a first carbon concentration formed on the first gate insulating film. An insulated gate field effect transistor of
A second gate insulating film formed on the semiconductor substrate; and a second tantalum carbide film having a second carbon concentration different from the first carbon concentration formed on the second gate insulating film. A semiconductor device comprising: a second insulated gate field effect transistor having a second gate electrode. Forming a gate insulating film on the semiconductor substrate;
Forming a tantalum carbide film on the gate insulating film;
A method of manufacturing an insulated gate semiconductor device, comprising: forming a mask pattern having an opening exposing a part of the tantalum carbide film, and performing a hydrogen plasma treatment. Forming a p-channel field effect transistor using the tantalum carbide film as a gate electrode not subjected to hydrogen plasma treatment in a region other than the region corresponding to the opening; and receiving a hydrogen plasma treatment in the region corresponding to the opening The method of manufacturing an insulated gate semiconductor device according to claim 2, further comprising: forming an n-channel field effect transistor using the tantalum carbide film as a gate electrode. The method for manufacturing an insulated gate semiconductor device according to claim 2, further comprising a step of performing a second hydrogen plasma treatment after removing the mask pattern. 5. The device according to claim 2, wherein the gate insulating film is made of at least one of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, and its silicate, aluminate, aluminum oxide, or tantalum pentoxide. 2. A method for manufacturing an insulated gate semiconductor device according to item 1.

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