JP6082752B2 - メモリ応答の順序付けのためのメモリ装置、コンピュータシステムおよび方法 - Google Patents

メモリ応答の順序付けのためのメモリ装置、コンピュータシステムおよび方法 Download PDF

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JP6082752B2
JP6082752B2 JP2014547242A JP2014547242A JP6082752B2 JP 6082752 B2 JP6082752 B2 JP 6082752B2 JP 2014547242 A JP2014547242 A JP 2014547242A JP 2014547242 A JP2014547242 A JP 2014547242A JP 6082752 B2 JP6082752 B2 JP 6082752B2
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responses
memory
commands
response
ordering
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JP2015500541A (ja
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エム． ウォーカー，ロバート
エム． ウォーカー，ロバート
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マイクロン テクノロジー， インク．
マイクロン テクノロジー， インク．
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2014547242A 2011-12-13 2012-11-02 メモリ応答の順序付けのためのメモリ装置、コンピュータシステムおよび方法 Active JP6082752B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/324,877 2011-12-13
US13/324,877 US8880819B2 (en) 2011-12-13 2011-12-13 Memory apparatuses, computer systems and methods for ordering memory responses
PCT/US2012/063327 WO2013089937A1 (en) 2011-12-13 2012-11-02 Memory apparatuses, computer systems and methods for ordering memory responses

Publications (2)

Publication Number Publication Date
JP2015500541A JP2015500541A (ja) 2015-01-05
JP6082752B2 true JP6082752B2 (ja) 2017-02-15

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JP2014547242A Active JP6082752B2 (ja) 2011-12-13 2012-11-02 メモリ応答の順序付けのためのメモリ装置、コンピュータシステムおよび方法

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US (2) US8880819B2 (zh)
EP (1) EP2791941A4 (zh)
JP (1) JP6082752B2 (zh)
KR (1) KR101709385B1 (zh)
CN (1) CN103999159B (zh)
TW (1) TWI496003B (zh)
WO (1) WO2013089937A1 (zh)

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Also Published As

Publication number Publication date
US20130151741A1 (en) 2013-06-13
KR20140102738A (ko) 2014-08-22
US9575907B2 (en) 2017-02-21
US8880819B2 (en) 2014-11-04
TW201342067A (zh) 2013-10-16
KR101709385B1 (ko) 2017-02-22
US20150052318A1 (en) 2015-02-19
EP2791941A4 (en) 2015-03-11
CN103999159B (zh) 2017-07-25
CN103999159A (zh) 2014-08-20
WO2013089937A1 (en) 2013-06-20
TWI496003B (zh) 2015-08-11
EP2791941A1 (en) 2014-10-22
JP2015500541A (ja) 2015-01-05

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