JP6081757B2 - Sample hold circuit and switching power supply circuit - Google Patents

Description

  The present invention relates to a sample hold circuit and a switching power supply circuit using the sample hold circuit.

  2. Description of the Related Art Conventionally, as one of power supply circuits that output a predetermined DC voltage, a switching power supply circuit that converts an input voltage into a predetermined voltage value and outputs it by on / off control of a switching element (switching transistor) is used. ing.

  In such a switching power supply circuit, a sample hold circuit is used to detect the current of the switching element. FIG. 7 shows a configuration example of a conventional switching power supply circuit disclosed in Patent Document 1. FIG. 7 shows a circuit configuration of the sample hold circuit 21 in the switching power supply circuit.

  The switching power supply circuit shown in FIG. 7 converts the input voltage VIN into a predetermined voltage VOUT by on / off control of the switching element S1. When the switching element S1 is ON, the terminal of the inductor L1 and the resistor R1 are short-circuited, the current of the inductor L1 is increased, and energy is stored in the inductor L1.

  When the switching element S1 is OFF, the source-drain of the switching element S1 is cut off, and the current of the inductor L1 is supplied to the output portion of the voltage VOUT via the diode D1. The switching control signal generation circuit 3 monitors the voltage VFB obtained by resistance division of the voltage VOUT and the source voltage of the switching element S1 sampled and held by the sample hold circuit 21 so that the voltage VOUT becomes a predetermined voltage. Generate Vq.

  The source voltage of the switching element S <b> 1 becomes a voltage V <b> 1 through an amplifier in the current detection circuit 5 and is input to the sample hold circuit 21. The voltage V1 is sampled and held by the sample and hold switching transistor S2 and the capacitor C2, and the sampled and held voltage Vs is sent to the switching control signal generation circuit 3.

  8 shows the control signal Vq for the switching element S1, the ON / OFF of the switching element S1, the source voltage of the switching element S1, and the amplifier output V1 in the current detection circuit 5 in the switching power supply circuit shown in FIG. It shows the time variation of the control signal Vg for the switching transistor S2, ON / OFF of the switching transistor S2, and the sample hold voltage Vs.

  As each switching transistor (S1, S2), an N-type MOS transistor is generally used. Therefore, the voltage of each control signal (Vq, Vg) is at a high level (HI) when the switching transistor is turned on, and is at a low level (LO) when the switching transistor is turned off.

  As shown in FIG. 8, when the switching transistor S2 is ON, the amplifier output and the capacitor C2 are short-circuited, and the capacitor C2 is charged with the voltage V1. When the switching transistor S2 is OFF, the voltage of the capacitor C2 is held.

  As shown in FIG. 8, the sample hold circuit 21 samples and holds the source voltage of the switching element S1 immediately before the control signal Vq changes from HI to LO. In this way, the current value of the inductor L1 immediately before the switching element S1 is turned off is monitored.

JP 2008-35609 A

  As a problem in the above circuit configuration, there is a problem that the current consumption and the circuit scale of the amplifier in the current detection circuit are increased. In order to correctly sample and hold in the situation shown in FIG. 8, the amplifier output V1 must follow the triangular wave of the source voltage of the switching element S1. Since the frequency of the triangular wave is generally several tens of kHz to several MHz, it is necessary to increase the speed of the amplifier at a high frequency, and it is necessary to increase the current consumption and the circuit scale of the amplifier.

  As shown in FIG. 9, if the sample-and-hold switching transistor S2 is directly connected to the source of the switching element S1 without an amplifier (omitting the amplifier), the current consumption and the circuit scale can be reduced. Seems to be possible. However, in this case, as shown below, there is a problem that the signal is not correctly held.

  The source voltage of the switching element S1 shown in FIG. 8 is actually a negative voltage VN at the falling edge of the triangular wave, as shown in FIG. The cause of the negative voltage is that the control signal Vq is switched from HI to LO at the moment when the switching element S1 is turned OFF, and the source voltage is pulled to the negative voltage via the gate-source parasitic capacitance of the switching element S1. It is in.

  Due to the generation of the negative voltage, the source voltage becomes lower than the gate voltage Vg of the sample-and-hold switching transistor S2, and the transistor S2 is turned on. Therefore, there is a problem that the electric charge held in the capacitor C2 is discharged and cannot be correctly sampled and held.

  Further, since the falling waveform of the triangular wave is generally steep as several tens ns to several hundreds ns, the voltage of the capacitor C2 fluctuates through the parasitic capacitance between the source and drain of the sample-and-hold switching transistor S2. There is a problem that sample hold is not possible.

  In addition to the steep falling waveform, if noise enters during the hold period, there is a problem that the voltage of the capacitor C2 fluctuates for the same reason and the sample-and-hold cannot be performed correctly. For the reason described above, the switching element S1 is connected to the sample hold circuit 21 through an amplifier.

  SUMMARY OF THE INVENTION In view of the above-described problems, the present invention provides a sample-and-hold circuit that makes it easy to correctly perform sample-and-hold while reducing power consumption and circuit scale, and a switching power supply circuit including the sample-and-hold circuit. And

  A sample and hold circuit according to the present invention includes an input terminal to which a voltage signal is input, an output terminal, a capacitor, first to fourth transistors that are N-type MOS transistors, and a P-type MOS transistor, and includes a sampling period, A sample-and-hold circuit that samples and holds the voltage signal using the capacitor in accordance with a control signal indicating a hold period, and outputs a result of the sample-and-hold from the output terminal, wherein the first transistor includes a gate Is connected to the drain of the P-type MOS transistor, the gate of the second transistor, and the drain of the third transistor, the source is the input terminal, the source of the second transistor, The P-type MOS transistor is connected to a back gate, and the control signal is input to the gate. The source is connected to its own back gate and is maintained at a predetermined voltage higher than the voltage signal. The second transistor has a drain connected to the output terminal and is grounded via the capacitor, and the back gate is connected to the first gate. 3 is connected to the source and back gate of the transistor 3 and connected to the drain of the fourth transistor through a resistor. The third transistor has the control signal input to the gate, and the fourth transistor The back gate is grounded.

  According to this configuration, it is easy to correctly perform sample and hold while reducing power consumption and circuit scale.

  More specifically, in the configuration described above, the control signal is a binary signal that becomes a ground voltage during the sample period and becomes the predetermined voltage during the hold period, and is supplied to the gate of the fourth transistor. A signal having a phase opposite to that of the control signal may be input.

  More specifically, the above configuration further includes a fifth transistor that is an N-type MOS transistor between the second transistor and the capacitor, and the source of the fifth transistor is connected to the drain of the second transistor. The drain may be connected to the output terminal and grounded via the capacitor, and the back gate may be grounded.

  More specifically, in the configuration described above, a signal in a state where a signal having a phase opposite to that of the control signal is shifted in a direction that is advanced by a predetermined minute time is input to the gate of the fifth transistor. Also good.

  A switching power supply circuit according to the present invention is a switching power supply circuit that includes the sample hold circuit having the above-described configuration and outputs a predetermined DC voltage by controlling on / off of the switching element, and a current flowing through the switching element. A voltage corresponding to is input to the input terminal as the voltage signal, and the switching element is controlled based on the result of the sample and hold.

  According to the sample and hold circuit according to the present invention, it becomes easy to correctly perform the sample and hold while reducing the power consumption and the circuit scale. Further, according to the switching power supply circuit according to the present invention, it is possible to enjoy the advantages of the sample hold circuit according to the present invention.

It is a block diagram of the switching power supply circuit which concerns on embodiment of this invention. It is a block diagram of the sample hold circuit which concerns on 1st Embodiment. 3 is a timing chart of various signals according to the first embodiment. It is a block diagram of the sample hold circuit which concerns on 2nd Embodiment. It is a timing chart of various signals etc. concerning a 2nd embodiment. It is a more detailed timing chart of the various signals etc. which concern on 2nd Embodiment. It is a block diagram of the switching power supply circuit which concerns on a prior art example. It is a timing chart of various signals etc. concerning a conventional example. It is explanatory drawing regarding the switching power supply circuit at the time of abbreviate | omitting amplifier. It is explanatory drawing regarding the switching power supply circuit at the time of abbreviate | omitting amplifier.

  Embodiments of the present invention will be described below by taking the first embodiment and the second embodiment as examples.

1. First Embodiment [Overall Configuration of Switching Power Supply Circuit, etc.]
First, the first embodiment will be described. FIG. 1 is a configuration diagram (circuit block diagram) of a switching power supply circuit 1 according to the present embodiment. As shown in the figure, the switching power supply circuit 1 includes a reference pulse generation circuit 2, a switching control signal generation circuit 3, a DC-DC converter 4, a sample hold circuit SH, a resistor R1, and a negation circuit 7.

  The reference pulse generation circuit 2 is a circuit that generates a reference pulse signal having a predetermined period, and supplies the generated reference pulse signal Vp to the switching control signal generation circuit 3.

  The switching control signal generation circuit 3 includes a timing signal generation circuit 6, a logic circuit 14, a triangular wave generation circuit 15, a differential amplification circuit 16, a comparison circuit 17, an addition circuit 18, and a voltage source that outputs a DC voltage VREF. . The timing signal generation circuit 6 includes a negation circuit 11, a delay circuit 12, and a logical product circuit 13.

  The negative circuit 11 inputs the negative signal Vb of the reference pulse signal Vp to the delay circuit 12 when the reference pulse signal Vp is input. The delay circuit 12 generates a predetermined delay with respect to the input signal Vb, and then inputs the delayed signal Vc to the AND circuit 13.

  The logical product circuit 13 receives the signal Vc output from the delay circuit 12 and the reference pulse signal Vp, and outputs an output signal VG1 related to these logical products. The signal VG1 is input to the logic circuit 14 as the timing signal VG1, and also input to the sample and hold circuit SH as a control signal VG1 for controlling the operation of the sample and hold circuit SH. A period in which the control signal VG1 is at a low level corresponds to a sample period for sample and hold, and a period in which the control signal VG1 is at a high level corresponds to a hold period. The signal VG1 is also input to the negation circuit 7.

  The high level voltage of the signal VG1 is set to be equal to the voltage of the power supply VCC (VCC voltage) used in the sample hold circuit SH. The voltage of the low level state of the signal VG1 is set to be equal to the voltage at the ground point (GND voltage) in the switching power supply circuit 1.

  The logic circuit 14 has two terminals of a set terminal S and a reset terminal R as input terminals, and outputs an output signal (switching control signal Vq) corresponding to the logic content shown below according to the level of the input signal. To do.

  That is, when the signal (reset signal) input to the reset terminal R is in a high level state (high state), the logic circuit 14 outputs regardless of the signal level of the signal (set signal) input to the set terminal. When the signal is in a low level state (low state) and the reset signal is in the low state and the set signal is in the high state, the output signal is in the high state. The logic circuit 14 can be constituted by, for example, a reset signal priority type RS flip-flop circuit.

  In such a configuration, when the output signal Va of the comparison circuit 17 input to the reset terminal R is in the low state and the signal VG1 input to the set terminal S rises to the high state, it responds to this rise. Thus, when the switching control signal Vq rises to the high state and then the output signal Va rises, the switching control signal Vq falls to the low state in response to the rising. That is, when the value of the signal V2 exceeds the value of the signal V0, the signal Va rises, and as a result, the switching control signal Vq falls, so the switching control signal depends on the comparison result between the signal V2 and the signal V0. The duty ratio of Vq can be controlled.

  The switching element S1 (N-channel MOSFET) is turned on when the switching control signal Vq is in a high state and turned off when the switching control signal Vq is in a low state. In other words, the on / off control of the switching element S1 is performed according to the comparison result between the signal V2 and the signal V0. In particular, since the magnitude of the signal V2 depends on the detection current IS1 flowing through the switching element S1, it can be said that on / off control of the switching element S1 can be performed based on the value of the detection current IS1.

  The triangular wave generation circuit 15 generates a triangular wave or a sawtooth wave synchronized with the reference pulse signal based on the reference pulse signal Vp output from the reference pulse generation circuit 2 and outputs the triangular wave or the sawtooth wave to the adding circuit 18 (hereinafter, the sawtooth wave is referred to as a sawtooth wave). Including "triangular wave"). The adder circuit 18 adds the voltage signal Vs output from the sample hold circuit SH and the triangular wave output signal Vd output from the triangular wave generation circuit 15, and gives the added output voltage V 2 to the comparison circuit 17.

  The differential amplifier circuit 16 receives the DC voltage VREF set to a predetermined reference voltage value and the feedback input voltage VFB, respectively, and gives a signal V0 obtained by amplifying the voltage difference to the comparator circuit 17.

  The comparison circuit 17 compares the output signal V2 of the adder circuit 18 with the output signal V0 of the differential amplifier circuit 16, and a signal Va representing the comparison result as a binary level is one input terminal of the logic circuit 14. Input to the reset terminal R.

  The adder circuit 18 adds the signal Vs supplied from the sample hold circuit SH and the signal Vd output from the triangular wave generating circuit 15, and gives an output signal V 2 representing the result to the comparator circuit 17.

  The negation circuit 7 reverses the polarity of the control signal VG1 and outputs it as a control signal VG1_INV used for control of the sample hold circuit SH. That is, the control signal VG1 and the control signal VG1_INV are in an opposite phase relationship. The control signal VG1_INV is input to the sample hold circuit SH.

  The DC-DC converter 4 includes circuit elements including a DC voltage source E1 that outputs a voltage VIN, an inductor L1, a diode D1, a switching element S1, and a capacitor C1. Note that the switching element S1 in the present embodiment is assumed to be composed of an N-channel MOSFET as an example. The switching element S1 includes a drain electrode pd, a source electrode ps, and a gate electrode pg.

  As shown in FIG. 1, one terminal p1 of the inductor L1 is connected to the positive voltage side of the DC voltage source E1, and the other terminal p2 is connected to the anode electrode pa of the diode D1 and the drain electrode pd of the switching element S1. Connected.

  Further, the cathode electrode pk of the diode D1 and one electrode p3 of the capacitor C1 are connected, and the other electrode p4 of the capacitor C1 is connected to the negative voltage side of the DC voltage source E1. The voltage across the capacitor C1 is used as an output voltage VOUT in a subsequent circuit or the like.

  The switching element S1 is subjected to on / off control (control of conduction / cut-off between the source and drain) when a switching control signal Vq is given to the gate electrode pg from the switching control signal generation circuit 3. When the switching element S1 is in the on state, the current IS1 flows through the switching element S1.

  The source electrode ps of the switching element S1 is connected to one end of the sample hold circuit SH and the resistor R1. The other end of the resistor R1 is grounded. As a result, when the current IS1 flows to the ground point through the resistor R1, a voltage corresponding to the magnitude of the current IS1 (corresponding to the detection result of the magnitude of the current IS1) is input to the sample hold circuit SH as the voltage signal IN1. Is done.

  The sample and hold circuit SH has a terminal Tin to which the voltage signal IN1 is input, a terminal Tcon1 to which the control signal VG1 is input, a terminal Tcon2 to which the control signal VG1_INV is input, and a terminal Tout that outputs the signal Vs. ing. The sample and hold circuit SH samples and holds the voltage signal IN1, and outputs the result of the sample and hold as a signal Vs from the terminal Tout.

[Sample hold circuit configuration]
Next, the configuration of the sample hold circuit SH will be described in detail. FIG. 2 is a configuration diagram of the sample hold circuit SH. As shown in the figure, the sample hold circuit SH includes each terminal (Tin, Tcon1, Tcon2, Tout), four N-type MOS transistors (TrN1 to TrN4), a P-type MOS transistor TrP1, and a sample-hold capacitor C2. And a resistor R2.

  The gate GN1 of the N-type MOS transistor TrN1 is connected to the terminal Tcon1 and receives the control signal VG1. The drain DN1 of the N-type MOS transistor TrN1 is connected to the drain DP1 of the P-type MOS transistor TrP1, the gate GN2 of the N-type MOS transistor TrN2, and the drain DN3 of the N-type MOS transistor TrN3. The source SN1 of the N-type MOS transistor TrN1 is connected to the terminal Tin, the source SN2 of the N-type MOS transistor TrN2, and its own back gate BN1.

  The gate GP1 of the P-type MOS transistor TrP1 is connected to the terminal Tcon1, and receives the control signal VG1. The source SP1 of the P-type MOS transistor TrP1 is connected to the power supply VCC and its own back gate BP1.

  The drain DN2 of the N-type MOS transistor TrN2 is connected to the terminal N1 on one side of the sample-hold capacitor C2 and to the terminal Tout. The back gate BN2 of the N-type MOS transistor TrN2 is connected to the source SN3 of the N-type MOS transistor TrN3, the back gate BN3 of the N-type MOS transistor TrN3, and the terminal N2 on one side of the resistor R1.

  The gate GN3 of the N-type MOS transistor TrN3 is connected to the terminal Tcon1 and receives the control signal VG1. The gate GN4 of the N-type MOS transistor TrN4 is connected to the terminal Tcon2, and receives the control signal VG1_INV. The source SN4 of the N-type MOS transistor TrN4 is connected to the ground point (GND). The drain DN4 of the N-type MOS transistor TrN4 is connected to the terminal N3 on one side of the resistor R1. The back gate BN4 of the N-type MOS transistor TrN4 is connected to the ground point (GND).

  A terminal N4 on one side of the sample and hold capacitor C2 is connected to a ground point (GND). The VCC voltage, which is the voltage of the power supply VCC, is set appropriately so as to be maintained at a predetermined voltage higher than the voltage signal VIN1 input to the terminal Tin. For example, the value of the VCC voltage is set to a value higher than the upper limit value of the voltage that the voltage signal VIN1 can take.

  The control signal VG1 takes two values of the GND voltage and the VCC voltage, and becomes the GND voltage when sampling and holding, and becomes the VCC voltage when holding. Further, the control signal VG1 and the control signal VG1_INV are in a phase relationship with each other. That is, the control signal VG1_INV takes a binary value of the GND voltage and the VCC voltage, becomes the VCC voltage when sampling and holding, and becomes the GND voltage when holding. The source voltage of the switching element S1 is directly input to the terminal Tin without going through an amplifier circuit or the like.

  FIG. 3 shows input voltage VIN1, control signal VG1, control signal VG1_INV voltage, ON / OFF of each transistor, gate voltage VGN2 of N-type MOS transistor TrN2, back gate voltage VBN2, ON / OFF of N-type MOS transistor TrN2, 4 is a timing chart showing a change with time for each of the sample hold voltage Vs (N1 terminal voltage of the capacitor C2).

  At the time of holding, since the N-type MOS transistors TrN1 and TrN3 are ON, the N-type MOS transistor TrN2 is turned OFF because the source, gate, and back gate voltages are the same voltage. Even when the voltage of the voltage signal IN1 becomes a negative voltage, in the N-type MOS transistor TrN2, all the voltages of the source, the gate, and the back gate become a negative voltage. Therefore, the capacitor C2 can hold the hold voltage without turning on the N-type MOS transistor TrN2.

  At the time of sampling, since the P-type MOS transistor TrP1 and the N-type MOS transistor TrN4 are turned on, the gate voltage of the N-type MOS transistor TrN2 becomes the VCC voltage, and the back gate voltage becomes the GND voltage. As a result, the source and drain of the N-type MOS transistor TrN2 are short-circuited, and the capacitor C2 is charged.

  In addition, the parasitic diode between the back gate and the drain of the N-type MOS transistors TrN1 and TrN3 has the highest drain voltage during the period when these transistors are OFF, so no current flows. Abnormal operation or abnormal current does not occur. The resistor R2 is inserted in order to limit the current of the N-type MOS transistor TrN4 when it becomes a negative voltage during holding.

  In addition, the sample hold circuit SH having the configuration shown in FIG. 2 can be configured to further reduce the influence of noise by adding a transistor. Hereinafter, the sample hold circuit SH configured as described above will be described as a second embodiment.

2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, an N-type MOS transistor TrN5 is added to the sample and hold circuit SH, and a part related to the point that the control signal VG0_INV used for controlling the sample and hold circuit SH is input. Basically, this is equivalent to the first embodiment. In the following description, emphasis is placed on the description of the points different from the first embodiment, and description of common points may be omitted.

  FIG. 4 is a configuration diagram of the sample and hold circuit SH according to the second embodiment. Compared to the first embodiment, the sample and hold circuit SH shown in FIG. 4 has an N type MOS transistor TrN5 added between the drain DN2 of the N type MOS transistor TrN2 and the terminal N1 on one side of the sample and hold capacitor C2. It becomes the composition.

  4 includes a terminal Tcon3 to which a control signal VG0_INV is input. The control signal VG0_INV is generated in the switching power supply circuit 1 and input to the terminal Tcon3.

  The gate GN5 of the N-type MOS transistor TrN5 is connected to the terminal Tcon3 and receives the control signal VG0_INV. The drain DN5 of the N-type MOS transistor TrN5 is connected to the terminal N1 on one side of the sample and hold capacitor C2. The source SN5 of the N-type MOS transistor TrN5 is connected to the drain DN2 of the N-type MOS transistor TrN2. The back gate BN5 of the N-type MOS transistor TrN5 is connected to the ground point (GND).

  The control signal VG0_INV is a signal that takes a binary value of the GND voltage and the VCC voltage, and is a signal equivalent to the control signal VG1_INV or a signal in a state where the control signal VG1_INV is shifted in a direction to advance by a predetermined minute time Δt1. (The purpose of shifting in this way will be apparent from the description given later). That is, the control signal VG0_INV is generally the VCC voltage when sampling and holding, and the GND voltage when holding.

  In the sample and hold circuit SH shown in FIG. 4, both the N-type MOS transistors TrN2 and TrN5 are turned ON and the capacitor C2 is charged by the voltage of the voltage signal IN1 when the sample and hold is sampled. At the time of holding, both the N-type MOS transistors TrN2 and TrN5 are turned OFF, and the voltage of the capacitor C2 is held.

  In the first embodiment (see FIG. 2), the drain DN2 of the N-type MOS transistor TrN2 is directly connected to the capacitor C2. Therefore, between the terminal Tin and the capacitor C2, the source-drain parasitic capacitance and the back gate-drain parasitic capacitance of the N-type MOS transistor TrN2 are connected in parallel. As a result, during holding, the voltage signal IN1 becomes a factor that has a relatively large effect on the capacitor C2 via these parasitic capacitances.

  However, in the second embodiment (see FIG. 4), between the terminal Tin and the capacitor C2, the N-type MOS transistor TrN2 has a parallel portion of the source-drain parasitic capacitance and the back gate-drain parasitic capacitance. The source-drain parasitic capacitance of the type MOS transistor TrN5 is connected in series. As a result, the combined capacitance is reduced, so that even if a steep waveform or noise is applied to the voltage of the voltage signal IN1 during holding, the influence on the capacitor C2 via the parasitic capacitance can be reduced.

  If the size of the N-type MOS transistor is reduced so that the size of the parasitic capacitance between the source and drain of the N-type MOS transistor is smaller than the size of the capacitance of the sample-and-hold capacitor C2, the corresponding amount is reduced. The influence on the capacitor C2 through the parasitic capacitance can be reduced.

  Two sample-and-hold switching transistors are connected in series between the terminal Tin and the sample-and-hold capacitor C2, the back gate of the switching transistor TrN5 on the side close to the capacitor C2 is connected to GND, and its size (switching transistor TrN5, etc.) By reducing the size, the influence of input noise on the capacitor C2 via the source-drain capacitance is reduced.

  In addition, by making the control signal VG0_INV a signal in which the control signal VG1_INV (a signal having a phase opposite to that of the control signal VG1) is shifted in a direction to advance the signal by a predetermined minute time Δt1, the influence of switching noise can be further avoided. An effect can be obtained. This point will be described below with reference to FIGS. 5 and 6.

  FIG. 5 is a timing chart showing temporal changes of various signals in the second embodiment. In FIG. 5, compared to FIG. 3, a chart of the time change of the control signal VG0_INV and the time change of ON / OFF of the N-type MOS transistor TrN5 is added. FIG. 6 is an enlarged view of a part of FIG. 5 in more detail.

  The control signal VG0_INV is a signal that takes two values of the GND voltage and the VCC voltage. As described above, the control signal VG1_INV (a signal having a phase opposite to that of the control signal VG1) is shifted in a direction that is advanced by a minute time Δt1. It has become. In other words, the control signal VG1_INV (a signal having a phase opposite to that of the control signal VG1) is a signal in which the control signal VG0_INV is delayed by a minute time Δt1.

  When such a control signal VG0_INV is input, the N-type MOS transistor TrN5 is turned off before the N-type MOS transistor TrN2. Therefore, the voltage signal IN1 can be given to the capacitor C2 until immediately before the hold, and the influence of the switching noise of the N-type MOS transistor TrN2 can be avoided. Thereby, the sample and hold circuit SH can sample and hold an accurate voltage.

3. Others As described above, the sample-and-hold circuit SH of each embodiment includes the terminal Tin (input terminal) to which the voltage signal IN1 is input, the terminal Tout (output terminal), the capacitor C2, and four N-type MOS transistors (TrN1). ~ TrN4), a P-type MOS transistor TrP1 is provided. The sample hold circuit SH is configured to sample and hold the voltage signal IN1 using the capacitor C2 according to the control signal VG1 indicating the sample period and the hold period, and to output the result of the sample hold from the terminal Tout. ing.

  The N-type MOS transistor TrN1 has a gate to which a control signal VG1 is input, a drain connected to the drain of the P-type MOS transistor TrP1, a gate of the N-type MOS transistor TrN2, and a drain of the N-type MOS transistor TrN3, and a source connected to the terminal Tin. And the source of the N-type MOS transistor TrN2 and its own back gate.

  Further, the P-type MOS transistor TrP1 is supplied with the control signal VG1 at its gate, the source is connected to its own back gate, and is maintained at a predetermined VCC voltage higher than the voltage signal IN1.

  The N-type MOS transistor TrN2 has a drain connected to the terminal Tout and grounded via the capacitor C2, and a back gate connected to the source and back gate of the N-type MOS transistor TrN3 and an N-type via the resistor R2. It is connected to the drain of the MOS transistor TrN4.

  Further, the control signal VG1 is input to the gate of the N-type MOS transistor TrN3. The N-type MOS transistor TrN4 has a source and a back gate that are grounded. The control signal VG1 is a binary signal that becomes the GND voltage in the sample period and becomes VCC in the hold period, and a signal having a phase opposite to that of the control signal VG1 is input to the gate of the N-type MOS transistor TrN4. It is like that.

  Therefore, according to the sample and hold circuit SH, it is not necessary to provide an amplifier or the like between the switching element S1, and it is possible to correctly perform the sample and hold while reducing power consumption and circuit scale. It has become.

  The sample and hold circuit SH of the second embodiment further includes an N-type MOS transistor TrN5 between the N-type MOS transistor TrN2 and the capacitor C2. The source of the N-type MOS transistor TrN5 is connected to the drain of the N-type MOS transistor TrN2, the drain is connected to the terminal Tout and grounded via the capacitor C2, and the back gate is grounded. Therefore, according to the sample and hold circuit SH of the second embodiment, the influence of noise can be further reduced.

  The switching power supply circuit 1 of each embodiment includes a sample hold circuit SH, and outputs a predetermined DC voltage VOUT by controlling the switching element S1 on / off. In the switching power supply circuit 1, a voltage corresponding to the current flowing through the switching element S1 is input to the terminal Tin as the voltage signal IN1. Further, based on the result of the sample hold, the switching control signal generation circuit 3 generates and outputs the switching control signal Vq, and the switching element S1 is controlled.

  The configuration of the present invention can be variously modified in addition to the above embodiment without departing from the spirit of the invention. That is, the above-described embodiment is an example in all respects, and should be considered not restrictive. The technical scope of the present invention is shown not by the above description of the embodiment but by the scope of the claims, and is understood to include all modifications within the meaning and scope equivalent to the scope of the claims. Should.

  The present invention can be used for a switching power supply circuit and the like.

DESCRIPTION OF SYMBOLS 1 Switching power supply circuit 2 Reference pulse generation circuit 3 Switching control signal generation circuit 4 DC-DC converter 6 Timing signal generation circuit 7 Negative circuit 11 Negative circuit 12 Delay circuit 13 AND circuit 14 Logic circuit 15 Triangular wave generation circuit 16 Differential amplifier circuit 17 Comparison circuit 18 Addition circuit SH Sample hold circuit C2 Sample hold capacitor R1, R2 Resistance Tin terminal (input terminal)
Tcon1 terminal Tcon2 terminal Tcon3 terminal Tout terminal (output terminal)
TrN1 N-type MOS transistor (first transistor)
TrN2 N-type MOS transistor (second transistor)
TrN3 N-type MOS transistor (third transistor)
TrN4 N-type MOS transistor (fourth transistor)
TrN5 N-type MOS transistor (fifth transistor)
TrP1 P-type MOS transistor

Claims (5)

An input terminal to which a voltage signal is input, an output terminal, a capacitor, first to fourth transistors which are N-type MOS transistors, and a P-type MOS transistor;
In accordance with a control signal indicating a sample period and a hold period, a sample and hold circuit that performs sample and hold of the voltage signal using the capacitor and outputs a result of the sample and hold from the output terminal,
The first transistor is
The control signal is input to the gate, the drain is connected to the drain of the P-type MOS transistor, the gate of the second transistor, and the drain of the third transistor, the source is the input terminal, the source of the second transistor, and itself Connected to the back gate,
The P-type MOS transistor is
The control signal is input to the gate, the source is connected to its back gate and maintained at a predetermined voltage higher than the voltage signal,
The second transistor is
A drain is connected to the output terminal and grounded via the capacitor, and a back gate is connected to the source and back gate of the third transistor and is connected to the drain of the fourth transistor via a resistor,
The third transistor is
The control signal is input to the gate,
The fourth transistor is
The source and back gate are grounded ,
In the hold period, the first transistor and the third transistor are turned on, and the second transistor, the fourth transistor, and the P-type MOS transistor are turned off,
In the sampling period, the first transistor and the third transistor are turned off, and the second transistor, the fourth transistor, and the P-type MOS transistor are turned on. A featured sample-and-hold circuit. The control signal is a binary signal that becomes a ground voltage in the sample period and becomes the predetermined voltage in the hold period,
2. The sample and hold circuit according to claim 1, wherein a signal having a phase opposite to that of the control signal is input to a gate of the fourth transistor. A fifth transistor that is an N-type MOS transistor is further provided between the second transistor and the capacitor,
The fifth transistor is
The source is connected to the drain of the second transistor, the drain is connected to the output terminal and grounded via the capacitor, the back gate is grounded , and the hold period is advanced by a predetermined minute time. 3. The method according to claim 1 , wherein the sampling period is turned off during the period shifted in the direction, and the sampling period is turned on during the period shifted in the direction advanced by the minute time. The sample-and-hold circuit described. The gate of the fifth transistor
Sample-and-hold circuit according to claim 3 in which the signal state said control signal is shifted in a direction to advance the reverse phase signal by the short time, characterized in that the input. A sample hold circuit according to any one of claims 1 to 4,
A switching power supply circuit that outputs a predetermined DC voltage by controlling on / off of the switching element,
A voltage corresponding to the current flowing through the switching element is input to the input terminal as the voltage signal,
A switching power supply circuit that controls the switching element based on the result of the sample hold.

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