JP6079163B2 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus equipped with the electro-optical device.

  A liquid crystal device as an example of an electro-optical device has a structure in which liquid crystal is sandwiched between a pair of substrates, and one of the pair of substrates is a thin film transistor (hereinafter abbreviated as TFT) or a pixel. The element substrate is provided with an electrode, and the other substrate is a counter substrate provided with a common electrode having translucency.

  For example, in the element substrate of the liquid crystal device described in Patent Document 1, a TFT, an interlayer insulating film, a pixel electrode, an insulating film, and an alignment film are stacked in this order. The TFT and the pixel electrode are connected via a contact hole formed in the interlayer insulating film. A recess formed in the pixel electrode due to the contact hole is covered with an insulating film. The insulating film is formed to have a sealed cavity at a position corresponding to the recess. Then, by performing a polishing process (planarization process) on the insulating film, the surface in contact with the alignment film becomes flat, and uneven alignment due to unevenness on the surface of the insulating film is suppressed.

JP 2011-164249 A

  In the liquid crystal device described in Patent Document 1, the insulating film disposed between the pixel electrode and the alignment film reduces the effective voltage applied to the liquid crystal between the pixel electrode and the common electrode. Although it is necessary to reduce the thickness of the insulating film, there is a limit to the thickness that can be reduced by polishing. Specifically, if the insulating film is made too thin by the polishing process, the cavities are exposed, and the alignment state of the liquid crystal is disturbed in the region where the cavities are exposed. Therefore, there is a limit to the film thickness that can be thinned by the polishing process. That is, in order to make the insulating film thinner, it is necessary to make the cavity of the insulating film formed at a position corresponding to the concave portion smaller.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A method for manufacturing an electro-optical device according to this application example includes a pixel switching element, a conductive film formed above the pixel switching element, a contact hole, and formed above the conductive film. An insulating film, a pixel electrode formed above the insulating film, a first dielectric film formed above the pixel electrode, and a second dielectric film formed above the first dielectric film. A part of the upper surface of the insulating film, wherein the pixel switching element and the pixel electrode are electrically connected to each other through the contact hole. Forming a pixel electrode having a first recess at a position corresponding to the contact hole so as to cover the sidewall of the insulating film in which the contact hole is formed and the conductive film exposed from the contact hole. Forming a first dielectric film covering the pixel electrode and having a first cavity sealed at a position corresponding to the first recess, and planarization for thinning the first dielectric film A step of exposing the first cavity to form a second recess, and a second cover covering the thinned first dielectric film and sealed at a position corresponding to the second recess. And a step of forming a second dielectric film having a cavity.

According to the present invention, when the pixel electrode is formed so as to cover the side wall in which the contact hole of the insulating film is formed and the conductive film exposed from the contact hole (the side wall and the bottom surface of the contact hole), it corresponds to the contact hole of the pixel electrode. A first recess is formed at the position. When the pixel electrode is covered with the first dielectric film, a sealed first cavity is formed at a position corresponding to the first recess. Further, when the first dielectric film is thinned so that the sealed first cavity is exposed, a second recess is formed at a position corresponding to the contact hole of the first dielectric film. Since the second recess is disposed inside the first recess, the opening size of the top of the second recess is smaller than the opening size of the top of the first recess. Further, when the first dielectric film is covered with the second dielectric film, a second cavity is formed at a position corresponding to the second recess. Since the opening size of the top of the second recess is small, the second cavity formed at a position corresponding to the second recess is smaller than the first cavity, and the apex of the second cavity ( The position of the upper end is lower than the position of the apex (upper end) of the first cavity.
Thus, the dielectric film having a cavity at a position corresponding to the concave portion has a cavity when the dielectric film has two layers (first cavity) rather than a cavity when the dielectric film has one layer (first cavity) ( The position of the apex (upper end) of the cavity can be lowered in the second cavity). Therefore, the thickness of the dielectric film is smaller in the configuration with two dielectric films (the configuration of the present invention) than in the configuration with one dielectric film (the configuration described in Patent Document 1). be able to. That is, compared with the method described in Patent Document 1, the dielectric films (first dielectric film and second dielectric film) stacked on the pixel electrode can be thinned, and thus supplied from the pixel electrode. Display signal deterioration (effective voltage drop) can be suppressed.

  Application Example 2 In the method of manufacturing the electro-optical device according to the application example described above, the step of forming the first dielectric film and the step of forming the second dielectric film include a material gas containing organooxysilane It is preferable that the silicon oxide film be formed by plasma CVD using a silicon oxide film.

  Plasma CVD using a material gas containing organooxysilane is a film forming method having excellent step coverage, and can uniformly cover the inside (side wall, bottom surface) of the recess with a predetermined film thickness. The silicon oxide film (first dielectric film) uniformly covers the inside of the first recess with a predetermined film thickness, so that the first cavity is easily formed at a position corresponding to the first recess. be able to. The silicon oxide film (second dielectric film) uniformly covers the inside of the second recess formed by opening the first cavity with a predetermined film thickness, thereby corresponding to the second recess. The second cavity can be easily formed at the position.

  Application Example 3 In the method of manufacturing an electro-optical device according to the application example described above, the step of planarizing the first dielectric film is performed by either chemical mechanical polishing or anisotropic dry etching. It is preferable to provide the process.

  The first dielectric film is thinned (thinned) by a flattening process to expose (open) the sealed first cavity to form a second recess. The first dielectric film is parallel to the surface of the first dielectric film in addition to the direction orthogonal to the surface of the first dielectric film (the surface of the substrate on which the first dielectric film is formed). When the film thickness is also reduced, the opening dimension of the second recess (the dimension in the parallel direction) is increased by the film reduction in the parallel direction. Therefore, in order to reduce the opening size of the second recess, it is preferable that the planarization treatment performed on the first dielectric film suppresses the film reduction in the direction parallel to the surface of the first dielectric film. . In chemical mechanical polishing or anisotropic dry etching, film thickness reduction proceeds in a direction perpendicular to the surface of the first dielectric film, and film thickness reduction in a direction parallel to the surface of the first dielectric film is suppressed. The Therefore, the planarization treatment applied to the first dielectric film is preferably a chemical mechanical polishing method or an anisotropic dry etching method.

  Application Example 4 In the method of manufacturing the electro-optical device according to the application example, the second dielectric film is thinned in the second dielectric film in a range where the second cavity is not exposed. It is preferable that a second planarization process is performed, and the second planarization process includes a polishing step and a step of etching the polished surface after the polishing step.

  Since the method of manufacturing the electro-optical device described in the above application example includes a polishing step and a step of etching the polishing surface, the fine scratches on the polishing surface generated in the polishing step can be reduced by etching. it can. That is, the polished surface of the second dielectric film can be finished to a smoother surface.

  Application Example 5 A method of manufacturing an electro-optical device according to this application example includes a pixel switching element, a conductive film formed above the pixel switching element, a contact hole, and formed above the conductive film. An insulating film, a pixel electrode formed above the insulating film, a first dielectric film formed above the pixel electrode, and a second dielectric film formed above the first dielectric film. A part of the upper surface of the insulating film, wherein the pixel switching element and the pixel electrode are electrically connected to each other through the contact hole. Forming a pixel electrode having a first recess at a position corresponding to the contact hole so as to cover the sidewall of the insulating film in which the contact hole is formed and the conductive film exposed from the contact hole. Forming the first silicon oxide film having a second recess at a position corresponding to the first recess by plasma CVD using a material gas containing silicon hydride and covering the pixel electrode; Forming the second silicon oxide film having a cavity sealed at a position corresponding to the second concave portion by covering the first silicon oxide film by plasma CVD using a material gas containing And a step of performing a flattening process for thinning the second silicon oxide film within a range in which the hollow is not exposed.

  According to this application example, the pixel electrode is formed so as to cover the side wall in which the contact hole of the insulating film is formed and the conductive film exposed from the contact hole (the side wall and the bottom surface of the contact hole), and corresponds to the contact hole of the pixel electrode. A first recess is formed at a position to be performed. When the pixel electrode is covered with a first silicon oxide film formed by plasma CVD using a material gas containing silicon hydride, a second recess is formed at a position corresponding to the first recess. Plasma CVD using a material gas containing silicon hydride is a film forming method inferior in step coverage, and an overhang having a thick film is formed near the top of the first recess. This overhang forms a second recess with a smaller opening size. Further, when the first silicon oxide film is covered with a second silicon oxide film formed by plasma CVD using a material gas containing organooxysilane, a sealed cavity is formed at a position corresponding to the second recess. Is done. Plasma CVD using a material gas containing organooxysilane has excellent step coverage as compared with the case where silicon hydride is used as the material and gas, and the inner side (side wall, bottom surface) of the second recess has a predetermined film thickness. It can be covered uniformly. That is, the second silicon oxide film uniformly covers the inside of the second recess with a predetermined film thickness, thereby reducing the cavity formed at the position corresponding to the second recess and the position of the apex of the cavity. Can be lowered. Since the position of the apex of the cavity is low, the thickness of the second silicon oxide film can be reduced if the second silicon oxide film is planarized so as not to expose the cavity. Since the second silicon oxide film formed on the pixel electrode can be thinned, the deterioration of the display signal applied from the pixel electrode (decrease in effective voltage) is reduced, and a high-quality display can be provided.

  Application Example 6 In the method of manufacturing an electro-optical device according to the application example described above, it is preferable that the step of performing the planarization includes a polishing step and a step of etching the polishing surface after the polishing step. .

  Since the method of manufacturing the electro-optical device described in the above application example includes a polishing step and a step of etching the polishing surface, the fine scratches on the polishing surface generated in the polishing step can be reduced by etching. it can. That is, the polished surface of the second silicon oxide film can be finished to a smoother surface.

  Application Example 7 An electro-optical device according to this application example includes a pixel switching element, a conductive film formed above the pixel switching element, and an insulating film having a contact hole and formed above the conductive film. And covering a part of the upper surface of the insulating film, a sidewall of the insulating film in which the contact hole is formed, and the conductive film exposed from the contact hole, and electrically connecting the pixel switching element through the contact hole. First pixel electrode formed by plasma CVD using a material gas containing silicon hydride and a material gas containing silicon hydride, covering the pixel electrode, and having a second recess formed at a position corresponding to the first recess It is formed by plasma CVD using a silicon oxide film and a material gas containing organooxysilane, covers the first silicon oxide film, and corresponds to the second recess. Wherein the sealed cavity in a position that is provided with a second silicon oxide film formed, a.

  According to the electro-optical device according to this application example, the side wall in which the contact hole of the insulating film is formed and the conductive film exposed from the contact hole (the side wall and the bottom surface of the contact hole) are covered with the pixel electrode to correspond to the contact hole. A first recess is formed at the position, and the opening size of the top of the first recess is smaller than the opening size of the top of the contact hole. A pixel electrode is covered with a first silicon oxide film formed by plasma CVD using a material gas containing silicon hydride, and a second recess is formed at a position corresponding to the first recess. Plasma CVD using a material gas containing silicon hydride is a film formation method inferior to the step coverage, and a thick overhang is formed at the top of the first recess. By this overhang, a second recess having a smaller opening size can be formed. A second silicon oxide film formed by plasma CVD using a material gas containing organooxysilane is covered with the first silicon oxide film to form a sealed cavity at a position corresponding to the second recess. Plasma CVD using a material gas containing organooxysilane is a film forming method with excellent step coverage, and can uniformly cover the inside (side wall, bottom surface) of the second recess with a predetermined film thickness. That is, the second silicon oxide film uniformly covers the inside of the second recess with a predetermined film thickness, so that the cavity formed at the position corresponding to the second recess is reduced, and the position of the apex of the cavity is also Lower. That is, the second silicon oxide film that forms the cavity can be thinned. Therefore, the second silicon oxide film on the pixel electrode can be thinned, and deterioration of the display signal supplied from the pixel electrode (decrease in effective voltage) can be suppressed.

  Application Example 8 An electronic apparatus according to this application example includes the electro-optical device described in the application example.

  Since the electronic apparatus according to this application example includes the electro-optical device described in the above application example, an electronic apparatus having a high-quality display function, such as a projector, a direct-view TV, a mobile phone, a portable audio apparatus, Various electronic devices such as a personal computer, a video camera monitor, a car navigation device, an electronic notebook, a calculator, a workstation, a video phone, a POS terminal, and a digital still camera can be realized.

(A) is a schematic plan view which shows the structure of a liquid crystal device, (b) is a schematic sectional drawing of the liquid crystal device along the H-H 'line | wire of (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device according to the first embodiment. FIG. 2 is a schematic plan view of a plurality of adjacent pixels in the first embodiment. FIG. 4 is a schematic sectional view taken along line A-A ′ of FIG. 3. FIG. 5 is a schematic cross-sectional view of a region C (pixel contact region) surrounded by a broken line in FIG. 4. 3 is a flowchart showing a process for forming a pixel contact region in the first embodiment. FIG. 7 is a schematic cross-sectional view showing a state of a pixel contact region after undergoing each step of FIG. 6. FIG. 6 is a schematic cross-sectional view illustrating a state of a pixel contact region in a liquid crystal device according to a second embodiment. 9 is a flowchart showing a process for forming a pixel contact region in the second embodiment. FIG. 10 is a schematic cross-sectional view illustrating a state of a pixel contact region after undergoing each process of FIG. 9. Sectional drawing after depositing a silicon oxide film of about 1000 nm on the board | substrate with which the recessed part was formed. The top view which shows the structure of the optical system of the 3 plate type projector as an electronic device.

  Embodiments of the present invention will be described below with reference to the drawings. Such an embodiment shows one aspect of the present invention and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. In each of the following drawings, the scale of each layer or each part is made different from the actual scale so that each layer or each part can be recognized on the drawing.

(Embodiment 1)
"Outline of electro-optical device"
A liquid crystal device 100 that is an example of an electro-optical device according to this embodiment is a reflective liquid crystal device that includes a thin film transistor (hereinafter referred to as TFT) 30 that is an example of a pixel switching element. The liquid crystal device 100 can be suitably used as, for example, a reflection type light modulation element of a liquid crystal projector described later.

First, the overall configuration of the liquid crystal device 100 according to the present embodiment will be described with reference to FIGS. 1 and 2.
1A is a schematic plan view showing the configuration of the liquid crystal device, and FIG. 1B is a schematic cross-sectional view of the liquid crystal device taken along line HH ′ of FIG. 1A. FIG. 3 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 according to this embodiment includes an element substrate 10 and a counter substrate 20 that are disposed to face each other, a liquid crystal layer 50 that is sandwiched between the pair of substrates, and the like. have.

  The element substrate 10 is made of, for example, a transparent quartz substrate, a glass substrate, or an opaque silicon substrate, and is larger than the counter substrate 20. In addition, the element substrate 10 is bonded to the counter substrate 20 via a sealing material 52 that is arranged without a break along the outer periphery of the counter substrate 20. A liquid crystal having negative dielectric anisotropy is sealed in a region surrounded by the sealing material 52 to form a liquid crystal layer 50.

In the sealing (filling) of liquid crystal between a pair of substrates in the present embodiment, a sealing material 52 is disposed along the outer periphery of one of the pair of substrates, and a predetermined amount of liquid crystal is placed inside the sealing material 52. An ODF (One Drop Fill) method is adopted in which one substrate on which the liquid crystal is dropped and the other substrate are bonded together under reduced pressure.
As the sealing material 52, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. Spacers (not shown) are mixed in the sealing material 52 to keep the distance between the pair of substrates constant.

On the inner side of the sealing material 52, a parting portion 53 is provided so as to surround the pixel region E.
In the pixel region E, a plurality of pixels P are arranged in a matrix. The pixel region E may include a plurality of dummy pixels arranged so as to surround a plurality of effective pixels P that contribute to display.

  A data line driving circuit 101 is provided between the sealing material 52 along one side of the element substrate 10 and the one side. Further, an inspection circuit 103 is provided between the sealing material 52 and the pixel region E along the other one side facing the one side. Further, a scanning line driving circuit 104 is provided between the sealing material 52 and the pixel region E along the other two sides orthogonal to the one side and facing each other. Between the sealing material 52 and the pixel region E along the other one side facing the one side, a plurality of wirings 105 that connect the two scanning line driving circuits 104 are provided. Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 104 are connected to a plurality of external connection terminals 102 arranged along the one side.

  Hereinafter, the direction along the one side is the X direction, the direction along the other two sides orthogonal to the one side and facing each other is the Y direction, and the X direction and the Y direction are orthogonal to the element. The direction from the substrate 10 toward the counter substrate 20 will be described as the Z direction.

  As shown in FIG. 1B, on the surface of the element substrate 10 on the liquid crystal layer 50 side, the reflective pixel electrode 9 provided for each pixel P, the TFT 30, and the alignment film covering the plurality of pixel electrodes 9 are provided. 18 etc. are formed. The TFT 30 is an example of the “pixel switching element” in the present invention. Details of the pixel P will be described later.

  The counter substrate 20 is made of, for example, a transparent material such as a quartz substrate or a glass substrate, and is provided on the surface on the liquid crystal layer 50 side across the parting portion 53, the planarizing layer 22 covering the parting portion 53, and the pixel region E. The counter electrode 21, the dielectric layer 19 covering the counter electrode 21, the alignment film 25, and the like are formed.

  The parting part 53 is made of, for example, a light-shielding metal or metal oxide, and is provided at a position overlapping the scanning line driving circuit 104 and the inspection circuit 103 in a plan view as shown in FIG. Thus, the light incident from the counter substrate 20 side is shielded, and the malfunction of these drive circuits is prevented. Further, unnecessary stray light is shielded from entering the pixel region E to ensure high contrast in the display of the pixel region E.

  The planarization layer 22 can be formed by using, for example, a silicon oxide film that is a light-transmitting inorganic insulating material by using an atmospheric pressure or a low pressure CVD method. The film thickness is such that unevenness on the surface caused by the formation of the parting portion 53 on the counter substrate 20 can be alleviated.

The counter electrode 21 is made of a transparent conductive material such as ITO (Indium Tin Oxide). The counter electrode 21 is electrically connected to the routing wiring on the element substrate 10 side by the vertical conduction portions 106 provided at the four corners of the counter substrate 20.
The dielectric layer 19 is made of, for example, a silicon oxide film and has a role of making the work function on the pixel electrode 9 side and the work function on the counter electrode 21 side coincide with each other or approximately the same. The dielectric layer 19 may be composed of a plurality of dielectric films.

  The alignment film 18 on the element substrate 10 side and the alignment film 25 on the counter substrate 20 side are set based on the optical design of the liquid crystal device 100, and in this embodiment, an oblique deposition film of an inorganic material such as a silicon oxide film ( Inorganic alignment film). Liquid crystal molecules having negative dielectric anisotropy are aligned substantially perpendicularly with a pretilt in a predetermined direction with respect to the alignment film surface. The alignment films 18 and 25 may be organic alignment films such as polyimide.

  The counter substrate 20 has a recess 20 a formed in a portion overlapping the sealing material 52 in a planar manner. The recess 20a is formed from the outside of the parting portion 53 of the counter substrate 20 to the outer periphery of the substrate. The planarization layer 22, the counter electrode 21, the dielectric layer 19, and the alignment film 25 are also formed in the recess 20a. When the thickness of the liquid crystal layer 50 when the element substrate 10 and the counter substrate 20 are arranged to face each other with the liquid crystal layer 50 interposed therebetween is d, the sealing material 52 includes the liquid crystal layer 50 in consideration of the depth of the recess 20a. A spacer (not shown) having a diameter larger than the thickness d is included. According to such a cross-sectional structure of the counter substrate 20, the element substrate 10 and the counter substrate 20 are disposed to be opposed to each other using the sealing material 52 including a spacer having a diameter larger than the thickness d of the liquid crystal layer 50. Therefore, variation in the thickness of the liquid crystal layer 50 can be suppressed.

  As shown in FIG. 2, the liquid crystal device 100 includes a plurality of scanning lines 11 and a plurality of data lines 6 a as signal lines that are insulated and orthogonal to each other at least in the pixel region E, and capacitance lines parallel to the scanning lines 11. 60. The arrangement of the capacitor line 60 is not limited to this, and may be arranged so as to be parallel to the data line 6a.

  A pixel electrode 9, a TFT 30, and a storage capacitor 70 are provided in a region divided by the scanning line 11 and the data line 6a, and these constitute a pixel circuit of the pixel P.

  The scanning line 11 is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the source of the TFT 30. The pixel electrode 9 is electrically connected to the drain of the TFT 30.

  The data line 6a is connected to the data line driving circuit 101 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 101 to the pixels P. The scanning lines 11 are connected to a scanning line driving circuit 104 (see FIG. 1), and supply scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 104 to each pixel P. The image signals D1 to Dn supplied from the data line driving circuit 101 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 104 supplies the scanning signals SC1 to SCm to the scanning line 11 at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 9 at a predetermined timing. It is the structure written in. A predetermined level of the image signals D1 to Dn written to the liquid crystal layer 50 through the pixel electrode 9 is between the pixel electrode 9 and the counter electrode 21 functioning as a common electrode disposed to face the liquid crystal layer 50. Is held for a certain period.

  In order to prevent the retained image signals D1 to Dn from leaking (deteriorating), a storage capacitor 70 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the counter electrode 21. The storage capacitor 70 is provided between the drain of the TFT 30 and the capacitor line 60.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG.

  Such a liquid crystal device 100 is of a reflective type, and the optical design of a normally black mode in which the reflectance is minimized when no voltage is applied to the pixel P or a normally white mode in which the reflectance is maximized when no voltage is applied. Is adopted. Depending on the optical design, a polarizing element is arranged on the light incident side (emission side).

`` Pixel configuration ''
Next, a specific configuration of the pixel P that realizes the above-described operation will be described with reference to FIGS.

  FIG. 3 is a schematic plan view of a plurality of adjacent pixels, and FIG. 4 is a schematic cross-sectional view taken along the line A-A ′ of FIG. 3. In FIG. 3, for convenience of explanation, illustration of a portion located above the pixel electrode 9 is omitted.

  In FIG. 3, a plurality of pixel electrodes 9 are provided in a matrix on the element substrate 10. A data line 6 a and a scanning line 11 are provided along the vertical and horizontal boundaries of the pixel electrode 9. In other words, the scanning line 11 extends along the X direction, and the data line 6 a extends along the Y direction so as to intersect the scanning line 11. The scanning line 11 includes a first scanning line 11a also serving as a lower light-shielding film, and a second scanning line 11b formed integrally with the gate electrode 3a (gate), and includes two scanning lines along the X direction. Heavy wiring. A pixel switching TFT 30 is provided at each of the locations where the scanning line 11 and the data line 6a intersect each other. Thus, since the first scanning line 11a and the second scanning line 11b are double-wired, the electrical resistance of the scanning line 11 can be lowered as a whole. In addition, even if one of the first scanning line 11a and the second scanning line 11b has a defect such as disconnection, the other can be made to function redundantly, so that the reliability of the liquid crystal device 100 can be improved. it can.

Hereinafter, the stacked structure of the pixels P provided on the base material of the element substrate 10 will be described in order from the first layer.
The first layer is provided with the first scanning line 11a with a thickness of, for example, 200 nm made of conductive polysilicon, refractory metal, refractory metal silicide, or the like. The first scanning line 11a has a portion extending along the X direction as shown in FIG. 3, and a portion extending from the portion along the Y direction so as to overlap the channel region 1a ′ of the TFT 30. .

  As shown in FIG. 3, the first scanning line 11a includes a channel region 1a ′ of the TFT 30, a data line side LDD region 1b and a pixel electrode side LDD region 1c, a data line side source / drain region 1d (source), and a pixel electrode. It is formed so as to include a region facing the side source / drain region 1e (drain). The first scanning line 11 a is a light shielding film that shields the channel region 1 a ′ of the TFT 30 and is disposed below the TFT 30.

  In FIG. 4, the first scanning line 11 a arranged in the first layer and the second layer TFT 30 are insulated by the base insulating film 12. In addition to the function of insulating the TFT 30 from the first scanning line 11a, the base insulating film 12 is formed on the entire surface of the element substrate 10, so that the surface of the element substrate 10 is roughened when it is polished, or remains after cleaning. It has a function of preventing the deterioration of the characteristics of the pixel switching TFT 30 due to. The base insulating film 12 has a two-layer structure in which, for example, a TEOS (ethyl silicate) film is laminated with a film thickness of 300 nm and an HTO (High Temperature Oxide) film is laminated with a film thickness of 50 nm.

  In the second layer, the semiconductor film 1a of the TFT 30 is provided, and the gate electrode 3a is provided above the semiconductor film 1a via the gate insulating film 2.

  As shown in FIGS. 3 and 4, the semiconductor film 1a is made of, for example, polysilicon, has a film thickness of 55 nm, has a channel region 1a ′ having a channel length along the Y direction, a data line side LDD region 1b, and It comprises a pixel electrode side LDD region 1c, a data line side source / drain region 1d, and a pixel electrode side source / drain region 1e. That is, the TFT 30 has an LDD structure.

  The data line side source / drain region 1d and the pixel electrode side source / drain region 1e are formed substantially in mirror symmetry along the Y direction with respect to the channel region 1a '. The data line side LDD region 1b is formed between the channel region 1a 'and the data line side source / drain region 1d. The pixel electrode side LDD region 1c is formed between the channel region 1a 'and the pixel electrode side source / drain region 1e. The data line side LDD region 1b, the pixel electrode side LDD region 1c, the data line side source / drain region 1d, and the pixel electrode side source / drain region 1e are impurity regions formed by implanting impurities into the semiconductor film 1a by, for example, an ion implantation method. is there. The TFT 30 preferably has an LDD structure, but may have an offset structure in which no impurity is implanted into the data line side LDD region 1b and the pixel electrode side LDD region 1c.

  3 and 4, the second scanning line 11b is formed integrally with the gate electrode 3a by stacking, for example, conductive polysilicon and tungsten silicide (WSi) with a film thickness of 60 nm. As shown in FIG. 3, in the second scanning line 11b, a portion extending in the Y direction so as to overlap the channel region 1a ′ in plan view functions as the gate electrode 3a and along the Y direction. It has a portion extending in the X direction in parallel with the first scanning line 11a from the extending portion.

  In the second scanning line 11 b, the gate electrode 3 a formed integrally with the second scanning line 11 b is insulated from the semiconductor film 1 a by the gate insulating film 2. In the present embodiment, as shown in FIGS. 3 and 4, a contact hole 810 is opened in the base insulating film 12 on the side of the semiconductor film 1 a. The gate electrode 3a is continuously formed up to the contact hole 810 and is electrically connected to the first scanning line 11a.

  In FIG. 4, an interlayer insulating film 41 that provides interlayer insulation between the second layer and the third layer is provided above the TFT 30. The interlayer insulating film 41 is formed of a TEOS film having a thickness of 300 nm, for example. A contact hole 83 for electrically connecting the pixel electrode side source / drain region 1 e and the lower capacitor electrode 71 of the storage capacitor 70 is opened in the interlayer insulating film 41. Further, a contact hole 81 for electrically connecting the data line side source / drain region 1d and the data line 6a is also opened.

  In the third layer above the interlayer insulating film 41, a storage capacitor 70 having a lower capacitor electrode 71 and an upper capacitor electrode 60a facing the lower capacitor electrode 71 through the dielectric film 75 is formed. In the storage capacitor 70, the scanning line 11 and the data line 6a are formed in plan view in order to increase the area of the region where the lower capacitor electrode 71, the dielectric film 75, and the upper capacitor electrode 60a overlap and increase the capacitance value. It is arranged so as to protrude from the region to the vicinity of the center of the pixel electrode 9.

  The upper capacitor electrode 60 a is formed integrally with the capacitor line 60. The capacitor line 60 has, for example, a three-layer structure in which an aluminum (Al) film having a thickness of 150 nm is sandwiched between titanium nitride (TiN) films having a thickness of 50 nm and 100 nm. Although the detailed illustration of the capacity line 60 is omitted, the capacity line 60 extends from the display area E in which the pixel electrode 9 is disposed, is electrically connected to a constant potential source, and has a fixed potential. Maintained. As shown in FIG. 3, the capacitor line 60 extends along the Y direction so as to overlap the data line side LDD region 1b, the pixel electrode side LDD region 1c, and the pixel electrode side source / drain region 1e on the semiconductor film 1a. A region extending in the X direction from the portion and overlapping with the lower capacitor electrode 71 is an upper capacitor electrode 60a. Therefore, the upper capacitor electrode 60a functions as a fixed potential side capacitor electrode maintained at a fixed potential.

  The lower capacitor electrode 71 is made of conductive polysilicon with a film thickness of 100 nm, for example. In FIG. 3, the lower capacitor electrode 71 has a portion extending in each of the Y direction and the X direction so as to overlap the upper capacitor electrode 60a. The portion extending in the Y direction overlaps with the pixel electrode side source / drain region 1 e and is electrically connected through the contact hole 83. The lower capacitor electrode 71 is electrically connected to the fourth relay layer 93 through the contact hole 84 in a portion extending in the X direction. The relay layer 93 is electrically connected to the fifth relay layer 67 through the contact hole 85. Further, the relay layer 67 is electrically connected to the pixel electrode 9 through the contact hole 86. Accordingly, the lower capacitor electrode 71 functions as a pixel potential side capacitor electrode maintained at the pixel potential.

  The dielectric film 75 has a two-layer structure in which, for example, an HTO film having a thickness of 4 nm and a silicon nitride (SiN) film having a thickness of 15 nm are stacked.

  In FIG. 4, on the upper layer side of the storage capacitor 70, an interlayer insulating film 42 that insulates between the third layer and the fourth layer is formed of a TEOS film having a thickness of 400 nm, for example. The contact hole 84 is opened so as to penetrate the interlayer insulating film 42 and reach the surface of the lower capacitor electrode 71. The contact hole 81 is opened through the interlayer insulating films 42 and 41 and the gate insulating film 2 and reaches the surface of the semiconductor film 1a.

3 and 4, the data line 6a and the relay layer 93 are provided in the fourth layer. In FIG. 4, the data line 6 a is electrically connected to the data line side source / drain region 1 d of the semiconductor film 1 a through the contact hole 81. The relay layer 93 is electrically connected to the lower capacitor electrode 71 through the contact hole 84. For the data line 6a and the relay layer 93, for example, a titanium (Ti) film having a thickness of 20 nm, a TiN film having a thickness of 50 nm, an Al film having a thickness of 350 nm, and a TiN film having a thickness of 150 nm are stacked in this order. It has a four-layer structure.
In the region corresponding to the contact hole 84, the upper capacitor electrode 60a and the dielectric film 75 are removed by etching (opening) so that the relay layer 93 and the upper capacitor electrode 60a are not short-circuited.

  In FIG. 4, an interlayer insulating film 43 that insulates between the fourth layer and the fifth layer is formed of a TEOS film having a film thickness of 600 nm, for example, above the data line 6a and the relay layer 93. The contact hole 85 is opened through the interlayer insulating film 43 and reaches the surface of the relay layer 93. Preferably, the surface of the interlayer insulating film 43 is planarized by, for example, a CMP (Chemical Mechanical Polishing) method.

  In the fifth layer, a shield layer 65 and a relay layer 67 are provided. In FIG. 3, the shield layer 65 extends in the same direction as the data line 6a, that is, along the Y direction. In the semiconductor film 1a, the data line 6a and the shield are formed in regions facing the channel region 1a ′, the data line side LDD region 1b and the pixel electrode side LDD region 1c, and the data line side source / drain region 1d and the pixel electrode side source / drain region 1e. Layer 65 is wired. Therefore, light traveling from the upper layer side with respect to the semiconductor film 1a can be shielded by the data line 6a and the shield layer 65.

In FIG. 4, the relay layer 67 is preferably formed in the same layer as the shield layer 65, is electrically connected to the pixel electrode 9, and relays the electrical connection between the pixel electrode 9 and the relay layer 93. . The shield layer 65 and the relay layer 67 have a two-layer structure in which, for example, an Al film having a thickness of 350 nm and a TiN film having a thickness of 150 nm are stacked.
The relay layer 67 is an example of the “conductive film” in the present invention.

In FIG. 4, on the upper layer side of the shield layer 65 and the relay layer 67, an interlayer insulating film 44 for interlayer insulation between the fifth layer and the sixth layer is, for example, a TEOS film having a film thickness of 600 nm and a film thickness of 75 nm. It is formed by a two-layer structure made of a BSG (boron silicate glass) film. The contact hole 86 is opened through the interlayer insulating film 44 and reaches the surface of the relay layer 67. The interlayer insulating film 44 is flattened so as to have a flat surface. As described above, the relay layer 67 and the pixel electrode 9 are electrically connected through the contact hole 86.
The interlayer insulating film 44 is an example of the “insulating film” in the present invention, and the contact hole 86 is an example of the “contact hole” in the present invention.

  3 and 4, the pixel electrode 9 is formed on the sixth layer. As shown in FIG. 4, the pixel electrode 9 is relayed through the contact holes 83, 84, 85, 86 by the relay layer 67 and the relay layer 93 and the lower capacitor electrode 71, and the pixel electrode of the semiconductor film 1 a. It is electrically connected to the side source / drain region 1e.

In order to suppress the risk of damage to the storage capacitor 70 in the process of forming the contact hole 86, the contact hole 86 is located at a position where it does not overlap the storage capacitor 70 in a plane, that is, at the approximate center of the pixel P (pixel electrode 9). Is arranged. Note that the contact hole 86 may be disposed so as to overlap the pixel electrode 9 in a planar manner, and may be disposed, for example, at the peripheral edge of the pixel electrode 9.
Note that a dielectric film (for example, silicon nitride) having a high refractive index may be laminated on the dielectric layer 46 to form a dielectric multilayer film, which may be a reflection-enhancing film that improves the brightness of reflected light from the pixel electrode 9. Further, silicon oxide may be formed as an insulating film on the dielectric film having a high refractive index.

  In FIG. 4, the pixel electrode 9 is formed so as to cover the side wall and the bottom surface of the contact hole 86, and a recess 90 is formed at a position corresponding to the contact hole 86. The pixel electrode 9 is covered with a dielectric layer 46, and a sealed cavity 95 is formed at a position corresponding to the recess 90.

The dielectric layer 46 is covered with the alignment film 18. As described above, the alignment film 18 is an obliquely deposited film (inorganic alignment film) of an inorganic material such as a silicon oxide film. The dielectric layer 46 is a base film for the alignment film 18 and has a role of making the work function on the pixel electrode 9 side coincide with or similar to the work function on the counter electrode 21 side.
Hereinafter, a region where the contact hole 86 having the cavity 95 is formed is referred to as a pixel contact region.

"Outline of pixel contact area"
FIG. 5 is a schematic cross-sectional view corresponding to a region C surrounded by a broken line in FIG. 4, that is, a schematic cross-sectional view showing a state of a pixel contact region. 5 is a cross-sectional view of the contact hole 86 along the Y direction. Hereinafter, an outline of the pixel contact region will be described with reference to FIG.

  In FIG. 5, a contact hole 86 is formed in the interlayer insulating film 44 disposed above the TFT 30. The pixel electrode 9 includes a part of the upper surface of the interlayer insulating film 44 and the bottom surface of the contact hole 86 (the surface of the relay layer 67, the exposed portion of the relay layer 67 from the interlayer insulating film 44) and the side wall (the side wall of the interlayer insulating film 44). ) And a recess 90 is formed at a position corresponding to the contact hole 86. The pixel electrode 9 is made of a conductive material having reflectivity.

  The dielectric layer 46 includes a first dielectric film 46 a formed in contact with the pixel electrode 9 and a second dielectric film 46 b formed in contact with the alignment film 18. The first dielectric film 46a covers the side wall and bottom surface of the recess 90 (the surface of the pixel electrode 9 formed in the contact hole 86). A recess 91 is formed by the upper surface of the first dielectric film 46 a at a position corresponding to the recess 90. The second dielectric film 46b includes an upper surface of the first dielectric film 46a formed above the interlayer insulating film 44, and sidewalls and bottom surfaces of the recess 91 (of the first dielectric film 46a formed in the recess 90). Surface). The opening of the recess 91 is closed by the second dielectric film 46 b, and a sealed cavity 95 is formed at a position corresponding to the recess 91.

  The first dielectric film 46a is an example of the “first dielectric film” in the present invention, and the second dielectric film 46b is an example of the “second dielectric film” in the present invention. The recess 90 is an example of the “first recess” in the present invention, the recess 91 is an example of the “second recess” in the present invention, and the cavity 95 is an example of the “second cavity” in the present invention. It is.

"Liquid crystal device manufacturing method"
Next, a method for manufacturing the liquid crystal device 100 relating to the pixel contact region (region C in FIG. 4), which is a characteristic part of the present invention, will be described. Further, the manufacturing method of the liquid crystal device 100 other than the pixel contact region uses a known technique, and a description thereof is omitted.

FIG. 6 is a flowchart showing a process for forming the pixel contact region. FIG. 7 is a schematic cross-sectional view showing the state of the pixel contact region after the respective steps shown in FIG.
In FIG. 7, L1 indicates the opening size (length in the Y direction) of the top of the contact hole 86, L2 indicates the opening size of the top of the recess 90, and L3 indicates the opening size of the top of the recess 91. Further, H1 indicates the height of the apex (upper end) of the cavity 94 (distance in the Z direction from the surface of the pixel electrode 9), and H2 indicates the height of the apex (upper end) of the cavity 95.
Hereinafter, an outline of a method for manufacturing a liquid crystal device in the pixel contact region will be described with reference to FIGS.

  In step S <b> 1 of FIG. 6, the interlayer insulating film 44 is etched by a known technique such as dry etching to form a contact hole 86 that penetrates the interlayer insulating film 44. The film thickness of the interlayer insulating film 44 is approximately 700 nm.

  FIG. 7A shows the state after step S1. The opening dimension L1 at the top of the contact hole 86 is approximately 1000 nm.

  In step S2 of FIG. 6, a conductive material is formed to cover the interlayer insulating film 44 and the contact hole 86, and is patterned using a known technique, thereby forming the pixel electrode 9 having reflectivity. The pixel electrode 9 is formed so as to cover a part of the interlayer insulating film 44 and the side wall and bottom surface of the contact hole 86 (the surface of the relay layer 67). The pixel electrode 9 is composed of titanium having a thickness of approximately 50 nm in contact with the relay layer 67 and aluminum having a thickness of approximately 150 nm in contact with the first dielectric film 46a.

  FIG. 7B shows the state after step S2. Since the film thickness of the pixel electrode 9 covering the contact hole 86 is sufficiently smaller than the dimension of the contact hole 86, the pixel electrode 9 is formed to cover the side wall and the bottom surface of the contact hole 86 and corresponds to the contact hole 86. A recess 90 is formed at the position. The opening dimension L2 at the top of the recess 90 is smaller than the opening dimension L1 at the top of the contact hole 86, and is approximately 700 nm to 800 nm.

In step S3 of FIG. 6, the first dielectric film 46a is formed to cover the surface of the pixel electrode 9 and the bottom and side walls of the recess 90. The first dielectric film 46a is formed by a chemical vapor deposition method in which a material gas is chemically reacted in a gas phase and a reaction product is deposited on a substrate. Specifically, the first dielectric film 46a is a silicon oxide film formed by plasma CVD using a material gas containing TEOS (tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ )). The film thickness of the first dielectric film 46a is approximately 1000 nm.

  FIG. 7C shows the state after step S3. The opening at the top of the recess 90 is closed with the first dielectric film 46a before the recess 90 is filled with the first dielectric film 46a, and a sealed cavity 94 is formed at a position corresponding to the recess 90. Is done. At this time, the apex (upper end) of the cavity 94 is formed to protrude outward (Z direction) from the recess 90 (formed above the uppermost surface of the pixel electrode 9). Outside the recess 90, the width (length and diameter in the Y direction) of the cavity 94 gradually decreases in the Z direction, forming a pointed apex in the Z direction. The apex of the cavity 94 is formed at a position protruding from the surface of the pixel electrode 9 in the Z direction. The height H1 of the apex of the cavity 94 is approximately 400 nm to 500 nm from the surface of the pixel electrode 9.

Plasma CVD using a material gas containing TEOS is a film forming method with excellent step coverage, and covers the inside (side wall, bottom) of the recess 90 with a first dielectric film 46a having a relatively uniform film thickness. be able to. As a result, the cavity 94 can be made smaller as compared with a film forming method having inferior step coverage. The cavity 94 is exposed (opened) in the next step (step S4) and becomes a recess 91. However, since the cavity 94 is small, the recess 91 has a small opening dimension L3. Therefore, the first dielectric film 46a is preferably formed by a film forming method having excellent step coverage, that is, plasma CVD using a material gas containing TEOS. The material gas for forming the first dielectric film 46a is preferably organic oxysilane. Besides TEOS described above, TRIE (triethoxysilane (SiH (OC ₂ H ₅ ) ₃ )), TMS (tetramethoxysilane (Si) _{(OCH 3) 4)),} C 2 H 5 Si (OC 2 H 5) 3, Si (OC 3 H 7) 4 and the like can be used.
The cavity 94 is an example of the “first cavity” in the present invention.

  In step S4 of FIG. 6, a flattening process is performed to thin the portion of the first dielectric film 46a formed above the pixel electrode 9, and the sealed cavity 94 is exposed in the first dielectric film 46a. . The first dielectric film 46a is thinned (decreased) to a thickness of approximately 100 nm to 200 nm on the pixel electrode 9 by CMP (Chemical Mechanical Polishing). In CMP, a flat polished surface can be obtained at a high speed due to the balance between the chemical action of the chemical components contained in the polishing liquid and the mechanical action due to the relative movement of the abrasive and the polished surface. Specifically, in CMP, polishing is performed while relatively rotating a surface plate on which a polishing cloth (pad) made of nonwoven fabric, polyurethane foam, porous fluororesin, or the like is attached and a holder for holding the element substrate 10. .

  FIG. 7D shows the state after step S4. The first dielectric film 46a is thinned by CMP to expose (open) the sealed cavity 94, and a recess 91 is formed at a position corresponding to the recess 90. The opening dimension L3 at the top of the recess 91 is as small as approximately 200 nm to 300 nm.

  Since the purpose of step S4 is to form a recess having a small opening size, in the planarization process for thinning the first dielectric film 46a, the direction perpendicular to the surface of the first dielectric film 46a (Z direction) It is desirable to make the film thinner. For example, when a planarization process (thinning process) is performed by isotropic etching such as wet etching, the film is also reduced in the direction along the surface of the first dielectric film 46a (X direction, Y direction), and the recess 91 Since the opening dimension L3 of the top part of becomes large, it is not preferable. For this reason, as the planarization process in step S4, a method of reducing the film thickness in a direction (Z direction) perpendicular to the surface of the first dielectric film 46a, such as CMP or anisotropic dry etching, is preferable. As anisotropic dry etching, for example, RIE (reactive ion etching) can be used.

  In step S5 of FIG. 6, the second dielectric film 46b is formed on the first dielectric film 46a that has been subjected to the planarization process. The second dielectric film 46b is formed to cover the first dielectric film 46a by plasma CVD using a material gas containing TEOS. The film thickness of the second dielectric film 46b is approximately 500 nm.

  FIG. 7E shows the state after step S5. The opening 95 at the top of the recess 91 is closed with the second dielectric film 46b sooner than the inside of the recess 91 is filled with the second dielectric film 46b, and the cavity 95 is sealed at a position corresponding to the recess 91. Is formed. The above-described plasma CVD using a material gas containing TEOS is excellent in step coverage and can cover the inside (side wall, bottom surface) of the recess 91 with the second dielectric film 46b having a relatively uniform film thickness. . As a result, the volume of the cavity 95 formed at a position corresponding to the recess 91 is reduced and the apex of the cavity 95 is also reduced as compared with the film forming method having inferior step coverage.

  The volume and apex height H2 of the cavity 95 formed corresponding to the recess 91 vary depending on the opening size L3 of the top of the recess 91 and the method of forming the second dielectric film 46b. That is, when the opening dimension L3 at the top of the recess 91 is reduced and the second dielectric film 46b is formed by a film forming method having excellent step coverage, the volume of the cavity 95 and the height H2 of the apex are reduced. In the present embodiment, the height H2 of the apex of the cavity 95 is approximately 150 nm to 250 nm.

As described above, the second dielectric film 46b is preferably formed by a film forming method excellent in a film forming method having excellent step coverage, that is, plasma CVD using a material gas containing TEOS. The material gas for forming the second dielectric film 46b is preferably organic oxysilane. Besides TEOS described above, TRIE (triethoxysilane (SiH (OC ₂ H ₅ ) ₃ )), TMS (tetramethoxysilane (Si) _{(OCH 3) 4)),} C 2 H 5 Si (OC 2 H 5) 3, Si (OC 3 H 7) 4 and the like can be used.

  The cavity 94 shown in FIG. 7C corresponds to “a cavity sealed at a position corresponding to the recess” formed by a known technique. As described above, the height H1 of the apex of the cavity 94 formed by a known technique is approximately 400 nm to 500 nm. In the present invention, it is possible to reduce the height of the apex of the cavity sealed at a position corresponding to the recess by reducing the opening size of the top of the recess as compared with the known technique. The height H2 of the apex of the cavity 95 formed by the method of the present invention is approximately 150 nm to 250 nm, and is reduced to about ½ or less of the height H1 of the cavity 94 formed by a known method. .

In step S6 of FIG. 6, a planarization process for thinning the second dielectric film 46b is performed within a range that does not expose the cavity 95 sealed in the second dielectric film 46b. The flattening process for thinning the second dielectric film 46b includes a polishing process and an etching process for reducing the thickness of the polished surface by etching. Specifically, in the polishing step, the second dielectric film 46b is planarized (thin film reduction) by CMP (Chemical Mechanical Polishing). Since CMP is a mechanical polishing method, mechanical fluctuations in the polishing amount and scratches on the polished surface inevitably occur. For this reason, after performing a polishing process by CMP, an etching process for smoothing the polished surface is performed. The etching process is a process of chemically reducing the polishing surface of the second dielectric film 46b, and reduces fine scratches and the like generated by the polishing process. The amount of film can be accurately controlled. In this embodiment, the polished surface is subjected to an etching process by dry etching. This etching process may be performed by wet etching in addition to dry etching.
The planarization process for thinning the second dielectric film 46b is an example of the “second planarization process” in the present invention.

  FIG. 7F illustrates the state after step S6. When the cavity 95 is exposed, display defects such as alignment unevenness are caused. Therefore, the second dielectric film 46b needs to be thinned (thinned) within a range where the cavity 95 is not exposed. Further, when the thickness of the dielectric layer 46 composed of the first dielectric film 46 a and the second dielectric film 46 b is increased, the effective voltage applied to the liquid crystal layer 50 between the pixel electrode 9 and the counter electrode 21 is increased. It is preferable that the thickness of the dielectric layer 46 is small because it decreases. In the present embodiment, the thickness of the dielectric layer 46 is approximately 250 nm to 300 nm.

  As described above, the height from the vertex of the cavity 95 according to the present embodiment to the upper surface of the pixel electrode 9 is higher than the height H1 from the vertex of the cavity (cavity 94) formed by a known technique to the upper surface of the pixel electrode 9. Since the height H2 of the second dielectric film 46b is reduced, the height of the top of the cavity 95 is lower than the top of the cavity (cavity 94), and the thickness of the second dielectric film 46b thinned in a range where the cavity 95 is not exposed is set to be small. Can be small.

As described above, according to the liquid crystal device 100 according to the present embodiment, the following effects can be obtained.
(1) The pixel electrode 9 is covered with the first dielectric film 46a, and after the cavity 94 is formed at a position corresponding to the concave portion 90 of the pixel electrode 9, a flattening process for thinning the first dielectric film 46a is performed. The cavity 94 is exposed, and a recess 91 having a smaller opening size is formed at a position corresponding to the recess 90. Next, the first dielectric film 46 a is covered with the second dielectric film 46 b, and a cavity 95 is formed at a position corresponding to the recess 91. Since the opening dimension L2 at the top of the recess 91 is small, and the second dielectric film 46b is formed by a film forming method having excellent step coverage, a cavity formed at a position corresponding to the recess 91 is formed. 95 can be reduced, and the height H2 of the apex of the cavity 95 can be reduced. Then, the thickness of the second dielectric film 46b that has been thinned can be reduced as long as the cavity 95 is not exposed. Therefore, a decrease in effective voltage applied to the liquid crystal layer 50 between the pixel electrode 9 and the counter electrode 21 is suppressed, and a higher quality display can be provided.

  (2) The first dielectric film 46a is selectively thinned in the Z direction by CMP, and the thinning in the Y direction and the X direction is suppressed. As a result, the flattening process of the first dielectric film 46a that exposes the cavity 95 and forms the recess 91 suppresses the cavity 95 (recess 91) from spreading in the X direction and the Y direction. Can be formed.

  (3) The planarization process applied to the second dielectric film 46b includes a polishing process for mechanically reducing the film and an etching process for chemically reducing the film. In the polishing process in which the film is mechanically reduced, minute scratches are inevitably generated on the polished surface. Therefore, the scratches can be reduced by etching the polished surface, and a smoother surface can be obtained.

(Embodiment 2)
FIG. 8 is a schematic cross-sectional view showing the state of the pixel contact region in the liquid crystal device according to the second embodiment, and corresponds to FIG. FIG. 9 is a process flow showing a method of manufacturing a liquid crystal device relating to the pixel contact region, and corresponds to FIG. FIG. 10 is a schematic cross-sectional view showing the state of the pixel contact region after the respective steps shown in FIG. 9 and corresponds to FIG.
Hereinafter, with reference to FIGS. 8 to 10, the liquid crystal device 110 according to the present embodiment will be described focusing on differences from the first embodiment. Moreover, about the same component as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  The liquid crystal device 110 according to the present embodiment is different from the first embodiment in the manufacturing method of the pixel contact region, and the other configurations are the same as those in the first embodiment.

"Outline of pixel contact area"
The dielectric layer 46 includes a first dielectric film 46 a formed in contact with the pixel electrode 9 and a second dielectric film 46 b formed in contact with the alignment film 18. The first dielectric film 46 a covers the side wall and the bottom surface of the recess 90, and a recess 92 is formed at a position corresponding to the recess 90. The second dielectric film 46b is formed to cover the surface of the first dielectric film 46a and the side walls and bottom surface of the recess 92. The opening of the recess 92 is closed by the second dielectric film 46 b, and a sealed cavity 96 is formed at a position corresponding to the recess 92.
The recess 92 is an example of the “second recess” in the present invention, and the cavity 96 is an example of the “cavity” in the present invention.

"Liquid crystal device manufacturing method"
Next, a manufacturing method of the liquid crystal device 110 relating to the pixel contact region, which is a characteristic part of the present invention, will be described. Further, the manufacturing method of the liquid crystal device 110 other than the pixel contact region uses a known technique, and a description thereof is omitted.
In the present embodiment, the step of forming the first dielectric film 46a (see step S13, FIG. 9) is different from the step of forming the first dielectric film 46a in the first embodiment (see step S3, FIG. 6). Furthermore, the present embodiment is different in that the flattening process (see step S4, FIG. 6) for the first dielectric film 46a in the first embodiment is omitted. Except for these differences, the second embodiment is the same as the first embodiment.

In step S13 of FIG. 9, the first dielectric film 46a is formed to cover the surface of the pixel electrode 9 and the bottom and side walls of the recess 90. The film thickness of the first dielectric film 46a is 100 nm to 200 nm. As will be described in detail later, the first dielectric film 46a is formed by a film forming method having poor step coverage, that is, plasma CVD using a material gas containing silicon hydride. Specifically, the first dielectric film 46a is a silicon oxide film formed by plasma CVD using a material gas containing silane (SiH ₄ ). As a material gas for forming the first dielectric film 46a, disilane (Si ₂ H ₆ ) or the like can be used in addition to the silane described above. The silicon hydride in the present invention includes polysilanes such as disilane (Si ₂ H ₆ ) having a plurality of Si atoms.

  FIG. 10C shows the state after step S13. Since the film thickness of the first dielectric film 46a covering the recess 90 is sufficiently smaller than the dimension of the recess 90, the first dielectric film 46a is formed to cover the side wall and the bottom surface of the recess contact hole. A recess 92 is formed at a position corresponding to. The opening dimension L4 at the top of the recess 92 is approximately 200 nm to 300 nm.

In step S5 of FIG. 9, a second dielectric film 46b is formed to cover the first dielectric film 46a. The film thickness of the second dielectric film 46b is approximately 800 nm to 900 nm. As will be described in detail later, the second dielectric film 46b is formed by a film forming method having excellent step coverage, that is, plasma CVD using a material gas containing organooxysilane. Specifically, the second dielectric film 46b is a silicon oxide film formed by plasma CVD using a material gas containing TEOS (tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ )). The material gas for forming the second dielectric film 46b is preferably organic oxysilane. Besides TEOS described above, TRIE (triethoxysilane (SiH (OC ₂ H ₅ ) ₃ )), TMS (tetramethoxysilane (Si) _{(OCH 3) 4)),} C 2 H 5 Si (OC 2 H 5) 3, Si (OC 3 H 7) 4 and the like can be used.

  FIG. 10D shows the state after step S5. A cavity 96 is formed in the second dielectric film 46 b so as to cover the first dielectric film 46 a and be sealed at a position corresponding to the recess 92. Similar to the first embodiment, the apex of the cavity 96 is formed to protrude outward (Z direction) from the recess 92. That is, outside the recess 92, the width of the cavity 96 (the length in the Y direction) gradually decreases in the Z direction and forms a sharp apex in the Z direction. The apex of the cavity 96 is formed at a position protruding from the surface of the pixel electrode 9 in the Z direction. In the present embodiment, the height H3 of the apex of the cavity 96 is approximately 150 nm to 250 nm.

  In step S6 of FIG. 9, a planarization process for thinning the second dielectric film 46b is performed within a range in which the cavity 96 sealed in the second dielectric film 46b is not exposed. The flattening process for thinning the second dielectric film 46b includes a polishing process and an etching process for reducing the thickness of the polished surface by etching.

  FIG. 10E shows the state after step S6. When the cavity 96 is exposed, display defects such as alignment unevenness are caused. Therefore, the second dielectric film 46b is thinned (thinned) within a range where the cavity 96 is not exposed. In the present embodiment, the thickness of the dielectric layer 46 is approximately 250 nm to 300 nm.

“Method of forming first dielectric film and second dielectric film”
FIG. 11 is a cross-sectional view after a silicon oxide film having a thickness of about 1000 nm is deposited on a substrate (see FIG. 10B) on which a recess 90 is formed. In FIG. 11A, a silicon oxide film (hereinafter referred to as a silicon oxide film A) formed by the same film formation conditions as the first dielectric film 46a, that is, a film formation method inferior in step coverage, is deposited. In FIG. 11B, a silicon oxide film (hereinafter referred to as a silicon oxide film B) formed by the same film formation condition as the second dielectric film 46b, that is, a film formation method having excellent step coverage is deposited. ing.
Hereinafter, a film forming method suitable for the first dielectric film 46a and the second dielectric film 46b will be described with reference to FIG.

  In FIG. 11A, when a silicon oxide film A having a thickness of about 1000 nm is deposited on the substrate on which the recess 90 is formed by the same film formation conditions as the first dielectric film 46a, that is, by plasma CVD using a material gas containing silane. A sealed cavity 97 is formed at a position corresponding to the recess 90. In the drawing, the height of the apex of the cavity 97 (distance in the Z direction from the surface of the pixel electrode 9) is indicated by reference numeral H4.

In FIG. 11B, when a silicon oxide film B having a thickness of about 1000 nm is deposited on the substrate on which the recess 90 is formed by the same film formation conditions as the second dielectric film 46b, that is, by plasma CVD using a material gas containing TEOS. A sealed cavity 98 is formed at a position corresponding to the recess 90. In the figure, the height of the apex of the cavity 98 is indicated by reference numeral H5.
In plasma CVD, a reaction is generated from a material gas by decomposing a material gas such as silane or TEOS and an oxidizing gas (a material gas as an oxygen supply source) such as nitrous oxide (N ₂ O) or oxygen in plasma. This is a film forming method in which a precursor radical of a product (hereinafter referred to as a precursor) and an oxygen radical generated from an oxidizing gas are reacted to form a silicon oxide film. In the plasma CVD, a silicon oxide film is deposited through a process of a gas phase reaction process, a surface reaction process, and a deposited film reaction process.

  In the plasma CVD using the material gas containing silane shown in FIG. 11A, since the reactivity of silane is high, the gas phase reaction process (chemical reaction in the gas phase) becomes dominant. That is, the precursor and oxygen radicals mainly react in the gas phase, and the silicon oxide film A generated in the gas phase is deposited on the substrate. Since the silicon oxide film A generated in the vapor phase is difficult to deposit on the inside (side wall, bottom surface) of the recess 90, the deposition rate of the silicon oxide film A is small inside the recess 90 and large outside the recess 90. . Further, in the concave portion 90, the deeper the concave portion 90 (the closer to the bottom surface), the harder the silicon oxide film A generated in the vapor phase is deposited, and the lower the deposition rate of the silicon oxide film A is. As a result, the film thickness of the silicon oxide film A formed on the sidewall of the recess 90 becomes thinner as it approaches the bottom surface of the recess 90. Further, in the vicinity of the top of the concave portion 90, there is no obstacle that hinders the deposition of the silicon oxide film A, and the deposition rate is the same as the outer side of the concave portion 90. For this reason, the silicon oxide film A becomes thick near the top of the recess 90, and the silicon oxide film A is formed so as to protrude in the Y direction. As described above, since the film thickness of the silicon oxide film A covering the step region (recess 90) varies, plasma CVD using a material gas containing silane (silicon hydride) is a film forming method inferior in step coverage. Become.

The opening at the top of the recess 90 is closed with the silicon oxide film A before the inside of the recess 90 is filled with the silicon oxide film A, and a sealed cavity 97 is formed at a position corresponding to the recess 90. . The cavity 97 sharply narrows in the Z direction outside the recess 90. As a result, a vertex protruding in the Z direction is formed in the cavity 97. The apex height H4 of the cavity 97 is approximately 600 nm.
As described above, the cavity 97 in the silicon oxide film A formed by the film forming method inferior in the step coverage has a feature that it sharply narrows in the Z direction in the region outside the recess 90.

  In the concave portion 92 formed of the first dielectric film 46a shown in FIG. 10C, it is preferable that the opening dimension L4 at the top of the concave portion 92 is smaller. When the first dielectric film 46a is formed by a film formation method having inferior step coverage, the first dielectric film 46a becomes thick near the top of the recess 92, and an overhang of the first dielectric film 46a is formed. By this overhang, the opening dimension L4 at the top of the recess 92 can be further shortened. Therefore, the method of forming the first dielectric film 46a is preferably a film forming method having inferior step coverage, that is, plasma CVD using a material gas containing silane.

  In plasma CVD using a material gas containing TEOS shown in FIG. 11B, the surface reaction process (chemical reaction on the surface of the pixel electrode 9) is dominant, and the silicon oxide film B is formed. Specifically, a precursor formed in plasma is adsorbed on the surface of the pixel electrode 9 and reacts with oxygen radicals to form a silicon oxide film B. As a result, the silicon oxide film B is formed so as to cover the side walls and the bottom surface of the recess 90 with a relatively uniform film thickness. Therefore, plasma CVD using a material gas containing TEOS has excellent step coverage. Become a method. The film thickness of the silicon oxide film B covering the side wall of the recess 90 is larger than the film thickness of the silicon oxide film A covering the side wall of the recess 90, and the width of the cavity 98 (the length in the Y direction) inside the recess 90. Is smaller than the width of the cavity 97. Outside the recess 90, the width of the cavity 98 (the length in the Y direction) gradually decreases in the Z direction, and a vertex protruding in the Z direction is formed. The apex height H5 of the cavity 98 is approximately 400 nm.

  As described above, the silicon oxide film B formed by the film forming method having excellent step coverage covers the sidewall and the bottom surface of the recess 90 with a relatively uniform film thickness, and is formed by the film forming method having inferior step coverage. Compared with the oxide film A, it is formed thicker on the inner side (side wall, bottom surface) of the recess 90. As a result, the volume of the cavity 98 formed by the film forming method having excellent step coverage is smaller than the volume of the cavity 97 formed by the film forming method having inferior step coverage. Further, the height H5 of the apex of the cavity 98 formed by the film forming method excellent in step coverage is lower than the height H4 of the apex of the cavity 97 formed by the film forming method inferior in step coverage.

  The volume of the cavity 96 formed by the second dielectric film 46b at the position corresponding to the recess 92 shown in FIG. 10D is preferably small, and the height H3 of the apex of the cavity 96 is preferably low. Therefore, the second dielectric film 46b is preferably formed by a film forming method having excellent step coverage, that is, plasma CVD using a material gas containing TEOS.

  TEOS has carbon atoms (ethoxy groups), and the silicon oxide film A formed by plasma CVD using a material gas containing TEOS contains carbon as an impurity. On the other hand, since silane has no carbon atoms, the silicon oxide film B formed by plasma CVD using a material gas containing silane is different from the silicon oxide film A formed by plasma CVD using a material gas containing TEOS. In comparison, the carbon content as an impurity is reduced. Therefore, the dielectric layer 46 in this embodiment has a silicon oxide film (silicon oxide film A) with a low carbon content formed in contact with the pixel electrode 9 and a carbon content formed in contact with the alignment film 18. It is composed of many silicon oxide films (silicon oxide film B).

  As described above, according to the liquid crystal device 110 according to the present embodiment, the following effects can be obtained in addition to the effect (3) in the first embodiment.

(1) The concave portion 90 of the pixel electrode 9 is covered with a first dielectric film 46a made of a silicon oxide film formed by plasma CVD using a material gas containing silane. Then, the concave portion 92 having a small opening dimension L4 can be formed at a position corresponding to the concave portion 90 without performing a planarization process for thinning the first dielectric film 46a. Further, the recess 92 of the first dielectric film 46a is covered with a second dielectric film 46b made of a silicon oxide film formed by plasma CVD using a material gas containing TEOS. As a result, a cavity 96 having a low apex height H3 from the pixel electrode 9 can be formed.
Since the height H3 of the apex of the cavity 96 is low, the second dielectric film 46b can be thinned to a smaller thickness as long as the cavity 96 is not exposed. As a result, the thickness of the dielectric layer 46 composed of the first dielectric film 46 a and the second dielectric film 46 b can be set to approximately 250 nm to 300 nm, and the liquid crystal layer is formed between the pixel electrode 9 and the counter electrode 21. The reduction in effective voltage applied to 50 is reduced, and a higher quality display can be provided.

  (2) Since the step of planarizing the first dielectric film 46a (see step S4, FIG. 6) is omitted, the liquid crystal device 110 that is cheaper than that of the first embodiment can be provided.

(Embodiment 3)
<Electronic equipment>
Next, with reference to FIG. 12, an example of an electronic apparatus equipped with the liquid crystal device according to the above-described embodiment will be described. FIG. 12 is a plan view showing a configuration of an optical system of a three-plate projector (liquid crystal projector) as an electronic apparatus.

  The projector 1000 of this embodiment includes three reflective light modulation elements 310R, 310G, and 310B corresponding to red (R) light, green (G) light, and blue (B) light, respectively. The emitted light beam is modulated by each of the reflection type light modulation elements 310R, 310G, and 310B according to an image signal to form image light, and the image light is enlarged and projected onto a screen or the like. The liquid crystal device 100 or the liquid crystal device 110 according to the above-described embodiment is mounted on the reflective light modulation elements 310R, 310G, and 310B.

  The projector 1000 includes an illumination optical system 600, a color separation optical system 200, collimating lenses 250R, 250G, and 250B, retardation plates 260R, 260G, and 260B, polarizing beam splitters 320R, 320G, and 320B, and reflective light. Modulation elements 310R, 310G, and 310B, a cross dichroic prism 400 that is a light combining unit, and a projection optical unit 500 are provided.

  The illumination optical system 600 includes a light source 611 composed of an ultra-high pressure mercury lamp, a reflector 612 composed of a parabolic mirror, a lens array 620, a polarization conversion element 640, and the like. The radial light beam emitted from the light source 611 is converted into a plurality of partial light beams by the reflector 612 and the lens array 620, and is emitted to the color separation optical system 200 as S-polarized light by the polarization conversion element 640.

  The color separation optical system 200 has a function of separating the light beam emitted from the illumination optical system 600 into three color lights of R light, G light, and B light. The color separation optical system 200 includes a B light reflecting dichroic mirror 210, an RG light reflecting dichroic mirror 220, a G light reflecting dichroic mirror 230, and reflecting mirrors 240 and 245.

  Of the luminous flux emitted from the illumination optical system 600, the B light component is reflected by the B light reflecting dichroic mirror 210, and further reflected by the reflecting mirror 240 to reach the collimating lens 250B. On the other hand, among the light beams emitted from the illumination optical system 600, R light and G light components are reflected by the RG light reflecting dichroic mirror 220 and further reflected by the reflecting mirror 245 to reach the G light reflecting dichroic mirror 230. The G light component is reflected by the G light reflecting dichroic mirror 230 and reaches the collimating lens 250G, and the R light component is transmitted through the G light reflecting dichroic mirror 230 and reaches the collimating lens 250R.

  The collimating lenses 250R, 250G, and 250B convert a plurality of partial light beams emitted from the illumination optical system 600 into substantially parallel light beams, and illuminate corresponding reflective light modulation elements 310R, 310G, and 310B. The phase difference plates 260R, 260G, and 260B convert each color light (S-polarized light) that has passed through the collimating lenses 250R, 250G, and 250B into P-polarized light.

  The polarization beam splitter 320G transmits the G light (P-polarized light) emitted from the phase difference plate 260G and emits it to the reflective light modulation element 310G. Then, the polarization beam splitter 320G reflects the G light reflected by the reflective light modulation element 310G and modulated into S-polarized light and emits it to the cross dichroic prism 400.

  The polarizing beam splitters 320R and 320B have the same function as the polarizing beam splitter 320G. The polarization beam splitters 320R and 320B transmit the R light (P-polarized light) and B light (P-polarized light) emitted from the phase difference plates 260R and 260B, respectively, and are emitted to the reflective light modulation elements 310R and 310B, respectively. Of the R light and B light reflected by the reflective light modulation elements 310R and 310B, S polarized light is reflected and emitted to the cross dichroic prism 400, respectively.

  The cross dichroic prism 400 is formed into a prismatic shape with a substantially square cross section by bonding four triangular prisms, and dielectric multilayer films 410 and 420 are provided along the X-shaped bonding surface. ing. The dielectric multilayer film 410 transmits G light and reflects R light, and the dielectric multilayer film 420 transmits G light and reflects B light. The cross dichroic prism 400 then combines the modulated lights of the respective color lights emitted from the polarization beam splitters 320R, 320G, and 320B from the incident surfaces 400R, 400G, and 400B to form image light that represents a color image. Then, the light is emitted to the projection optical unit 500. The image light is enlarged and projected by the projection optical unit 500.

  Since the projector 1000 according to the present embodiment is applied with the liquid crystal device 100 or the liquid crystal device 110 according to the present invention, a high-quality display can be provided.

  In addition to projectors, electronic devices include direct-view televisions, mobile phones, portable audio devices, personal computers, video camera monitors, car navigation devices, electronic notebooks, calculators, workstations, video phones, POS terminals, The liquid crystal device 100 or the liquid crystal device 110 according to the present invention can be applied to various electronic devices such as a digital still camera.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. The electro-optic manufacturing method and the electronic apparatus to which the electro-optic is applied are also included in the technical scope of the present invention. Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

(Modification 1)
In the first embodiment, step S6 (planarization process of the second dielectric film 46b) shown in FIG. 6 can be omitted. Specifically, the first dielectric film 46a is subjected to a planarization process in step S4 shown in FIG. 6, and the surface of the first dielectric film 46a in contact with the second dielectric film 46b is flattened. Since the second dielectric film 46b is formed in contact with the surface of the first dielectric film 46a, it has a flat surface (surface). Accordingly, by forming the second dielectric film 46b with a film thickness as small as possible so as to close the concave portion 91 of the first dielectric film 46a and form the cavity 95, step S6 (second dielectric film 46b shown in FIG. Flattening process) can be omitted. According to this, a cheaper liquid crystal device can be provided as compared with the first embodiment.

(Modification 2)
Embodiments of the present invention are not limited to reflective liquid crystal devices. For example, the present invention can be applied to a transmissive liquid crystal device.
Furthermore, the present invention is not limited to being applied to the liquid crystal device 100 or the liquid crystal device 110, and can also be applied to, for example, a light emitting device having an organic electroluminescence element. According to this, it is possible to reduce the occurrence of luminance unevenness due to the recess caused by the contact hole 86.

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor film, 1a '... Channel region, 1b ... Data line side LDD region, 1c ... Pixel electrode side LDD region, 1d ... Data line side source / drain region, 1e ... Pixel electrode side source / drain region, 2 ... Gate insulating film 3a ... gate electrode, 6a ... data line, 9 ... pixel electrode, 9a ... first conductive film, 9b ... second conductive film, 10 ... element substrate, 11 ... scanning line, 12 ... base insulating film, 18, 25 ... Alignment film, 19 ... Dielectric layer, 20 ... Counter substrate, 20a ... Recess, 21 ... Counter electrode, 22 ... Flattening layer, 30 ... TFT, 41, 42, 43, 44 ... Interlayer insulation film, 46 ... Dielectric layer 46a ... first dielectric film, 46b ... second dielectric film, 50 ... liquid crystal layer, 52 ... sealing material, 53 ... parting part, 60 ... capacitive line, 60a ... upper capacitive electrode, 65 ... shield layer, 67, 93 ... Relay layer, 70 ... Storage capacity, 71 ... Part capacitance electrode, 75 ... dielectric film, 81, 84, 85, 86, 810 ... contact hole, 90, 91, 92 ... recess, 94, 95, 96 ... cavity, 100, 110 ... liquid crystal device, 101 ... data line Drive circuit 102... External connection terminals 103. Inspection circuit 104 Scanning line drive circuit 105 Wiring 106 Vertical conduction part 200 Color separation optical system 210 B light reflection dichroic mirror 220 RG light reflecting dichroic mirror, 230 ... G light reflecting dichroic mirror, 240, 245 ... Reflecting mirror, 250B, 250G, 250R ... Parallelizing lens, 260G, 260R ... Phase difference plate, 310G, 310R ... Reflective light modulation element, 320G, 320R: Polarizing beam splitter, 400: Cross dichroic prism, 400R: Entrance plane, 4 0,420 ... dielectric multilayer film, 500 ... projection section, 600 ... illumination optical system, 611 ... light source, 612 ... Reflector 620 ... lens array, 640 ... polarization conversion element, 1000 ... projector.

Claims (6)

A pixel switching element, a conductive film formed above the pixel switching element, an insulating film having a contact hole and formed above the conductive film, a pixel electrode formed above the insulating film, A first dielectric film formed above the pixel electrode; and a second dielectric film formed above the first dielectric film; and the pixel through the contact hole. A method of manufacturing an electro-optical device in which a switching element and the pixel electrode are electrically connected,
A first portion is provided at a position corresponding to the contact hole so as to cover a part of the upper surface of the insulating film, a sidewall of the insulating film in which the contact hole is formed, and the conductive film exposed from the contact hole. Forming a pixel electrode having a recess of
Forming a first dielectric film covering the pixel electrode and having a first cavity sealed at a position corresponding to the first recess;
Performing a planarization process for thinning the first dielectric film, exposing the first cavity, and forming a second recess;
Forming a second dielectric film covering the thinned first dielectric film and having a second cavity sealed at a position corresponding to the second recess;
A method for manufacturing an electro-optical device.   The step of forming the first dielectric film and the step of forming the second dielectric film are steps of forming a silicon oxide film by plasma CVD using a material gas containing organooxysilane. The method of manufacturing an electro-optical device according to claim 1.   3. The electricity according to claim 1, wherein the step of planarizing the first dielectric film includes a step of chemical mechanical polishing or anisotropic dry etching. 4. Manufacturing method of optical device. The second dielectric film is subjected to a second planarization process for reducing the thickness of the second dielectric film in a range where the second cavity is not exposed,
4. The electro-optical device according to claim 1, wherein the second planarization process includes a polishing step and a step of etching a polishing surface after the polishing step. 5. Device manufacturing method. A pixel switching element, a conductive film formed above the pixel switching element, an insulating film having a contact hole and formed above the conductive film, a pixel electrode formed above the insulating film, A first dielectric film formed above the pixel electrode; and a second dielectric film formed above the first dielectric film; and the pixel through the contact hole. A method of manufacturing an electro-optical device in which a switching element and the pixel electrode are electrically connected,
A first portion is provided at a position corresponding to the contact hole so as to cover a part of the upper surface of the insulating film, a sidewall of the insulating film in which the contact hole is formed, and the conductive film exposed from the contact hole. Forming a pixel electrode having a recess of
Forming the first silicon oxide film having a second recess at a position corresponding to the first recess by plasma CVD using a material gas containing silicon hydride;
A step of forming the second silicon oxide film having a hermetically sealed cavity at a position corresponding to the second recess by plasma CVD using a material gas containing organooxysilane. When,
Applying a planarization treatment to thin the second silicon oxide film in a range where the sealed cavity is not exposed;
A method for manufacturing an electro-optical device.   6. The method of manufacturing an electro-optical device according to claim 5, wherein the step of performing the planarization includes a polishing step and a step of etching a polished surface after the polishing step.

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